ia64/xen-unstable

changeset 15477:204519fceeef

[IA64] Minor reformating and comments for vmx_fault.c

Signed-off-by: Tristan Gingold <tgingold@free.fr>
author Alex Williamson <alex.williamson@hp.com>
date Thu Jul 05 13:30:25 2007 -0600 (2007-07-05)
parents 5927f10462cd
children d87d99738428
files xen/arch/ia64/vmx/vmx_fault.c
line diff
     1.1 --- a/xen/arch/ia64/vmx/vmx_fault.c	Thu Jul 05 13:24:42 2007 -0600
     1.2 +++ b/xen/arch/ia64/vmx/vmx_fault.c	Thu Jul 05 13:30:25 2007 -0600
     1.3 @@ -1,6 +1,6 @@
     1.4  /* -*-  Mode:C; c-basic-offset:4; tab-width:4; indent-tabs-mode:nil -*- */
     1.5  /*
     1.6 - * vmx_process.c: handling VMX architecture-related VM exits
     1.7 + * vmx_fault.c: handling VMX architecture-related VM exits
     1.8   * Copyright (c) 2005, Intel Corporation.
     1.9   *
    1.10   * This program is free software; you can redistribute it and/or modify it
    1.11 @@ -314,7 +314,7 @@ static int vmx_handle_lds(REGS* regs)
    1.12  
    1.13  /* We came here because the H/W VHPT walker failed to find an entry */
    1.14  IA64FAULT
    1.15 -vmx_hpw_miss(u64 vadr , u64 vec, REGS* regs)
    1.16 +vmx_hpw_miss(u64 vadr, u64 vec, REGS* regs)
    1.17  {
    1.18      IA64_PSR vpsr;
    1.19      int type;
    1.20 @@ -334,13 +334,15 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
    1.21      else
    1.22          panic_domain(regs, "wrong vec:%lx\n", vec);
    1.23  
    1.24 -    if(is_physical_mode(v)&&(!(vadr<<1>>62))){
    1.25 -        if(vec==2){
    1.26 +    /* Physical mode and region is 0 or 4.  */
    1.27 +    if (is_physical_mode(v) && (!((vadr<<1)>>62))) {
    1.28 +        if (vec == 2) {
    1.29 +            /* DTLB miss.  */
    1.30              if (misr.sp) /* Refer to SDM Vol2 Table 4-11,4-12 */
    1.31                  return vmx_handle_lds(regs);
    1.32              if (v->domain != dom0
    1.33                  && __gpfn_is_io(v->domain, (vadr << 1) >> (PAGE_SHIFT + 1))) {
    1.34 -                emulate_io_inst(v,((vadr<<1)>>1),4);   //  UC
    1.35 +                emulate_io_inst(v, ((vadr<<1)>>1),4);   //  UC
    1.36                  return IA64_FAULT;
    1.37              }
    1.38          }
    1.39 @@ -349,7 +351,7 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
    1.40      }
    1.41      
    1.42  try_again:
    1.43 -    if((data=vtlb_lookup(v, vadr,type))!=0){
    1.44 +    if ((data=vtlb_lookup(v, vadr,type)) != 0) {
    1.45          if (v->domain != dom0 && type == DSIDE_TLB) {
    1.46              if (misr.sp) { /* Refer to SDM Vol2 Table 4-10,4-12 */
    1.47                  if ((data->ma == VA_MATTR_UC) || (data->ma == VA_MATTR_UCE))
    1.48 @@ -372,7 +374,7 @@ try_again:
    1.49          }
    1.50          thash_vhpt_insert(v, data->page_flags, data->itir, vadr, type);
    1.51  
    1.52 -    }else if(type == DSIDE_TLB){
    1.53 +    } else if (type == DSIDE_TLB) {
    1.54      
    1.55          if (misr.sp)
    1.56              return vmx_handle_lds(regs);
    1.57 @@ -380,11 +382,11 @@ try_again:
    1.58          vcpu_get_rr(v, vadr, &rr);
    1.59          itir = rr & (RR_RID_MASK | RR_PS_MASK);
    1.60  
    1.61 -        if(!vhpt_enabled(v, vadr, misr.rs?RSE_REF:DATA_REF)){
    1.62 +        if (!vhpt_enabled(v, vadr, misr.rs ? RSE_REF : DATA_REF)) {
    1.63              if (GOS_WINDOWS(v)) {
    1.64                  /* windows use region 4 and 5 for identity mapping */
    1.65                  if (REGION_NUMBER(vadr) == 4 && !(regs->cr_ipsr & IA64_PSR_CPL)
    1.66 -                    && (REGION_OFFSET(vadr)<= _PAGE_PPN_MASK)) {
    1.67 +                    && (REGION_OFFSET(vadr) <= _PAGE_PPN_MASK)) {
    1.68  
    1.69                      pteval = PAGEALIGN(REGION_OFFSET(vadr), itir_ps(itir)) |
    1.70                               (_PAGE_P | _PAGE_A | _PAGE_D |
    1.71 @@ -397,7 +399,7 @@ try_again:
    1.72                  }
    1.73  
    1.74                  if (REGION_NUMBER(vadr) == 5 && !(regs->cr_ipsr & IA64_PSR_CPL)
    1.75 -                    && (REGION_OFFSET(vadr)<= _PAGE_PPN_MASK)) {
    1.76 +                    && (REGION_OFFSET(vadr) <= _PAGE_PPN_MASK)) {
    1.77  
    1.78                      pteval = PAGEALIGN(REGION_OFFSET(vadr),itir_ps(itir)) |
    1.79                               (_PAGE_P | _PAGE_A | _PAGE_D |
    1.80 @@ -410,11 +412,11 @@ try_again:
    1.81                  }
    1.82              }
    1.83  
    1.84 -            if(vpsr.ic){
    1.85 +            if (vpsr.ic) {
    1.86                  vcpu_set_isr(v, misr.val);
    1.87                  alt_dtlb(v, vadr);
    1.88                  return IA64_FAULT;
    1.89 -            } else{
    1.90 +            } else {
    1.91                  nested_dtlb(v);
    1.92                  return IA64_FAULT;
    1.93              }
    1.94 @@ -466,7 +468,7 @@ try_again:
    1.95                  vcpu_set_isr(v, misr.val);
    1.96                  dtlb_fault(v, vadr);
    1.97                  return IA64_FAULT;
    1.98 -            }else{
    1.99 +            } else {
   1.100                  nested_dtlb(v);
   1.101                  return IA64_FAULT;
   1.102              }
   1.103 @@ -481,7 +483,7 @@ try_again:
   1.104                  return IA64_FAULT;
   1.105              }
   1.106          }
   1.107 -    }else if(type == ISIDE_TLB){
   1.108 +    } else if (type == ISIDE_TLB) {
   1.109      
   1.110          if (!vpsr.ic)
   1.111              misr.ni = 1;