ia64/xen-unstable

changeset 15240:1f8fb764f843

Add VMX memory-mapped Local APIC access optimization.

Some operating systems access the local APIC TPR very frequently, and
we handle that using software-based local APIC virtualization in Xen
today. Such virtualization incurs a number of VM exits from the
memory-access instructions against the APIC page in the guest.

The attached patch enables the TPR shadow feature that provides APIC
TPR virtualization in hardware. Our tests indicate it can
significantly boost the performance of such guests including 32-bit
Windows XP/2003.

Moreover, with the patch, local APIC accesses other than TPR in guests
are intercepted directly as APIC_ACCESS VM exits rather than
PAGE_FAULT VM exits; this can lower the emulation cost of such
accesses.

Signed-off-by: Dexuan Cui <dexuan.cui@intel.com>
author kfraser@localhost.localdomain
date Wed May 30 16:48:28 2007 +0100 (2007-05-30)
parents 1f1d1b43951e
children 96a59a5ae656
files xen/arch/x86/hvm/hvm.c xen/arch/x86/hvm/vlapic.c xen/arch/x86/hvm/vmx/intr.c xen/arch/x86/hvm/vmx/vmcs.c xen/arch/x86/hvm/vmx/vmx.c xen/include/asm-x86/hvm/domain.h xen/include/asm-x86/hvm/vlapic.h xen/include/asm-x86/hvm/vmx/vmcs.h xen/include/asm-x86/hvm/vmx/vmx.h xen/include/asm-x86/msr.h
line diff
     1.1 --- a/xen/arch/x86/hvm/hvm.c	Wed May 30 13:10:20 2007 +0100
     1.2 +++ b/xen/arch/x86/hvm/hvm.c	Wed May 30 16:48:28 2007 +0100
     1.3 @@ -226,6 +226,7 @@ int hvm_domain_initialise(struct domain 
     1.4  
     1.5      spin_lock_init(&d->arch.hvm_domain.pbuf_lock);
     1.6      spin_lock_init(&d->arch.hvm_domain.irq_lock);
     1.7 +    spin_lock_init(&d->arch.hvm_domain.vapic_access_lock);
     1.8  
     1.9      rc = paging_enable(d, PG_refcounts|PG_translate|PG_external);
    1.10      if ( rc != 0 )
     2.1 --- a/xen/arch/x86/hvm/vlapic.c	Wed May 30 13:10:20 2007 +0100
     2.2 +++ b/xen/arch/x86/hvm/vlapic.c	Wed May 30 16:48:28 2007 +0100
     2.3 @@ -79,8 +79,6 @@ static unsigned int vlapic_lvt_mask[VLAP
     2.4  #define vlapic_lvtt_period(vlapic)                              \
     2.5      (vlapic_get_reg(vlapic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC)
     2.6  
     2.7 -#define vlapic_base_address(vlapic)                             \
     2.8 -    (vlapic->hw.apic_base_msr & MSR_IA32_APICBASE_BASE)
     2.9  
    2.10  /*
    2.11   * Generic APIC bitmap vector update & search routines.
     3.1 --- a/xen/arch/x86/hvm/vmx/intr.c	Wed May 30 13:10:20 2007 +0100
     3.2 +++ b/xen/arch/x86/hvm/vmx/intr.c	Wed May 30 16:48:28 2007 +0100
     3.3 @@ -67,7 +67,6 @@ static inline int is_interruptibility_st
     3.4      return __vmread(GUEST_INTERRUPTIBILITY_INFO);
     3.5  }
     3.6  
     3.7 -#ifdef __x86_64__
     3.8  static void update_tpr_threshold(struct vlapic *vlapic)
     3.9  {
    3.10      int max_irr, tpr;
    3.11 @@ -75,6 +74,11 @@ static void update_tpr_threshold(struct 
    3.12      if ( !cpu_has_vmx_tpr_shadow )
    3.13          return;
    3.14  
    3.15 +#ifdef __i386__
    3.16 +    if ( !vlapic->mmap_vtpr_enabled )
    3.17 +        return;
    3.18 +#endif
    3.19 +
    3.20      if ( !vlapic_enabled(vlapic) || 
    3.21           ((max_irr = vlapic_find_highest_irr(vlapic)) == -1) )
    3.22      {
    3.23 @@ -85,9 +89,6 @@ static void update_tpr_threshold(struct 
    3.24      tpr = vlapic_get_reg(vlapic, APIC_TASKPRI) & 0xF0;
    3.25      __vmwrite(TPR_THRESHOLD, (max_irr > tpr) ? (tpr >> 4) : (max_irr >> 4));
    3.26  }
    3.27 -#else
    3.28 -#define update_tpr_threshold(v) ((void)0)
    3.29 -#endif
    3.30  
    3.31  asmlinkage void vmx_intr_assist(void)
    3.32  {
     4.1 --- a/xen/arch/x86/hvm/vmx/vmcs.c	Wed May 30 13:10:20 2007 +0100
     4.2 +++ b/xen/arch/x86/hvm/vmx/vmcs.c	Wed May 30 16:48:28 2007 +0100
     4.3 @@ -40,6 +40,7 @@
     4.4  /* Dynamic (run-time adjusted) execution control flags. */
     4.5  u32 vmx_pin_based_exec_control __read_mostly;
     4.6  u32 vmx_cpu_based_exec_control __read_mostly;
     4.7 +u32 vmx_secondary_exec_control __read_mostly;
     4.8  u32 vmx_vmexit_control __read_mostly;
     4.9  u32 vmx_vmentry_control __read_mostly;
    4.10  
    4.11 @@ -60,11 +61,15 @@ static u32 adjust_vmx_controls(u32 ctl_m
    4.12      return ctl;
    4.13  }
    4.14  
    4.15 +#define vmx_has_secondary_exec_ctls \
    4.16 +    (_vmx_cpu_based_exec_control & ACTIVATE_SECONDARY_CONTROLS)
    4.17 +
    4.18  void vmx_init_vmcs_config(void)
    4.19  {
    4.20      u32 vmx_msr_low, vmx_msr_high, min, opt;
    4.21      u32 _vmx_pin_based_exec_control;
    4.22      u32 _vmx_cpu_based_exec_control;
    4.23 +    u32 _vmx_secondary_exec_control = 0;
    4.24      u32 _vmx_vmexit_control;
    4.25      u32 _vmx_vmentry_control;
    4.26  
    4.27 @@ -80,9 +85,8 @@ void vmx_init_vmcs_config(void)
    4.28             CPU_BASED_ACTIVATE_IO_BITMAP |
    4.29             CPU_BASED_USE_TSC_OFFSETING);
    4.30      opt = CPU_BASED_ACTIVATE_MSR_BITMAP;
    4.31 -#ifdef __x86_64__
    4.32      opt |= CPU_BASED_TPR_SHADOW;
    4.33 -#endif
    4.34 +    opt |= ACTIVATE_SECONDARY_CONTROLS;
    4.35      _vmx_cpu_based_exec_control = adjust_vmx_controls(
    4.36          min, opt, MSR_IA32_VMX_PROCBASED_CTLS_MSR);
    4.37  #ifdef __x86_64__
    4.38 @@ -92,8 +96,19 @@ void vmx_init_vmcs_config(void)
    4.39          _vmx_cpu_based_exec_control = adjust_vmx_controls(
    4.40              min, opt, MSR_IA32_VMX_PROCBASED_CTLS_MSR);
    4.41      }
    4.42 +#elif defined(__i386__)
    4.43 +    if ( !vmx_has_secondary_exec_ctls )
    4.44 +        _vmx_cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
    4.45  #endif
    4.46  
    4.47 +    if ( vmx_has_secondary_exec_ctls )
    4.48 +    {
    4.49 +        min = 0;
    4.50 +        opt = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
    4.51 +        _vmx_secondary_exec_control = adjust_vmx_controls(
    4.52 +            min, opt, MSR_IA32_VMX_PROCBASED_CTLS2);
    4.53 +    }
    4.54 +
    4.55      min = VM_EXIT_ACK_INTR_ON_EXIT;
    4.56      opt = 0;
    4.57  #ifdef __x86_64__
    4.58 @@ -113,6 +128,8 @@ void vmx_init_vmcs_config(void)
    4.59          vmcs_revision_id = vmx_msr_low;
    4.60          vmx_pin_based_exec_control = _vmx_pin_based_exec_control;
    4.61          vmx_cpu_based_exec_control = _vmx_cpu_based_exec_control;
    4.62 +        if ( vmx_has_secondary_exec_ctls )
    4.63 +            vmx_secondary_exec_control = _vmx_secondary_exec_control;
    4.64          vmx_vmexit_control         = _vmx_vmexit_control;
    4.65          vmx_vmentry_control        = _vmx_vmentry_control;
    4.66      }
    4.67 @@ -121,6 +138,8 @@ void vmx_init_vmcs_config(void)
    4.68          BUG_ON(vmcs_revision_id != vmx_msr_low);
    4.69          BUG_ON(vmx_pin_based_exec_control != _vmx_pin_based_exec_control);
    4.70          BUG_ON(vmx_cpu_based_exec_control != _vmx_cpu_based_exec_control);
    4.71 +        if ( vmx_has_secondary_exec_ctls )
    4.72 +            BUG_ON(vmx_secondary_exec_control != _vmx_secondary_exec_control);
    4.73          BUG_ON(vmx_vmexit_control != _vmx_vmexit_control);
    4.74          BUG_ON(vmx_vmentry_control != _vmx_vmentry_control);
    4.75      }
    4.76 @@ -291,6 +310,8 @@ static void construct_vmcs(struct vcpu *
    4.77      __vmwrite(VM_ENTRY_CONTROLS, vmx_vmentry_control);
    4.78      __vmwrite(CPU_BASED_VM_EXEC_CONTROL, vmx_cpu_based_exec_control);
    4.79      v->arch.hvm_vcpu.u.vmx.exec_control = vmx_cpu_based_exec_control;
    4.80 +    if ( vmx_cpu_based_exec_control & ACTIVATE_SECONDARY_CONTROLS )
    4.81 +        __vmwrite(SECONDARY_VM_EXEC_CONTROL, vmx_secondary_exec_control);
    4.82  
    4.83      if ( cpu_has_vmx_msr_bitmap )
    4.84          __vmwrite(MSR_BITMAP, virt_to_maddr(vmx_msr_bitmap));
    4.85 @@ -417,7 +438,7 @@ static void construct_vmcs(struct vcpu *
    4.86      __vmwrite(CR4_READ_SHADOW, v->arch.hvm_vmx.cpu_shadow_cr4);
    4.87  
    4.88  #ifdef __x86_64__ 
    4.89 -    /* VLAPIC TPR optimisation. */
    4.90 +    /* CR8 based VLAPIC TPR optimization. */
    4.91      if ( cpu_has_vmx_tpr_shadow )
    4.92      {
    4.93          __vmwrite(VIRTUAL_APIC_PAGE_ADDR,
    4.94 @@ -426,6 +447,16 @@ static void construct_vmcs(struct vcpu *
    4.95      }
    4.96  #endif
    4.97  
    4.98 +    /* Memory-mapped based VLAPIC TPR optimization. */
    4.99 +    if ( cpu_has_vmx_mmap_vtpr_optimization )
   4.100 +    {
   4.101 +        __vmwrite(VIRTUAL_APIC_PAGE_ADDR,
   4.102 +                    page_to_maddr(vcpu_vlapic(v)->regs_page));
   4.103 +        __vmwrite(TPR_THRESHOLD, 0);
   4.104 +
   4.105 +        vcpu_vlapic(v)->mmap_vtpr_enabled = 1;
   4.106 +    }
   4.107 +
   4.108      __vmwrite(GUEST_LDTR_SELECTOR, 0);
   4.109      __vmwrite(GUEST_LDTR_BASE, 0);
   4.110      __vmwrite(GUEST_LDTR_LIMIT, 0);
   4.111 @@ -496,6 +527,18 @@ void vmx_do_resume(struct vcpu *v)
   4.112          vmx_set_host_env(v);
   4.113      }
   4.114  
   4.115 +    if ( !v->arch.hvm_vmx.launched && vcpu_vlapic(v)->mmap_vtpr_enabled )
   4.116 +    {
   4.117 +        struct page_info *pg = change_guest_physmap_for_vtpr(v->domain, 1);
   4.118 +
   4.119 +        if ( pg == NULL )
   4.120 +        {
   4.121 +            gdprintk(XENLOG_ERR, "change_guest_physmap_for_vtpr failed!\n");
   4.122 +            domain_crash_synchronous();
   4.123 +        }
   4.124 +        __vmwrite(APIC_ACCESS_ADDR, page_to_maddr(pg));
   4.125 +    }
   4.126 +
   4.127      debug_state = v->domain->debugger_attached;
   4.128      if ( unlikely(v->arch.hvm_vcpu.debug_state_latch != debug_state) )
   4.129      {
     5.1 --- a/xen/arch/x86/hvm/vmx/vmx.c	Wed May 30 13:10:20 2007 +0100
     5.2 +++ b/xen/arch/x86/hvm/vmx/vmx.c	Wed May 30 16:48:28 2007 +0100
     5.3 @@ -2483,6 +2483,114 @@ done:
     5.4      return 1;
     5.5  }
     5.6  
     5.7 +struct page_info * change_guest_physmap_for_vtpr(struct domain *d,
     5.8 +                                                 int enable_vtpr)
     5.9 +{
    5.10 +    struct page_info *pg;
    5.11 +    unsigned long pfn, mfn;
    5.12 +
    5.13 +    spin_lock(&d->arch.hvm_domain.vapic_access_lock);
    5.14 +
    5.15 +    pg = d->arch.hvm_domain.apic_access_page;
    5.16 +    pfn = paddr_to_pfn(APIC_DEFAULT_PHYS_BASE);
    5.17 +
    5.18 +    if ( enable_vtpr )
    5.19 +    {
    5.20 +        if ( d->arch.hvm_domain.physmap_changed_for_vlapic_access )
    5.21 +            goto out;
    5.22 +
    5.23 +        if ( pg == NULL )
    5.24 +            pg = alloc_domheap_page(d);
    5.25 +        if ( pg == NULL )
    5.26 +        {
    5.27 +            gdprintk(XENLOG_ERR, "alloc_domheap_pages() failed!\n");
    5.28 +            goto out;
    5.29 +        }
    5.30 +
    5.31 +        mfn = page_to_mfn(pg);
    5.32 +        d->arch.hvm_domain.apic_access_page = pg;
    5.33 +
    5.34 +        guest_physmap_add_page(d, pfn, mfn);
    5.35 +
    5.36 +        d->arch.hvm_domain.physmap_changed_for_vlapic_access = 1;
    5.37 +
    5.38 +        goto out;
    5.39 +    }
    5.40 +    else
    5.41 +    {
    5.42 +        if ( d->arch.hvm_domain.physmap_changed_for_vlapic_access )
    5.43 +        {
    5.44 +            mfn = page_to_mfn(pg);
    5.45 +            guest_physmap_remove_page(d, pfn, mfn);
    5.46 +            flush_tlb_mask(d->domain_dirty_cpumask);
    5.47 +
    5.48 +            d->arch.hvm_domain.physmap_changed_for_vlapic_access = 0;
    5.49 +        }
    5.50 +        pg = NULL;
    5.51 +        goto out;
    5.52 +    }
    5.53 +
    5.54 +out:
    5.55 +    spin_unlock(&d->arch.hvm_domain.vapic_access_lock);
    5.56 +    return pg;
    5.57 +}
    5.58 +
    5.59 +static void check_vlapic_msr_for_vtpr(struct vcpu *v)
    5.60 +{
    5.61 +    struct vlapic *vlapic = vcpu_vlapic(v);
    5.62 +    int    mmap_vtpr_enabled = vcpu_vlapic(v)->mmap_vtpr_enabled;
    5.63 +    uint32_t tmp;
    5.64 +
    5.65 +
    5.66 +    if ( vlapic_hw_disabled(vlapic) && mmap_vtpr_enabled )
    5.67 +    {
    5.68 +        vcpu_vlapic(v)->mmap_vtpr_enabled = 0;    
    5.69 +
    5.70 +#ifdef __i386__
    5.71 +        v->arch.hvm_vcpu.u.vmx.exec_control &= ~CPU_BASED_TPR_SHADOW;
    5.72 +        __vmwrite(CPU_BASED_VM_EXEC_CONTROL,
    5.73 +                  v->arch.hvm_vcpu.u.vmx.exec_control);
    5.74 +#elif defined(__x86_64__)
    5.75 +        if ( !cpu_has_vmx_tpr_shadow )
    5.76 +        {
    5.77 +            v->arch.hvm_vcpu.u.vmx.exec_control &= ~CPU_BASED_TPR_SHADOW;
    5.78 +            __vmwrite(CPU_BASED_VM_EXEC_CONTROL,
    5.79 +                v->arch.hvm_vcpu.u.vmx.exec_control);
    5.80 +        }
    5.81 +#endif
    5.82 +        tmp  = __vmread(SECONDARY_VM_EXEC_CONTROL);
    5.83 +        tmp &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
    5.84 +        __vmwrite(SECONDARY_VM_EXEC_CONTROL, tmp);
    5.85 +
    5.86 +        change_guest_physmap_for_vtpr(v->domain, 0);
    5.87 +    }
    5.88 +    else if ( !vlapic_hw_disabled(vlapic) && !mmap_vtpr_enabled &&
    5.89 +              cpu_has_vmx_mmap_vtpr_optimization )
    5.90 +    {
    5.91 +        vcpu_vlapic(v)->mmap_vtpr_enabled = 1;
    5.92 +
    5.93 +        v->arch.hvm_vcpu.u.vmx.exec_control |=
    5.94 +            ( ACTIVATE_SECONDARY_CONTROLS | CPU_BASED_TPR_SHADOW );
    5.95 +        __vmwrite(CPU_BASED_VM_EXEC_CONTROL,
    5.96 +                  v->arch.hvm_vcpu.u.vmx.exec_control);
    5.97 +        tmp  = __vmread(SECONDARY_VM_EXEC_CONTROL);
    5.98 +        tmp |= SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
    5.99 +        __vmwrite(SECONDARY_VM_EXEC_CONTROL, tmp);
   5.100 +
   5.101 +        change_guest_physmap_for_vtpr(v->domain, 1);
   5.102 +    }
   5.103 +
   5.104 +    if ( vcpu_vlapic(v)->mmap_vtpr_enabled &&
   5.105 +        !vlapic_hw_disabled(vlapic) &&
   5.106 +        (vlapic_base_address(vlapic) != APIC_DEFAULT_PHYS_BASE) )
   5.107 +    {
   5.108 +        gdprintk(XENLOG_ERR,
   5.109 +                 "Local APIC base address is set to 0x%016"PRIx64"!\n",
   5.110 +                  vlapic_base_address(vlapic));
   5.111 +        domain_crash_synchronous();
   5.112 +    }
   5.113 +}
   5.114 +
   5.115  static inline int vmx_do_msr_write(struct cpu_user_regs *regs)
   5.116  {
   5.117      u32 ecx = regs->ecx;
   5.118 @@ -2511,6 +2619,7 @@ static inline int vmx_do_msr_write(struc
   5.119          break;
   5.120      case MSR_IA32_APICBASE:
   5.121          vlapic_msr_set(vcpu_vlapic(v), msr_content);
   5.122 +        check_vlapic_msr_for_vtpr(v);
   5.123          break;
   5.124      default:
   5.125          if ( !long_mode_do_msr_write(regs) )
   5.126 @@ -2823,6 +2932,15 @@ asmlinkage void vmx_vmexit_handler(struc
   5.127  
   5.128      case EXIT_REASON_TPR_BELOW_THRESHOLD:
   5.129          break;
   5.130 +    case EXIT_REASON_APIC_ACCESS:
   5.131 +    {
   5.132 +        unsigned long offset;
   5.133 +
   5.134 +        exit_qualification = __vmread(EXIT_QUALIFICATION);
   5.135 +        offset = exit_qualification & 0x0fffUL;        
   5.136 +        handle_mmio(APIC_DEFAULT_PHYS_BASE | offset);
   5.137 +        break;
   5.138 +    }
   5.139  
   5.140      default:
   5.141      exit_and_crash:
     6.1 --- a/xen/include/asm-x86/hvm/domain.h	Wed May 30 13:10:20 2007 +0100
     6.2 +++ b/xen/include/asm-x86/hvm/domain.h	Wed May 30 16:48:28 2007 +0100
     6.3 @@ -41,6 +41,11 @@ struct hvm_domain {
     6.4      s64                    tsc_frequency;
     6.5      struct pl_time         pl_time;
     6.6  
     6.7 +    /* For memory-mapped vLAPIC/vTPR access optimization */
     6.8 +    spinlock_t             vapic_access_lock;
     6.9 +    int                    physmap_changed_for_vlapic_access : 1;
    6.10 +    struct page_info       *apic_access_page;
    6.11 +
    6.12      struct hvm_io_handler  io_handler;
    6.13  
    6.14      /* Lock protects access to irq, vpic and vioapic. */
     7.1 --- a/xen/include/asm-x86/hvm/vlapic.h	Wed May 30 13:10:20 2007 +0100
     7.2 +++ b/xen/include/asm-x86/hvm/vlapic.h	Wed May 30 16:48:28 2007 +0100
     7.3 @@ -49,12 +49,17 @@
     7.4  #define vlapic_disabled(vlapic)    ((vlapic)->hw.disabled)
     7.5  #define vlapic_enabled(vlapic)     (!vlapic_disabled(vlapic))
     7.6  
     7.7 +#define vlapic_base_address(vlapic)                             \
     7.8 +    (vlapic->hw.apic_base_msr & MSR_IA32_APICBASE_BASE)
     7.9 +
    7.10  struct vlapic {
    7.11      struct hvm_hw_lapic      hw;
    7.12      struct hvm_hw_lapic_regs *regs;
    7.13      struct periodic_time     pt;
    7.14      s_time_t                 timer_last_update;
    7.15      struct page_info         *regs_page;
    7.16 +
    7.17 +    int                      mmap_vtpr_enabled : 1;
    7.18  };
    7.19  
    7.20  static inline uint32_t vlapic_get_reg(struct vlapic *vlapic, uint32_t reg)
     8.1 --- a/xen/include/asm-x86/hvm/vmx/vmcs.h	Wed May 30 13:10:20 2007 +0100
     8.2 +++ b/xen/include/asm-x86/hvm/vmx/vmcs.h	Wed May 30 16:48:28 2007 +0100
     8.3 @@ -106,6 +106,7 @@ void vmx_vmcs_exit(struct vcpu *v);
     8.4  #define CPU_BASED_ACTIVATE_MSR_BITMAP   0x10000000
     8.5  #define CPU_BASED_MONITOR_EXITING       0x20000000
     8.6  #define CPU_BASED_PAUSE_EXITING         0x40000000
     8.7 +#define ACTIVATE_SECONDARY_CONTROLS     0x80000000
     8.8  extern u32 vmx_cpu_based_exec_control;
     8.9  
    8.10  #define PIN_BASED_EXT_INTR_MASK         0x00000001
    8.11 @@ -121,8 +122,16 @@ extern u32 vmx_vmexit_control;
    8.12  #define VM_ENTRY_DEACT_DUAL_MONITOR     0x00000800
    8.13  extern u32 vmx_vmentry_control;
    8.14  
    8.15 +#define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
    8.16 +extern u32 vmx_secondary_exec_control;
    8.17 +
    8.18 +#define cpu_has_vmx_virtualize_apic_accesses \
    8.19 +    (vmx_secondary_exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES)
    8.20  #define cpu_has_vmx_tpr_shadow \
    8.21      (vmx_cpu_based_exec_control & CPU_BASED_TPR_SHADOW)
    8.22 +#define cpu_has_vmx_mmap_vtpr_optimization \
    8.23 +    (cpu_has_vmx_virtualize_apic_accesses && cpu_has_vmx_tpr_shadow)
    8.24 +
    8.25  #define cpu_has_vmx_msr_bitmap \
    8.26      (vmx_cpu_based_exec_control & CPU_BASED_ACTIVATE_MSR_BITMAP)
    8.27  extern char *vmx_msr_bitmap;
    8.28 @@ -160,6 +169,8 @@ enum vmcs_field {
    8.29      TSC_OFFSET_HIGH                 = 0x00002011,
    8.30      VIRTUAL_APIC_PAGE_ADDR          = 0x00002012,
    8.31      VIRTUAL_APIC_PAGE_ADDR_HIGH     = 0x00002013,
    8.32 +    APIC_ACCESS_ADDR                = 0x00002014,
    8.33 +    APIC_ACCESS_ADDR_HIGH           = 0x00002015, 
    8.34      VMCS_LINK_POINTER               = 0x00002800,
    8.35      VMCS_LINK_POINTER_HIGH          = 0x00002801,
    8.36      GUEST_IA32_DEBUGCTL             = 0x00002802,
     9.1 --- a/xen/include/asm-x86/hvm/vmx/vmx.h	Wed May 30 13:10:20 2007 +0100
     9.2 +++ b/xen/include/asm-x86/hvm/vmx/vmx.h	Wed May 30 16:48:28 2007 +0100
     9.3 @@ -33,6 +33,9 @@ void vmx_intr_assist(void);
     9.4  void vmx_do_resume(struct vcpu *);
     9.5  void set_guest_time(struct vcpu *v, u64 gtime);
     9.6  
     9.7 +extern struct page_info *change_guest_physmap_for_vtpr(struct domain *d,
     9.8 +                                                       int enable_vtpr);
     9.9 +
    9.10  /*
    9.11   * Exit Reasons
    9.12   */
    9.13 @@ -81,6 +84,7 @@ void set_guest_time(struct vcpu *v, u64 
    9.14  #define EXIT_REASON_MACHINE_CHECK       41
    9.15  
    9.16  #define EXIT_REASON_TPR_BELOW_THRESHOLD 43
    9.17 +#define EXIT_REASON_APIC_ACCESS         44
    9.18  
    9.19  /*
    9.20   * Interruption-information format
    10.1 --- a/xen/include/asm-x86/msr.h	Wed May 30 13:10:20 2007 +0100
    10.2 +++ b/xen/include/asm-x86/msr.h	Wed May 30 16:48:28 2007 +0100
    10.3 @@ -119,6 +119,7 @@ static inline void wrmsrl(unsigned int m
    10.4  #define MSR_IA32_VMX_CR0_FIXED1                 0x487
    10.5  #define MSR_IA32_VMX_CR4_FIXED0                 0x488
    10.6  #define MSR_IA32_VMX_CR4_FIXED1                 0x489
    10.7 +#define MSR_IA32_VMX_PROCBASED_CTLS2            0x48b
    10.8  #define IA32_FEATURE_CONTROL_MSR                0x3a
    10.9  #define IA32_FEATURE_CONTROL_MSR_LOCK           0x1
   10.10  #define IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON   0x4