ia64/xen-unstable

changeset 5976:1ee9236cc224

Merge after removing dependency on linux-2.6.11 source tree
author djm@kirby.fc.hp.com
date Mon Aug 08 12:21:23 2005 -0700 (2005-08-08)
parents be8fe9b3987c 0380b4cc3c1a
children 88bfc84c5a75
files xen/arch/ia64/Makefile xen/arch/ia64/Rules.mk xen/arch/ia64/linux-xen/efi.c xen/arch/ia64/linux-xen/entry.S xen/arch/ia64/linux-xen/entry.h xen/arch/ia64/linux-xen/head.S xen/arch/ia64/linux-xen/irq_ia64.c xen/arch/ia64/linux-xen/mm_contig.c xen/arch/ia64/linux-xen/pal.S xen/arch/ia64/linux-xen/setup.c xen/arch/ia64/linux-xen/time.c xen/arch/ia64/linux-xen/tlb.c xen/arch/ia64/linux-xen/unaligned.c xen/arch/ia64/linux/cmdline.c xen/arch/ia64/linux/efi_stub.S xen/arch/ia64/linux/extable.c xen/arch/ia64/linux/hpsim.S xen/arch/ia64/linux/ia64_ksyms.c xen/arch/ia64/linux/irq_lsapic.c xen/arch/ia64/linux/lib/Makefile xen/arch/ia64/linux/lib/bitop.c xen/arch/ia64/linux/lib/carta_random.S xen/arch/ia64/linux/lib/checksum.c xen/arch/ia64/linux/lib/clear_page.S xen/arch/ia64/linux/lib/clear_user.S xen/arch/ia64/linux/lib/copy_page.S xen/arch/ia64/linux/lib/copy_page_mck.S xen/arch/ia64/linux/lib/copy_user.S xen/arch/ia64/linux/lib/csum_partial_copy.c xen/arch/ia64/linux/lib/dec_and_lock.c xen/arch/ia64/linux/lib/do_csum.S xen/arch/ia64/linux/lib/flush.S xen/arch/ia64/linux/lib/idiv32.S xen/arch/ia64/linux/lib/idiv64.S xen/arch/ia64/linux/lib/io.c xen/arch/ia64/linux/lib/ip_fast_csum.S xen/arch/ia64/linux/lib/memcpy.S xen/arch/ia64/linux/lib/memcpy_mck.S xen/arch/ia64/linux/lib/memset.S xen/arch/ia64/linux/lib/strlen.S xen/arch/ia64/linux/lib/strlen_user.S xen/arch/ia64/linux/lib/strncpy_from_user.S xen/arch/ia64/linux/lib/strnlen_user.S xen/arch/ia64/linux/lib/xor.S xen/arch/ia64/linux/linuxextable.c xen/arch/ia64/linux/machvec.c xen/arch/ia64/linux/minstate.h xen/arch/ia64/linux/patch.c xen/arch/ia64/linux/pcdp.h xen/arch/ia64/linux/sal.c xen/arch/ia64/tools/mkbuildtree xen/arch/ia64/xen.lds.S xen/include/asm-ia64/linux-xen/asm/gcc_intrin.h xen/include/asm-ia64/linux-xen/asm/hpsim_ssc.h xen/include/asm-ia64/linux-xen/asm/ia64regs.h xen/include/asm-ia64/linux-xen/asm/io.h xen/include/asm-ia64/linux-xen/asm/kregs.h xen/include/asm-ia64/linux-xen/asm/mca_asm.h xen/include/asm-ia64/linux-xen/asm/page.h xen/include/asm-ia64/linux-xen/asm/pal.h xen/include/asm-ia64/linux-xen/asm/pgalloc.h xen/include/asm-ia64/linux-xen/asm/processor.h xen/include/asm-ia64/linux-xen/asm/ptrace.h xen/include/asm-ia64/linux-xen/asm/sn/sn_sal.h xen/include/asm-ia64/linux-xen/asm/system.h xen/include/asm-ia64/linux-xen/asm/types.h xen/include/asm-ia64/linux-xen/asm/uaccess.h xen/include/asm-ia64/linux-xen/linux/cpumask.h xen/include/asm-ia64/linux-xen/linux/hardirq.h xen/include/asm-ia64/linux-xen/linux/interrupt.h xen/include/asm-ia64/linux/asm-generic/bug.h xen/include/asm-ia64/linux/asm-generic/div64.h xen/include/asm-ia64/linux/asm-generic/errno-base.h xen/include/asm-ia64/linux/asm-generic/errno.h xen/include/asm-ia64/linux/asm-generic/ide_iops.h xen/include/asm-ia64/linux/asm-generic/iomap.h xen/include/asm-ia64/linux/asm-generic/pci-dma-compat.h xen/include/asm-ia64/linux/asm-generic/pci.h xen/include/asm-ia64/linux/asm-generic/pgtable-nopud.h xen/include/asm-ia64/linux/asm-generic/pgtable.h xen/include/asm-ia64/linux/asm-generic/sections.h xen/include/asm-ia64/linux/asm-generic/topology.h xen/include/asm-ia64/linux/asm-generic/vmlinux.lds.h xen/include/asm-ia64/linux/asm/acpi.h xen/include/asm-ia64/linux/asm/asmmacro.h xen/include/asm-ia64/linux/asm/atomic.h xen/include/asm-ia64/linux/asm/bitops.h xen/include/asm-ia64/linux/asm/break.h xen/include/asm-ia64/linux/asm/bug.h xen/include/asm-ia64/linux/asm/byteorder.h xen/include/asm-ia64/linux/asm/cache.h xen/include/asm-ia64/linux/asm/cacheflush.h xen/include/asm-ia64/linux/asm/checksum.h xen/include/asm-ia64/linux/asm/current.h xen/include/asm-ia64/linux/asm/delay.h xen/include/asm-ia64/linux/asm/desc.h xen/include/asm-ia64/linux/asm/div64.h xen/include/asm-ia64/linux/asm/dma-mapping.h xen/include/asm-ia64/linux/asm/dma.h xen/include/asm-ia64/linux/asm/errno.h xen/include/asm-ia64/linux/asm/fpu.h xen/include/asm-ia64/linux/asm/hardirq.h xen/include/asm-ia64/linux/asm/hdreg.h xen/include/asm-ia64/linux/asm/hw_irq.h xen/include/asm-ia64/linux/asm/ia32.h xen/include/asm-ia64/linux/asm/intrinsics.h xen/include/asm-ia64/linux/asm/ioctl.h xen/include/asm-ia64/linux/asm/irq.h xen/include/asm-ia64/linux/asm/linkage.h xen/include/asm-ia64/linux/asm/machvec.h xen/include/asm-ia64/linux/asm/machvec_hpsim.h xen/include/asm-ia64/linux/asm/mca.h xen/include/asm-ia64/linux/asm/meminit.h xen/include/asm-ia64/linux/asm/mman.h xen/include/asm-ia64/linux/asm/module.h xen/include/asm-ia64/linux/asm/numa.h xen/include/asm-ia64/linux/asm/param.h xen/include/asm-ia64/linux/asm/patch.h xen/include/asm-ia64/linux/asm/pci.h xen/include/asm-ia64/linux/asm/pdb.h xen/include/asm-ia64/linux/asm/percpu.h xen/include/asm-ia64/linux/asm/pgtable.h xen/include/asm-ia64/linux/asm/ptrace_offsets.h xen/include/asm-ia64/linux/asm/rse.h xen/include/asm-ia64/linux/asm/rwsem.h xen/include/asm-ia64/linux/asm/sal.h xen/include/asm-ia64/linux/asm/scatterlist.h xen/include/asm-ia64/linux/asm/sections.h xen/include/asm-ia64/linux/asm/semaphore.h xen/include/asm-ia64/linux/asm/setup.h xen/include/asm-ia64/linux/asm/sigcontext.h xen/include/asm-ia64/linux/asm/signal.h xen/include/asm-ia64/linux/asm/smp.h xen/include/asm-ia64/linux/asm/sn/arch.h xen/include/asm-ia64/linux/asm/sn/geo.h xen/include/asm-ia64/linux/asm/sn/nodepda.h xen/include/asm-ia64/linux/asm/sn/sn_cpuid.h xen/include/asm-ia64/linux/asm/spinlock.h xen/include/asm-ia64/linux/asm/string.h xen/include/asm-ia64/linux/asm/thread_info.h xen/include/asm-ia64/linux/asm/timex.h xen/include/asm-ia64/linux/asm/tlbflush.h xen/include/asm-ia64/linux/asm/topology.h xen/include/asm-ia64/linux/asm/unaligned.h xen/include/asm-ia64/linux/asm/unistd.h xen/include/asm-ia64/linux/asm/unwind.h xen/include/asm-ia64/linux/asm/ustack.h xen/include/asm-ia64/linux/bcd.h xen/include/asm-ia64/linux/bitmap.h xen/include/asm-ia64/linux/bitops.h xen/include/asm-ia64/linux/bootmem.h xen/include/asm-ia64/linux/byteorder/generic.h xen/include/asm-ia64/linux/byteorder/little_endian.h xen/include/asm-ia64/linux/byteorder/swab.h xen/include/asm-ia64/linux/cpu.h xen/include/asm-ia64/linux/device.h xen/include/asm-ia64/linux/dma-mapping.h xen/include/asm-ia64/linux/efi.h xen/include/asm-ia64/linux/err.h xen/include/asm-ia64/linux/file.h xen/include/asm-ia64/linux/gfp.h xen/include/asm-ia64/linux/initrd.h xen/include/asm-ia64/linux/ioport.h xen/include/asm-ia64/linux/jiffies.h xen/include/asm-ia64/linux/kernel_stat.h xen/include/asm-ia64/linux/kmalloc_sizes.h xen/include/asm-ia64/linux/linkage.h xen/include/asm-ia64/linux/linuxtime.h xen/include/asm-ia64/linux/mmzone.h xen/include/asm-ia64/linux/module.h xen/include/asm-ia64/linux/numa.h xen/include/asm-ia64/linux/page-flags.h xen/include/asm-ia64/linux/percpu.h xen/include/asm-ia64/linux/preempt.h xen/include/asm-ia64/linux/proc_fs.h xen/include/asm-ia64/linux/profile.h xen/include/asm-ia64/linux/ptrace.h xen/include/asm-ia64/linux/random.h xen/include/asm-ia64/linux/rbtree.h xen/include/asm-ia64/linux/rtc.h xen/include/asm-ia64/linux/rwsem.h xen/include/asm-ia64/linux/seq_file.h xen/include/asm-ia64/linux/seqlock.h xen/include/asm-ia64/linux/serial.h xen/include/asm-ia64/linux/serial_core.h xen/include/asm-ia64/linux/signal.h xen/include/asm-ia64/linux/slab.h xen/include/asm-ia64/linux/smp_lock.h xen/include/asm-ia64/linux/stddef.h xen/include/asm-ia64/linux/swap.h xen/include/asm-ia64/linux/thread_info.h xen/include/asm-ia64/linux/threads.h xen/include/asm-ia64/linux/timex.h xen/include/asm-ia64/linux/topology.h xen/include/asm-ia64/linux/tty.h xen/include/asm-ia64/linux/wait.h
line diff
     1.1 --- a/xen/arch/ia64/Makefile	Tue Aug 02 15:38:45 2005 -0700
     1.2 +++ b/xen/arch/ia64/Makefile	Mon Aug 08 12:21:23 2005 -0700
     1.3 @@ -1,5 +1,7 @@
     1.4  include $(BASEDIR)/Rules.mk
     1.5  
     1.6 +VPATH = linux linux-xen
     1.7 +
     1.8  # libs-y	+= arch/ia64/lib/lib.a
     1.9  
    1.10  OBJS = xensetup.o setup.o time.o irq.o ia64_ksyms.o process.o smp.o \
    1.11 @@ -75,7 +77,7 @@ xen.lds.s: xen.lds.S
    1.12  		-o xen.lds.s xen.lds.S
    1.13  
    1.14  ia64lib.o:
    1.15 -	$(MAKE) -C lib && cp lib/ia64lib.o .
    1.16 +	$(MAKE) -C linux/lib && cp linux/lib/ia64lib.o .
    1.17  
    1.18  clean:
    1.19  	rm -f *.o *~ core  xen.lds.s $(BASEDIR)/include/asm-ia64/.offsets.h.stamp asm-offsets.s
     2.1 --- a/xen/arch/ia64/Rules.mk	Tue Aug 02 15:38:45 2005 -0700
     2.2 +++ b/xen/arch/ia64/Rules.mk	Mon Aug 08 12:21:23 2005 -0700
     2.3 @@ -6,14 +6,21 @@ ifneq ($(COMPILE_ARCH),$(TARGET_ARCH))
     2.4  CROSS_COMPILE ?= /usr/local/sp_env/v2.2.5/i686/bin/ia64-unknown-linux-
     2.5  endif
     2.6  AFLAGS  += -D__ASSEMBLY__
     2.7 -CPPFLAGS  += -I$(BASEDIR)/include -I$(BASEDIR)/include/asm-ia64
     2.8 +CPPFLAGS  += -I$(BASEDIR)/include -I$(BASEDIR)/include/asm-ia64 	\
     2.9 +             -I$(BASEDIR)/include/asm-ia64/linux 			\
    2.10 +	     -I$(BASEDIR)/include/asm-ia64/linux-xen 			\
    2.11 +             -I$(BASEDIR)/arch/ia64/linux -I$(BASEDIR)/arch/ia64/linux-xen
    2.12 +
    2.13  CFLAGS  := -nostdinc -fno-builtin -fno-common -fno-strict-aliasing
    2.14  #CFLAGS  += -O3		# -O3 over-inlines making debugging tough!
    2.15  CFLAGS  += -O2		# but no optimization causes compile errors!
    2.16  #CFLAGS  += -iwithprefix include -Wall -DMONITOR_BASE=$(MONITOR_BASE)
    2.17  CFLAGS  += -iwithprefix include -Wall
    2.18  CFLAGS  += -fomit-frame-pointer -I$(BASEDIR)/include -D__KERNEL__
    2.19 -CFLAGS  += -I$(BASEDIR)/include/asm-ia64
    2.20 +CFLAGS  += -I$(BASEDIR)/include/asm-ia64 -I$(BASEDIR)/include/asm-ia64/linux \
    2.21 +           -I$(BASEDIR)/include/asm-ia64/linux 				\
    2.22 +           -I$(BASEDIR)/include/asm-ia64/linux-xen 			\
    2.23 +           -I$(BASEDIR)/arch/ia64/linux -I$(BASEDIR)/arch/ia64/linux-xen
    2.24  CFLAGS  += -Wno-pointer-arith -Wredundant-decls
    2.25  CFLAGS  += -DIA64 -DXEN -DLINUX_2_6
    2.26  CFLAGS	+= -ffixed-r13 -mfixed-range=f12-f15,f32-f127
     3.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     3.2 +++ b/xen/arch/ia64/linux-xen/efi.c	Mon Aug 08 12:21:23 2005 -0700
     3.3 @@ -0,0 +1,866 @@
     3.4 +/*
     3.5 + * Extensible Firmware Interface
     3.6 + *
     3.7 + * Based on Extensible Firmware Interface Specification version 0.9 April 30, 1999
     3.8 + *
     3.9 + * Copyright (C) 1999 VA Linux Systems
    3.10 + * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
    3.11 + * Copyright (C) 1999-2003 Hewlett-Packard Co.
    3.12 + *	David Mosberger-Tang <davidm@hpl.hp.com>
    3.13 + *	Stephane Eranian <eranian@hpl.hp.com>
    3.14 + *
    3.15 + * All EFI Runtime Services are not implemented yet as EFI only
    3.16 + * supports physical mode addressing on SoftSDV. This is to be fixed
    3.17 + * in a future version.  --drummond 1999-07-20
    3.18 + *
    3.19 + * Implemented EFI runtime services and virtual mode calls.  --davidm
    3.20 + *
    3.21 + * Goutham Rao: <goutham.rao@intel.com>
    3.22 + *	Skip non-WB memory and ignore empty memory ranges.
    3.23 + */
    3.24 +#include <linux/config.h>
    3.25 +#include <linux/module.h>
    3.26 +#include <linux/kernel.h>
    3.27 +#include <linux/init.h>
    3.28 +#include <linux/types.h>
    3.29 +#include <linux/time.h>
    3.30 +#include <linux/efi.h>
    3.31 +
    3.32 +#include <asm/io.h>
    3.33 +#include <asm/kregs.h>
    3.34 +#include <asm/meminit.h>
    3.35 +#include <asm/pgtable.h>
    3.36 +#include <asm/processor.h>
    3.37 +#include <asm/mca.h>
    3.38 +
    3.39 +#define EFI_DEBUG	0
    3.40 +
    3.41 +extern efi_status_t efi_call_phys (void *, ...);
    3.42 +
    3.43 +struct efi efi;
    3.44 +EXPORT_SYMBOL(efi);
    3.45 +static efi_runtime_services_t *runtime;
    3.46 +static unsigned long mem_limit = ~0UL, max_addr = ~0UL;
    3.47 +
    3.48 +#define efi_call_virt(f, args...)	(*(f))(args)
    3.49 +
    3.50 +#define STUB_GET_TIME(prefix, adjust_arg)							  \
    3.51 +static efi_status_t										  \
    3.52 +prefix##_get_time (efi_time_t *tm, efi_time_cap_t *tc)						  \
    3.53 +{												  \
    3.54 +	struct ia64_fpreg fr[6];								  \
    3.55 +	efi_time_cap_t *atc = NULL;								  \
    3.56 +	efi_status_t ret;									  \
    3.57 +												  \
    3.58 +	if (tc)											  \
    3.59 +		atc = adjust_arg(tc);								  \
    3.60 +	ia64_save_scratch_fpregs(fr);								  \
    3.61 +	ret = efi_call_##prefix((efi_get_time_t *) __va(runtime->get_time), adjust_arg(tm), atc); \
    3.62 +	ia64_load_scratch_fpregs(fr);								  \
    3.63 +	return ret;										  \
    3.64 +}
    3.65 +
    3.66 +#define STUB_SET_TIME(prefix, adjust_arg)							\
    3.67 +static efi_status_t										\
    3.68 +prefix##_set_time (efi_time_t *tm)								\
    3.69 +{												\
    3.70 +	struct ia64_fpreg fr[6];								\
    3.71 +	efi_status_t ret;									\
    3.72 +												\
    3.73 +	ia64_save_scratch_fpregs(fr);								\
    3.74 +	ret = efi_call_##prefix((efi_set_time_t *) __va(runtime->set_time), adjust_arg(tm));	\
    3.75 +	ia64_load_scratch_fpregs(fr);								\
    3.76 +	return ret;										\
    3.77 +}
    3.78 +
    3.79 +#define STUB_GET_WAKEUP_TIME(prefix, adjust_arg)						\
    3.80 +static efi_status_t										\
    3.81 +prefix##_get_wakeup_time (efi_bool_t *enabled, efi_bool_t *pending, efi_time_t *tm)		\
    3.82 +{												\
    3.83 +	struct ia64_fpreg fr[6];								\
    3.84 +	efi_status_t ret;									\
    3.85 +												\
    3.86 +	ia64_save_scratch_fpregs(fr);								\
    3.87 +	ret = efi_call_##prefix((efi_get_wakeup_time_t *) __va(runtime->get_wakeup_time),	\
    3.88 +				adjust_arg(enabled), adjust_arg(pending), adjust_arg(tm));	\
    3.89 +	ia64_load_scratch_fpregs(fr);								\
    3.90 +	return ret;										\
    3.91 +}
    3.92 +
    3.93 +#define STUB_SET_WAKEUP_TIME(prefix, adjust_arg)						\
    3.94 +static efi_status_t										\
    3.95 +prefix##_set_wakeup_time (efi_bool_t enabled, efi_time_t *tm)					\
    3.96 +{												\
    3.97 +	struct ia64_fpreg fr[6];								\
    3.98 +	efi_time_t *atm = NULL;									\
    3.99 +	efi_status_t ret;									\
   3.100 +												\
   3.101 +	if (tm)											\
   3.102 +		atm = adjust_arg(tm);								\
   3.103 +	ia64_save_scratch_fpregs(fr);								\
   3.104 +	ret = efi_call_##prefix((efi_set_wakeup_time_t *) __va(runtime->set_wakeup_time),	\
   3.105 +				enabled, atm);							\
   3.106 +	ia64_load_scratch_fpregs(fr);								\
   3.107 +	return ret;										\
   3.108 +}
   3.109 +
   3.110 +#define STUB_GET_VARIABLE(prefix, adjust_arg)						\
   3.111 +static efi_status_t									\
   3.112 +prefix##_get_variable (efi_char16_t *name, efi_guid_t *vendor, u32 *attr,		\
   3.113 +		       unsigned long *data_size, void *data)				\
   3.114 +{											\
   3.115 +	struct ia64_fpreg fr[6];							\
   3.116 +	u32 *aattr = NULL;									\
   3.117 +	efi_status_t ret;								\
   3.118 +											\
   3.119 +	if (attr)									\
   3.120 +		aattr = adjust_arg(attr);						\
   3.121 +	ia64_save_scratch_fpregs(fr);							\
   3.122 +	ret = efi_call_##prefix((efi_get_variable_t *) __va(runtime->get_variable),	\
   3.123 +				adjust_arg(name), adjust_arg(vendor), aattr,		\
   3.124 +				adjust_arg(data_size), adjust_arg(data));		\
   3.125 +	ia64_load_scratch_fpregs(fr);							\
   3.126 +	return ret;									\
   3.127 +}
   3.128 +
   3.129 +#define STUB_GET_NEXT_VARIABLE(prefix, adjust_arg)						\
   3.130 +static efi_status_t										\
   3.131 +prefix##_get_next_variable (unsigned long *name_size, efi_char16_t *name, efi_guid_t *vendor)	\
   3.132 +{												\
   3.133 +	struct ia64_fpreg fr[6];								\
   3.134 +	efi_status_t ret;									\
   3.135 +												\
   3.136 +	ia64_save_scratch_fpregs(fr);								\
   3.137 +	ret = efi_call_##prefix((efi_get_next_variable_t *) __va(runtime->get_next_variable),	\
   3.138 +				adjust_arg(name_size), adjust_arg(name), adjust_arg(vendor));	\
   3.139 +	ia64_load_scratch_fpregs(fr);								\
   3.140 +	return ret;										\
   3.141 +}
   3.142 +
   3.143 +#define STUB_SET_VARIABLE(prefix, adjust_arg)						\
   3.144 +static efi_status_t									\
   3.145 +prefix##_set_variable (efi_char16_t *name, efi_guid_t *vendor, unsigned long attr,	\
   3.146 +		       unsigned long data_size, void *data)				\
   3.147 +{											\
   3.148 +	struct ia64_fpreg fr[6];							\
   3.149 +	efi_status_t ret;								\
   3.150 +											\
   3.151 +	ia64_save_scratch_fpregs(fr);							\
   3.152 +	ret = efi_call_##prefix((efi_set_variable_t *) __va(runtime->set_variable),	\
   3.153 +				adjust_arg(name), adjust_arg(vendor), attr, data_size,	\
   3.154 +				adjust_arg(data));					\
   3.155 +	ia64_load_scratch_fpregs(fr);							\
   3.156 +	return ret;									\
   3.157 +}
   3.158 +
   3.159 +#define STUB_GET_NEXT_HIGH_MONO_COUNT(prefix, adjust_arg)					\
   3.160 +static efi_status_t										\
   3.161 +prefix##_get_next_high_mono_count (u32 *count)							\
   3.162 +{												\
   3.163 +	struct ia64_fpreg fr[6];								\
   3.164 +	efi_status_t ret;									\
   3.165 +												\
   3.166 +	ia64_save_scratch_fpregs(fr);								\
   3.167 +	ret = efi_call_##prefix((efi_get_next_high_mono_count_t *)				\
   3.168 +				__va(runtime->get_next_high_mono_count), adjust_arg(count));	\
   3.169 +	ia64_load_scratch_fpregs(fr);								\
   3.170 +	return ret;										\
   3.171 +}
   3.172 +
   3.173 +#define STUB_RESET_SYSTEM(prefix, adjust_arg)					\
   3.174 +static void									\
   3.175 +prefix##_reset_system (int reset_type, efi_status_t status,			\
   3.176 +		       unsigned long data_size, efi_char16_t *data)		\
   3.177 +{										\
   3.178 +	struct ia64_fpreg fr[6];						\
   3.179 +	efi_char16_t *adata = NULL;						\
   3.180 +										\
   3.181 +	if (data)								\
   3.182 +		adata = adjust_arg(data);					\
   3.183 +										\
   3.184 +	ia64_save_scratch_fpregs(fr);						\
   3.185 +	efi_call_##prefix((efi_reset_system_t *) __va(runtime->reset_system),	\
   3.186 +			  reset_type, status, data_size, adata);		\
   3.187 +	/* should not return, but just in case... */				\
   3.188 +	ia64_load_scratch_fpregs(fr);						\
   3.189 +}
   3.190 +
   3.191 +#define phys_ptr(arg)	((__typeof__(arg)) ia64_tpa(arg))
   3.192 +
   3.193 +STUB_GET_TIME(phys, phys_ptr)
   3.194 +STUB_SET_TIME(phys, phys_ptr)
   3.195 +STUB_GET_WAKEUP_TIME(phys, phys_ptr)
   3.196 +STUB_SET_WAKEUP_TIME(phys, phys_ptr)
   3.197 +STUB_GET_VARIABLE(phys, phys_ptr)
   3.198 +STUB_GET_NEXT_VARIABLE(phys, phys_ptr)
   3.199 +STUB_SET_VARIABLE(phys, phys_ptr)
   3.200 +STUB_GET_NEXT_HIGH_MONO_COUNT(phys, phys_ptr)
   3.201 +STUB_RESET_SYSTEM(phys, phys_ptr)
   3.202 +
   3.203 +#define id(arg)	arg
   3.204 +
   3.205 +STUB_GET_TIME(virt, id)
   3.206 +STUB_SET_TIME(virt, id)
   3.207 +STUB_GET_WAKEUP_TIME(virt, id)
   3.208 +STUB_SET_WAKEUP_TIME(virt, id)
   3.209 +STUB_GET_VARIABLE(virt, id)
   3.210 +STUB_GET_NEXT_VARIABLE(virt, id)
   3.211 +STUB_SET_VARIABLE(virt, id)
   3.212 +STUB_GET_NEXT_HIGH_MONO_COUNT(virt, id)
   3.213 +STUB_RESET_SYSTEM(virt, id)
   3.214 +
   3.215 +void
   3.216 +efi_gettimeofday (struct timespec *ts)
   3.217 +{
   3.218 +	efi_time_t tm;
   3.219 +
   3.220 +	memset(ts, 0, sizeof(ts));
   3.221 +	if ((*efi.get_time)(&tm, NULL) != EFI_SUCCESS)
   3.222 +		return;
   3.223 +
   3.224 +	ts->tv_sec = mktime(tm.year, tm.month, tm.day, tm.hour, tm.minute, tm.second);
   3.225 +	ts->tv_nsec = tm.nanosecond;
   3.226 +}
   3.227 +
   3.228 +static int
   3.229 +is_available_memory (efi_memory_desc_t *md)
   3.230 +{
   3.231 +	if (!(md->attribute & EFI_MEMORY_WB))
   3.232 +		return 0;
   3.233 +
   3.234 +	switch (md->type) {
   3.235 +	      case EFI_LOADER_CODE:
   3.236 +	      case EFI_LOADER_DATA:
   3.237 +	      case EFI_BOOT_SERVICES_CODE:
   3.238 +	      case EFI_BOOT_SERVICES_DATA:
   3.239 +	      case EFI_CONVENTIONAL_MEMORY:
   3.240 +		return 1;
   3.241 +	}
   3.242 +	return 0;
   3.243 +}
   3.244 +
   3.245 +/*
   3.246 + * Trim descriptor MD so its starts at address START_ADDR.  If the descriptor covers
   3.247 + * memory that is normally available to the kernel, issue a warning that some memory
   3.248 + * is being ignored.
   3.249 + */
   3.250 +static void
   3.251 +trim_bottom (efi_memory_desc_t *md, u64 start_addr)
   3.252 +{
   3.253 +	u64 num_skipped_pages;
   3.254 +
   3.255 +	if (md->phys_addr >= start_addr || !md->num_pages)
   3.256 +		return;
   3.257 +
   3.258 +	num_skipped_pages = (start_addr - md->phys_addr) >> EFI_PAGE_SHIFT;
   3.259 +	if (num_skipped_pages > md->num_pages)
   3.260 +		num_skipped_pages = md->num_pages;
   3.261 +
   3.262 +	if (is_available_memory(md))
   3.263 +		printk(KERN_NOTICE "efi.%s: ignoring %luKB of memory at 0x%lx due to granule hole "
   3.264 +		       "at 0x%lx\n", __FUNCTION__,
   3.265 +		       (num_skipped_pages << EFI_PAGE_SHIFT) >> 10,
   3.266 +		       md->phys_addr, start_addr - IA64_GRANULE_SIZE);
   3.267 +	/*
   3.268 +	 * NOTE: Don't set md->phys_addr to START_ADDR because that could cause the memory
   3.269 +	 * descriptor list to become unsorted.  In such a case, md->num_pages will be
   3.270 +	 * zero, so the Right Thing will happen.
   3.271 +	 */
   3.272 +	md->phys_addr += num_skipped_pages << EFI_PAGE_SHIFT;
   3.273 +	md->num_pages -= num_skipped_pages;
   3.274 +}
   3.275 +
   3.276 +static void
   3.277 +trim_top (efi_memory_desc_t *md, u64 end_addr)
   3.278 +{
   3.279 +	u64 num_dropped_pages, md_end_addr;
   3.280 +
   3.281 +	md_end_addr = md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT);
   3.282 +
   3.283 +	if (md_end_addr <= end_addr || !md->num_pages)
   3.284 +		return;
   3.285 +
   3.286 +	num_dropped_pages = (md_end_addr - end_addr) >> EFI_PAGE_SHIFT;
   3.287 +	if (num_dropped_pages > md->num_pages)
   3.288 +		num_dropped_pages = md->num_pages;
   3.289 +
   3.290 +	if (is_available_memory(md))
   3.291 +		printk(KERN_NOTICE "efi.%s: ignoring %luKB of memory at 0x%lx due to granule hole "
   3.292 +		       "at 0x%lx\n", __FUNCTION__,
   3.293 +		       (num_dropped_pages << EFI_PAGE_SHIFT) >> 10,
   3.294 +		       md->phys_addr, end_addr);
   3.295 +	md->num_pages -= num_dropped_pages;
   3.296 +}
   3.297 +
   3.298 +/*
   3.299 + * Walks the EFI memory map and calls CALLBACK once for each EFI memory descriptor that
   3.300 + * has memory that is available for OS use.
   3.301 + */
   3.302 +void
   3.303 +efi_memmap_walk (efi_freemem_callback_t callback, void *arg)
   3.304 +{
   3.305 +	int prev_valid = 0;
   3.306 +	struct range {
   3.307 +		u64 start;
   3.308 +		u64 end;
   3.309 +	} prev, curr;
   3.310 +	void *efi_map_start, *efi_map_end, *p, *q;
   3.311 +	efi_memory_desc_t *md, *check_md;
   3.312 +	u64 efi_desc_size, start, end, granule_addr, last_granule_addr, first_non_wb_addr = 0;
   3.313 +	unsigned long total_mem = 0;
   3.314 +
   3.315 +	efi_map_start = __va(ia64_boot_param->efi_memmap);
   3.316 +	efi_map_end   = efi_map_start + ia64_boot_param->efi_memmap_size;
   3.317 +	efi_desc_size = ia64_boot_param->efi_memdesc_size;
   3.318 +
   3.319 +	for (p = efi_map_start; p < efi_map_end; p += efi_desc_size) {
   3.320 +		md = p;
   3.321 +
   3.322 +		/* skip over non-WB memory descriptors; that's all we're interested in... */
   3.323 +		if (!(md->attribute & EFI_MEMORY_WB))
   3.324 +			continue;
   3.325 +
   3.326 +#ifdef XEN
   3.327 +// this works around a problem in the ski bootloader
   3.328 +{
   3.329 +		extern long running_on_sim;
   3.330 +		if (running_on_sim && md->type != EFI_CONVENTIONAL_MEMORY)
   3.331 +			continue;
   3.332 +}
   3.333 +// this is a temporary hack to avoid CONFIG_VIRTUAL_MEM_MAP
   3.334 +		if (md->phys_addr >= 0x100000000) continue;
   3.335 +#endif
   3.336 +		/*
   3.337 +		 * granule_addr is the base of md's first granule.
   3.338 +		 * [granule_addr - first_non_wb_addr) is guaranteed to
   3.339 +		 * be contiguous WB memory.
   3.340 +		 */
   3.341 +		granule_addr = GRANULEROUNDDOWN(md->phys_addr);
   3.342 +		first_non_wb_addr = max(first_non_wb_addr, granule_addr);
   3.343 +
   3.344 +		if (first_non_wb_addr < md->phys_addr) {
   3.345 +			trim_bottom(md, granule_addr + IA64_GRANULE_SIZE);
   3.346 +			granule_addr = GRANULEROUNDDOWN(md->phys_addr);
   3.347 +			first_non_wb_addr = max(first_non_wb_addr, granule_addr);
   3.348 +		}
   3.349 +
   3.350 +		for (q = p; q < efi_map_end; q += efi_desc_size) {
   3.351 +			check_md = q;
   3.352 +
   3.353 +			if ((check_md->attribute & EFI_MEMORY_WB) &&
   3.354 +			    (check_md->phys_addr == first_non_wb_addr))
   3.355 +				first_non_wb_addr += check_md->num_pages << EFI_PAGE_SHIFT;
   3.356 +			else
   3.357 +				break;		/* non-WB or hole */
   3.358 +		}
   3.359 +
   3.360 +		last_granule_addr = GRANULEROUNDDOWN(first_non_wb_addr);
   3.361 +		if (last_granule_addr < md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT))
   3.362 +			trim_top(md, last_granule_addr);
   3.363 +
   3.364 +		if (is_available_memory(md)) {
   3.365 +			if (md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT) >= max_addr) {
   3.366 +				if (md->phys_addr >= max_addr)
   3.367 +					continue;
   3.368 +				md->num_pages = (max_addr - md->phys_addr) >> EFI_PAGE_SHIFT;
   3.369 +				first_non_wb_addr = max_addr;
   3.370 +			}
   3.371 +
   3.372 +			if (total_mem >= mem_limit)
   3.373 +				continue;
   3.374 +
   3.375 +			if (total_mem + (md->num_pages << EFI_PAGE_SHIFT) > mem_limit) {
   3.376 +				unsigned long limit_addr = md->phys_addr;
   3.377 +
   3.378 +				limit_addr += mem_limit - total_mem;
   3.379 +				limit_addr = GRANULEROUNDDOWN(limit_addr);
   3.380 +
   3.381 +				if (md->phys_addr > limit_addr)
   3.382 +					continue;
   3.383 +
   3.384 +				md->num_pages = (limit_addr - md->phys_addr) >>
   3.385 +				                EFI_PAGE_SHIFT;
   3.386 +				first_non_wb_addr = max_addr = md->phys_addr +
   3.387 +				              (md->num_pages << EFI_PAGE_SHIFT);
   3.388 +			}
   3.389 +			total_mem += (md->num_pages << EFI_PAGE_SHIFT);
   3.390 +
   3.391 +			if (md->num_pages == 0)
   3.392 +				continue;
   3.393 +
   3.394 +			curr.start = PAGE_OFFSET + md->phys_addr;
   3.395 +			curr.end   = curr.start + (md->num_pages << EFI_PAGE_SHIFT);
   3.396 +
   3.397 +			if (!prev_valid) {
   3.398 +				prev = curr;
   3.399 +				prev_valid = 1;
   3.400 +			} else {
   3.401 +				if (curr.start < prev.start)
   3.402 +					printk(KERN_ERR "Oops: EFI memory table not ordered!\n");
   3.403 +
   3.404 +				if (prev.end == curr.start) {
   3.405 +					/* merge two consecutive memory ranges */
   3.406 +					prev.end = curr.end;
   3.407 +				} else {
   3.408 +					start = PAGE_ALIGN(prev.start);
   3.409 +					end = prev.end & PAGE_MASK;
   3.410 +					if ((end > start) && (*callback)(start, end, arg) < 0)
   3.411 +						return;
   3.412 +					prev = curr;
   3.413 +				}
   3.414 +			}
   3.415 +		}
   3.416 +	}
   3.417 +	if (prev_valid) {
   3.418 +		start = PAGE_ALIGN(prev.start);
   3.419 +		end = prev.end & PAGE_MASK;
   3.420 +		if (end > start)
   3.421 +			(*callback)(start, end, arg);
   3.422 +	}
   3.423 +}
   3.424 +
   3.425 +/*
   3.426 + * Look for the PAL_CODE region reported by EFI and maps it using an
   3.427 + * ITR to enable safe PAL calls in virtual mode.  See IA-64 Processor
   3.428 + * Abstraction Layer chapter 11 in ADAG
   3.429 + */
   3.430 +
   3.431 +void *
   3.432 +efi_get_pal_addr (void)
   3.433 +{
   3.434 +	void *efi_map_start, *efi_map_end, *p;
   3.435 +	efi_memory_desc_t *md;
   3.436 +	u64 efi_desc_size;
   3.437 +	int pal_code_count = 0;
   3.438 +	u64 vaddr, mask;
   3.439 +
   3.440 +	efi_map_start = __va(ia64_boot_param->efi_memmap);
   3.441 +	efi_map_end   = efi_map_start + ia64_boot_param->efi_memmap_size;
   3.442 +	efi_desc_size = ia64_boot_param->efi_memdesc_size;
   3.443 +
   3.444 +	for (p = efi_map_start; p < efi_map_end; p += efi_desc_size) {
   3.445 +		md = p;
   3.446 +		if (md->type != EFI_PAL_CODE)
   3.447 +			continue;
   3.448 +
   3.449 +		if (++pal_code_count > 1) {
   3.450 +			printk(KERN_ERR "Too many EFI Pal Code memory ranges, dropped @ %lx\n",
   3.451 +			       md->phys_addr);
   3.452 +			continue;
   3.453 +		}
   3.454 +		/*
   3.455 +		 * The only ITLB entry in region 7 that is used is the one installed by
   3.456 +		 * __start().  That entry covers a 64MB range.
   3.457 +		 */
   3.458 +		mask  = ~((1 << KERNEL_TR_PAGE_SHIFT) - 1);
   3.459 +		vaddr = PAGE_OFFSET + md->phys_addr;
   3.460 +
   3.461 +		/*
   3.462 +		 * We must check that the PAL mapping won't overlap with the kernel
   3.463 +		 * mapping.
   3.464 +		 *
   3.465 +		 * PAL code is guaranteed to be aligned on a power of 2 between 4k and
   3.466 +		 * 256KB and that only one ITR is needed to map it. This implies that the
   3.467 +		 * PAL code is always aligned on its size, i.e., the closest matching page
   3.468 +		 * size supported by the TLB. Therefore PAL code is guaranteed never to
   3.469 +		 * cross a 64MB unless it is bigger than 64MB (very unlikely!).  So for
   3.470 +		 * now the following test is enough to determine whether or not we need a
   3.471 +		 * dedicated ITR for the PAL code.
   3.472 +		 */
   3.473 +		if ((vaddr & mask) == (KERNEL_START & mask)) {
   3.474 +			printk(KERN_INFO "%s: no need to install ITR for PAL code\n",
   3.475 +			       __FUNCTION__);
   3.476 +			continue;
   3.477 +		}
   3.478 +
   3.479 +		if (md->num_pages << EFI_PAGE_SHIFT > IA64_GRANULE_SIZE)
   3.480 +			panic("Woah!  PAL code size bigger than a granule!");
   3.481 +
   3.482 +#if EFI_DEBUG
   3.483 +		mask  = ~((1 << IA64_GRANULE_SHIFT) - 1);
   3.484 +
   3.485 +		printk(KERN_INFO "CPU %d: mapping PAL code [0x%lx-0x%lx) into [0x%lx-0x%lx)\n",
   3.486 +			smp_processor_id(), md->phys_addr,
   3.487 +			md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT),
   3.488 +			vaddr & mask, (vaddr & mask) + IA64_GRANULE_SIZE);
   3.489 +#endif
   3.490 +		return __va(md->phys_addr);
   3.491 +	}
   3.492 +	printk(KERN_WARNING "%s: no PAL-code memory-descriptor found",
   3.493 +	       __FUNCTION__);
   3.494 +	return NULL;
   3.495 +}
   3.496 +
   3.497 +void
   3.498 +efi_map_pal_code (void)
   3.499 +{
   3.500 +	void *pal_vaddr = efi_get_pal_addr ();
   3.501 +	u64 psr;
   3.502 +
   3.503 +	if (!pal_vaddr)
   3.504 +		return;
   3.505 +
   3.506 +	/*
   3.507 +	 * Cannot write to CRx with PSR.ic=1
   3.508 +	 */
   3.509 +	psr = ia64_clear_ic();
   3.510 +	ia64_itr(0x1, IA64_TR_PALCODE, GRANULEROUNDDOWN((unsigned long) pal_vaddr),
   3.511 +		 pte_val(pfn_pte(__pa(pal_vaddr) >> PAGE_SHIFT, PAGE_KERNEL)),
   3.512 +		 IA64_GRANULE_SHIFT);
   3.513 +	ia64_set_psr(psr);		/* restore psr */
   3.514 +	ia64_srlz_i();
   3.515 +}
   3.516 +
   3.517 +void __init
   3.518 +efi_init (void)
   3.519 +{
   3.520 +	void *efi_map_start, *efi_map_end;
   3.521 +	efi_config_table_t *config_tables;
   3.522 +	efi_char16_t *c16;
   3.523 +	u64 efi_desc_size;
   3.524 +	char *cp, *end, vendor[100] = "unknown";
   3.525 +	extern char saved_command_line[];
   3.526 +	int i;
   3.527 +
   3.528 +	/* it's too early to be able to use the standard kernel command line support... */
   3.529 +	for (cp = saved_command_line; *cp; ) {
   3.530 +		if (memcmp(cp, "mem=", 4) == 0) {
   3.531 +			cp += 4;
   3.532 +			mem_limit = memparse(cp, &end);
   3.533 +			if (end != cp)
   3.534 +				break;
   3.535 +			cp = end;
   3.536 +		} else if (memcmp(cp, "max_addr=", 9) == 0) {
   3.537 +			cp += 9;
   3.538 +			max_addr = GRANULEROUNDDOWN(memparse(cp, &end));
   3.539 +			if (end != cp)
   3.540 +				break;
   3.541 +			cp = end;
   3.542 +		} else {
   3.543 +			while (*cp != ' ' && *cp)
   3.544 +				++cp;
   3.545 +			while (*cp == ' ')
   3.546 +				++cp;
   3.547 +		}
   3.548 +	}
   3.549 +	if (max_addr != ~0UL)
   3.550 +		printk(KERN_INFO "Ignoring memory above %luMB\n", max_addr >> 20);
   3.551 +
   3.552 +	efi.systab = __va(ia64_boot_param->efi_systab);
   3.553 +
   3.554 +	/*
   3.555 +	 * Verify the EFI Table
   3.556 +	 */
   3.557 +	if (efi.systab == NULL)
   3.558 +		panic("Woah! Can't find EFI system table.\n");
   3.559 +	if (efi.systab->hdr.signature != EFI_SYSTEM_TABLE_SIGNATURE)
   3.560 +		panic("Woah! EFI system table signature incorrect\n");
   3.561 +	if ((efi.systab->hdr.revision ^ EFI_SYSTEM_TABLE_REVISION) >> 16 != 0)
   3.562 +		printk(KERN_WARNING "Warning: EFI system table major version mismatch: "
   3.563 +		       "got %d.%02d, expected %d.%02d\n",
   3.564 +		       efi.systab->hdr.revision >> 16, efi.systab->hdr.revision & 0xffff,
   3.565 +		       EFI_SYSTEM_TABLE_REVISION >> 16, EFI_SYSTEM_TABLE_REVISION & 0xffff);
   3.566 +
   3.567 +	config_tables = __va(efi.systab->tables);
   3.568 +
   3.569 +	/* Show what we know for posterity */
   3.570 +	c16 = __va(efi.systab->fw_vendor);
   3.571 +	if (c16) {
   3.572 +		for (i = 0;i < (int) sizeof(vendor) && *c16; ++i)
   3.573 +			vendor[i] = *c16++;
   3.574 +		vendor[i] = '\0';
   3.575 +	}
   3.576 +
   3.577 +	printk(KERN_INFO "EFI v%u.%.02u by %s:",
   3.578 +	       efi.systab->hdr.revision >> 16, efi.systab->hdr.revision & 0xffff, vendor);
   3.579 +
   3.580 +	for (i = 0; i < (int) efi.systab->nr_tables; i++) {
   3.581 +		if (efi_guidcmp(config_tables[i].guid, MPS_TABLE_GUID) == 0) {
   3.582 +			efi.mps = __va(config_tables[i].table);
   3.583 +			printk(" MPS=0x%lx", config_tables[i].table);
   3.584 +		} else if (efi_guidcmp(config_tables[i].guid, ACPI_20_TABLE_GUID) == 0) {
   3.585 +			efi.acpi20 = __va(config_tables[i].table);
   3.586 +			printk(" ACPI 2.0=0x%lx", config_tables[i].table);
   3.587 +		} else if (efi_guidcmp(config_tables[i].guid, ACPI_TABLE_GUID) == 0) {
   3.588 +			efi.acpi = __va(config_tables[i].table);
   3.589 +			printk(" ACPI=0x%lx", config_tables[i].table);
   3.590 +		} else if (efi_guidcmp(config_tables[i].guid, SMBIOS_TABLE_GUID) == 0) {
   3.591 +			efi.smbios = __va(config_tables[i].table);
   3.592 +			printk(" SMBIOS=0x%lx", config_tables[i].table);
   3.593 +		} else if (efi_guidcmp(config_tables[i].guid, SAL_SYSTEM_TABLE_GUID) == 0) {
   3.594 +			efi.sal_systab = __va(config_tables[i].table);
   3.595 +			printk(" SALsystab=0x%lx", config_tables[i].table);
   3.596 +		} else if (efi_guidcmp(config_tables[i].guid, HCDP_TABLE_GUID) == 0) {
   3.597 +			efi.hcdp = __va(config_tables[i].table);
   3.598 +			printk(" HCDP=0x%lx", config_tables[i].table);
   3.599 +		}
   3.600 +	}
   3.601 +	printk("\n");
   3.602 +
   3.603 +	runtime = __va(efi.systab->runtime);
   3.604 +	efi.get_time = phys_get_time;
   3.605 +	efi.set_time = phys_set_time;
   3.606 +	efi.get_wakeup_time = phys_get_wakeup_time;
   3.607 +	efi.set_wakeup_time = phys_set_wakeup_time;
   3.608 +	efi.get_variable = phys_get_variable;
   3.609 +	efi.get_next_variable = phys_get_next_variable;
   3.610 +	efi.set_variable = phys_set_variable;
   3.611 +	efi.get_next_high_mono_count = phys_get_next_high_mono_count;
   3.612 +	efi.reset_system = phys_reset_system;
   3.613 +
   3.614 +	efi_map_start = __va(ia64_boot_param->efi_memmap);
   3.615 +	efi_map_end   = efi_map_start + ia64_boot_param->efi_memmap_size;
   3.616 +	efi_desc_size = ia64_boot_param->efi_memdesc_size;
   3.617 +
   3.618 +#if EFI_DEBUG
   3.619 +	/* print EFI memory map: */
   3.620 +	{
   3.621 +		efi_memory_desc_t *md;
   3.622 +		void *p;
   3.623 +
   3.624 +		for (i = 0, p = efi_map_start; p < efi_map_end; ++i, p += efi_desc_size) {
   3.625 +			md = p;
   3.626 +			printk("mem%02u: type=%u, attr=0x%lx, range=[0x%016lx-0x%016lx) (%luMB)\n",
   3.627 +			       i, md->type, md->attribute, md->phys_addr,
   3.628 +			       md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT),
   3.629 +			       md->num_pages >> (20 - EFI_PAGE_SHIFT));
   3.630 +		}
   3.631 +	}
   3.632 +#endif
   3.633 +
   3.634 +	efi_map_pal_code();
   3.635 +	efi_enter_virtual_mode();
   3.636 +}
   3.637 +
   3.638 +void
   3.639 +efi_enter_virtual_mode (void)
   3.640 +{
   3.641 +	void *efi_map_start, *efi_map_end, *p;
   3.642 +	efi_memory_desc_t *md;
   3.643 +	efi_status_t status;
   3.644 +	u64 efi_desc_size;
   3.645 +
   3.646 +	efi_map_start = __va(ia64_boot_param->efi_memmap);
   3.647 +	efi_map_end   = efi_map_start + ia64_boot_param->efi_memmap_size;
   3.648 +	efi_desc_size = ia64_boot_param->efi_memdesc_size;
   3.649 +
   3.650 +	for (p = efi_map_start; p < efi_map_end; p += efi_desc_size) {
   3.651 +		md = p;
   3.652 +		if (md->attribute & EFI_MEMORY_RUNTIME) {
   3.653 +			/*
   3.654 +			 * Some descriptors have multiple bits set, so the order of
   3.655 +			 * the tests is relevant.
   3.656 +			 */
   3.657 +			if (md->attribute & EFI_MEMORY_WB) {
   3.658 +				md->virt_addr = (u64) __va(md->phys_addr);
   3.659 +			} else if (md->attribute & EFI_MEMORY_UC) {
   3.660 +				md->virt_addr = (u64) ioremap(md->phys_addr, 0);
   3.661 +			} else if (md->attribute & EFI_MEMORY_WC) {
   3.662 +#if 0
   3.663 +				md->virt_addr = ia64_remap(md->phys_addr, (_PAGE_A | _PAGE_P
   3.664 +									   | _PAGE_D
   3.665 +									   | _PAGE_MA_WC
   3.666 +									   | _PAGE_PL_0
   3.667 +									   | _PAGE_AR_RW));
   3.668 +#else
   3.669 +				printk(KERN_INFO "EFI_MEMORY_WC mapping\n");
   3.670 +				md->virt_addr = (u64) ioremap(md->phys_addr, 0);
   3.671 +#endif
   3.672 +			} else if (md->attribute & EFI_MEMORY_WT) {
   3.673 +#if 0
   3.674 +				md->virt_addr = ia64_remap(md->phys_addr, (_PAGE_A | _PAGE_P
   3.675 +									   | _PAGE_D | _PAGE_MA_WT
   3.676 +									   | _PAGE_PL_0
   3.677 +									   | _PAGE_AR_RW));
   3.678 +#else
   3.679 +				printk(KERN_INFO "EFI_MEMORY_WT mapping\n");
   3.680 +				md->virt_addr = (u64) ioremap(md->phys_addr, 0);
   3.681 +#endif
   3.682 +			}
   3.683 +		}
   3.684 +	}
   3.685 +
   3.686 +	status = efi_call_phys(__va(runtime->set_virtual_address_map),
   3.687 +			       ia64_boot_param->efi_memmap_size,
   3.688 +			       efi_desc_size, ia64_boot_param->efi_memdesc_version,
   3.689 +			       ia64_boot_param->efi_memmap);
   3.690 +	if (status != EFI_SUCCESS) {
   3.691 +		printk(KERN_WARNING "warning: unable to switch EFI into virtual mode "
   3.692 +		       "(status=%lu)\n", status);
   3.693 +		return;
   3.694 +	}
   3.695 +
   3.696 +	/*
   3.697 +	 * Now that EFI is in virtual mode, we call the EFI functions more efficiently:
   3.698 +	 */
   3.699 +	efi.get_time = virt_get_time;
   3.700 +	efi.set_time = virt_set_time;
   3.701 +	efi.get_wakeup_time = virt_get_wakeup_time;
   3.702 +	efi.set_wakeup_time = virt_set_wakeup_time;
   3.703 +	efi.get_variable = virt_get_variable;
   3.704 +	efi.get_next_variable = virt_get_next_variable;
   3.705 +	efi.set_variable = virt_set_variable;
   3.706 +	efi.get_next_high_mono_count = virt_get_next_high_mono_count;
   3.707 +	efi.reset_system = virt_reset_system;
   3.708 +}
   3.709 +
   3.710 +/*
   3.711 + * Walk the EFI memory map looking for the I/O port range.  There can only be one entry of
   3.712 + * this type, other I/O port ranges should be described via ACPI.
   3.713 + */
   3.714 +u64
   3.715 +efi_get_iobase (void)
   3.716 +{
   3.717 +	void *efi_map_start, *efi_map_end, *p;
   3.718 +	efi_memory_desc_t *md;
   3.719 +	u64 efi_desc_size;
   3.720 +
   3.721 +	efi_map_start = __va(ia64_boot_param->efi_memmap);
   3.722 +	efi_map_end   = efi_map_start + ia64_boot_param->efi_memmap_size;
   3.723 +	efi_desc_size = ia64_boot_param->efi_memdesc_size;
   3.724 +
   3.725 +	for (p = efi_map_start; p < efi_map_end; p += efi_desc_size) {
   3.726 +		md = p;
   3.727 +		if (md->type == EFI_MEMORY_MAPPED_IO_PORT_SPACE) {
   3.728 +			if (md->attribute & EFI_MEMORY_UC)
   3.729 +				return md->phys_addr;
   3.730 +		}
   3.731 +	}
   3.732 +	return 0;
   3.733 +}
   3.734 +
   3.735 +#ifdef XEN
   3.736 +// variation of efi_get_iobase which returns entire memory descriptor
   3.737 +efi_memory_desc_t *
   3.738 +efi_get_io_md (void)
   3.739 +{
   3.740 +	void *efi_map_start, *efi_map_end, *p;
   3.741 +	efi_memory_desc_t *md;
   3.742 +	u64 efi_desc_size;
   3.743 +
   3.744 +	efi_map_start = __va(ia64_boot_param->efi_memmap);
   3.745 +	efi_map_end   = efi_map_start + ia64_boot_param->efi_memmap_size;
   3.746 +	efi_desc_size = ia64_boot_param->efi_memdesc_size;
   3.747 +
   3.748 +	for (p = efi_map_start; p < efi_map_end; p += efi_desc_size) {
   3.749 +		md = p;
   3.750 +		if (md->type == EFI_MEMORY_MAPPED_IO_PORT_SPACE) {
   3.751 +			if (md->attribute & EFI_MEMORY_UC)
   3.752 +				return md;
   3.753 +		}
   3.754 +	}
   3.755 +	return 0;
   3.756 +}
   3.757 +#endif
   3.758 +
   3.759 +u32
   3.760 +efi_mem_type (unsigned long phys_addr)
   3.761 +{
   3.762 +	void *efi_map_start, *efi_map_end, *p;
   3.763 +	efi_memory_desc_t *md;
   3.764 +	u64 efi_desc_size;
   3.765 +
   3.766 +	efi_map_start = __va(ia64_boot_param->efi_memmap);
   3.767 +	efi_map_end   = efi_map_start + ia64_boot_param->efi_memmap_size;
   3.768 +	efi_desc_size = ia64_boot_param->efi_memdesc_size;
   3.769 +
   3.770 +	for (p = efi_map_start; p < efi_map_end; p += efi_desc_size) {
   3.771 +		md = p;
   3.772 +
   3.773 +		if (phys_addr - md->phys_addr < (md->num_pages << EFI_PAGE_SHIFT))
   3.774 +			 return md->type;
   3.775 +	}
   3.776 +	return 0;
   3.777 +}
   3.778 +
   3.779 +u64
   3.780 +efi_mem_attributes (unsigned long phys_addr)
   3.781 +{
   3.782 +	void *efi_map_start, *efi_map_end, *p;
   3.783 +	efi_memory_desc_t *md;
   3.784 +	u64 efi_desc_size;
   3.785 +
   3.786 +	efi_map_start = __va(ia64_boot_param->efi_memmap);
   3.787 +	efi_map_end   = efi_map_start + ia64_boot_param->efi_memmap_size;
   3.788 +	efi_desc_size = ia64_boot_param->efi_memdesc_size;
   3.789 +
   3.790 +	for (p = efi_map_start; p < efi_map_end; p += efi_desc_size) {
   3.791 +		md = p;
   3.792 +
   3.793 +		if (phys_addr - md->phys_addr < (md->num_pages << EFI_PAGE_SHIFT))
   3.794 +			return md->attribute;
   3.795 +	}
   3.796 +	return 0;
   3.797 +}
   3.798 +EXPORT_SYMBOL(efi_mem_attributes);
   3.799 +
   3.800 +int
   3.801 +valid_phys_addr_range (unsigned long phys_addr, unsigned long *size)
   3.802 +{
   3.803 +	void *efi_map_start, *efi_map_end, *p;
   3.804 +	efi_memory_desc_t *md;
   3.805 +	u64 efi_desc_size;
   3.806 +
   3.807 +	efi_map_start = __va(ia64_boot_param->efi_memmap);
   3.808 +	efi_map_end   = efi_map_start + ia64_boot_param->efi_memmap_size;
   3.809 +	efi_desc_size = ia64_boot_param->efi_memdesc_size;
   3.810 +
   3.811 +	for (p = efi_map_start; p < efi_map_end; p += efi_desc_size) {
   3.812 +		md = p;
   3.813 +
   3.814 +		if (phys_addr - md->phys_addr < (md->num_pages << EFI_PAGE_SHIFT)) {
   3.815 +			if (!(md->attribute & EFI_MEMORY_WB))
   3.816 +				return 0;
   3.817 +
   3.818 +			if (*size > md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT) - phys_addr)
   3.819 +				*size = md->phys_addr + (md->num_pages << EFI_PAGE_SHIFT) - phys_addr;
   3.820 +			return 1;
   3.821 +		}
   3.822 +	}
   3.823 +	return 0;
   3.824 +}
   3.825 +
   3.826 +int __init
   3.827 +efi_uart_console_only(void)
   3.828 +{
   3.829 +	efi_status_t status;
   3.830 +	char *s, name[] = "ConOut";
   3.831 +	efi_guid_t guid = EFI_GLOBAL_VARIABLE_GUID;
   3.832 +	efi_char16_t *utf16, name_utf16[32];
   3.833 +	unsigned char data[1024];
   3.834 +	unsigned long size = sizeof(data);
   3.835 +	struct efi_generic_dev_path *hdr, *end_addr;
   3.836 +	int uart = 0;
   3.837 +
   3.838 +	/* Convert to UTF-16 */
   3.839 +	utf16 = name_utf16;
   3.840 +	s = name;
   3.841 +	while (*s)
   3.842 +		*utf16++ = *s++ & 0x7f;
   3.843 +	*utf16 = 0;
   3.844 +
   3.845 +	status = efi.get_variable(name_utf16, &guid, NULL, &size, data);
   3.846 +	if (status != EFI_SUCCESS) {
   3.847 +		printk(KERN_ERR "No EFI %s variable?\n", name);
   3.848 +		return 0;
   3.849 +	}
   3.850 +
   3.851 +	hdr = (struct efi_generic_dev_path *) data;
   3.852 +	end_addr = (struct efi_generic_dev_path *) ((u8 *) data + size);
   3.853 +	while (hdr < end_addr) {
   3.854 +		if (hdr->type == EFI_DEV_MSG &&
   3.855 +		    hdr->sub_type == EFI_DEV_MSG_UART)
   3.856 +			uart = 1;
   3.857 +		else if (hdr->type == EFI_DEV_END_PATH ||
   3.858 +			  hdr->type == EFI_DEV_END_PATH2) {
   3.859 +			if (!uart)
   3.860 +				return 0;
   3.861 +			if (hdr->sub_type == EFI_DEV_END_ENTIRE)
   3.862 +				return 1;
   3.863 +			uart = 0;
   3.864 +		}
   3.865 +		hdr = (struct efi_generic_dev_path *) ((u8 *) hdr + hdr->length);
   3.866 +	}
   3.867 +	printk(KERN_ERR "Malformed %s value\n", name);
   3.868 +	return 0;
   3.869 +}
     4.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     4.2 +++ b/xen/arch/ia64/linux-xen/entry.S	Mon Aug 08 12:21:23 2005 -0700
     4.3 @@ -0,0 +1,1653 @@
     4.4 +/*
     4.5 + * ia64/kernel/entry.S
     4.6 + *
     4.7 + * Kernel entry points.
     4.8 + *
     4.9 + * Copyright (C) 1998-2003, 2005 Hewlett-Packard Co
    4.10 + *	David Mosberger-Tang <davidm@hpl.hp.com>
    4.11 + * Copyright (C) 1999, 2002-2003
    4.12 + *	Asit Mallick <Asit.K.Mallick@intel.com>
    4.13 + * 	Don Dugger <Don.Dugger@intel.com>
    4.14 + *	Suresh Siddha <suresh.b.siddha@intel.com>
    4.15 + *	Fenghua Yu <fenghua.yu@intel.com>
    4.16 + * Copyright (C) 1999 VA Linux Systems
    4.17 + * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
    4.18 + */
    4.19 +/*
    4.20 + * ia64_switch_to now places correct virtual mapping in in TR2 for
    4.21 + * kernel stack. This allows us to handle interrupts without changing
    4.22 + * to physical mode.
    4.23 + *
    4.24 + * Jonathan Nicklin	<nicklin@missioncriticallinux.com>
    4.25 + * Patrick O'Rourke	<orourke@missioncriticallinux.com>
    4.26 + * 11/07/2000
    4.27 + */
    4.28 +/*
    4.29 + * Global (preserved) predicate usage on syscall entry/exit path:
    4.30 + *
    4.31 + *	pKStk:		See entry.h.
    4.32 + *	pUStk:		See entry.h.
    4.33 + *	pSys:		See entry.h.
    4.34 + *	pNonSys:	!pSys
    4.35 + */
    4.36 +
    4.37 +#include <linux/config.h>
    4.38 +
    4.39 +#include <asm/asmmacro.h>
    4.40 +#include <asm/cache.h>
    4.41 +#include <asm/errno.h>
    4.42 +#include <asm/kregs.h>
    4.43 +#include <asm/offsets.h>
    4.44 +#include <asm/pgtable.h>
    4.45 +#include <asm/percpu.h>
    4.46 +#include <asm/processor.h>
    4.47 +#include <asm/thread_info.h>
    4.48 +#include <asm/unistd.h>
    4.49 +
    4.50 +#include "minstate.h"
    4.51 +
    4.52 +#ifndef XEN
    4.53 +	/*
    4.54 +	 * execve() is special because in case of success, we need to
    4.55 +	 * setup a null register window frame.
    4.56 +	 */
    4.57 +ENTRY(ia64_execve)
    4.58 +	/*
    4.59 +	 * Allocate 8 input registers since ptrace() may clobber them
    4.60 +	 */
    4.61 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
    4.62 +	alloc loc1=ar.pfs,8,2,4,0
    4.63 +	mov loc0=rp
    4.64 +	.body
    4.65 +	mov out0=in0			// filename
    4.66 +	;;				// stop bit between alloc and call
    4.67 +	mov out1=in1			// argv
    4.68 +	mov out2=in2			// envp
    4.69 +	add out3=16,sp			// regs
    4.70 +	br.call.sptk.many rp=sys_execve
    4.71 +.ret0:
    4.72 +#ifdef CONFIG_IA32_SUPPORT
    4.73 +	/*
    4.74 +	 * Check if we're returning to ia32 mode. If so, we need to restore ia32 registers
    4.75 +	 * from pt_regs.
    4.76 +	 */
    4.77 +	adds r16=PT(CR_IPSR)+16,sp
    4.78 +	;;
    4.79 +	ld8 r16=[r16]
    4.80 +#endif
    4.81 +	cmp4.ge p6,p7=r8,r0
    4.82 +	mov ar.pfs=loc1			// restore ar.pfs
    4.83 +	sxt4 r8=r8			// return 64-bit result
    4.84 +	;;
    4.85 +	stf.spill [sp]=f0
    4.86 +(p6)	cmp.ne pKStk,pUStk=r0,r0	// a successful execve() lands us in user-mode...
    4.87 +	mov rp=loc0
    4.88 +(p6)	mov ar.pfs=r0			// clear ar.pfs on success
    4.89 +(p7)	br.ret.sptk.many rp
    4.90 +
    4.91 +	/*
    4.92 +	 * In theory, we'd have to zap this state only to prevent leaking of
    4.93 +	 * security sensitive state (e.g., if current->mm->dumpable is zero).  However,
    4.94 +	 * this executes in less than 20 cycles even on Itanium, so it's not worth
    4.95 +	 * optimizing for...).
    4.96 +	 */
    4.97 +	mov ar.unat=0; 		mov ar.lc=0
    4.98 +	mov r4=0;		mov f2=f0;		mov b1=r0
    4.99 +	mov r5=0;		mov f3=f0;		mov b2=r0
   4.100 +	mov r6=0;		mov f4=f0;		mov b3=r0
   4.101 +	mov r7=0;		mov f5=f0;		mov b4=r0
   4.102 +	ldf.fill f12=[sp];	mov f13=f0;		mov b5=r0
   4.103 +	ldf.fill f14=[sp];	ldf.fill f15=[sp];	mov f16=f0
   4.104 +	ldf.fill f17=[sp];	ldf.fill f18=[sp];	mov f19=f0
   4.105 +	ldf.fill f20=[sp];	ldf.fill f21=[sp];	mov f22=f0
   4.106 +	ldf.fill f23=[sp];	ldf.fill f24=[sp];	mov f25=f0
   4.107 +	ldf.fill f26=[sp];	ldf.fill f27=[sp];	mov f28=f0
   4.108 +	ldf.fill f29=[sp];	ldf.fill f30=[sp];	mov f31=f0
   4.109 +#ifdef CONFIG_IA32_SUPPORT
   4.110 +	tbit.nz p6,p0=r16, IA64_PSR_IS_BIT
   4.111 +	movl loc0=ia64_ret_from_ia32_execve
   4.112 +	;;
   4.113 +(p6)	mov rp=loc0
   4.114 +#endif
   4.115 +	br.ret.sptk.many rp
   4.116 +END(ia64_execve)
   4.117 +
   4.118 +/*
   4.119 + * sys_clone2(u64 flags, u64 ustack_base, u64 ustack_size, u64 parent_tidptr, u64 child_tidptr,
   4.120 + *	      u64 tls)
   4.121 + */
   4.122 +GLOBAL_ENTRY(sys_clone2)
   4.123 +	/*
   4.124 +	 * Allocate 8 input registers since ptrace() may clobber them
   4.125 +	 */
   4.126 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
   4.127 +	alloc r16=ar.pfs,8,2,6,0
   4.128 +	DO_SAVE_SWITCH_STACK
   4.129 +	adds r2=PT(R16)+IA64_SWITCH_STACK_SIZE+16,sp
   4.130 +	mov loc0=rp
   4.131 +	mov loc1=r16				// save ar.pfs across do_fork
   4.132 +	.body
   4.133 +	mov out1=in1
   4.134 +	mov out3=in2
   4.135 +	tbit.nz p6,p0=in0,CLONE_SETTLS_BIT
   4.136 +	mov out4=in3	// parent_tidptr: valid only w/CLONE_PARENT_SETTID
   4.137 +	;;
   4.138 +(p6)	st8 [r2]=in5				// store TLS in r16 for copy_thread()
   4.139 +	mov out5=in4	// child_tidptr:  valid only w/CLONE_CHILD_SETTID or CLONE_CHILD_CLEARTID
   4.140 +	adds out2=IA64_SWITCH_STACK_SIZE+16,sp	// out2 = &regs
   4.141 +	mov out0=in0				// out0 = clone_flags
   4.142 +	br.call.sptk.many rp=do_fork
   4.143 +.ret1:	.restore sp
   4.144 +	adds sp=IA64_SWITCH_STACK_SIZE,sp	// pop the switch stack
   4.145 +	mov ar.pfs=loc1
   4.146 +	mov rp=loc0
   4.147 +	br.ret.sptk.many rp
   4.148 +END(sys_clone2)
   4.149 +
   4.150 +/*
   4.151 + * sys_clone(u64 flags, u64 ustack_base, u64 parent_tidptr, u64 child_tidptr, u64 tls)
   4.152 + *	Deprecated.  Use sys_clone2() instead.
   4.153 + */
   4.154 +GLOBAL_ENTRY(sys_clone)
   4.155 +	/*
   4.156 +	 * Allocate 8 input registers since ptrace() may clobber them
   4.157 +	 */
   4.158 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
   4.159 +	alloc r16=ar.pfs,8,2,6,0
   4.160 +	DO_SAVE_SWITCH_STACK
   4.161 +	adds r2=PT(R16)+IA64_SWITCH_STACK_SIZE+16,sp
   4.162 +	mov loc0=rp
   4.163 +	mov loc1=r16				// save ar.pfs across do_fork
   4.164 +	.body
   4.165 +	mov out1=in1
   4.166 +	mov out3=16				// stacksize (compensates for 16-byte scratch area)
   4.167 +	tbit.nz p6,p0=in0,CLONE_SETTLS_BIT
   4.168 +	mov out4=in2	// parent_tidptr: valid only w/CLONE_PARENT_SETTID
   4.169 +	;;
   4.170 +(p6)	st8 [r2]=in4				// store TLS in r13 (tp)
   4.171 +	mov out5=in3	// child_tidptr:  valid only w/CLONE_CHILD_SETTID or CLONE_CHILD_CLEARTID
   4.172 +	adds out2=IA64_SWITCH_STACK_SIZE+16,sp	// out2 = &regs
   4.173 +	mov out0=in0				// out0 = clone_flags
   4.174 +	br.call.sptk.many rp=do_fork
   4.175 +.ret2:	.restore sp
   4.176 +	adds sp=IA64_SWITCH_STACK_SIZE,sp	// pop the switch stack
   4.177 +	mov ar.pfs=loc1
   4.178 +	mov rp=loc0
   4.179 +	br.ret.sptk.many rp
   4.180 +END(sys_clone)
   4.181 +#endif /* !XEN */
   4.182 +
   4.183 +/*
   4.184 + * prev_task <- ia64_switch_to(struct task_struct *next)
   4.185 + *	With Ingo's new scheduler, interrupts are disabled when this routine gets
   4.186 + *	called.  The code starting at .map relies on this.  The rest of the code
   4.187 + *	doesn't care about the interrupt masking status.
   4.188 + */
   4.189 +GLOBAL_ENTRY(ia64_switch_to)
   4.190 +	.prologue
   4.191 +	alloc r16=ar.pfs,1,0,0,0
   4.192 +	DO_SAVE_SWITCH_STACK
   4.193 +	.body
   4.194 +
   4.195 +	adds r22=IA64_TASK_THREAD_KSP_OFFSET,r13
   4.196 +	movl r25=init_task
   4.197 +	mov r27=IA64_KR(CURRENT_STACK)
   4.198 +	adds r21=IA64_TASK_THREAD_KSP_OFFSET,in0
   4.199 +#ifdef XEN
   4.200 +	dep r20=0,in0,60,4		// physical address of "next"
   4.201 +#else
   4.202 +	dep r20=0,in0,61,3		// physical address of "next"
   4.203 +#endif
   4.204 +	;;
   4.205 +	st8 [r22]=sp			// save kernel stack pointer of old task
   4.206 +	shr.u r26=r20,IA64_GRANULE_SHIFT
   4.207 +	cmp.eq p7,p6=r25,in0
   4.208 +	;;
   4.209 +	/*
   4.210 +	 * If we've already mapped this task's page, we can skip doing it again.
   4.211 +	 */
   4.212 +(p6)	cmp.eq p7,p6=r26,r27
   4.213 +(p6)	br.cond.dpnt .map
   4.214 +	;;
   4.215 +.done:
   4.216 +(p6)	ssm psr.ic			// if we had to map, reenable the psr.ic bit FIRST!!!
   4.217 +	;;
   4.218 +(p6)	srlz.d
   4.219 +	ld8 sp=[r21]			// load kernel stack pointer of new task
   4.220 +	mov IA64_KR(CURRENT)=in0	// update "current" application register
   4.221 +	mov r8=r13			// return pointer to previously running task
   4.222 +	mov r13=in0			// set "current" pointer
   4.223 +	;;
   4.224 +	DO_LOAD_SWITCH_STACK
   4.225 +
   4.226 +#ifdef CONFIG_SMP
   4.227 +	sync.i				// ensure "fc"s done by this CPU are visible on other CPUs
   4.228 +#endif
   4.229 +	br.ret.sptk.many rp		// boogie on out in new context
   4.230 +
   4.231 +.map:
   4.232 +#ifdef XEN
   4.233 +	// avoid overlapping with kernel TR
   4.234 +	movl r25=KERNEL_START
   4.235 +	dep  r23=0,in0,0,KERNEL_TR_PAGE_SHIFT
   4.236 +	;;
   4.237 +	cmp.eq p7,p0=r25,r23
   4.238 +	;;
   4.239 +(p7)	mov IA64_KR(CURRENT_STACK)=r26	// remember last page we mapped...
   4.240 +(p7)	br.cond.sptk .done
   4.241 +#endif
   4.242 +	rsm psr.ic			// interrupts (psr.i) are already disabled here
   4.243 +	movl r25=PAGE_KERNEL
   4.244 +	;;
   4.245 +	srlz.d
   4.246 +	or r23=r25,r20			// construct PA | page properties
   4.247 +	mov r25=IA64_GRANULE_SHIFT<<2
   4.248 +	;;
   4.249 +	mov cr.itir=r25
   4.250 +	mov cr.ifa=in0			// VA of next task...
   4.251 +	;;
   4.252 +	mov r25=IA64_TR_CURRENT_STACK
   4.253 +	mov IA64_KR(CURRENT_STACK)=r26	// remember last page we mapped...
   4.254 +	;;
   4.255 +	itr.d dtr[r25]=r23		// wire in new mapping...
   4.256 +	br.cond.sptk .done
   4.257 +END(ia64_switch_to)
   4.258 +
   4.259 +/*
   4.260 + * Note that interrupts are enabled during save_switch_stack and load_switch_stack.  This
   4.261 + * means that we may get an interrupt with "sp" pointing to the new kernel stack while
   4.262 + * ar.bspstore is still pointing to the old kernel backing store area.  Since ar.rsc,
   4.263 + * ar.rnat, ar.bsp, and ar.bspstore are all preserved by interrupts, this is not a
   4.264 + * problem.  Also, we don't need to specify unwind information for preserved registers
   4.265 + * that are not modified in save_switch_stack as the right unwind information is already
   4.266 + * specified at the call-site of save_switch_stack.
   4.267 + */
   4.268 +
   4.269 +/*
   4.270 + * save_switch_stack:
   4.271 + *	- r16 holds ar.pfs
   4.272 + *	- b7 holds address to return to
   4.273 + *	- rp (b0) holds return address to save
   4.274 + */
   4.275 +GLOBAL_ENTRY(save_switch_stack)
   4.276 +	.prologue
   4.277 +	.altrp b7
   4.278 +	flushrs			// flush dirty regs to backing store (must be first in insn group)
   4.279 +	.save @priunat,r17
   4.280 +	mov r17=ar.unat		// preserve caller's
   4.281 +	.body
   4.282 +#ifdef CONFIG_ITANIUM
   4.283 +	adds r2=16+128,sp
   4.284 +	adds r3=16+64,sp
   4.285 +	adds r14=SW(R4)+16,sp
   4.286 +	;;
   4.287 +	st8.spill [r14]=r4,16		// spill r4
   4.288 +	lfetch.fault.excl.nt1 [r3],128
   4.289 +	;;
   4.290 +	lfetch.fault.excl.nt1 [r2],128
   4.291 +	lfetch.fault.excl.nt1 [r3],128
   4.292 +	;;
   4.293 +	lfetch.fault.excl [r2]
   4.294 +	lfetch.fault.excl [r3]
   4.295 +	adds r15=SW(R5)+16,sp
   4.296 +#else
   4.297 +	add r2=16+3*128,sp
   4.298 +	add r3=16,sp
   4.299 +	add r14=SW(R4)+16,sp
   4.300 +	;;
   4.301 +	st8.spill [r14]=r4,SW(R6)-SW(R4)	// spill r4 and prefetch offset 0x1c0
   4.302 +	lfetch.fault.excl.nt1 [r3],128	//		prefetch offset 0x010
   4.303 +	;;
   4.304 +	lfetch.fault.excl.nt1 [r3],128	//		prefetch offset 0x090
   4.305 +	lfetch.fault.excl.nt1 [r2],128	//		prefetch offset 0x190
   4.306 +	;;
   4.307 +	lfetch.fault.excl.nt1 [r3]	//		prefetch offset 0x110
   4.308 +	lfetch.fault.excl.nt1 [r2]	//		prefetch offset 0x210
   4.309 +	adds r15=SW(R5)+16,sp
   4.310 +#endif
   4.311 +	;;
   4.312 +	st8.spill [r15]=r5,SW(R7)-SW(R5)	// spill r5
   4.313 +	mov.m ar.rsc=0			// put RSE in mode: enforced lazy, little endian, pl 0
   4.314 +	add r2=SW(F2)+16,sp		// r2 = &sw->f2
   4.315 +	;;
   4.316 +	st8.spill [r14]=r6,SW(B0)-SW(R6)	// spill r6
   4.317 +	mov.m r18=ar.fpsr		// preserve fpsr
   4.318 +	add r3=SW(F3)+16,sp		// r3 = &sw->f3
   4.319 +	;;
   4.320 +	stf.spill [r2]=f2,32
   4.321 +	mov.m r19=ar.rnat
   4.322 +	mov r21=b0
   4.323 +
   4.324 +	stf.spill [r3]=f3,32
   4.325 +	st8.spill [r15]=r7,SW(B2)-SW(R7)	// spill r7
   4.326 +	mov r22=b1
   4.327 +	;;
   4.328 +	// since we're done with the spills, read and save ar.unat:
   4.329 +	mov.m r29=ar.unat
   4.330 +	mov.m r20=ar.bspstore
   4.331 +	mov r23=b2
   4.332 +	stf.spill [r2]=f4,32
   4.333 +	stf.spill [r3]=f5,32
   4.334 +	mov r24=b3
   4.335 +	;;
   4.336 +	st8 [r14]=r21,SW(B1)-SW(B0)		// save b0
   4.337 +	st8 [r15]=r23,SW(B3)-SW(B2)		// save b2
   4.338 +	mov r25=b4
   4.339 +	mov r26=b5
   4.340 +	;;
   4.341 +	st8 [r14]=r22,SW(B4)-SW(B1)		// save b1
   4.342 +	st8 [r15]=r24,SW(AR_PFS)-SW(B3)		// save b3
   4.343 +	mov r21=ar.lc		// I-unit
   4.344 +	stf.spill [r2]=f12,32
   4.345 +	stf.spill [r3]=f13,32
   4.346 +	;;
   4.347 +	st8 [r14]=r25,SW(B5)-SW(B4)		// save b4
   4.348 +	st8 [r15]=r16,SW(AR_LC)-SW(AR_PFS)	// save ar.pfs
   4.349 +	stf.spill [r2]=f14,32
   4.350 +	stf.spill [r3]=f15,32
   4.351 +	;;
   4.352 +	st8 [r14]=r26				// save b5
   4.353 +	st8 [r15]=r21				// save ar.lc
   4.354 +	stf.spill [r2]=f16,32
   4.355 +	stf.spill [r3]=f17,32
   4.356 +	;;
   4.357 +	stf.spill [r2]=f18,32
   4.358 +	stf.spill [r3]=f19,32
   4.359 +	;;
   4.360 +	stf.spill [r2]=f20,32
   4.361 +	stf.spill [r3]=f21,32
   4.362 +	;;
   4.363 +	stf.spill [r2]=f22,32
   4.364 +	stf.spill [r3]=f23,32
   4.365 +	;;
   4.366 +	stf.spill [r2]=f24,32
   4.367 +	stf.spill [r3]=f25,32
   4.368 +	;;
   4.369 +	stf.spill [r2]=f26,32
   4.370 +	stf.spill [r3]=f27,32
   4.371 +	;;
   4.372 +	stf.spill [r2]=f28,32
   4.373 +	stf.spill [r3]=f29,32
   4.374 +	;;
   4.375 +	stf.spill [r2]=f30,SW(AR_UNAT)-SW(F30)
   4.376 +	stf.spill [r3]=f31,SW(PR)-SW(F31)
   4.377 +	add r14=SW(CALLER_UNAT)+16,sp
   4.378 +	;;
   4.379 +	st8 [r2]=r29,SW(AR_RNAT)-SW(AR_UNAT)	// save ar.unat
   4.380 +	st8 [r14]=r17,SW(AR_FPSR)-SW(CALLER_UNAT) // save caller_unat
   4.381 +	mov r21=pr
   4.382 +	;;
   4.383 +	st8 [r2]=r19,SW(AR_BSPSTORE)-SW(AR_RNAT) // save ar.rnat
   4.384 +	st8 [r3]=r21				// save predicate registers
   4.385 +	;;
   4.386 +	st8 [r2]=r20				// save ar.bspstore
   4.387 +	st8 [r14]=r18				// save fpsr
   4.388 +	mov ar.rsc=3		// put RSE back into eager mode, pl 0
   4.389 +	br.cond.sptk.many b7
   4.390 +END(save_switch_stack)
   4.391 +
   4.392 +/*
   4.393 + * load_switch_stack:
   4.394 + *	- "invala" MUST be done at call site (normally in DO_LOAD_SWITCH_STACK)
   4.395 + *	- b7 holds address to return to
   4.396 + *	- must not touch r8-r11
   4.397 + */
   4.398 +#ifdef XEN
   4.399 +GLOBAL_ENTRY(load_switch_stack)
   4.400 +#else
   4.401 +ENTRY(load_switch_stack)
   4.402 +#endif
   4.403 +	.prologue
   4.404 +	.altrp b7
   4.405 +
   4.406 +	.body
   4.407 +	lfetch.fault.nt1 [sp]
   4.408 +	adds r2=SW(AR_BSPSTORE)+16,sp
   4.409 +	adds r3=SW(AR_UNAT)+16,sp
   4.410 +	mov ar.rsc=0						// put RSE into enforced lazy mode
   4.411 +	adds r14=SW(CALLER_UNAT)+16,sp
   4.412 +	adds r15=SW(AR_FPSR)+16,sp
   4.413 +	;;
   4.414 +	ld8 r27=[r2],(SW(B0)-SW(AR_BSPSTORE))	// bspstore
   4.415 +	ld8 r29=[r3],(SW(B1)-SW(AR_UNAT))	// unat
   4.416 +	;;
   4.417 +	ld8 r21=[r2],16		// restore b0
   4.418 +	ld8 r22=[r3],16		// restore b1
   4.419 +	;;
   4.420 +	ld8 r23=[r2],16		// restore b2
   4.421 +	ld8 r24=[r3],16		// restore b3
   4.422 +	;;
   4.423 +	ld8 r25=[r2],16		// restore b4
   4.424 +	ld8 r26=[r3],16		// restore b5
   4.425 +	;;
   4.426 +	ld8 r16=[r2],(SW(PR)-SW(AR_PFS))	// ar.pfs
   4.427 +	ld8 r17=[r3],(SW(AR_RNAT)-SW(AR_LC))	// ar.lc
   4.428 +	;;
   4.429 +	ld8 r28=[r2]		// restore pr
   4.430 +	ld8 r30=[r3]		// restore rnat
   4.431 +	;;
   4.432 +	ld8 r18=[r14],16	// restore caller's unat
   4.433 +	ld8 r19=[r15],24	// restore fpsr
   4.434 +	;;
   4.435 +	ldf.fill f2=[r14],32
   4.436 +	ldf.fill f3=[r15],32
   4.437 +	;;
   4.438 +	ldf.fill f4=[r14],32
   4.439 +	ldf.fill f5=[r15],32
   4.440 +	;;
   4.441 +	ldf.fill f12=[r14],32
   4.442 +	ldf.fill f13=[r15],32
   4.443 +	;;
   4.444 +	ldf.fill f14=[r14],32
   4.445 +	ldf.fill f15=[r15],32
   4.446 +	;;
   4.447 +	ldf.fill f16=[r14],32
   4.448 +	ldf.fill f17=[r15],32
   4.449 +	;;
   4.450 +	ldf.fill f18=[r14],32
   4.451 +	ldf.fill f19=[r15],32
   4.452 +	mov b0=r21
   4.453 +	;;
   4.454 +	ldf.fill f20=[r14],32
   4.455 +	ldf.fill f21=[r15],32
   4.456 +	mov b1=r22
   4.457 +	;;
   4.458 +	ldf.fill f22=[r14],32
   4.459 +	ldf.fill f23=[r15],32
   4.460 +	mov b2=r23
   4.461 +	;;
   4.462 +	mov ar.bspstore=r27
   4.463 +	mov ar.unat=r29		// establish unat holding the NaT bits for r4-r7
   4.464 +	mov b3=r24
   4.465 +	;;
   4.466 +	ldf.fill f24=[r14],32
   4.467 +	ldf.fill f25=[r15],32
   4.468 +	mov b4=r25
   4.469 +	;;
   4.470 +	ldf.fill f26=[r14],32
   4.471 +	ldf.fill f27=[r15],32
   4.472 +	mov b5=r26
   4.473 +	;;
   4.474 +	ldf.fill f28=[r14],32
   4.475 +	ldf.fill f29=[r15],32
   4.476 +	mov ar.pfs=r16
   4.477 +	;;
   4.478 +	ldf.fill f30=[r14],32
   4.479 +	ldf.fill f31=[r15],24
   4.480 +	mov ar.lc=r17
   4.481 +	;;
   4.482 +	ld8.fill r4=[r14],16
   4.483 +	ld8.fill r5=[r15],16
   4.484 +	mov pr=r28,-1
   4.485 +	;;
   4.486 +	ld8.fill r6=[r14],16
   4.487 +	ld8.fill r7=[r15],16
   4.488 +
   4.489 +	mov ar.unat=r18				// restore caller's unat
   4.490 +	mov ar.rnat=r30				// must restore after bspstore but before rsc!
   4.491 +	mov ar.fpsr=r19				// restore fpsr
   4.492 +	mov ar.rsc=3				// put RSE back into eager mode, pl 0
   4.493 +	br.cond.sptk.many b7
   4.494 +END(load_switch_stack)
   4.495 +
   4.496 +#ifndef XEN
   4.497 +GLOBAL_ENTRY(__ia64_syscall)
   4.498 +	.regstk 6,0,0,0
   4.499 +	mov r15=in5				// put syscall number in place
   4.500 +	break __BREAK_SYSCALL
   4.501 +	movl r2=errno
   4.502 +	cmp.eq p6,p7=-1,r10
   4.503 +	;;
   4.504 +(p6)	st4 [r2]=r8
   4.505 +(p6)	mov r8=-1
   4.506 +	br.ret.sptk.many rp
   4.507 +END(__ia64_syscall)
   4.508 +
   4.509 +GLOBAL_ENTRY(execve)
   4.510 +	mov r15=__NR_execve			// put syscall number in place
   4.511 +	break __BREAK_SYSCALL
   4.512 +	br.ret.sptk.many rp
   4.513 +END(execve)
   4.514 +
   4.515 +GLOBAL_ENTRY(clone)
   4.516 +	mov r15=__NR_clone			// put syscall number in place
   4.517 +	break __BREAK_SYSCALL
   4.518 +	br.ret.sptk.many rp
   4.519 +END(clone)
   4.520 +
   4.521 +	/*
   4.522 +	 * Invoke a system call, but do some tracing before and after the call.
   4.523 +	 * We MUST preserve the current register frame throughout this routine
   4.524 +	 * because some system calls (such as ia64_execve) directly
   4.525 +	 * manipulate ar.pfs.
   4.526 +	 */
   4.527 +GLOBAL_ENTRY(ia64_trace_syscall)
   4.528 +	PT_REGS_UNWIND_INFO(0)
   4.529 +	/*
   4.530 +	 * We need to preserve the scratch registers f6-f11 in case the system
   4.531 +	 * call is sigreturn.
   4.532 +	 */
   4.533 +	adds r16=PT(F6)+16,sp
   4.534 +	adds r17=PT(F7)+16,sp
   4.535 +	;;
   4.536 + 	stf.spill [r16]=f6,32
   4.537 + 	stf.spill [r17]=f7,32
   4.538 +	;;
   4.539 + 	stf.spill [r16]=f8,32
   4.540 + 	stf.spill [r17]=f9,32
   4.541 +	;;
   4.542 + 	stf.spill [r16]=f10
   4.543 + 	stf.spill [r17]=f11
   4.544 +	br.call.sptk.many rp=syscall_trace_enter // give parent a chance to catch syscall args
   4.545 +	adds r16=PT(F6)+16,sp
   4.546 +	adds r17=PT(F7)+16,sp
   4.547 +	;;
   4.548 +	ldf.fill f6=[r16],32
   4.549 +	ldf.fill f7=[r17],32
   4.550 +	;;
   4.551 +	ldf.fill f8=[r16],32
   4.552 +	ldf.fill f9=[r17],32
   4.553 +	;;
   4.554 +	ldf.fill f10=[r16]
   4.555 +	ldf.fill f11=[r17]
   4.556 +	// the syscall number may have changed, so re-load it and re-calculate the
   4.557 +	// syscall entry-point:
   4.558 +	adds r15=PT(R15)+16,sp			// r15 = &pt_regs.r15 (syscall #)
   4.559 +	;;
   4.560 +	ld8 r15=[r15]
   4.561 +	mov r3=NR_syscalls - 1
   4.562 +	;;
   4.563 +	adds r15=-1024,r15
   4.564 +	movl r16=sys_call_table
   4.565 +	;;
   4.566 +	shladd r20=r15,3,r16			// r20 = sys_call_table + 8*(syscall-1024)
   4.567 +	cmp.leu p6,p7=r15,r3
   4.568 +	;;
   4.569 +(p6)	ld8 r20=[r20]				// load address of syscall entry point
   4.570 +(p7)	movl r20=sys_ni_syscall
   4.571 +	;;
   4.572 +	mov b6=r20
   4.573 +	br.call.sptk.many rp=b6			// do the syscall
   4.574 +.strace_check_retval:
   4.575 +	cmp.lt p6,p0=r8,r0			// syscall failed?
   4.576 +	adds r2=PT(R8)+16,sp			// r2 = &pt_regs.r8
   4.577 +	adds r3=PT(R10)+16,sp			// r3 = &pt_regs.r10
   4.578 +	mov r10=0
   4.579 +(p6)	br.cond.sptk strace_error		// syscall failed ->
   4.580 +	;;					// avoid RAW on r10
   4.581 +.strace_save_retval:
   4.582 +.mem.offset 0,0; st8.spill [r2]=r8		// store return value in slot for r8
   4.583 +.mem.offset 8,0; st8.spill [r3]=r10		// clear error indication in slot for r10
   4.584 +	br.call.sptk.many rp=syscall_trace_leave // give parent a chance to catch return value
   4.585 +.ret3:	br.cond.sptk .work_pending_syscall_end
   4.586 +
   4.587 +strace_error:
   4.588 +	ld8 r3=[r2]				// load pt_regs.r8
   4.589 +	sub r9=0,r8				// negate return value to get errno value
   4.590 +	;;
   4.591 +	cmp.ne p6,p0=r3,r0			// is pt_regs.r8!=0?
   4.592 +	adds r3=16,r2				// r3=&pt_regs.r10
   4.593 +	;;
   4.594 +(p6)	mov r10=-1
   4.595 +(p6)	mov r8=r9
   4.596 +	br.cond.sptk .strace_save_retval
   4.597 +END(ia64_trace_syscall)
   4.598 +
   4.599 +	/*
   4.600 +	 * When traced and returning from sigreturn, we invoke syscall_trace but then
   4.601 +	 * go straight to ia64_leave_kernel rather than ia64_leave_syscall.
   4.602 +	 */
   4.603 +GLOBAL_ENTRY(ia64_strace_leave_kernel)
   4.604 +	PT_REGS_UNWIND_INFO(0)
   4.605 +{	/*
   4.606 +	 * Some versions of gas generate bad unwind info if the first instruction of a
   4.607 +	 * procedure doesn't go into the first slot of a bundle.  This is a workaround.
   4.608 +	 */
   4.609 +	nop.m 0
   4.610 +	nop.i 0
   4.611 +	br.call.sptk.many rp=syscall_trace_leave // give parent a chance to catch return value
   4.612 +}
   4.613 +.ret4:	br.cond.sptk ia64_leave_kernel
   4.614 +END(ia64_strace_leave_kernel)
   4.615 +#endif
   4.616 +
   4.617 +GLOBAL_ENTRY(ia64_ret_from_clone)
   4.618 +	PT_REGS_UNWIND_INFO(0)
   4.619 +{	/*
   4.620 +	 * Some versions of gas generate bad unwind info if the first instruction of a
   4.621 +	 * procedure doesn't go into the first slot of a bundle.  This is a workaround.
   4.622 +	 */
   4.623 +	nop.m 0
   4.624 +	nop.i 0
   4.625 +	/*
   4.626 +	 * We need to call schedule_tail() to complete the scheduling process.
   4.627 +	 * Called by ia64_switch_to() after do_fork()->copy_thread().  r8 contains the
   4.628 +	 * address of the previously executing task.
   4.629 +	 */
   4.630 +	br.call.sptk.many rp=ia64_invoke_schedule_tail
   4.631 +}
   4.632 +#ifdef XEN
   4.633 +	// new domains are cloned but not exec'ed so switch to user mode here
   4.634 +	cmp.ne pKStk,pUStk=r0,r0
   4.635 +#ifdef CONFIG_VTI
   4.636 +	br.cond.spnt ia64_leave_hypervisor
   4.637 +#else // CONFIG_VTI
   4.638 +	br.cond.spnt ia64_leave_kernel
   4.639 +#endif // CONFIG_VTI
   4.640 +#else
   4.641 +.ret8:
   4.642 +	adds r2=TI_FLAGS+IA64_TASK_SIZE,r13
   4.643 +	;;
   4.644 +	ld4 r2=[r2]
   4.645 +	;;
   4.646 +	mov r8=0
   4.647 +	and r2=_TIF_SYSCALL_TRACEAUDIT,r2
   4.648 +	;;
   4.649 +	cmp.ne p6,p0=r2,r0
   4.650 +(p6)	br.cond.spnt .strace_check_retval
   4.651 +#endif
   4.652 +	;;					// added stop bits to prevent r8 dependency
   4.653 +END(ia64_ret_from_clone)
   4.654 +	// fall through
   4.655 +GLOBAL_ENTRY(ia64_ret_from_syscall)
   4.656 +	PT_REGS_UNWIND_INFO(0)
   4.657 +	cmp.ge p6,p7=r8,r0			// syscall executed successfully?
   4.658 +	adds r2=PT(R8)+16,sp			// r2 = &pt_regs.r8
   4.659 +	mov r10=r0				// clear error indication in r10
   4.660 +(p7)	br.cond.spnt handle_syscall_error	// handle potential syscall failure
   4.661 +END(ia64_ret_from_syscall)
   4.662 +	// fall through
   4.663 +/*
   4.664 + * ia64_leave_syscall(): Same as ia64_leave_kernel, except that it doesn't
   4.665 + *	need to switch to bank 0 and doesn't restore the scratch registers.
   4.666 + *	To avoid leaking kernel bits, the scratch registers are set to
   4.667 + *	the following known-to-be-safe values:
   4.668 + *
   4.669 + *		  r1: restored (global pointer)
   4.670 + *		  r2: cleared
   4.671 + *		  r3: 1 (when returning to user-level)
   4.672 + *	      r8-r11: restored (syscall return value(s))
   4.673 + *		 r12: restored (user-level stack pointer)
   4.674 + *		 r13: restored (user-level thread pointer)
   4.675 + *		 r14: cleared
   4.676 + *		 r15: restored (syscall #)
   4.677 + *	     r16-r17: cleared
   4.678 + *		 r18: user-level b6
   4.679 + *		 r19: cleared
   4.680 + *		 r20: user-level ar.fpsr
   4.681 + *		 r21: user-level b0
   4.682 + *		 r22: cleared
   4.683 + *		 r23: user-level ar.bspstore
   4.684 + *		 r24: user-level ar.rnat
   4.685 + *		 r25: user-level ar.unat
   4.686 + *		 r26: user-level ar.pfs
   4.687 + *		 r27: user-level ar.rsc
   4.688 + *		 r28: user-level ip
   4.689 + *		 r29: user-level psr
   4.690 + *		 r30: user-level cfm
   4.691 + *		 r31: user-level pr
   4.692 + *	      f6-f11: cleared
   4.693 + *		  pr: restored (user-level pr)
   4.694 + *		  b0: restored (user-level rp)
   4.695 + *	          b6: restored
   4.696 + *		  b7: cleared
   4.697 + *	     ar.unat: restored (user-level ar.unat)
   4.698 + *	      ar.pfs: restored (user-level ar.pfs)
   4.699 + *	      ar.rsc: restored (user-level ar.rsc)
   4.700 + *	     ar.rnat: restored (user-level ar.rnat)
   4.701 + *	 ar.bspstore: restored (user-level ar.bspstore)
   4.702 + *	     ar.fpsr: restored (user-level ar.fpsr)
   4.703 + *	      ar.ccv: cleared
   4.704 + *	      ar.csd: cleared
   4.705 + *	      ar.ssd: cleared
   4.706 + */
   4.707 +ENTRY(ia64_leave_syscall)
   4.708 +	PT_REGS_UNWIND_INFO(0)
   4.709 +	/*
   4.710 +	 * work.need_resched etc. mustn't get changed by this CPU before it returns to
   4.711 +	 * user- or fsys-mode, hence we disable interrupts early on.
   4.712 +	 *
   4.713 +	 * p6 controls whether current_thread_info()->flags needs to be check for
   4.714 +	 * extra work.  We always check for extra work when returning to user-level.
   4.715 +	 * With CONFIG_PREEMPT, we also check for extra work when the preempt_count
   4.716 +	 * is 0.  After extra work processing has been completed, execution
   4.717 +	 * resumes at .work_processed_syscall with p6 set to 1 if the extra-work-check
   4.718 +	 * needs to be redone.
   4.719 +	 */
   4.720 +#ifdef CONFIG_PREEMPT
   4.721 +	rsm psr.i				// disable interrupts
   4.722 +	cmp.eq pLvSys,p0=r0,r0			// pLvSys=1: leave from syscall
   4.723 +(pKStk) adds r20=TI_PRE_COUNT+IA64_TASK_SIZE,r13
   4.724 +	;;
   4.725 +	.pred.rel.mutex pUStk,pKStk
   4.726 +(pKStk) ld4 r21=[r20]			// r21 <- preempt_count
   4.727 +(pUStk)	mov r21=0			// r21 <- 0
   4.728 +	;;
   4.729 +	cmp.eq p6,p0=r21,r0		// p6 <- pUStk || (preempt_count == 0)
   4.730 +#else /* !CONFIG_PREEMPT */
   4.731 +(pUStk)	rsm psr.i
   4.732 +	cmp.eq pLvSys,p0=r0,r0		// pLvSys=1: leave from syscall
   4.733 +(pUStk)	cmp.eq.unc p6,p0=r0,r0		// p6 <- pUStk
   4.734 +#endif
   4.735 +.work_processed_syscall:
   4.736 +	adds r2=PT(LOADRS)+16,r12
   4.737 +	adds r3=PT(AR_BSPSTORE)+16,r12
   4.738 +#ifdef XEN
   4.739 +	;;
   4.740 +#else
   4.741 +	adds r18=TI_FLAGS+IA64_TASK_SIZE,r13
   4.742 +	;;
   4.743 +(p6)	ld4 r31=[r18]				// load current_thread_info()->flags
   4.744 +#endif
   4.745 +	ld8 r19=[r2],PT(B6)-PT(LOADRS)		// load ar.rsc value for "loadrs"
   4.746 +	mov b7=r0		// clear b7
   4.747 +	;;
   4.748 +	ld8 r23=[r3],PT(R11)-PT(AR_BSPSTORE)	// load ar.bspstore (may be garbage)
   4.749 +	ld8 r18=[r2],PT(R9)-PT(B6)		// load b6
   4.750 +#ifndef XEN
   4.751 +(p6)	and r15=TIF_WORK_MASK,r31		// any work other than TIF_SYSCALL_TRACE?
   4.752 +#endif
   4.753 +	;;
   4.754 +	mov r16=ar.bsp				// M2  get existing backing store pointer
   4.755 +#ifndef XEN
   4.756 +(p6)	cmp4.ne.unc p6,p0=r15, r0		// any special work pending?
   4.757 +(p6)	br.cond.spnt .work_pending_syscall
   4.758 +#endif
   4.759 +	;;
   4.760 +	// start restoring the state saved on the kernel stack (struct pt_regs):
   4.761 +	ld8 r9=[r2],PT(CR_IPSR)-PT(R9)
   4.762 +	ld8 r11=[r3],PT(CR_IIP)-PT(R11)
   4.763 +	mov f6=f0		// clear f6
   4.764 +	;;
   4.765 +	invala			// M0|1 invalidate ALAT
   4.766 +	rsm psr.i | psr.ic	// M2 initiate turning off of interrupt and interruption collection
   4.767 +	mov f9=f0		// clear f9
   4.768 +
   4.769 +	ld8 r29=[r2],16		// load cr.ipsr
   4.770 +	ld8 r28=[r3],16			// load cr.iip
   4.771 +	mov f8=f0		// clear f8
   4.772 +	;;
   4.773 +	ld8 r30=[r2],16		// M0|1 load cr.ifs
   4.774 +	mov.m ar.ssd=r0		// M2 clear ar.ssd
   4.775 +	cmp.eq p9,p0=r0,r0	// set p9 to indicate that we should restore cr.ifs
   4.776 +	;;
   4.777 +	ld8 r25=[r3],16		// M0|1 load ar.unat
   4.778 +	mov.m ar.csd=r0		// M2 clear ar.csd
   4.779 +	mov r22=r0		// clear r22
   4.780 +	;;
   4.781 +	ld8 r26=[r2],PT(B0)-PT(AR_PFS)	// M0|1 load ar.pfs
   4.782 +(pKStk)	mov r22=psr		// M2 read PSR now that interrupts are disabled
   4.783 +	mov f10=f0		// clear f10
   4.784 +	;;
   4.785 +	ld8 r21=[r2],PT(AR_RNAT)-PT(B0) // load b0
   4.786 +	ld8 r27=[r3],PT(PR)-PT(AR_RSC)	// load ar.rsc
   4.787 +	mov f11=f0		// clear f11
   4.788 +	;;
   4.789 +	ld8 r24=[r2],PT(AR_FPSR)-PT(AR_RNAT)	// load ar.rnat (may be garbage)
   4.790 +	ld8 r31=[r3],PT(R1)-PT(PR)		// load predicates
   4.791 +(pUStk) add r14=IA64_TASK_THREAD_ON_USTACK_OFFSET,r13
   4.792 +	;;
   4.793 +	ld8 r20=[r2],PT(R12)-PT(AR_FPSR)	// load ar.fpsr
   4.794 +	ld8.fill r1=[r3],16	// load r1
   4.795 +(pUStk) mov r17=1
   4.796 +	;;
   4.797 +	srlz.d			// M0  ensure interruption collection is off
   4.798 +	ld8.fill r13=[r3],16
   4.799 +	mov f7=f0		// clear f7
   4.800 +	;;
   4.801 +	ld8.fill r12=[r2]	// restore r12 (sp)
   4.802 +	ld8.fill r15=[r3]	// restore r15
   4.803 +#ifdef XEN
   4.804 +	movl r3=THIS_CPU(ia64_phys_stacked_size_p8)
   4.805 +#else
   4.806 +	addl r3=THIS_CPU(ia64_phys_stacked_size_p8),r0
   4.807 +#endif
   4.808 +	;;
   4.809 +(pUStk)	ld4 r3=[r3]		// r3 = cpu_data->phys_stacked_size_p8
   4.810 +(pUStk) st1 [r14]=r17
   4.811 +	mov b6=r18		// I0  restore b6
   4.812 +	;;
   4.813 +	mov r14=r0		// clear r14
   4.814 +	shr.u r18=r19,16	// I0|1 get byte size of existing "dirty" partition
   4.815 +(pKStk) br.cond.dpnt.many skip_rbs_switch
   4.816 +
   4.817 +	mov.m ar.ccv=r0		// clear ar.ccv
   4.818 +(pNonSys) br.cond.dpnt.many dont_preserve_current_frame
   4.819 +	br.cond.sptk.many rbs_switch
   4.820 +END(ia64_leave_syscall)
   4.821 +
   4.822 +#ifdef CONFIG_IA32_SUPPORT
   4.823 +GLOBAL_ENTRY(ia64_ret_from_ia32_execve)
   4.824 +	PT_REGS_UNWIND_INFO(0)
   4.825 +	adds r2=PT(R8)+16,sp			// r2 = &pt_regs.r8
   4.826 +	adds r3=PT(R10)+16,sp			// r3 = &pt_regs.r10
   4.827 +	;;
   4.828 +	.mem.offset 0,0
   4.829 +	st8.spill [r2]=r8	// store return value in slot for r8 and set unat bit
   4.830 +	.mem.offset 8,0
   4.831 +	st8.spill [r3]=r0	// clear error indication in slot for r10 and set unat bit
   4.832 +END(ia64_ret_from_ia32_execve_syscall)
   4.833 +	// fall through
   4.834 +#endif /* CONFIG_IA32_SUPPORT */
   4.835 +GLOBAL_ENTRY(ia64_leave_kernel)
   4.836 +	PT_REGS_UNWIND_INFO(0)
   4.837 +	/*
   4.838 +	 * work.need_resched etc. mustn't get changed by this CPU before it returns to
   4.839 +	 * user- or fsys-mode, hence we disable interrupts early on.
   4.840 +	 *
   4.841 +	 * p6 controls whether current_thread_info()->flags needs to be check for
   4.842 +	 * extra work.  We always check for extra work when returning to user-level.
   4.843 +	 * With CONFIG_PREEMPT, we also check for extra work when the preempt_count
   4.844 +	 * is 0.  After extra work processing has been completed, execution
   4.845 +	 * resumes at .work_processed_syscall with p6 set to 1 if the extra-work-check
   4.846 +	 * needs to be redone.
   4.847 +	 */
   4.848 +#ifdef CONFIG_PREEMPT
   4.849 +	rsm psr.i				// disable interrupts
   4.850 +	cmp.eq p0,pLvSys=r0,r0			// pLvSys=0: leave from kernel
   4.851 +(pKStk)	adds r20=TI_PRE_COUNT+IA64_TASK_SIZE,r13
   4.852 +	;;
   4.853 +	.pred.rel.mutex pUStk,pKStk
   4.854 +(pKStk)	ld4 r21=[r20]			// r21 <- preempt_count
   4.855 +(pUStk)	mov r21=0			// r21 <- 0
   4.856 +	;;
   4.857 +	cmp.eq p6,p0=r21,r0		// p6 <- pUStk || (preempt_count == 0)
   4.858 +#else
   4.859 +(pUStk)	rsm psr.i
   4.860 +	cmp.eq p0,pLvSys=r0,r0		// pLvSys=0: leave from kernel
   4.861 +(pUStk)	cmp.eq.unc p6,p0=r0,r0		// p6 <- pUStk
   4.862 +#endif
   4.863 +.work_processed_kernel:
   4.864 +#ifdef XEN
   4.865 +	alloc loc0=ar.pfs,0,1,1,0
   4.866 +	adds out0=16,r12
   4.867 +	;;
   4.868 +(p6)	br.call.sptk.many b0=deliver_pending_interrupt
   4.869 +	mov ar.pfs=loc0
   4.870 +	mov r31=r0
   4.871 +#else
   4.872 +	adds r17=TI_FLAGS+IA64_TASK_SIZE,r13
   4.873 +	;;
   4.874 +(p6)	ld4 r31=[r17]				// load current_thread_info()->flags
   4.875 +#endif
   4.876 +	adds r21=PT(PR)+16,r12
   4.877 +	;;
   4.878 +
   4.879 +	lfetch [r21],PT(CR_IPSR)-PT(PR)
   4.880 +	adds r2=PT(B6)+16,r12
   4.881 +	adds r3=PT(R16)+16,r12
   4.882 +	;;
   4.883 +	lfetch [r21]
   4.884 +	ld8 r28=[r2],8		// load b6
   4.885 +	adds r29=PT(R24)+16,r12
   4.886 +
   4.887 +	ld8.fill r16=[r3]
   4.888 +	adds r30=PT(AR_CCV)+16,r12
   4.889 +(p6)	and r19=TIF_WORK_MASK,r31		// any work other than TIF_SYSCALL_TRACE?
   4.890 +	;;
   4.891 +	adds r3=PT(AR_CSD)-PT(R16),r3
   4.892 +	ld8.fill r24=[r29]
   4.893 +	ld8 r15=[r30]		// load ar.ccv
   4.894 +(p6)	cmp4.ne.unc p6,p0=r19, r0		// any special work pending?
   4.895 +	;;
   4.896 +	ld8 r29=[r2],16		// load b7
   4.897 +	ld8 r30=[r3],16		// load ar.csd
   4.898 +#ifndef XEN
   4.899 +(p6)	br.cond.spnt .work_pending
   4.900 +#endif
   4.901 +	;;
   4.902 +	ld8 r31=[r2],16		// load ar.ssd
   4.903 +	ld8.fill r8=[r3],16
   4.904 +	;;
   4.905 +	ld8.fill r9=[r2],16
   4.906 +	ld8.fill r10=[r3],PT(R17)-PT(R10)
   4.907 +	;;
   4.908 +	ld8.fill r11=[r2],PT(R18)-PT(R11)
   4.909 +	ld8.fill r17=[r3],16
   4.910 +	;;
   4.911 +	ld8.fill r18=[r2],16
   4.912 +	ld8.fill r19=[r3],16
   4.913 +	;;
   4.914 +	ld8.fill r20=[r2],16
   4.915 +	ld8.fill r21=[r3],16
   4.916 +	mov ar.csd=r30
   4.917 +	mov ar.ssd=r31
   4.918 +	;;
   4.919 +	rsm psr.i | psr.ic	// initiate turning off of interrupt and interruption collection
   4.920 +	invala			// invalidate ALAT
   4.921 +	;;
   4.922 +	ld8.fill r22=[r2],24
   4.923 +	ld8.fill r23=[r3],24
   4.924 +	mov b6=r28
   4.925 +	;;
   4.926 +	ld8.fill r25=[r2],16
   4.927 +	ld8.fill r26=[r3],16
   4.928 +	mov b7=r29
   4.929 +	;;
   4.930 +	ld8.fill r27=[r2],16
   4.931 +	ld8.fill r28=[r3],16
   4.932 +	;;
   4.933 +	ld8.fill r29=[r2],16
   4.934 +	ld8.fill r30=[r3],24
   4.935 +	;;
   4.936 +	ld8.fill r31=[r2],PT(F9)-PT(R31)
   4.937 +	adds r3=PT(F10)-PT(F6),r3
   4.938 +	;;
   4.939 +	ldf.fill f9=[r2],PT(F6)-PT(F9)
   4.940 +	ldf.fill f10=[r3],PT(F8)-PT(F10)
   4.941 +	;;
   4.942 +	ldf.fill f6=[r2],PT(F7)-PT(F6)
   4.943 +	;;
   4.944 +	ldf.fill f7=[r2],PT(F11)-PT(F7)
   4.945 +	ldf.fill f8=[r3],32
   4.946 +	;;
   4.947 +	srlz.i			// ensure interruption collection is off
   4.948 +	mov ar.ccv=r15
   4.949 +	;;
   4.950 +	ldf.fill f11=[r2]
   4.951 +	bsw.0			// switch back to bank 0 (no stop bit required beforehand...)
   4.952 +	;;
   4.953 +(pUStk)	mov r18=IA64_KR(CURRENT)// M2 (12 cycle read latency)
   4.954 +	adds r16=PT(CR_IPSR)+16,r12
   4.955 +	adds r17=PT(CR_IIP)+16,r12
   4.956 +
   4.957 +(pKStk)	mov r22=psr		// M2 read PSR now that interrupts are disabled
   4.958 +	nop.i 0
   4.959 +	nop.i 0
   4.960 +	;;
   4.961 +	ld8 r29=[r16],16	// load cr.ipsr
   4.962 +	ld8 r28=[r17],16	// load cr.iip
   4.963 +	;;
   4.964 +	ld8 r30=[r16],16	// load cr.ifs
   4.965 +	ld8 r25=[r17],16	// load ar.unat
   4.966 +	;;
   4.967 +	ld8 r26=[r16],16	// load ar.pfs
   4.968 +	ld8 r27=[r17],16	// load ar.rsc
   4.969 +	cmp.eq p9,p0=r0,r0	// set p9 to indicate that we should restore cr.ifs
   4.970 +	;;
   4.971 +	ld8 r24=[r16],16	// load ar.rnat (may be garbage)
   4.972 +	ld8 r23=[r17],16	// load ar.bspstore (may be garbage)
   4.973 +	;;
   4.974 +	ld8 r31=[r16],16	// load predicates
   4.975 +	ld8 r21=[r17],16	// load b0
   4.976 +	;;
   4.977 +	ld8 r19=[r16],16	// load ar.rsc value for "loadrs"
   4.978 +	ld8.fill r1=[r17],16	// load r1
   4.979 +	;;
   4.980 +	ld8.fill r12=[r16],16
   4.981 +	ld8.fill r13=[r17],16
   4.982 +(pUStk)	adds r18=IA64_TASK_THREAD_ON_USTACK_OFFSET,r18
   4.983 +	;;
   4.984 +	ld8 r20=[r16],16	// ar.fpsr
   4.985 +	ld8.fill r15=[r17],16
   4.986 +	;;
   4.987 +	ld8.fill r14=[r16],16
   4.988 +	ld8.fill r2=[r17]
   4.989 +(pUStk)	mov r17=1
   4.990 +	;;
   4.991 +	ld8.fill r3=[r16]
   4.992 +(pUStk)	st1 [r18]=r17		// restore current->thread.on_ustack
   4.993 +	shr.u r18=r19,16	// get byte size of existing "dirty" partition
   4.994 +	;;
   4.995 +	mov r16=ar.bsp		// get existing backing store pointer
   4.996 +#ifdef XEN
   4.997 +	movl r17=THIS_CPU(ia64_phys_stacked_size_p8)
   4.998 +#else
   4.999 +	addl r17=THIS_CPU(ia64_phys_stacked_size_p8),r0
  4.1000 +#endif
  4.1001 +	;;
  4.1002 +	ld4 r17=[r17]		// r17 = cpu_data->phys_stacked_size_p8
  4.1003 +(pKStk)	br.cond.dpnt skip_rbs_switch
  4.1004 +
  4.1005 +	/*
  4.1006 +	 * Restore user backing store.
  4.1007 +	 *
  4.1008 +	 * NOTE: alloc, loadrs, and cover can't be predicated.
  4.1009 +	 */
  4.1010 +(pNonSys) br.cond.dpnt dont_preserve_current_frame
  4.1011 +
  4.1012 +rbs_switch:
  4.1013 +	cover				// add current frame into dirty partition and set cr.ifs
  4.1014 +	;;
  4.1015 +	mov r19=ar.bsp			// get new backing store pointer
  4.1016 +	sub r16=r16,r18			// krbs = old bsp - size of dirty partition
  4.1017 +	cmp.ne p9,p0=r0,r0		// clear p9 to skip restore of cr.ifs
  4.1018 +	;;
  4.1019 +	sub r19=r19,r16			// calculate total byte size of dirty partition
  4.1020 +	add r18=64,r18			// don't force in0-in7 into memory...
  4.1021 +	;;
  4.1022 +	shl r19=r19,16			// shift size of dirty partition into loadrs position
  4.1023 +	;;
  4.1024 +dont_preserve_current_frame:
  4.1025 +	/*
  4.1026 +	 * To prevent leaking bits between the kernel and user-space,
  4.1027 +	 * we must clear the stacked registers in the "invalid" partition here.
  4.1028 +	 * Not pretty, but at least it's fast (3.34 registers/cycle on Itanium,
  4.1029 +	 * 5 registers/cycle on McKinley).
  4.1030 +	 */
  4.1031 +#	define pRecurse	p6
  4.1032 +#	define pReturn	p7
  4.1033 +#ifdef CONFIG_ITANIUM
  4.1034 +#	define Nregs	10
  4.1035 +#else
  4.1036 +#	define Nregs	14
  4.1037 +#endif
  4.1038 +	alloc loc0=ar.pfs,2,Nregs-2,2,0
  4.1039 +	shr.u loc1=r18,9		// RNaTslots <= floor(dirtySize / (64*8))
  4.1040 +	sub r17=r17,r18			// r17 = (physStackedSize + 8) - dirtySize
  4.1041 +	;;
  4.1042 +	mov ar.rsc=r19			// load ar.rsc to be used for "loadrs"
  4.1043 +	shladd in0=loc1,3,r17
  4.1044 +	mov in1=0
  4.1045 +	;;
  4.1046 +	TEXT_ALIGN(32)
  4.1047 +rse_clear_invalid:
  4.1048 +#ifdef CONFIG_ITANIUM
  4.1049 +	// cycle 0
  4.1050 + { .mii
  4.1051 +	alloc loc0=ar.pfs,2,Nregs-2,2,0
  4.1052 +	cmp.lt pRecurse,p0=Nregs*8,in0	// if more than Nregs regs left to clear, (re)curse
  4.1053 +	add out0=-Nregs*8,in0
  4.1054 +}{ .mfb
  4.1055 +	add out1=1,in1			// increment recursion count
  4.1056 +	nop.f 0
  4.1057 +	nop.b 0				// can't do br.call here because of alloc (WAW on CFM)
  4.1058 +	;;
  4.1059 +}{ .mfi	// cycle 1
  4.1060 +	mov loc1=0
  4.1061 +	nop.f 0
  4.1062 +	mov loc2=0
  4.1063 +}{ .mib
  4.1064 +	mov loc3=0
  4.1065 +	mov loc4=0
  4.1066 +(pRecurse) br.call.sptk.many b0=rse_clear_invalid
  4.1067 +
  4.1068 +}{ .mfi	// cycle 2
  4.1069 +	mov loc5=0
  4.1070 +	nop.f 0
  4.1071 +	cmp.ne pReturn,p0=r0,in1	// if recursion count != 0, we need to do a br.ret
  4.1072 +}{ .mib
  4.1073 +	mov loc6=0
  4.1074 +	mov loc7=0
  4.1075 +(pReturn) br.ret.sptk.many b0
  4.1076 +}
  4.1077 +#else /* !CONFIG_ITANIUM */
  4.1078 +	alloc loc0=ar.pfs,2,Nregs-2,2,0
  4.1079 +	cmp.lt pRecurse,p0=Nregs*8,in0	// if more than Nregs regs left to clear, (re)curse
  4.1080 +	add out0=-Nregs*8,in0
  4.1081 +	add out1=1,in1			// increment recursion count
  4.1082 +	mov loc1=0
  4.1083 +	mov loc2=0
  4.1084 +	;;
  4.1085 +	mov loc3=0
  4.1086 +	mov loc4=0
  4.1087 +	mov loc5=0
  4.1088 +	mov loc6=0
  4.1089 +	mov loc7=0
  4.1090 +(pRecurse) br.call.sptk.few b0=rse_clear_invalid
  4.1091 +	;;
  4.1092 +	mov loc8=0
  4.1093 +	mov loc9=0
  4.1094 +	cmp.ne pReturn,p0=r0,in1	// if recursion count != 0, we need to do a br.ret
  4.1095 +	mov loc10=0
  4.1096 +	mov loc11=0
  4.1097 +(pReturn) br.ret.sptk.many b0
  4.1098 +#endif /* !CONFIG_ITANIUM */
  4.1099 +#	undef pRecurse
  4.1100 +#	undef pReturn
  4.1101 +	;;
  4.1102 +	alloc r17=ar.pfs,0,0,0,0	// drop current register frame
  4.1103 +	;;
  4.1104 +	loadrs
  4.1105 +	;;
  4.1106 +skip_rbs_switch:
  4.1107 +	mov ar.unat=r25		// M2
  4.1108 +(pKStk)	extr.u r22=r22,21,1	// I0 extract current value of psr.pp from r22
  4.1109 +(pLvSys)mov r19=r0		// A  clear r19 for leave_syscall, no-op otherwise
  4.1110 +	;;
  4.1111 +(pUStk)	mov ar.bspstore=r23	// M2
  4.1112 +(pKStk)	dep r29=r22,r29,21,1	// I0 update ipsr.pp with psr.pp
  4.1113 +(pLvSys)mov r16=r0		// A  clear r16 for leave_syscall, no-op otherwise
  4.1114 +	;;
  4.1115 +	mov cr.ipsr=r29		// M2
  4.1116 +	mov ar.pfs=r26		// I0
  4.1117 +(pLvSys)mov r17=r0		// A  clear r17 for leave_syscall, no-op otherwise
  4.1118 +
  4.1119 +(p9)	mov cr.ifs=r30		// M2
  4.1120 +	mov b0=r21		// I0
  4.1121 +(pLvSys)mov r18=r0		// A  clear r18 for leave_syscall, no-op otherwise
  4.1122 +
  4.1123 +	mov ar.fpsr=r20		// M2
  4.1124 +	mov cr.iip=r28		// M2
  4.1125 +	nop 0
  4.1126 +	;;
  4.1127 +(pUStk)	mov ar.rnat=r24		// M2 must happen with RSE in lazy mode
  4.1128 +	nop 0
  4.1129 +(pLvSys)mov r2=r0
  4.1130 +
  4.1131 +	mov ar.rsc=r27		// M2
  4.1132 +	mov pr=r31,-1		// I0
  4.1133 +	rfi			// B
  4.1134 +
  4.1135 +#ifndef XEN
  4.1136 +	/*
  4.1137 +	 * On entry:
  4.1138 +	 *	r20 = &current->thread_info->pre_count (if CONFIG_PREEMPT)
  4.1139 +	 *	r31 = current->thread_info->flags
  4.1140 +	 * On exit:
  4.1141 +	 *	p6 = TRUE if work-pending-check needs to be redone
  4.1142 +	 */
  4.1143 +.work_pending_syscall:
  4.1144 +	add r2=-8,r2
  4.1145 +	add r3=-8,r3
  4.1146 +	;;
  4.1147 +	st8 [r2]=r8
  4.1148 +	st8 [r3]=r10
  4.1149 +.work_pending:
  4.1150 +	tbit.nz p6,p0=r31,TIF_SIGDELAYED		// signal delayed from  MCA/INIT/NMI/PMI context?
  4.1151 +(p6)	br.cond.sptk.few .sigdelayed
  4.1152 +	;;
  4.1153 +	tbit.z p6,p0=r31,TIF_NEED_RESCHED		// current_thread_info()->need_resched==0?
  4.1154 +(p6)	br.cond.sptk.few .notify
  4.1155 +#ifdef CONFIG_PREEMPT
  4.1156 +(pKStk) dep r21=-1,r0,PREEMPT_ACTIVE_BIT,1
  4.1157 +	;;
  4.1158 +(pKStk) st4 [r20]=r21
  4.1159 +	ssm psr.i		// enable interrupts
  4.1160 +#endif
  4.1161 +	br.call.spnt.many rp=schedule
  4.1162 +.ret9:	cmp.eq p6,p0=r0,r0				// p6 <- 1
  4.1163 +	rsm psr.i		// disable interrupts
  4.1164 +	;;
  4.1165 +#ifdef CONFIG_PREEMPT
  4.1166 +(pKStk)	adds r20=TI_PRE_COUNT+IA64_TASK_SIZE,r13
  4.1167 +	;;
  4.1168 +(pKStk)	st4 [r20]=r0		// preempt_count() <- 0
  4.1169 +#endif
  4.1170 +(pLvSys)br.cond.sptk.few  .work_pending_syscall_end
  4.1171 +	br.cond.sptk.many .work_processed_kernel	// re-check
  4.1172 +
  4.1173 +.notify:
  4.1174 +(pUStk)	br.call.spnt.many rp=notify_resume_user
  4.1175 +.ret10:	cmp.ne p6,p0=r0,r0				// p6 <- 0
  4.1176 +(pLvSys)br.cond.sptk.few  .work_pending_syscall_end
  4.1177 +	br.cond.sptk.many .work_processed_kernel	// don't re-check
  4.1178 +
  4.1179 +// There is a delayed signal that was detected in MCA/INIT/NMI/PMI context where
  4.1180 +// it could not be delivered.  Deliver it now.  The signal might be for us and
  4.1181 +// may set TIF_SIGPENDING, so redrive ia64_leave_* after processing the delayed
  4.1182 +// signal.
  4.1183 +
  4.1184 +.sigdelayed:
  4.1185 +	br.call.sptk.many rp=do_sigdelayed
  4.1186 +	cmp.eq p6,p0=r0,r0				// p6 <- 1, always re-check
  4.1187 +(pLvSys)br.cond.sptk.few  .work_pending_syscall_end
  4.1188 +	br.cond.sptk.many .work_processed_kernel	// re-check
  4.1189 +
  4.1190 +.work_pending_syscall_end:
  4.1191 +	adds r2=PT(R8)+16,r12
  4.1192 +	adds r3=PT(R10)+16,r12
  4.1193 +	;;
  4.1194 +	ld8 r8=[r2]
  4.1195 +	ld8 r10=[r3]
  4.1196 +	br.cond.sptk.many .work_processed_syscall	// re-check
  4.1197 +#endif
  4.1198 +
  4.1199 +END(ia64_leave_kernel)
  4.1200 +
  4.1201 +ENTRY(handle_syscall_error)
  4.1202 +	/*
  4.1203 +	 * Some system calls (e.g., ptrace, mmap) can return arbitrary values which could
  4.1204 +	 * lead us to mistake a negative return value as a failed syscall.  Those syscall
  4.1205 +	 * must deposit a non-zero value in pt_regs.r8 to indicate an error.  If
  4.1206 +	 * pt_regs.r8 is zero, we assume that the call completed successfully.
  4.1207 +	 */
  4.1208 +	PT_REGS_UNWIND_INFO(0)
  4.1209 +	ld8 r3=[r2]		// load pt_regs.r8
  4.1210 +	;;
  4.1211 +	cmp.eq p6,p7=r3,r0	// is pt_regs.r8==0?
  4.1212 +	;;
  4.1213 +(p7)	mov r10=-1
  4.1214 +(p7)	sub r8=0,r8		// negate return value to get errno
  4.1215 +	br.cond.sptk ia64_leave_syscall
  4.1216 +END(handle_syscall_error)
  4.1217 +
  4.1218 +	/*
  4.1219 +	 * Invoke schedule_tail(task) while preserving in0-in7, which may be needed
  4.1220 +	 * in case a system call gets restarted.
  4.1221 +	 */
  4.1222 +GLOBAL_ENTRY(ia64_invoke_schedule_tail)
  4.1223 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
  4.1224 +	alloc loc1=ar.pfs,8,2,1,0
  4.1225 +	mov loc0=rp
  4.1226 +	mov out0=r8				// Address of previous task
  4.1227 +	;;
  4.1228 +	br.call.sptk.many rp=schedule_tail
  4.1229 +.ret11:	mov ar.pfs=loc1
  4.1230 +	mov rp=loc0
  4.1231 +	br.ret.sptk.many rp
  4.1232 +END(ia64_invoke_schedule_tail)
  4.1233 +
  4.1234 +#ifndef XEN
  4.1235 +	/*
  4.1236 +	 * Setup stack and call do_notify_resume_user().  Note that pSys and pNonSys need to
  4.1237 +	 * be set up by the caller.  We declare 8 input registers so the system call
  4.1238 +	 * args get preserved, in case we need to restart a system call.
  4.1239 +	 */
  4.1240 +ENTRY(notify_resume_user)
  4.1241 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
  4.1242 +	alloc loc1=ar.pfs,8,2,3,0 // preserve all eight input regs in case of syscall restart!
  4.1243 +	mov r9=ar.unat
  4.1244 +	mov loc0=rp				// save return address
  4.1245 +	mov out0=0				// there is no "oldset"
  4.1246 +	adds out1=8,sp				// out1=&sigscratch->ar_pfs
  4.1247 +(pSys)	mov out2=1				// out2==1 => we're in a syscall
  4.1248 +	;;
  4.1249 +(pNonSys) mov out2=0				// out2==0 => not a syscall
  4.1250 +	.fframe 16
  4.1251 +	.spillpsp ar.unat, 16			// (note that offset is relative to psp+0x10!)
  4.1252 +	st8 [sp]=r9,-16				// allocate space for ar.unat and save it
  4.1253 +	st8 [out1]=loc1,-8			// save ar.pfs, out1=&sigscratch
  4.1254 +	.body
  4.1255 +	br.call.sptk.many rp=do_notify_resume_user
  4.1256 +.ret15:	.restore sp
  4.1257 +	adds sp=16,sp				// pop scratch stack space
  4.1258 +	;;
  4.1259 +	ld8 r9=[sp]				// load new unat from sigscratch->scratch_unat
  4.1260 +	mov rp=loc0
  4.1261 +	;;
  4.1262 +	mov ar.unat=r9
  4.1263 +	mov ar.pfs=loc1
  4.1264 +	br.ret.sptk.many rp
  4.1265 +END(notify_resume_user)
  4.1266 +
  4.1267 +GLOBAL_ENTRY(sys_rt_sigsuspend)
  4.1268 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
  4.1269 +	alloc loc1=ar.pfs,8,2,3,0 // preserve all eight input regs in case of syscall restart!
  4.1270 +	mov r9=ar.unat
  4.1271 +	mov loc0=rp				// save return address
  4.1272 +	mov out0=in0				// mask
  4.1273 +	mov out1=in1				// sigsetsize
  4.1274 +	adds out2=8,sp				// out2=&sigscratch->ar_pfs
  4.1275 +	;;
  4.1276 +	.fframe 16
  4.1277 +	.spillpsp ar.unat, 16			// (note that offset is relative to psp+0x10!)
  4.1278 +	st8 [sp]=r9,-16				// allocate space for ar.unat and save it
  4.1279 +	st8 [out2]=loc1,-8			// save ar.pfs, out2=&sigscratch
  4.1280 +	.body
  4.1281 +	br.call.sptk.many rp=ia64_rt_sigsuspend
  4.1282 +.ret17:	.restore sp
  4.1283 +	adds sp=16,sp				// pop scratch stack space
  4.1284 +	;;
  4.1285 +	ld8 r9=[sp]				// load new unat from sw->caller_unat
  4.1286 +	mov rp=loc0
  4.1287 +	;;
  4.1288 +	mov ar.unat=r9
  4.1289 +	mov ar.pfs=loc1
  4.1290 +	br.ret.sptk.many rp
  4.1291 +END(sys_rt_sigsuspend)
  4.1292 +
  4.1293 +ENTRY(sys_rt_sigreturn)
  4.1294 +	PT_REGS_UNWIND_INFO(0)
  4.1295 +	/*
  4.1296 +	 * Allocate 8 input registers since ptrace() may clobber them
  4.1297 +	 */
  4.1298 +	alloc r2=ar.pfs,8,0,1,0
  4.1299 +	.prologue
  4.1300 +	PT_REGS_SAVES(16)
  4.1301 +	adds sp=-16,sp
  4.1302 +	.body
  4.1303 +	cmp.eq pNonSys,pSys=r0,r0		// sigreturn isn't a normal syscall...
  4.1304 +	;;
  4.1305 +	/*
  4.1306 +	 * leave_kernel() restores f6-f11 from pt_regs, but since the streamlined
  4.1307 +	 * syscall-entry path does not save them we save them here instead.  Note: we
  4.1308 +	 * don't need to save any other registers that are not saved by the stream-lined
  4.1309 +	 * syscall path, because restore_sigcontext() restores them.
  4.1310 +	 */
  4.1311 +	adds r16=PT(F6)+32,sp
  4.1312 +	adds r17=PT(F7)+32,sp
  4.1313 +	;;
  4.1314 + 	stf.spill [r16]=f6,32
  4.1315 + 	stf.spill [r17]=f7,32
  4.1316 +	;;
  4.1317 + 	stf.spill [r16]=f8,32
  4.1318 + 	stf.spill [r17]=f9,32
  4.1319 +	;;
  4.1320 + 	stf.spill [r16]=f10
  4.1321 + 	stf.spill [r17]=f11
  4.1322 +	adds out0=16,sp				// out0 = &sigscratch
  4.1323 +	br.call.sptk.many rp=ia64_rt_sigreturn
  4.1324 +.ret19:	.restore sp 0
  4.1325 +	adds sp=16,sp
  4.1326 +	;;
  4.1327 +	ld8 r9=[sp]				// load new ar.unat
  4.1328 +	mov.sptk b7=r8,ia64_leave_kernel
  4.1329 +	;;
  4.1330 +	mov ar.unat=r9
  4.1331 +	br.many b7
  4.1332 +END(sys_rt_sigreturn)
  4.1333 +#endif
  4.1334 +
  4.1335 +GLOBAL_ENTRY(ia64_prepare_handle_unaligned)
  4.1336 +	.prologue
  4.1337 +	/*
  4.1338 +	 * r16 = fake ar.pfs, we simply need to make sure privilege is still 0
  4.1339 +	 */
  4.1340 +	mov r16=r0
  4.1341 +	DO_SAVE_SWITCH_STACK
  4.1342 +	br.call.sptk.many rp=ia64_handle_unaligned	// stack frame setup in ivt
  4.1343 +.ret21:	.body
  4.1344 +	DO_LOAD_SWITCH_STACK
  4.1345 +	br.cond.sptk.many rp				// goes to ia64_leave_kernel
  4.1346 +END(ia64_prepare_handle_unaligned)
  4.1347 +
  4.1348 +#ifndef XEN
  4.1349 +	//
  4.1350 +	// unw_init_running(void (*callback)(info, arg), void *arg)
  4.1351 +	//
  4.1352 +#	define EXTRA_FRAME_SIZE	((UNW_FRAME_INFO_SIZE+15)&~15)
  4.1353 +
  4.1354 +GLOBAL_ENTRY(unw_init_running)
  4.1355 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(2)
  4.1356 +	alloc loc1=ar.pfs,2,3,3,0
  4.1357 +	;;
  4.1358 +	ld8 loc2=[in0],8
  4.1359 +	mov loc0=rp
  4.1360 +	mov r16=loc1
  4.1361 +	DO_SAVE_SWITCH_STACK
  4.1362 +	.body
  4.1363 +
  4.1364 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(2)
  4.1365 +	.fframe IA64_SWITCH_STACK_SIZE+EXTRA_FRAME_SIZE
  4.1366 +	SWITCH_STACK_SAVES(EXTRA_FRAME_SIZE)
  4.1367 +	adds sp=-EXTRA_FRAME_SIZE,sp
  4.1368 +	.body
  4.1369 +	;;
  4.1370 +	adds out0=16,sp				// &info
  4.1371 +	mov out1=r13				// current
  4.1372 +	adds out2=16+EXTRA_FRAME_SIZE,sp	// &switch_stack
  4.1373 +	br.call.sptk.many rp=unw_init_frame_info
  4.1374 +1:	adds out0=16,sp				// &info
  4.1375 +	mov b6=loc2
  4.1376 +	mov loc2=gp				// save gp across indirect function call
  4.1377 +	;;
  4.1378 +	ld8 gp=[in0]
  4.1379 +	mov out1=in1				// arg
  4.1380 +	br.call.sptk.many rp=b6			// invoke the callback function
  4.1381 +1:	mov gp=loc2				// restore gp
  4.1382 +
  4.1383 +	// For now, we don't allow changing registers from within
  4.1384 +	// unw_init_running; if we ever want to allow that, we'd
  4.1385 +	// have to do a load_switch_stack here:
  4.1386 +	.restore sp
  4.1387 +	adds sp=IA64_SWITCH_STACK_SIZE+EXTRA_FRAME_SIZE,sp
  4.1388 +
  4.1389 +	mov ar.pfs=loc1
  4.1390 +	mov rp=loc0
  4.1391 +	br.ret.sptk.many rp
  4.1392 +END(unw_init_running)
  4.1393 +
  4.1394 +	.rodata
  4.1395 +	.align 8
  4.1396 +	.globl sys_call_table
  4.1397 +sys_call_table:
  4.1398 +	data8 sys_ni_syscall		//  This must be sys_ni_syscall!  See ivt.S.
  4.1399 +	data8 sys_exit				// 1025
  4.1400 +	data8 sys_read
  4.1401 +	data8 sys_write
  4.1402 +	data8 sys_open
  4.1403 +	data8 sys_close
  4.1404 +	data8 sys_creat				// 1030
  4.1405 +	data8 sys_link
  4.1406 +	data8 sys_unlink
  4.1407 +	data8 ia64_execve
  4.1408 +	data8 sys_chdir
  4.1409 +	data8 sys_fchdir			// 1035
  4.1410 +	data8 sys_utimes
  4.1411 +	data8 sys_mknod
  4.1412 +	data8 sys_chmod
  4.1413 +	data8 sys_chown
  4.1414 +	data8 sys_lseek				// 1040
  4.1415 +	data8 sys_getpid
  4.1416 +	data8 sys_getppid
  4.1417 +	data8 sys_mount
  4.1418 +	data8 sys_umount
  4.1419 +	data8 sys_setuid			// 1045
  4.1420 +	data8 sys_getuid
  4.1421 +	data8 sys_geteuid
  4.1422 +	data8 sys_ptrace
  4.1423 +	data8 sys_access
  4.1424 +	data8 sys_sync				// 1050
  4.1425 +	data8 sys_fsync
  4.1426 +	data8 sys_fdatasync
  4.1427 +	data8 sys_kill
  4.1428 +	data8 sys_rename
  4.1429 +	data8 sys_mkdir				// 1055
  4.1430 +	data8 sys_rmdir
  4.1431 +	data8 sys_dup
  4.1432 +	data8 sys_pipe
  4.1433 +	data8 sys_times
  4.1434 +	data8 ia64_brk				// 1060
  4.1435 +	data8 sys_setgid
  4.1436 +	data8 sys_getgid
  4.1437 +	data8 sys_getegid
  4.1438 +	data8 sys_acct
  4.1439 +	data8 sys_ioctl				// 1065
  4.1440 +	data8 sys_fcntl
  4.1441 +	data8 sys_umask
  4.1442 +	data8 sys_chroot
  4.1443 +	data8 sys_ustat
  4.1444 +	data8 sys_dup2				// 1070
  4.1445 +	data8 sys_setreuid
  4.1446 +	data8 sys_setregid
  4.1447 +	data8 sys_getresuid
  4.1448 +	data8 sys_setresuid
  4.1449 +	data8 sys_getresgid			// 1075
  4.1450 +	data8 sys_setresgid
  4.1451 +	data8 sys_getgroups
  4.1452 +	data8 sys_setgroups
  4.1453 +	data8 sys_getpgid
  4.1454 +	data8 sys_setpgid			// 1080
  4.1455 +	data8 sys_setsid
  4.1456 +	data8 sys_getsid
  4.1457 +	data8 sys_sethostname
  4.1458 +	data8 sys_setrlimit
  4.1459 +	data8 sys_getrlimit			// 1085
  4.1460 +	data8 sys_getrusage
  4.1461 +	data8 sys_gettimeofday
  4.1462 +	data8 sys_settimeofday
  4.1463 +	data8 sys_select
  4.1464 +	data8 sys_poll				// 1090
  4.1465 +	data8 sys_symlink
  4.1466 +	data8 sys_readlink
  4.1467 +	data8 sys_uselib
  4.1468 +	data8 sys_swapon
  4.1469 +	data8 sys_swapoff			// 1095
  4.1470 +	data8 sys_reboot
  4.1471 +	data8 sys_truncate
  4.1472 +	data8 sys_ftruncate
  4.1473 +	data8 sys_fchmod
  4.1474 +	data8 sys_fchown			// 1100
  4.1475 +	data8 ia64_getpriority
  4.1476 +	data8 sys_setpriority
  4.1477 +	data8 sys_statfs
  4.1478 +	data8 sys_fstatfs
  4.1479 +	data8 sys_gettid			// 1105
  4.1480 +	data8 sys_semget
  4.1481 +	data8 sys_semop
  4.1482 +	data8 sys_semctl
  4.1483 +	data8 sys_msgget
  4.1484 +	data8 sys_msgsnd			// 1110
  4.1485 +	data8 sys_msgrcv
  4.1486 +	data8 sys_msgctl
  4.1487 +	data8 sys_shmget
  4.1488 +	data8 ia64_shmat
  4.1489 +	data8 sys_shmdt				// 1115
  4.1490 +	data8 sys_shmctl
  4.1491 +	data8 sys_syslog
  4.1492 +	data8 sys_setitimer
  4.1493 +	data8 sys_getitimer
  4.1494 +	data8 sys_ni_syscall			// 1120		/* was: ia64_oldstat */
  4.1495 +	data8 sys_ni_syscall					/* was: ia64_oldlstat */
  4.1496 +	data8 sys_ni_syscall					/* was: ia64_oldfstat */
  4.1497 +	data8 sys_vhangup
  4.1498 +	data8 sys_lchown
  4.1499 +	data8 sys_remap_file_pages		// 1125
  4.1500 +	data8 sys_wait4
  4.1501 +	data8 sys_sysinfo
  4.1502 +	data8 sys_clone
  4.1503 +	data8 sys_setdomainname
  4.1504 +	data8 sys_newuname			// 1130
  4.1505 +	data8 sys_adjtimex
  4.1506 +	data8 sys_ni_syscall					/* was: ia64_create_module */
  4.1507 +	data8 sys_init_module
  4.1508 +	data8 sys_delete_module
  4.1509 +	data8 sys_ni_syscall			// 1135		/* was: sys_get_kernel_syms */
  4.1510 +	data8 sys_ni_syscall					/* was: sys_query_module */
  4.1511 +	data8 sys_quotactl
  4.1512 +	data8 sys_bdflush
  4.1513 +	data8 sys_sysfs
  4.1514 +	data8 sys_personality			// 1140
  4.1515 +	data8 sys_ni_syscall		// sys_afs_syscall
  4.1516 +	data8 sys_setfsuid
  4.1517 +	data8 sys_setfsgid
  4.1518 +	data8 sys_getdents
  4.1519 +	data8 sys_flock				// 1145
  4.1520 +	data8 sys_readv
  4.1521 +	data8 sys_writev
  4.1522 +	data8 sys_pread64
  4.1523 +	data8 sys_pwrite64
  4.1524 +	data8 sys_sysctl			// 1150
  4.1525 +	data8 sys_mmap
  4.1526 +	data8 sys_munmap
  4.1527 +	data8 sys_mlock
  4.1528 +	data8 sys_mlockall
  4.1529 +	data8 sys_mprotect			// 1155
  4.1530 +	data8 ia64_mremap
  4.1531 +	data8 sys_msync
  4.1532 +	data8 sys_munlock
  4.1533 +	data8 sys_munlockall
  4.1534 +	data8 sys_sched_getparam		// 1160
  4.1535 +	data8 sys_sched_setparam
  4.1536 +	data8 sys_sched_getscheduler
  4.1537 +	data8 sys_sched_setscheduler
  4.1538 +	data8 sys_sched_yield
  4.1539 +	data8 sys_sched_get_priority_max	// 1165
  4.1540 +	data8 sys_sched_get_priority_min
  4.1541 +	data8 sys_sched_rr_get_interval
  4.1542 +	data8 sys_nanosleep
  4.1543 +	data8 sys_nfsservctl
  4.1544 +	data8 sys_prctl				// 1170
  4.1545 +	data8 sys_getpagesize
  4.1546 +	data8 sys_mmap2
  4.1547 +	data8 sys_pciconfig_read
  4.1548 +	data8 sys_pciconfig_write
  4.1549 +	data8 sys_perfmonctl			// 1175
  4.1550 +	data8 sys_sigaltstack
  4.1551 +	data8 sys_rt_sigaction
  4.1552 +	data8 sys_rt_sigpending
  4.1553 +	data8 sys_rt_sigprocmask
  4.1554 +	data8 sys_rt_sigqueueinfo		// 1180
  4.1555 +	data8 sys_rt_sigreturn
  4.1556 +	data8 sys_rt_sigsuspend
  4.1557 +	data8 sys_rt_sigtimedwait
  4.1558 +	data8 sys_getcwd
  4.1559 +	data8 sys_capget			// 1185
  4.1560 +	data8 sys_capset
  4.1561 +	data8 sys_sendfile64
  4.1562 +	data8 sys_ni_syscall		// sys_getpmsg (STREAMS)
  4.1563 +	data8 sys_ni_syscall		// sys_putpmsg (STREAMS)
  4.1564 +	data8 sys_socket			// 1190
  4.1565 +	data8 sys_bind
  4.1566 +	data8 sys_connect
  4.1567 +	data8 sys_listen
  4.1568 +	data8 sys_accept
  4.1569 +	data8 sys_getsockname			// 1195
  4.1570 +	data8 sys_getpeername
  4.1571 +	data8 sys_socketpair
  4.1572 +	data8 sys_send
  4.1573 +	data8 sys_sendto
  4.1574 +	data8 sys_recv				// 1200
  4.1575 +	data8 sys_recvfrom
  4.1576 +	data8 sys_shutdown
  4.1577 +	data8 sys_setsockopt
  4.1578 +	data8 sys_getsockopt
  4.1579 +	data8 sys_sendmsg			// 1205
  4.1580 +	data8 sys_recvmsg
  4.1581 +	data8 sys_pivot_root
  4.1582 +	data8 sys_mincore
  4.1583 +	data8 sys_madvise
  4.1584 +	data8 sys_newstat			// 1210
  4.1585 +	data8 sys_newlstat
  4.1586 +	data8 sys_newfstat
  4.1587 +	data8 sys_clone2
  4.1588 +	data8 sys_getdents64
  4.1589 +	data8 sys_getunwind			// 1215
  4.1590 +	data8 sys_readahead
  4.1591 +	data8 sys_setxattr
  4.1592 +	data8 sys_lsetxattr
  4.1593 +	data8 sys_fsetxattr
  4.1594 +	data8 sys_getxattr			// 1220
  4.1595 +	data8 sys_lgetxattr
  4.1596 +	data8 sys_fgetxattr
  4.1597 +	data8 sys_listxattr
  4.1598 +	data8 sys_llistxattr
  4.1599 +	data8 sys_flistxattr			// 1225
  4.1600 +	data8 sys_removexattr
  4.1601 +	data8 sys_lremovexattr
  4.1602 +	data8 sys_fremovexattr
  4.1603 +	data8 sys_tkill
  4.1604 +	data8 sys_futex				// 1230
  4.1605 +	data8 sys_sched_setaffinity
  4.1606 +	data8 sys_sched_getaffinity
  4.1607 +	data8 sys_set_tid_address
  4.1608 +	data8 sys_fadvise64_64
  4.1609 +	data8 sys_tgkill 			// 1235
  4.1610 +	data8 sys_exit_group
  4.1611 +	data8 sys_lookup_dcookie
  4.1612 +	data8 sys_io_setup
  4.1613 +	data8 sys_io_destroy
  4.1614 +	data8 sys_io_getevents			// 1240
  4.1615 +	data8 sys_io_submit
  4.1616 +	data8 sys_io_cancel
  4.1617 +	data8 sys_epoll_create
  4.1618 +	data8 sys_epoll_ctl
  4.1619 +	data8 sys_epoll_wait			// 1245
  4.1620 +	data8 sys_restart_syscall
  4.1621 +	data8 sys_semtimedop
  4.1622 +	data8 sys_timer_create
  4.1623 +	data8 sys_timer_settime
  4.1624 +	data8 sys_timer_gettime			// 1250
  4.1625 +	data8 sys_timer_getoverrun
  4.1626 +	data8 sys_timer_delete
  4.1627 +	data8 sys_clock_settime
  4.1628 +	data8 sys_clock_gettime
  4.1629 +	data8 sys_clock_getres			// 1255
  4.1630 +	data8 sys_clock_nanosleep
  4.1631 +	data8 sys_fstatfs64
  4.1632 +	data8 sys_statfs64
  4.1633 +	data8 sys_mbind
  4.1634 +	data8 sys_get_mempolicy			// 1260
  4.1635 +	data8 sys_set_mempolicy
  4.1636 +	data8 sys_mq_open
  4.1637 +	data8 sys_mq_unlink
  4.1638 +	data8 sys_mq_timedsend
  4.1639 +	data8 sys_mq_timedreceive		// 1265
  4.1640 +	data8 sys_mq_notify
  4.1641 +	data8 sys_mq_getsetattr
  4.1642 +	data8 sys_ni_syscall			// reserved for kexec_load
  4.1643 +	data8 sys_ni_syscall			// reserved for vserver
  4.1644 +	data8 sys_waitid			// 1270
  4.1645 +	data8 sys_add_key
  4.1646 +	data8 sys_request_key
  4.1647 +	data8 sys_keyctl
  4.1648 +	data8 sys_ni_syscall
  4.1649 +	data8 sys_ni_syscall			// 1275
  4.1650 +	data8 sys_ni_syscall
  4.1651 +	data8 sys_ni_syscall
  4.1652 +	data8 sys_ni_syscall
  4.1653 +	data8 sys_ni_syscall
  4.1654 +
  4.1655 +	.org sys_call_table + 8*NR_syscalls	// guard against failures to increase NR_syscalls
  4.1656 +#endif
     5.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     5.2 +++ b/xen/arch/ia64/linux-xen/entry.h	Mon Aug 08 12:21:23 2005 -0700
     5.3 @@ -0,0 +1,97 @@
     5.4 +#include <linux/config.h>
     5.5 +
     5.6 +/*
     5.7 + * Preserved registers that are shared between code in ivt.S and
     5.8 + * entry.S.  Be careful not to step on these!
     5.9 + */
    5.10 +#define PRED_LEAVE_SYSCALL	1 /* TRUE iff leave from syscall */
    5.11 +#define PRED_KERNEL_STACK	2 /* returning to kernel-stacks? */
    5.12 +#define PRED_USER_STACK		3 /* returning to user-stacks? */
    5.13 +#ifdef CONFIG_VTI
    5.14 +#define PRED_EMUL		2 /* Need to save r4-r7 for inst emulation */
    5.15 +#define PRED_NON_EMUL		3 /* No need to save r4-r7 for normal path */
    5.16 +#define PRED_BN0		6 /* Guest is in bank 0 */
    5.17 +#define PRED_BN1		7 /* Guest is in bank 1 */
    5.18 +#endif // CONFIG_VTI
    5.19 +#define PRED_SYSCALL		4 /* inside a system call? */
    5.20 +#define PRED_NON_SYSCALL	5 /* complement of PRED_SYSCALL */
    5.21 +
    5.22 +#ifdef __ASSEMBLY__
    5.23 +# define PASTE2(x,y)	x##y
    5.24 +# define PASTE(x,y)	PASTE2(x,y)
    5.25 +
    5.26 +# define pLvSys		PASTE(p,PRED_LEAVE_SYSCALL)
    5.27 +# define pKStk		PASTE(p,PRED_KERNEL_STACK)
    5.28 +# define pUStk		PASTE(p,PRED_USER_STACK)
    5.29 +#ifdef CONFIG_VTI
    5.30 +# define pEml		PASTE(p,PRED_EMUL)
    5.31 +# define pNonEml	PASTE(p,PRED_NON_EMUL)
    5.32 +# define pBN0		PASTE(p,PRED_BN0)
    5.33 +# define pBN1		PASTE(p,PRED_BN1)
    5.34 +#endif // CONFIG_VTI
    5.35 +# define pSys		PASTE(p,PRED_SYSCALL)
    5.36 +# define pNonSys	PASTE(p,PRED_NON_SYSCALL)
    5.37 +#endif
    5.38 +
    5.39 +#define PT(f)		(IA64_PT_REGS_##f##_OFFSET)
    5.40 +#define SW(f)		(IA64_SWITCH_STACK_##f##_OFFSET)
    5.41 +#ifdef CONFIG_VTI
    5.42 +#define VPD(f)      (VPD_##f##_START_OFFSET)
    5.43 +#endif // CONFIG_VTI
    5.44 +
    5.45 +#define PT_REGS_SAVES(off)			\
    5.46 +	.unwabi 3, 'i';				\
    5.47 +	.fframe IA64_PT_REGS_SIZE+16+(off);	\
    5.48 +	.spillsp rp, PT(CR_IIP)+16+(off);	\
    5.49 +	.spillsp ar.pfs, PT(CR_IFS)+16+(off);	\
    5.50 +	.spillsp ar.unat, PT(AR_UNAT)+16+(off);	\
    5.51 +	.spillsp ar.fpsr, PT(AR_FPSR)+16+(off);	\
    5.52 +	.spillsp pr, PT(PR)+16+(off);
    5.53 +
    5.54 +#define PT_REGS_UNWIND_INFO(off)		\
    5.55 +	.prologue;				\
    5.56 +	PT_REGS_SAVES(off);			\
    5.57 +	.body
    5.58 +
    5.59 +#define SWITCH_STACK_SAVES(off)							\
    5.60 +	.savesp ar.unat,SW(CALLER_UNAT)+16+(off);				\
    5.61 +	.savesp ar.fpsr,SW(AR_FPSR)+16+(off);					\
    5.62 +	.spillsp f2,SW(F2)+16+(off); .spillsp f3,SW(F3)+16+(off);		\
    5.63 +	.spillsp f4,SW(F4)+16+(off); .spillsp f5,SW(F5)+16+(off);		\
    5.64 +	.spillsp f16,SW(F16)+16+(off); .spillsp f17,SW(F17)+16+(off);		\
    5.65 +	.spillsp f18,SW(F18)+16+(off); .spillsp f19,SW(F19)+16+(off);		\
    5.66 +	.spillsp f20,SW(F20)+16+(off); .spillsp f21,SW(F21)+16+(off);		\
    5.67 +	.spillsp f22,SW(F22)+16+(off); .spillsp f23,SW(F23)+16+(off);		\
    5.68 +	.spillsp f24,SW(F24)+16+(off); .spillsp f25,SW(F25)+16+(off);		\
    5.69 +	.spillsp f26,SW(F26)+16+(off); .spillsp f27,SW(F27)+16+(off);		\
    5.70 +	.spillsp f28,SW(F28)+16+(off); .spillsp f29,SW(F29)+16+(off);		\
    5.71 +	.spillsp f30,SW(F30)+16+(off); .spillsp f31,SW(F31)+16+(off);		\
    5.72 +	.spillsp r4,SW(R4)+16+(off); .spillsp r5,SW(R5)+16+(off);		\
    5.73 +	.spillsp r6,SW(R6)+16+(off); .spillsp r7,SW(R7)+16+(off);		\
    5.74 +	.spillsp b0,SW(B0)+16+(off); .spillsp b1,SW(B1)+16+(off);		\
    5.75 +	.spillsp b2,SW(B2)+16+(off); .spillsp b3,SW(B3)+16+(off);		\
    5.76 +	.spillsp b4,SW(B4)+16+(off); .spillsp b5,SW(B5)+16+(off);		\
    5.77 +	.spillsp ar.pfs,SW(AR_PFS)+16+(off); .spillsp ar.lc,SW(AR_LC)+16+(off);	\
    5.78 +	.spillsp @priunat,SW(AR_UNAT)+16+(off);					\
    5.79 +	.spillsp ar.rnat,SW(AR_RNAT)+16+(off);					\
    5.80 +	.spillsp ar.bspstore,SW(AR_BSPSTORE)+16+(off);				\
    5.81 +	.spillsp pr,SW(PR)+16+(off))
    5.82 +
    5.83 +#define DO_SAVE_SWITCH_STACK			\
    5.84 +	movl r28=1f;				\
    5.85 +	;;					\
    5.86 +	.fframe IA64_SWITCH_STACK_SIZE;		\
    5.87 +	adds sp=-IA64_SWITCH_STACK_SIZE,sp;	\
    5.88 +	mov.ret.sptk b7=r28,1f;			\
    5.89 +	SWITCH_STACK_SAVES(0);			\
    5.90 +	br.cond.sptk.many save_switch_stack;	\
    5.91 +1:
    5.92 +
    5.93 +#define DO_LOAD_SWITCH_STACK			\
    5.94 +	movl r28=1f;				\
    5.95 +	;;					\
    5.96 +	invala;					\
    5.97 +	mov.ret.sptk b7=r28,1f;			\
    5.98 +	br.cond.sptk.many load_switch_stack;	\
    5.99 +1:	.restore sp;				\
   5.100 +	adds sp=IA64_SWITCH_STACK_SIZE,sp
     6.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     6.2 +++ b/xen/arch/ia64/linux-xen/head.S	Mon Aug 08 12:21:23 2005 -0700
     6.3 @@ -0,0 +1,1026 @@
     6.4 +/*
     6.5 + * Here is where the ball gets rolling as far as the kernel is concerned.
     6.6 + * When control is transferred to _start, the bootload has already
     6.7 + * loaded us to the correct address.  All that's left to do here is
     6.8 + * to set up the kernel's global pointer and jump to the kernel
     6.9 + * entry point.
    6.10 + *
    6.11 + * Copyright (C) 1998-2001, 2003, 2005 Hewlett-Packard Co
    6.12 + *	David Mosberger-Tang <davidm@hpl.hp.com>
    6.13 + *	Stephane Eranian <eranian@hpl.hp.com>
    6.14 + * Copyright (C) 1999 VA Linux Systems
    6.15 + * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
    6.16 + * Copyright (C) 1999 Intel Corp.
    6.17 + * Copyright (C) 1999 Asit Mallick <Asit.K.Mallick@intel.com>
    6.18 + * Copyright (C) 1999 Don Dugger <Don.Dugger@intel.com>
    6.19 + * Copyright (C) 2002 Fenghua Yu <fenghua.yu@intel.com>
    6.20 + *   -Optimize __ia64_save_fpu() and __ia64_load_fpu() for Itanium 2.
    6.21 + */
    6.22 +
    6.23 +#include <linux/config.h>
    6.24 +
    6.25 +#include <asm/asmmacro.h>
    6.26 +#include <asm/fpu.h>
    6.27 +#include <asm/kregs.h>
    6.28 +#include <asm/mmu_context.h>
    6.29 +#include <asm/offsets.h>
    6.30 +#include <asm/pal.h>
    6.31 +#include <asm/pgtable.h>
    6.32 +#include <asm/processor.h>
    6.33 +#include <asm/ptrace.h>
    6.34 +#include <asm/system.h>
    6.35 +
    6.36 +	.section __special_page_section,"ax"
    6.37 +
    6.38 +	.global empty_zero_page
    6.39 +empty_zero_page:
    6.40 +	.skip PAGE_SIZE
    6.41 +
    6.42 +	.global swapper_pg_dir
    6.43 +swapper_pg_dir:
    6.44 +	.skip PAGE_SIZE
    6.45 +
    6.46 +	.rodata
    6.47 +halt_msg:
    6.48 +	stringz "Halting kernel\n"
    6.49 +
    6.50 +	.text
    6.51 +
    6.52 +	.global start_ap
    6.53 +
    6.54 +	/*
    6.55 +	 * Start the kernel.  When the bootloader passes control to _start(), r28
    6.56 +	 * points to the address of the boot parameter area.  Execution reaches
    6.57 +	 * here in physical mode.
    6.58 +	 */
    6.59 +GLOBAL_ENTRY(_start)
    6.60 +start_ap:
    6.61 +	.prologue
    6.62 +	.save rp, r0		// terminate unwind chain with a NULL rp
    6.63 +	.body
    6.64 +
    6.65 +	rsm psr.i | psr.ic
    6.66 +	;;
    6.67 +	srlz.i
    6.68 +	;;
    6.69 +	/*
    6.70 +	 * Initialize kernel region registers:
    6.71 +	 *	rr[0]: VHPT enabled, page size = PAGE_SHIFT
    6.72 +	 *	rr[1]: VHPT enabled, page size = PAGE_SHIFT
    6.73 +	 *	rr[2]: VHPT enabled, page size = PAGE_SHIFT
    6.74 +	 *	rr[3]: VHPT enabled, page size = PAGE_SHIFT
    6.75 +	 *	rr[4]: VHPT enabled, page size = PAGE_SHIFT
    6.76 +	 *	rr[5]: VHPT enabled, page size = PAGE_SHIFT
    6.77 +	 *	rr[6]: VHPT disabled, page size = IA64_GRANULE_SHIFT
    6.78 +	 *	rr[7]: VHPT disabled, page size = IA64_GRANULE_SHIFT
    6.79 +	 * We initialize all of them to prevent inadvertently assuming
    6.80 +	 * something about the state of address translation early in boot.
    6.81 +	 */
    6.82 +	movl r6=((ia64_rid(IA64_REGION_ID_KERNEL, (0<<61)) << 8) | (PAGE_SHIFT << 2) | 1)
    6.83 +	movl r7=(0<<61)
    6.84 +	movl r8=((ia64_rid(IA64_REGION_ID_KERNEL, (1<<61)) << 8) | (PAGE_SHIFT << 2) | 1)
    6.85 +	movl r9=(1<<61)
    6.86 +	movl r10=((ia64_rid(IA64_REGION_ID_KERNEL, (2<<61)) << 8) | (PAGE_SHIFT << 2) | 1)
    6.87 +	movl r11=(2<<61)
    6.88 +	movl r12=((ia64_rid(IA64_REGION_ID_KERNEL, (3<<61)) << 8) | (PAGE_SHIFT << 2) | 1)
    6.89 +	movl r13=(3<<61)
    6.90 +	movl r14=((ia64_rid(IA64_REGION_ID_KERNEL, (4<<61)) << 8) | (PAGE_SHIFT << 2) | 1)
    6.91 +	movl r15=(4<<61)
    6.92 +	movl r16=((ia64_rid(IA64_REGION_ID_KERNEL, (5<<61)) << 8) | (PAGE_SHIFT << 2) | 1)
    6.93 +	movl r17=(5<<61)
    6.94 +	movl r18=((ia64_rid(IA64_REGION_ID_KERNEL, (6<<61)) << 8) | (IA64_GRANULE_SHIFT << 2))
    6.95 +	movl r19=(6<<61)
    6.96 +	movl r20=((ia64_rid(IA64_REGION_ID_KERNEL, (7<<61)) << 8) | (IA64_GRANULE_SHIFT << 2))
    6.97 +	movl r21=(7<<61)
    6.98 +	;;
    6.99 +	mov rr[r7]=r6
   6.100 +	mov rr[r9]=r8
   6.101 +	mov rr[r11]=r10
   6.102 +	mov rr[r13]=r12
   6.103 +	mov rr[r15]=r14
   6.104 +	mov rr[r17]=r16
   6.105 +	mov rr[r19]=r18
   6.106 +	mov rr[r21]=r20
   6.107 +	;;
   6.108 +	/*
   6.109 +	 * Now pin mappings into the TLB for kernel text and data
   6.110 +	 */
   6.111 +	mov r18=KERNEL_TR_PAGE_SHIFT<<2
   6.112 +	movl r17=KERNEL_START
   6.113 +	;;
   6.114 +	mov cr.itir=r18
   6.115 +	mov cr.ifa=r17
   6.116 +	mov r16=IA64_TR_KERNEL
   6.117 +	mov r3=ip
   6.118 +	movl r18=PAGE_KERNEL
   6.119 +	;;
   6.120 +	dep r2=0,r3,0,KERNEL_TR_PAGE_SHIFT
   6.121 +	;;
   6.122 +	or r18=r2,r18
   6.123 +	;;
   6.124 +	srlz.i
   6.125 +	;;
   6.126 +	itr.i itr[r16]=r18
   6.127 +	;;
   6.128 +	itr.d dtr[r16]=r18
   6.129 +	;;
   6.130 +	srlz.i
   6.131 +
   6.132 +	/*
   6.133 +	 * Switch into virtual mode:
   6.134 +	 */
   6.135 +#ifdef CONFIG_VTI
   6.136 +	movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH \
   6.137 +		  |IA64_PSR_DI)
   6.138 +#else // CONFIG_VTI
   6.139 +	movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN \
   6.140 +		  |IA64_PSR_DI)
   6.141 +#endif // CONFIG_VTI
   6.142 +	;;
   6.143 +	mov cr.ipsr=r16
   6.144 +	movl r17=1f
   6.145 +	;;
   6.146 +	mov cr.iip=r17
   6.147 +	mov cr.ifs=r0
   6.148 +	;;
   6.149 +	rfi
   6.150 +	;;
   6.151 +1:	// now we are in virtual mode
   6.152 +
   6.153 +	// set IVT entry point---can't access I/O ports without it
   6.154 +#ifdef CONFIG_VTI
   6.155 +    movl r3=vmx_ia64_ivt
   6.156 +#else // CONFIG_VTI
   6.157 +	movl r3=ia64_ivt
   6.158 +#endif // CONFIG_VTI
   6.159 +	;;
   6.160 +	mov cr.iva=r3
   6.161 +	movl r2=FPSR_DEFAULT
   6.162 +	;;
   6.163 +	srlz.i
   6.164 +	movl gp=__gp
   6.165 +
   6.166 +	mov ar.fpsr=r2
   6.167 +	;;
   6.168 +
   6.169 +#define isAP	p2	// are we an Application Processor?
   6.170 +#define isBP	p3	// are we the Bootstrap Processor?
   6.171 +
   6.172 +#ifdef CONFIG_SMP
   6.173 +	/*
   6.174 +	 * Find the init_task for the currently booting CPU.  At poweron, and in
   6.175 +	 * UP mode, task_for_booting_cpu is NULL.
   6.176 +	 */
   6.177 +	movl r3=task_for_booting_cpu
   6.178 + 	;;
   6.179 +	ld8 r3=[r3]
   6.180 +	movl r2=init_task
   6.181 +	;;
   6.182 +	cmp.eq isBP,isAP=r3,r0
   6.183 +	;;
   6.184 +(isAP)	mov r2=r3
   6.185 +#else
   6.186 +	movl r2=init_task
   6.187 +	cmp.eq isBP,isAP=r0,r0
   6.188 +#endif
   6.189 +	;;
   6.190 +	tpa r3=r2		// r3 == phys addr of task struct
   6.191 +	mov r16=-1
   6.192 +(isBP)	br.cond.dpnt .load_current // BP stack is on region 5 --- no need to map it
   6.193 +
   6.194 +	// load mapping for stack (virtaddr in r2, physaddr in r3)
   6.195 +	rsm psr.ic
   6.196 +	movl r17=PAGE_KERNEL
   6.197 +	;;
   6.198 +	srlz.d
   6.199 +	dep r18=0,r3,0,12
   6.200 +	;;
   6.201 +	or r18=r17,r18
   6.202 +#ifdef XEN
   6.203 +	dep r2=-1,r3,60,4	// IMVA of task
   6.204 +#else
   6.205 +	dep r2=-1,r3,61,3	// IMVA of task
   6.206 +#endif
   6.207 +	;;
   6.208 +	mov r17=rr[r2]
   6.209 +	shr.u r16=r3,IA64_GRANULE_SHIFT
   6.210 +	;;
   6.211 +	dep r17=0,r17,8,24
   6.212 +	;;
   6.213 +	mov cr.itir=r17
   6.214 +	mov cr.ifa=r2
   6.215 +
   6.216 +	mov r19=IA64_TR_CURRENT_STACK
   6.217 +	;;
   6.218 +	itr.d dtr[r19]=r18
   6.219 +	;;
   6.220 +	ssm psr.ic
   6.221 +	srlz.d
   6.222 +  	;;
   6.223 +
   6.224 +.load_current:
   6.225 +	// load the "current" pointer (r13) and ar.k6 with the current task
   6.226 +#ifdef CONFIG_VTI
   6.227 +	mov r21=r2		// virtual address
   6.228 +	;;
   6.229 +	bsw.1
   6.230 +	;;
   6.231 +#else // CONFIG_VTI
   6.232 +	mov IA64_KR(CURRENT)=r2		// virtual address
   6.233 +	mov IA64_KR(CURRENT_STACK)=r16
   6.234 +#endif // CONFIG_VTI
   6.235 +	mov r13=r2
   6.236 +	/*
   6.237 +	 * Reserve space at the top of the stack for "struct pt_regs".  Kernel threads
   6.238 +	 * don't store interesting values in that structure, but the space still needs
   6.239 +	 * to be there because time-critical stuff such as the context switching can
   6.240 +	 * be implemented more efficiently (for example, __switch_to()
   6.241 +	 * always sets the psr.dfh bit of the task it is switching to).
   6.242 +	 */
   6.243 +	addl r12=IA64_STK_OFFSET-IA64_PT_REGS_SIZE-16,r2
   6.244 +	addl r2=IA64_RBS_OFFSET,r2	// initialize the RSE
   6.245 +	mov ar.rsc=0		// place RSE in enforced lazy mode
   6.246 +	;;
   6.247 +	loadrs			// clear the dirty partition
   6.248 +	;;
   6.249 +	mov ar.bspstore=r2	// establish the new RSE stack
   6.250 +	;;
   6.251 +	mov ar.rsc=0x3		// place RSE in eager mode
   6.252 +
   6.253 +#ifdef XEN
   6.254 +(isBP)	dep r28=-1,r28,60,4	// make address virtual
   6.255 +#else
   6.256 +(isBP)	dep r28=-1,r28,61,3	// make address virtual
   6.257 +#endif
   6.258 +(isBP)	movl r2=ia64_boot_param
   6.259 +	;;
   6.260 +(isBP)	st8 [r2]=r28		// save the address of the boot param area passed by the bootloader
   6.261 +
   6.262 +#ifdef CONFIG_SMP
   6.263 +(isAP)	br.call.sptk.many rp=start_secondary
   6.264 +.ret0:
   6.265 +(isAP)	br.cond.sptk self
   6.266 +#endif
   6.267 +
   6.268 +	// This is executed by the bootstrap processor (bsp) only:
   6.269 +
   6.270 +#ifdef CONFIG_IA64_FW_EMU
   6.271 +	// initialize PAL & SAL emulator:
   6.272 +	br.call.sptk.many rp=sys_fw_init
   6.273 +.ret1:
   6.274 +#endif
   6.275 +	br.call.sptk.many rp=start_kernel
   6.276 +.ret2:	addl r3=@ltoff(halt_msg),gp
   6.277 +	;;
   6.278 +	alloc r2=ar.pfs,8,0,2,0
   6.279 +	;;
   6.280 +	ld8 out0=[r3]
   6.281 +	br.call.sptk.many b0=console_print
   6.282 +
   6.283 +self:	hint @pause
   6.284 +	;;
   6.285 +	br.sptk.many self		// endless loop
   6.286 +	;;
   6.287 +END(_start)
   6.288 +
   6.289 +GLOBAL_ENTRY(ia64_save_debug_regs)
   6.290 +	alloc r16=ar.pfs,1,0,0,0
   6.291 +	mov r20=ar.lc			// preserve ar.lc
   6.292 +	mov ar.lc=IA64_NUM_DBG_REGS-1
   6.293 +	mov r18=0
   6.294 +	add r19=IA64_NUM_DBG_REGS*8,in0
   6.295 +	;;
   6.296 +1:	mov r16=dbr[r18]
   6.297 +#ifdef CONFIG_ITANIUM
   6.298 +	;;
   6.299 +	srlz.d
   6.300 +#endif
   6.301 +	mov r17=ibr[r18]
   6.302 +	add r18=1,r18
   6.303 +	;;
   6.304 +	st8.nta [in0]=r16,8
   6.305 +	st8.nta [r19]=r17,8
   6.306 +	br.cloop.sptk.many 1b
   6.307 +	;;
   6.308 +	mov ar.lc=r20			// restore ar.lc
   6.309 +	br.ret.sptk.many rp
   6.310 +END(ia64_save_debug_regs)
   6.311 +
   6.312 +GLOBAL_ENTRY(ia64_load_debug_regs)
   6.313 +	alloc r16=ar.pfs,1,0,0,0
   6.314 +	lfetch.nta [in0]
   6.315 +	mov r20=ar.lc			// preserve ar.lc
   6.316 +	add r19=IA64_NUM_DBG_REGS*8,in0
   6.317 +	mov ar.lc=IA64_NUM_DBG_REGS-1
   6.318 +	mov r18=-1
   6.319 +	;;
   6.320 +1:	ld8.nta r16=[in0],8
   6.321 +	ld8.nta r17=[r19],8
   6.322 +	add r18=1,r18
   6.323 +	;;
   6.324 +	mov dbr[r18]=r16
   6.325 +#ifdef CONFIG_ITANIUM
   6.326 +	;;
   6.327 +	srlz.d				// Errata 132 (NoFix status)
   6.328 +#endif
   6.329 +	mov ibr[r18]=r17
   6.330 +	br.cloop.sptk.many 1b
   6.331 +	;;
   6.332 +	mov ar.lc=r20			// restore ar.lc
   6.333 +	br.ret.sptk.many rp
   6.334 +END(ia64_load_debug_regs)
   6.335 +
   6.336 +GLOBAL_ENTRY(__ia64_save_fpu)
   6.337 +	alloc r2=ar.pfs,1,4,0,0
   6.338 +	adds loc0=96*16-16,in0
   6.339 +	adds loc1=96*16-16-128,in0
   6.340 +	;;
   6.341 +	stf.spill.nta [loc0]=f127,-256
   6.342 +	stf.spill.nta [loc1]=f119,-256
   6.343 +	;;
   6.344 +	stf.spill.nta [loc0]=f111,-256
   6.345 +	stf.spill.nta [loc1]=f103,-256
   6.346 +	;;
   6.347 +	stf.spill.nta [loc0]=f95,-256
   6.348 +	stf.spill.nta [loc1]=f87,-256
   6.349 +	;;
   6.350 +	stf.spill.nta [loc0]=f79,-256
   6.351 +	stf.spill.nta [loc1]=f71,-256
   6.352 +	;;
   6.353 +	stf.spill.nta [loc0]=f63,-256
   6.354 +	stf.spill.nta [loc1]=f55,-256
   6.355 +	adds loc2=96*16-32,in0
   6.356 +	;;
   6.357 +	stf.spill.nta [loc0]=f47,-256
   6.358 +	stf.spill.nta [loc1]=f39,-256
   6.359 +	adds loc3=96*16-32-128,in0
   6.360 +	;;
   6.361 +	stf.spill.nta [loc2]=f126,-256
   6.362 +	stf.spill.nta [loc3]=f118,-256
   6.363 +	;;
   6.364 +	stf.spill.nta [loc2]=f110,-256
   6.365 +	stf.spill.nta [loc3]=f102,-256
   6.366 +	;;
   6.367 +	stf.spill.nta [loc2]=f94,-256
   6.368 +	stf.spill.nta [loc3]=f86,-256
   6.369 +	;;
   6.370 +	stf.spill.nta [loc2]=f78,-256
   6.371 +	stf.spill.nta [loc3]=f70,-256
   6.372 +	;;
   6.373 +	stf.spill.nta [loc2]=f62,-256
   6.374 +	stf.spill.nta [loc3]=f54,-256
   6.375 +	adds loc0=96*16-48,in0
   6.376 +	;;
   6.377 +	stf.spill.nta [loc2]=f46,-256
   6.378 +	stf.spill.nta [loc3]=f38,-256
   6.379 +	adds loc1=96*16-48-128,in0
   6.380 +	;;
   6.381 +	stf.spill.nta [loc0]=f125,-256
   6.382 +	stf.spill.nta [loc1]=f117,-256
   6.383 +	;;
   6.384 +	stf.spill.nta [loc0]=f109,-256
   6.385 +	stf.spill.nta [loc1]=f101,-256
   6.386 +	;;
   6.387 +	stf.spill.nta [loc0]=f93,-256
   6.388 +	stf.spill.nta [loc1]=f85,-256
   6.389 +	;;
   6.390 +	stf.spill.nta [loc0]=f77,-256
   6.391 +	stf.spill.nta [loc1]=f69,-256
   6.392 +	;;
   6.393 +	stf.spill.nta [loc0]=f61,-256
   6.394 +	stf.spill.nta [loc1]=f53,-256
   6.395 +	adds loc2=96*16-64,in0
   6.396 +	;;
   6.397 +	stf.spill.nta [loc0]=f45,-256
   6.398 +	stf.spill.nta [loc1]=f37,-256
   6.399 +	adds loc3=96*16-64-128,in0
   6.400 +	;;
   6.401 +	stf.spill.nta [loc2]=f124,-256
   6.402 +	stf.spill.nta [loc3]=f116,-256
   6.403 +	;;
   6.404 +	stf.spill.nta [loc2]=f108,-256
   6.405 +	stf.spill.nta [loc3]=f100,-256
   6.406 +	;;
   6.407 +	stf.spill.nta [loc2]=f92,-256
   6.408 +	stf.spill.nta [loc3]=f84,-256
   6.409 +	;;
   6.410 +	stf.spill.nta [loc2]=f76,-256
   6.411 +	stf.spill.nta [loc3]=f68,-256
   6.412 +	;;
   6.413 +	stf.spill.nta [loc2]=f60,-256
   6.414 +	stf.spill.nta [loc3]=f52,-256
   6.415 +	adds loc0=96*16-80,in0
   6.416 +	;;
   6.417 +	stf.spill.nta [loc2]=f44,-256
   6.418 +	stf.spill.nta [loc3]=f36,-256
   6.419 +	adds loc1=96*16-80-128,in0
   6.420 +	;;
   6.421 +	stf.spill.nta [loc0]=f123,-256
   6.422 +	stf.spill.nta [loc1]=f115,-256
   6.423 +	;;
   6.424 +	stf.spill.nta [loc0]=f107,-256
   6.425 +	stf.spill.nta [loc1]=f99,-256
   6.426 +	;;
   6.427 +	stf.spill.nta [loc0]=f91,-256
   6.428 +	stf.spill.nta [loc1]=f83,-256
   6.429 +	;;
   6.430 +	stf.spill.nta [loc0]=f75,-256
   6.431 +	stf.spill.nta [loc1]=f67,-256
   6.432 +	;;
   6.433 +	stf.spill.nta [loc0]=f59,-256
   6.434 +	stf.spill.nta [loc1]=f51,-256
   6.435 +	adds loc2=96*16-96,in0
   6.436 +	;;
   6.437 +	stf.spill.nta [loc0]=f43,-256
   6.438 +	stf.spill.nta [loc1]=f35,-256
   6.439 +	adds loc3=96*16-96-128,in0
   6.440 +	;;
   6.441 +	stf.spill.nta [loc2]=f122,-256
   6.442 +	stf.spill.nta [loc3]=f114,-256
   6.443 +	;;
   6.444 +	stf.spill.nta [loc2]=f106,-256
   6.445 +	stf.spill.nta [loc3]=f98,-256
   6.446 +	;;
   6.447 +	stf.spill.nta [loc2]=f90,-256
   6.448 +	stf.spill.nta [loc3]=f82,-256
   6.449 +	;;
   6.450 +	stf.spill.nta [loc2]=f74,-256
   6.451 +	stf.spill.nta [loc3]=f66,-256
   6.452 +	;;
   6.453 +	stf.spill.nta [loc2]=f58,-256
   6.454 +	stf.spill.nta [loc3]=f50,-256
   6.455 +	adds loc0=96*16-112,in0
   6.456 +	;;
   6.457 +	stf.spill.nta [loc2]=f42,-256
   6.458 +	stf.spill.nta [loc3]=f34,-256
   6.459 +	adds loc1=96*16-112-128,in0
   6.460 +	;;
   6.461 +	stf.spill.nta [loc0]=f121,-256
   6.462 +	stf.spill.nta [loc1]=f113,-256
   6.463 +	;;
   6.464 +	stf.spill.nta [loc0]=f105,-256
   6.465 +	stf.spill.nta [loc1]=f97,-256
   6.466 +	;;
   6.467 +	stf.spill.nta [loc0]=f89,-256
   6.468 +	stf.spill.nta [loc1]=f81,-256
   6.469 +	;;
   6.470 +	stf.spill.nta [loc0]=f73,-256
   6.471 +	stf.spill.nta [loc1]=f65,-256
   6.472 +	;;
   6.473 +	stf.spill.nta [loc0]=f57,-256
   6.474 +	stf.spill.nta [loc1]=f49,-256
   6.475 +	adds loc2=96*16-128,in0
   6.476 +	;;
   6.477 +	stf.spill.nta [loc0]=f41,-256
   6.478 +	stf.spill.nta [loc1]=f33,-256
   6.479 +	adds loc3=96*16-128-128,in0
   6.480 +	;;
   6.481 +	stf.spill.nta [loc2]=f120,-256
   6.482 +	stf.spill.nta [loc3]=f112,-256
   6.483 +	;;
   6.484 +	stf.spill.nta [loc2]=f104,-256
   6.485 +	stf.spill.nta [loc3]=f96,-256
   6.486 +	;;
   6.487 +	stf.spill.nta [loc2]=f88,-256
   6.488 +	stf.spill.nta [loc3]=f80,-256
   6.489 +	;;
   6.490 +	stf.spill.nta [loc2]=f72,-256
   6.491 +	stf.spill.nta [loc3]=f64,-256
   6.492 +	;;
   6.493 +	stf.spill.nta [loc2]=f56,-256
   6.494 +	stf.spill.nta [loc3]=f48,-256
   6.495 +	;;
   6.496 +	stf.spill.nta [loc2]=f40
   6.497 +	stf.spill.nta [loc3]=f32
   6.498 +	br.ret.sptk.many rp
   6.499 +END(__ia64_save_fpu)
   6.500 +
   6.501 +GLOBAL_ENTRY(__ia64_load_fpu)
   6.502 +	alloc r2=ar.pfs,1,2,0,0
   6.503 +	adds r3=128,in0
   6.504 +	adds r14=256,in0
   6.505 +	adds r15=384,in0
   6.506 +	mov loc0=512
   6.507 +	mov loc1=-1024+16
   6.508 +	;;
   6.509 +	ldf.fill.nta f32=[in0],loc0
   6.510 +	ldf.fill.nta f40=[ r3],loc0
   6.511 +	ldf.fill.nta f48=[r14],loc0
   6.512 +	ldf.fill.nta f56=[r15],loc0
   6.513 +	;;
   6.514 +	ldf.fill.nta f64=[in0],loc0
   6.515 +	ldf.fill.nta f72=[ r3],loc0
   6.516 +	ldf.fill.nta f80=[r14],loc0
   6.517 +	ldf.fill.nta f88=[r15],loc0
   6.518 +	;;
   6.519 +	ldf.fill.nta f96=[in0],loc1
   6.520 +	ldf.fill.nta f104=[ r3],loc1
   6.521 +	ldf.fill.nta f112=[r14],loc1
   6.522 +	ldf.fill.nta f120=[r15],loc1
   6.523 +	;;
   6.524 +	ldf.fill.nta f33=[in0],loc0
   6.525 +	ldf.fill.nta f41=[ r3],loc0
   6.526 +	ldf.fill.nta f49=[r14],loc0
   6.527 +	ldf.fill.nta f57=[r15],loc0
   6.528 +	;;
   6.529 +	ldf.fill.nta f65=[in0],loc0
   6.530 +	ldf.fill.nta f73=[ r3],loc0
   6.531 +	ldf.fill.nta f81=[r14],loc0
   6.532 +	ldf.fill.nta f89=[r15],loc0
   6.533 +	;;
   6.534 +	ldf.fill.nta f97=[in0],loc1
   6.535 +	ldf.fill.nta f105=[ r3],loc1
   6.536 +	ldf.fill.nta f113=[r14],loc1
   6.537 +	ldf.fill.nta f121=[r15],loc1
   6.538 +	;;
   6.539 +	ldf.fill.nta f34=[in0],loc0
   6.540 +	ldf.fill.nta f42=[ r3],loc0
   6.541 +	ldf.fill.nta f50=[r14],loc0
   6.542 +	ldf.fill.nta f58=[r15],loc0
   6.543 +	;;
   6.544 +	ldf.fill.nta f66=[in0],loc0
   6.545 +	ldf.fill.nta f74=[ r3],loc0
   6.546 +	ldf.fill.nta f82=[r14],loc0
   6.547 +	ldf.fill.nta f90=[r15],loc0
   6.548 +	;;
   6.549 +	ldf.fill.nta f98=[in0],loc1
   6.550 +	ldf.fill.nta f106=[ r3],loc1
   6.551 +	ldf.fill.nta f114=[r14],loc1
   6.552 +	ldf.fill.nta f122=[r15],loc1
   6.553 +	;;
   6.554 +	ldf.fill.nta f35=[in0],loc0
   6.555 +	ldf.fill.nta f43=[ r3],loc0
   6.556 +	ldf.fill.nta f51=[r14],loc0
   6.557 +	ldf.fill.nta f59=[r15],loc0
   6.558 +	;;
   6.559 +	ldf.fill.nta f67=[in0],loc0
   6.560 +	ldf.fill.nta f75=[ r3],loc0
   6.561 +	ldf.fill.nta f83=[r14],loc0
   6.562 +	ldf.fill.nta f91=[r15],loc0
   6.563 +	;;
   6.564 +	ldf.fill.nta f99=[in0],loc1
   6.565 +	ldf.fill.nta f107=[ r3],loc1
   6.566 +	ldf.fill.nta f115=[r14],loc1
   6.567 +	ldf.fill.nta f123=[r15],loc1
   6.568 +	;;
   6.569 +	ldf.fill.nta f36=[in0],loc0
   6.570 +	ldf.fill.nta f44=[ r3],loc0
   6.571 +	ldf.fill.nta f52=[r14],loc0
   6.572 +	ldf.fill.nta f60=[r15],loc0
   6.573 +	;;
   6.574 +	ldf.fill.nta f68=[in0],loc0
   6.575 +	ldf.fill.nta f76=[ r3],loc0
   6.576 +	ldf.fill.nta f84=[r14],loc0
   6.577 +	ldf.fill.nta f92=[r15],loc0
   6.578 +	;;
   6.579 +	ldf.fill.nta f100=[in0],loc1
   6.580 +	ldf.fill.nta f108=[ r3],loc1
   6.581 +	ldf.fill.nta f116=[r14],loc1
   6.582 +	ldf.fill.nta f124=[r15],loc1
   6.583 +	;;
   6.584 +	ldf.fill.nta f37=[in0],loc0
   6.585 +	ldf.fill.nta f45=[ r3],loc0
   6.586 +	ldf.fill.nta f53=[r14],loc0
   6.587 +	ldf.fill.nta f61=[r15],loc0
   6.588 +	;;
   6.589 +	ldf.fill.nta f69=[in0],loc0
   6.590 +	ldf.fill.nta f77=[ r3],loc0
   6.591 +	ldf.fill.nta f85=[r14],loc0
   6.592 +	ldf.fill.nta f93=[r15],loc0
   6.593 +	;;
   6.594 +	ldf.fill.nta f101=[in0],loc1
   6.595 +	ldf.fill.nta f109=[ r3],loc1
   6.596 +	ldf.fill.nta f117=[r14],loc1
   6.597 +	ldf.fill.nta f125=[r15],loc1
   6.598 +	;;
   6.599 +	ldf.fill.nta f38 =[in0],loc0
   6.600 +	ldf.fill.nta f46 =[ r3],loc0
   6.601 +	ldf.fill.nta f54 =[r14],loc0
   6.602 +	ldf.fill.nta f62 =[r15],loc0
   6.603 +	;;
   6.604 +	ldf.fill.nta f70 =[in0],loc0
   6.605 +	ldf.fill.nta f78 =[ r3],loc0
   6.606 +	ldf.fill.nta f86 =[r14],loc0
   6.607 +	ldf.fill.nta f94 =[r15],loc0
   6.608 +	;;
   6.609 +	ldf.fill.nta f102=[in0],loc1
   6.610 +	ldf.fill.nta f110=[ r3],loc1
   6.611 +	ldf.fill.nta f118=[r14],loc1
   6.612 +	ldf.fill.nta f126=[r15],loc1
   6.613 +	;;
   6.614 +	ldf.fill.nta f39 =[in0],loc0
   6.615 +	ldf.fill.nta f47 =[ r3],loc0
   6.616 +	ldf.fill.nta f55 =[r14],loc0
   6.617 +	ldf.fill.nta f63 =[r15],loc0
   6.618 +	;;
   6.619 +	ldf.fill.nta f71 =[in0],loc0
   6.620 +	ldf.fill.nta f79 =[ r3],loc0
   6.621 +	ldf.fill.nta f87 =[r14],loc0
   6.622 +	ldf.fill.nta f95 =[r15],loc0
   6.623 +	;;
   6.624 +	ldf.fill.nta f103=[in0]
   6.625 +	ldf.fill.nta f111=[ r3]
   6.626 +	ldf.fill.nta f119=[r14]
   6.627 +	ldf.fill.nta f127=[r15]
   6.628 +	br.ret.sptk.many rp
   6.629 +END(__ia64_load_fpu)
   6.630 +
   6.631 +GLOBAL_ENTRY(__ia64_init_fpu)
   6.632 +	stf.spill [sp]=f0		// M3
   6.633 +	mov	 f32=f0			// F
   6.634 +	nop.b	 0
   6.635 +
   6.636 +	ldfps	 f33,f34=[sp]		// M0
   6.637 +	ldfps	 f35,f36=[sp]		// M1
   6.638 +	mov      f37=f0			// F
   6.639 +	;;
   6.640 +
   6.641 +	setf.s	 f38=r0			// M2
   6.642 +	setf.s	 f39=r0			// M3
   6.643 +	mov      f40=f0			// F
   6.644 +
   6.645 +	ldfps	 f41,f42=[sp]		// M0
   6.646 +	ldfps	 f43,f44=[sp]		// M1
   6.647 +	mov      f45=f0			// F
   6.648 +
   6.649 +	setf.s	 f46=r0			// M2
   6.650 +	setf.s	 f47=r0			// M3
   6.651 +	mov      f48=f0			// F
   6.652 +
   6.653 +	ldfps	 f49,f50=[sp]		// M0
   6.654 +	ldfps	 f51,f52=[sp]		// M1
   6.655 +	mov      f53=f0			// F
   6.656 +
   6.657 +	setf.s	 f54=r0			// M2
   6.658 +	setf.s	 f55=r0			// M3
   6.659 +	mov      f56=f0			// F
   6.660 +
   6.661 +	ldfps	 f57,f58=[sp]		// M0
   6.662 +	ldfps	 f59,f60=[sp]		// M1
   6.663 +	mov      f61=f0			// F
   6.664 +
   6.665 +	setf.s	 f62=r0			// M2
   6.666 +	setf.s	 f63=r0			// M3
   6.667 +	mov      f64=f0			// F
   6.668 +
   6.669 +	ldfps	 f65,f66=[sp]		// M0
   6.670 +	ldfps	 f67,f68=[sp]		// M1
   6.671 +	mov      f69=f0			// F
   6.672 +
   6.673 +	setf.s	 f70=r0			// M2
   6.674 +	setf.s	 f71=r0			// M3
   6.675 +	mov      f72=f0			// F
   6.676 +
   6.677 +	ldfps	 f73,f74=[sp]		// M0
   6.678 +	ldfps	 f75,f76=[sp]		// M1
   6.679 +	mov      f77=f0			// F
   6.680 +
   6.681 +	setf.s	 f78=r0			// M2
   6.682 +	setf.s	 f79=r0			// M3
   6.683 +	mov      f80=f0			// F
   6.684 +
   6.685 +	ldfps	 f81,f82=[sp]		// M0
   6.686 +	ldfps	 f83,f84=[sp]		// M1
   6.687 +	mov      f85=f0			// F
   6.688 +
   6.689 +	setf.s	 f86=r0			// M2
   6.690 +	setf.s	 f87=r0			// M3
   6.691 +	mov      f88=f0			// F
   6.692 +
   6.693 +	/*
   6.694 +	 * When the instructions are cached, it would be faster to initialize
   6.695 +	 * the remaining registers with simply mov instructions (F-unit).
   6.696 +	 * This gets the time down to ~29 cycles.  However, this would use up
   6.697 +	 * 33 bundles, whereas continuing with the above pattern yields
   6.698 +	 * 10 bundles and ~30 cycles.
   6.699 +	 */
   6.700 +
   6.701 +	ldfps	 f89,f90=[sp]		// M0
   6.702 +	ldfps	 f91,f92=[sp]		// M1
   6.703 +	mov      f93=f0			// F
   6.704 +
   6.705 +	setf.s	 f94=r0			// M2
   6.706 +	setf.s	 f95=r0			// M3
   6.707 +	mov      f96=f0			// F
   6.708 +
   6.709 +	ldfps	 f97,f98=[sp]		// M0
   6.710 +	ldfps	 f99,f100=[sp]		// M1
   6.711 +	mov      f101=f0		// F
   6.712 +
   6.713 +	setf.s	 f102=r0		// M2
   6.714 +	setf.s	 f103=r0		// M3
   6.715 +	mov      f104=f0		// F
   6.716 +
   6.717 +	ldfps	 f105,f106=[sp]		// M0
   6.718 +	ldfps	 f107,f108=[sp]		// M1
   6.719 +	mov      f109=f0		// F
   6.720 +
   6.721 +	setf.s	 f110=r0		// M2
   6.722 +	setf.s	 f111=r0		// M3
   6.723 +	mov      f112=f0		// F
   6.724 +
   6.725 +	ldfps	 f113,f114=[sp]		// M0
   6.726 +	ldfps	 f115,f116=[sp]		// M1
   6.727 +	mov      f117=f0		// F
   6.728 +
   6.729 +	setf.s	 f118=r0		// M2
   6.730 +	setf.s	 f119=r0		// M3
   6.731 +	mov      f120=f0		// F
   6.732 +
   6.733 +	ldfps	 f121,f122=[sp]		// M0
   6.734 +	ldfps	 f123,f124=[sp]		// M1
   6.735 +	mov      f125=f0		// F
   6.736 +
   6.737 +	setf.s	 f126=r0		// M2
   6.738 +	setf.s	 f127=r0		// M3
   6.739 +	br.ret.sptk.many rp		// F
   6.740 +END(__ia64_init_fpu)
   6.741 +
   6.742 +/*
   6.743 + * Switch execution mode from virtual to physical
   6.744 + *
   6.745 + * Inputs:
   6.746 + *	r16 = new psr to establish
   6.747 + * Output:
   6.748 + *	r19 = old virtual address of ar.bsp
   6.749 + *	r20 = old virtual address of sp
   6.750 + *
   6.751 + * Note: RSE must already be in enforced lazy mode
   6.752 + */
   6.753 +GLOBAL_ENTRY(ia64_switch_mode_phys)
   6.754 + {
   6.755 +	alloc r2=ar.pfs,0,0,0,0
   6.756 +	rsm psr.i | psr.ic		// disable interrupts and interrupt collection
   6.757 +	mov r15=ip
   6.758 + }
   6.759 +	;;
   6.760 + {
   6.761 +	flushrs				// must be first insn in group
   6.762 +	srlz.i
   6.763 + }
   6.764 +	;;
   6.765 +	mov cr.ipsr=r16			// set new PSR
   6.766 +	add r3=1f-ia64_switch_mode_phys,r15
   6.767 +
   6.768 +	mov r19=ar.bsp
   6.769 +	mov r20=sp
   6.770 +	mov r14=rp			// get return address into a general register
   6.771 +	;;
   6.772 +
   6.773 +	// going to physical mode, use tpa to translate virt->phys
   6.774 +	tpa r17=r19
   6.775 +	tpa r3=r3
   6.776 +	tpa sp=sp
   6.777 +	tpa r14=r14
   6.778 +	;;
   6.779 +
   6.780 +	mov r18=ar.rnat			// save ar.rnat
   6.781 +	mov ar.bspstore=r17		// this steps on ar.rnat
   6.782 +	mov cr.iip=r3
   6.783 +	mov cr.ifs=r0
   6.784 +	;;
   6.785 +	mov ar.rnat=r18			// restore ar.rnat
   6.786 +	rfi				// must be last insn in group
   6.787 +	;;
   6.788 +1:	mov rp=r14
   6.789 +	br.ret.sptk.many rp
   6.790 +END(ia64_switch_mode_phys)
   6.791 +
   6.792 +/*
   6.793 + * Switch execution mode from physical to virtual
   6.794 + *
   6.795 + * Inputs:
   6.796 + *	r16 = new psr to establish
   6.797 + *	r19 = new bspstore to establish
   6.798 + *	r20 = new sp to establish
   6.799 + *
   6.800 + * Note: RSE must already be in enforced lazy mode
   6.801 + */
   6.802 +GLOBAL_ENTRY(ia64_switch_mode_virt)
   6.803 + {
   6.804 +	alloc r2=ar.pfs,0,0,0,0
   6.805 +	rsm psr.i | psr.ic		// disable interrupts and interrupt collection
   6.806 +	mov r15=ip
   6.807 + }
   6.808 +	;;
   6.809 + {
   6.810 +	flushrs				// must be first insn in group
   6.811 +	srlz.i
   6.812 + }
   6.813 +	;;
   6.814 +	mov cr.ipsr=r16			// set new PSR
   6.815 +	add r3=1f-ia64_switch_mode_virt,r15
   6.816 +
   6.817 +	mov r14=rp			// get return address into a general register
   6.818 +	;;
   6.819 +
   6.820 +	// going to virtual
   6.821 +	//   - for code addresses, set upper bits of addr to KERNEL_START
   6.822 +	//   - for stack addresses, copy from input argument
   6.823 +	movl r18=KERNEL_START
   6.824 +	dep r3=0,r3,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
   6.825 +	dep r14=0,r14,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
   6.826 +	mov sp=r20
   6.827 +	;;
   6.828 +	or r3=r3,r18
   6.829 +	or r14=r14,r18
   6.830 +	;;
   6.831 +
   6.832 +	mov r18=ar.rnat			// save ar.rnat
   6.833 +	mov ar.bspstore=r19		// this steps on ar.rnat
   6.834 +	mov cr.iip=r3
   6.835 +	mov cr.ifs=r0
   6.836 +	;;
   6.837 +	mov ar.rnat=r18			// restore ar.rnat
   6.838 +	rfi				// must be last insn in group
   6.839 +	;;
   6.840 +1:	mov rp=r14
   6.841 +	br.ret.sptk.many rp
   6.842 +END(ia64_switch_mode_virt)
   6.843 +
   6.844 +GLOBAL_ENTRY(ia64_delay_loop)
   6.845 +	.prologue
   6.846 +{	nop 0			// work around GAS unwind info generation bug...
   6.847 +	.save ar.lc,r2
   6.848 +	mov r2=ar.lc
   6.849 +	.body
   6.850 +	;;
   6.851 +	mov ar.lc=r32
   6.852 +}
   6.853 +	;;
   6.854 +	// force loop to be 32-byte aligned (GAS bug means we cannot use .align
   6.855 +	// inside function body without corrupting unwind info).
   6.856 +{	nop 0 }
   6.857 +1:	br.cloop.sptk.few 1b
   6.858 +	;;
   6.859 +	mov ar.lc=r2
   6.860 +	br.ret.sptk.many rp
   6.861 +END(ia64_delay_loop)
   6.862 +
   6.863 +/*
   6.864 + * Return a CPU-local timestamp in nano-seconds.  This timestamp is
   6.865 + * NOT synchronized across CPUs its return value must never be
   6.866 + * compared against the values returned on another CPU.  The usage in
   6.867 + * kernel/sched.c ensures that.
   6.868 + *
   6.869 + * The return-value of sched_clock() is NOT supposed to wrap-around.
   6.870 + * If it did, it would cause some scheduling hiccups (at the worst).
   6.871 + * Fortunately, with a 64-bit cycle-counter ticking at 100GHz, even
   6.872 + * that would happen only once every 5+ years.
   6.873 + *
   6.874 + * The code below basically calculates:
   6.875 + *
   6.876 + *   (ia64_get_itc() * local_cpu_data->nsec_per_cyc) >> IA64_NSEC_PER_CYC_SHIFT
   6.877 + *
   6.878 + * except that the multiplication and the shift are done with 128-bit
   6.879 + * intermediate precision so that we can produce a full 64-bit result.
   6.880 + */
   6.881 +GLOBAL_ENTRY(sched_clock)
   6.882 +#ifdef XEN
   6.883 +	movl r8=THIS_CPU(cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET
   6.884 +#else
   6.885 +	addl r8=THIS_CPU(cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0
   6.886 +#endif
   6.887 +	mov.m r9=ar.itc		// fetch cycle-counter				(35 cyc)
   6.888 +	;;
   6.889 +	ldf8 f8=[r8]
   6.890 +	;;
   6.891 +	setf.sig f9=r9		// certain to stall, so issue it _after_ ldf8...
   6.892 +	;;
   6.893 +	xmpy.lu f10=f9,f8	// calculate low 64 bits of 128-bit product	(4 cyc)
   6.894 +	xmpy.hu f11=f9,f8	// calculate high 64 bits of 128-bit product
   6.895 +	;;
   6.896 +	getf.sig r8=f10		//						(5 cyc)
   6.897 +	getf.sig r9=f11
   6.898 +	;;
   6.899 +	shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT
   6.900 +	br.ret.sptk.many rp
   6.901 +END(sched_clock)
   6.902 +
   6.903 +GLOBAL_ENTRY(start_kernel_thread)
   6.904 +	.prologue
   6.905 +	.save rp, r0				// this is the end of the call-chain
   6.906 +	.body
   6.907 +	alloc r2 = ar.pfs, 0, 0, 2, 0
   6.908 +	mov out0 = r9
   6.909 +	mov out1 = r11;;
   6.910 +	br.call.sptk.many rp = kernel_thread_helper;;
   6.911 +	mov out0 = r8
   6.912 +	br.call.sptk.many rp = sys_exit;;
   6.913 +1:	br.sptk.few 1b				// not reached
   6.914 +END(start_kernel_thread)
   6.915 +
   6.916 +#ifdef CONFIG_IA64_BRL_EMU
   6.917 +
   6.918 +/*
   6.919 + *  Assembly routines used by brl_emu.c to set preserved register state.
   6.920 + */
   6.921 +
   6.922 +#define SET_REG(reg)				\
   6.923 + GLOBAL_ENTRY(ia64_set_##reg);			\
   6.924 +	alloc r16=ar.pfs,1,0,0,0;		\
   6.925 +	mov reg=r32;				\
   6.926 +	;;					\
   6.927 +	br.ret.sptk.many rp;			\
   6.928 + END(ia64_set_##reg)
   6.929 +
   6.930 +SET_REG(b1);
   6.931 +SET_REG(b2);
   6.932 +SET_REG(b3);
   6.933 +SET_REG(b4);
   6.934 +SET_REG(b5);
   6.935 +
   6.936 +#endif /* CONFIG_IA64_BRL_EMU */
   6.937 +
   6.938 +#ifdef CONFIG_SMP
   6.939 +	/*
   6.940 +	 * This routine handles spinlock contention.  It uses a non-standard calling
   6.941 +	 * convention to avoid converting leaf routines into interior routines.  Because
   6.942 +	 * of this special convention, there are several restrictions:
   6.943 +	 *
   6.944 +	 * - do not use gp relative variables, this code is called from the kernel
   6.945 +	 *   and from modules, r1 is undefined.
   6.946 +	 * - do not use stacked registers, the caller owns them.
   6.947 +	 * - do not use the scratch stack space, the caller owns it.
   6.948 +	 * - do not use any registers other than the ones listed below
   6.949 +	 *
   6.950 +	 * Inputs:
   6.951 +	 *   ar.pfs - saved CFM of caller
   6.952 +	 *   ar.ccv - 0 (and available for use)
   6.953 +	 *   r27    - flags from spin_lock_irqsave or 0.  Must be preserved.
   6.954 +	 *   r28    - available for use.
   6.955 +	 *   r29    - available for use.
   6.956 +	 *   r30    - available for use.
   6.957 +	 *   r31    - address of lock, available for use.
   6.958 +	 *   b6     - return address
   6.959 +	 *   p14    - available for use.
   6.960 +	 *   p15    - used to track flag status.
   6.961 +	 *
   6.962 +	 * If you patch this code to use more registers, do not forget to update
   6.963 +	 * the clobber lists for spin_lock() in include/asm-ia64/spinlock.h.
   6.964 +	 */
   6.965 +
   6.966 +#if __GNUC__ < 3 || (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
   6.967 +
   6.968 +GLOBAL_ENTRY(ia64_spinlock_contention_pre3_4)
   6.969 +	.prologue
   6.970 +	.save ar.pfs, r0	// this code effectively has a zero frame size
   6.971 +	.save rp, r28
   6.972 +	.body
   6.973 +	nop 0
   6.974 +	tbit.nz p15,p0=r27,IA64_PSR_I_BIT
   6.975 +	.restore sp		// pop existing prologue after next insn
   6.976 +	mov b6 = r28
   6.977 +	.prologue
   6.978 +	.save ar.pfs, r0
   6.979 +	.altrp b6
   6.980 +	.body
   6.981 +	;;
   6.982 +(p15)	ssm psr.i		// reenable interrupts if they were on
   6.983 +				// DavidM says that srlz.d is slow and is not required in this case
   6.984 +.wait:
   6.985 +	// exponential backoff, kdb, lockmeter etc. go in here
   6.986 +	hint @pause
   6.987 +	ld4 r30=[r31]		// don't use ld4.bias; if it's contended, we won't write the word
   6.988 +	nop 0
   6.989 +	;;
   6.990 +	cmp4.ne p14,p0=r30,r0
   6.991 +(p14)	br.cond.sptk.few .wait
   6.992 +(p15)	rsm psr.i		// disable interrupts if we reenabled them
   6.993 +	br.cond.sptk.few b6	// lock is now free, try to acquire
   6.994 +	.global ia64_spinlock_contention_pre3_4_end	// for kernprof
   6.995 +ia64_spinlock_contention_pre3_4_end:
   6.996 +END(ia64_spinlock_contention_pre3_4)
   6.997 +
   6.998 +#else
   6.999 +
  6.1000 +GLOBAL_ENTRY(ia64_spinlock_contention)
  6.1001 +	.prologue
  6.1002 +	.altrp b6
  6.1003 +	.body
  6.1004 +	tbit.nz p15,p0=r27,IA64_PSR_I_BIT
  6.1005 +	;;
  6.1006 +.wait:
  6.1007 +(p15)	ssm psr.i		// reenable interrupts if they were on
  6.1008 +				// DavidM says that srlz.d is slow and is not required in this case
  6.1009 +.wait2:
  6.1010 +	// exponential backoff, kdb, lockmeter etc. go in here
  6.1011 +	hint @pause
  6.1012 +	ld4 r30=[r31]		// don't use ld4.bias; if it's contended, we won't write the word
  6.1013 +	;;
  6.1014 +	cmp4.ne p14,p0=r30,r0
  6.1015 +	mov r30 = 1
  6.1016 +(p14)	br.cond.sptk.few .wait2
  6.1017 +(p15)	rsm psr.i		// disable interrupts if we reenabled them
  6.1018 +	;;
  6.1019 +	cmpxchg4.acq r30=[r31], r30, ar.ccv
  6.1020 +	;;
  6.1021 +	cmp4.ne p14,p0=r0,r30
  6.1022 +(p14)	br.cond.sptk.few .wait
  6.1023 +
  6.1024 +	br.ret.sptk.many b6	// lock is now taken
  6.1025 +END(ia64_spinlock_contention)
  6.1026 +
  6.1027 +#endif
  6.1028 +
  6.1029 +#endif /* CONFIG_SMP */
     7.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     7.2 +++ b/xen/arch/ia64/linux-xen/irq_ia64.c	Mon Aug 08 12:21:23 2005 -0700
     7.3 @@ -0,0 +1,381 @@
     7.4 +/*
     7.5 + * linux/arch/ia64/kernel/irq.c
     7.6 + *
     7.7 + * Copyright (C) 1998-2001 Hewlett-Packard Co
     7.8 + *	Stephane Eranian <eranian@hpl.hp.com>
     7.9 + *	David Mosberger-Tang <davidm@hpl.hp.com>
    7.10 + *
    7.11 + *  6/10/99: Updated to bring in sync with x86 version to facilitate
    7.12 + *	     support for SMP and different interrupt controllers.
    7.13 + *
    7.14 + * 09/15/00 Goutham Rao <goutham.rao@intel.com> Implemented pci_irq_to_vector
    7.15 + *                      PCI to vector allocation routine.
    7.16 + * 04/14/2004 Ashok Raj <ashok.raj@intel.com>
    7.17 + *						Added CPU Hotplug handling for IPF.
    7.18 + */
    7.19 +
    7.20 +#include <linux/config.h>
    7.21 +#include <linux/module.h>
    7.22 +
    7.23 +#include <linux/jiffies.h>
    7.24 +#include <linux/errno.h>
    7.25 +#include <linux/init.h>
    7.26 +#include <linux/interrupt.h>
    7.27 +#include <linux/ioport.h>
    7.28 +#include <linux/kernel_stat.h>
    7.29 +#include <linux/slab.h>
    7.30 +#include <linux/ptrace.h>
    7.31 +#include <linux/random.h>	/* for rand_initialize_irq() */
    7.32 +#include <linux/signal.h>
    7.33 +#include <linux/smp.h>
    7.34 +#include <linux/smp_lock.h>
    7.35 +#include <linux/threads.h>
    7.36 +#include <linux/bitops.h>
    7.37 +
    7.38 +#include <asm/delay.h>
    7.39 +#include <asm/intrinsics.h>
    7.40 +#include <asm/io.h>
    7.41 +#include <asm/hw_irq.h>
    7.42 +#include <asm/machvec.h>
    7.43 +#include <asm/pgtable.h>
    7.44 +#include <asm/system.h>
    7.45 +
    7.46 +#ifdef CONFIG_PERFMON
    7.47 +# include <asm/perfmon.h>
    7.48 +#endif
    7.49 +
    7.50 +#define IRQ_DEBUG	0
    7.51 +
    7.52 +/* default base addr of IPI table */
    7.53 +void __iomem *ipi_base_addr = ((void __iomem *)
    7.54 +			       (__IA64_UNCACHED_OFFSET | IA64_IPI_DEFAULT_BASE_ADDR));
    7.55 +
    7.56 +/*
    7.57 + * Legacy IRQ to IA-64 vector translation table.
    7.58 + */
    7.59 +__u8 isa_irq_to_vector_map[16] = {
    7.60 +	/* 8259 IRQ translation, first 16 entries */
    7.61 +	0x2f, 0x20, 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29,
    7.62 +	0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21
    7.63 +};
    7.64 +EXPORT_SYMBOL(isa_irq_to_vector_map);
    7.65 +
    7.66 +static unsigned long ia64_vector_mask[BITS_TO_LONGS(IA64_NUM_DEVICE_VECTORS)];
    7.67 +
    7.68 +int
    7.69 +assign_irq_vector (int irq)
    7.70 +{
    7.71 +	int pos, vector;
    7.72 + again:
    7.73 +	pos = find_first_zero_bit(ia64_vector_mask, IA64_NUM_DEVICE_VECTORS);
    7.74 +	vector = IA64_FIRST_DEVICE_VECTOR + pos;
    7.75 +	if (vector > IA64_LAST_DEVICE_VECTOR)
    7.76 +		/* XXX could look for sharable vectors instead of panic'ing... */
    7.77 +		panic("assign_irq_vector: out of interrupt vectors!");
    7.78 +	if (test_and_set_bit(pos, ia64_vector_mask))
    7.79 +		goto again;
    7.80 +	return vector;
    7.81 +}
    7.82 +
    7.83 +void
    7.84 +free_irq_vector (int vector)
    7.85 +{
    7.86 +	int pos;
    7.87 +
    7.88 +	if (vector < IA64_FIRST_DEVICE_VECTOR || vector > IA64_LAST_DEVICE_VECTOR)
    7.89 +		return;
    7.90 +
    7.91 +	pos = vector - IA64_FIRST_DEVICE_VECTOR;
    7.92 +	if (!test_and_clear_bit(pos, ia64_vector_mask))
    7.93 +		printk(KERN_WARNING "%s: double free!\n", __FUNCTION__);
    7.94 +}
    7.95 +
    7.96 +#ifdef CONFIG_SMP
    7.97 +#	define IS_RESCHEDULE(vec)	(vec == IA64_IPI_RESCHEDULE)
    7.98 +#else
    7.99 +#	define IS_RESCHEDULE(vec)	(0)
   7.100 +#endif
   7.101 +/*
   7.102 + * That's where the IVT branches when we get an external
   7.103 + * interrupt. This branches to the correct hardware IRQ handler via
   7.104 + * function ptr.
   7.105 + */
   7.106 +void
   7.107 +ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
   7.108 +{
   7.109 +	unsigned long saved_tpr;
   7.110 +
   7.111 +#if IRQ_DEBUG
   7.112 +#ifdef XEN
   7.113 +	xen_debug_irq(vector, regs);
   7.114 +#endif
   7.115 +	{
   7.116 +		unsigned long bsp, sp;
   7.117 +
   7.118 +		/*
   7.119 +		 * Note: if the interrupt happened while executing in
   7.120 +		 * the context switch routine (ia64_switch_to), we may
   7.121 +		 * get a spurious stack overflow here.  This is
   7.122 +		 * because the register and the memory stack are not
   7.123 +		 * switched atomically.
   7.124 +		 */
   7.125 +		bsp = ia64_getreg(_IA64_REG_AR_BSP);
   7.126 +		sp = ia64_getreg(_IA64_REG_SP);
   7.127 +
   7.128 +		if ((sp - bsp) < 1024) {
   7.129 +			static unsigned char count;
   7.130 +			static long last_time;
   7.131 +
   7.132 +			if (jiffies - last_time > 5*HZ)
   7.133 +				count = 0;
   7.134 +			if (++count < 5) {
   7.135 +				last_time = jiffies;
   7.136 +				printk("ia64_handle_irq: DANGER: less than "
   7.137 +				       "1KB of free stack space!!\n"
   7.138 +				       "(bsp=0x%lx, sp=%lx)\n", bsp, sp);
   7.139 +			}
   7.140 +		}
   7.141 +	}
   7.142 +#endif /* IRQ_DEBUG */
   7.143 +
   7.144 +	/*
   7.145 +	 * Always set TPR to limit maximum interrupt nesting depth to
   7.146 +	 * 16 (without this, it would be ~240, which could easily lead
   7.147 +	 * to kernel stack overflows).
   7.148 +	 */
   7.149 +	irq_enter();
   7.150 +	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
   7.151 +	ia64_srlz_d();
   7.152 +	while (vector != IA64_SPURIOUS_INT_VECTOR) {
   7.153 +		if (!IS_RESCHEDULE(vector)) {
   7.154 +			ia64_setreg(_IA64_REG_CR_TPR, vector);
   7.155 +			ia64_srlz_d();
   7.156 +
   7.157 +#ifdef XEN
   7.158 +			if (!xen_do_IRQ(vector))
   7.159 +#endif
   7.160 +			__do_IRQ(local_vector_to_irq(vector), regs);
   7.161 +
   7.162 +			/*
   7.163 +			 * Disable interrupts and send EOI:
   7.164 +			 */
   7.165 +			local_irq_disable();
   7.166 +			ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
   7.167 +		}
   7.168 +		ia64_eoi();
   7.169 +		vector = ia64_get_ivr();
   7.170 +	}
   7.171 +	/*
   7.172 +	 * This must be done *after* the ia64_eoi().  For example, the keyboard softirq
   7.173 +	 * handler needs to be able to wait for further keyboard interrupts, which can't
   7.174 +	 * come through until ia64_eoi() has been done.
   7.175 +	 */
   7.176 +	irq_exit();
   7.177 +}
   7.178 +
   7.179 +#ifdef  CONFIG_VTI
   7.180 +#define vmx_irq_enter()		\
   7.181 +	add_preempt_count(HARDIRQ_OFFSET);
   7.182 +
   7.183 +/* Now softirq will be checked when leaving hypervisor, or else
   7.184 + * scheduler irq will be executed too early.
   7.185 + */
   7.186 +#define vmx_irq_exit(void)	\
   7.187 +	sub_preempt_count(HARDIRQ_OFFSET);
   7.188 +/*
   7.189 + * That's where the IVT branches when we get an external
   7.190 + * interrupt. This branches to the correct hardware IRQ handler via
   7.191 + * function ptr.
   7.192 + */
   7.193 +void
   7.194 +vmx_ia64_handle_irq (ia64_vector vector, struct pt_regs *regs)
   7.195 +{
   7.196 +	unsigned long saved_tpr;
   7.197 +	int	wake_dom0 = 0;
   7.198 +
   7.199 +
   7.200 +#if IRQ_DEBUG
   7.201 +	{
   7.202 +		unsigned long bsp, sp;
   7.203 +
   7.204 +		/*
   7.205 +		 * Note: if the interrupt happened while executing in
   7.206 +		 * the context switch routine (ia64_switch_to), we may
   7.207 +		 * get a spurious stack overflow here.  This is
   7.208 +		 * because the register and the memory stack are not
   7.209 +		 * switched atomically.
   7.210 +		 */
   7.211 +		bsp = ia64_getreg(_IA64_REG_AR_BSP);
   7.212 +		sp = ia64_getreg(_IA64_REG_AR_SP);
   7.213 +
   7.214 +		if ((sp - bsp) < 1024) {
   7.215 +			static unsigned char count;
   7.216 +			static long last_time;
   7.217 +
   7.218 +			if (jiffies - last_time > 5*HZ)
   7.219 +				count = 0;
   7.220 +			if (++count < 5) {
   7.221 +				last_time = jiffies;
   7.222 +				printk("ia64_handle_irq: DANGER: less than "
   7.223 +				       "1KB of free stack space!!\n"
   7.224 +				       "(bsp=0x%lx, sp=%lx)\n", bsp, sp);
   7.225 +			}
   7.226 +		}
   7.227 +	}
   7.228 +#endif /* IRQ_DEBUG */
   7.229 +
   7.230 +	/*
   7.231 +	 * Always set TPR to limit maximum interrupt nesting depth to
   7.232 +	 * 16 (without this, it would be ~240, which could easily lead
   7.233 +	 * to kernel stack overflows).
   7.234 +	 */
   7.235 +	vmx_irq_enter();
   7.236 +	saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
   7.237 +	ia64_srlz_d();
   7.238 +	while (vector != IA64_SPURIOUS_INT_VECTOR) {
   7.239 +	    if (!IS_RESCHEDULE(vector)) {
   7.240 +		ia64_setreg(_IA64_REG_CR_TPR, vector);
   7.241 +		ia64_srlz_d();
   7.242 +
   7.243 +		if (vector != IA64_TIMER_VECTOR) {
   7.244 +			/* FIXME: Leave IRQ re-route later */
   7.245 +			vmx_vcpu_pend_interrupt(dom0->vcpu[0],vector);
   7.246 +			wake_dom0 = 1;
   7.247 +		}
   7.248 +		else {	// FIXME: Handle Timer only now
   7.249 +			__do_IRQ(local_vector_to_irq(vector), regs);
   7.250 +		}
   7.251 +		
   7.252 +		/*
   7.253 +		 * Disable interrupts and send EOI:
   7.254 +		 */
   7.255 +		local_irq_disable();
   7.256 +		ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
   7.257 +	    }
   7.258 +	    else {
   7.259 +                printf("Oops: RESCHEDULE IPI absorbed by HV\n");
   7.260 +            }
   7.261 +	    ia64_eoi();
   7.262 +	    vector = ia64_get_ivr();
   7.263 +	}
   7.264 +	/*
   7.265 +	 * This must be done *after* the ia64_eoi().  For example, the keyboard softirq
   7.266 +	 * handler needs to be able to wait for further keyboard interrupts, which can't
   7.267 +	 * come through until ia64_eoi() has been done.
   7.268 +	 */
   7.269 +	vmx_irq_exit();
   7.270 +	if ( wake_dom0 && current != dom0 ) 
   7.271 +		domain_wake(dom0->vcpu[0]);
   7.272 +}
   7.273 +#endif
   7.274 +
   7.275 +
   7.276 +#ifdef CONFIG_HOTPLUG_CPU
   7.277 +/*
   7.278 + * This function emulates a interrupt processing when a cpu is about to be
   7.279 + * brought down.
   7.280 + */
   7.281 +void ia64_process_pending_intr(void)
   7.282 +{
   7.283 +	ia64_vector vector;
   7.284 +	unsigned long saved_tpr;
   7.285 +	extern unsigned int vectors_in_migration[NR_IRQS];
   7.286 +
   7.287 +	vector = ia64_get_ivr();
   7.288 +
   7.289 +	 irq_enter();
   7.290 +	 saved_tpr = ia64_getreg(_IA64_REG_CR_TPR);
   7.291 +	 ia64_srlz_d();
   7.292 +
   7.293 +	 /*
   7.294 +	  * Perform normal interrupt style processing
   7.295 +	  */
   7.296 +	while (vector != IA64_SPURIOUS_INT_VECTOR) {
   7.297 +		if (!IS_RESCHEDULE(vector)) {
   7.298 +			ia64_setreg(_IA64_REG_CR_TPR, vector);
   7.299 +			ia64_srlz_d();
   7.300 +
   7.301 +			/*
   7.302 +			 * Now try calling normal ia64_handle_irq as it would have got called
   7.303 +			 * from a real intr handler. Try passing null for pt_regs, hopefully
   7.304 +			 * it will work. I hope it works!.
   7.305 +			 * Probably could shared code.
   7.306 +			 */
   7.307 +			vectors_in_migration[local_vector_to_irq(vector)]=0;
   7.308 +			__do_IRQ(local_vector_to_irq(vector), NULL);
   7.309 +
   7.310 +			/*
   7.311 +			 * Disable interrupts and send EOI
   7.312 +			 */
   7.313 +			local_irq_disable();
   7.314 +			ia64_setreg(_IA64_REG_CR_TPR, saved_tpr);
   7.315 +		}
   7.316 +		ia64_eoi();
   7.317 +		vector = ia64_get_ivr();
   7.318 +	}
   7.319 +	irq_exit();
   7.320 +}
   7.321 +#endif
   7.322 +
   7.323 +
   7.324 +#ifdef CONFIG_SMP
   7.325 +extern irqreturn_t handle_IPI (int irq, void *dev_id, struct pt_regs *regs);
   7.326 +
   7.327 +static struct irqaction ipi_irqaction = {
   7.328 +	.handler =	handle_IPI,
   7.329 +	.flags =	SA_INTERRUPT,
   7.330 +	.name =		"IPI"
   7.331 +};
   7.332 +#endif
   7.333 +
   7.334 +void
   7.335 +register_percpu_irq (ia64_vector vec, struct irqaction *action)
   7.336 +{
   7.337 +	irq_desc_t *desc;
   7.338 +	unsigned int irq;
   7.339 +
   7.340 +	for (irq = 0; irq < NR_IRQS; ++irq)
   7.341 +		if (irq_to_vector(irq) == vec) {
   7.342 +			desc = irq_descp(irq);
   7.343 +			desc->status |= IRQ_PER_CPU;
   7.344 +			desc->handler = &irq_type_ia64_lsapic;
   7.345 +			if (action)
   7.346 +				setup_irq(irq, action);
   7.347 +		}
   7.348 +}
   7.349 +
   7.350 +void __init
   7.351 +init_IRQ (void)
   7.352 +{
   7.353 +	register_percpu_irq(IA64_SPURIOUS_INT_VECTOR, NULL);
   7.354 +#ifdef CONFIG_SMP
   7.355 +	register_percpu_irq(IA64_IPI_VECTOR, &ipi_irqaction);
   7.356 +#endif
   7.357 +#ifdef CONFIG_PERFMON
   7.358 +	pfm_init_percpu();
   7.359 +#endif
   7.360 +	platform_irq_init();
   7.361 +}
   7.362 +
   7.363 +void
   7.364 +ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect)
   7.365 +{
   7.366 +	void __iomem *ipi_addr;
   7.367 +	unsigned long ipi_data;
   7.368 +	unsigned long phys_cpu_id;
   7.369 +
   7.370 +#ifdef CONFIG_SMP
   7.371 +	phys_cpu_id = cpu_physical_id(cpu);
   7.372 +#else
   7.373 +	phys_cpu_id = (ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff;
   7.374 +#endif
   7.375 +
   7.376 +	/*
   7.377 +	 * cpu number is in 8bit ID and 8bit EID
   7.378 +	 */
   7.379 +
   7.380 +	ipi_data = (delivery_mode << 8) | (vector & 0xff);
   7.381 +	ipi_addr = ipi_base_addr + ((phys_cpu_id << 4) | ((redirect & 1) << 3));
   7.382 +
   7.383 +	writeq(ipi_data, ipi_addr);
   7.384 +}
     8.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     8.2 +++ b/xen/arch/ia64/linux-xen/mm_contig.c	Mon Aug 08 12:21:23 2005 -0700
     8.3 @@ -0,0 +1,305 @@
     8.4 +/*
     8.5 + * This file is subject to the terms and conditions of the GNU General Public
     8.6 + * License.  See the file "COPYING" in the main directory of this archive
     8.7 + * for more details.
     8.8 + *
     8.9 + * Copyright (C) 1998-2003 Hewlett-Packard Co
    8.10 + *	David Mosberger-Tang <davidm@hpl.hp.com>
    8.11 + *	Stephane Eranian <eranian@hpl.hp.com>
    8.12 + * Copyright (C) 2000, Rohit Seth <rohit.seth@intel.com>
    8.13 + * Copyright (C) 1999 VA Linux Systems
    8.14 + * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
    8.15 + * Copyright (C) 2003 Silicon Graphics, Inc. All rights reserved.
    8.16 + *
    8.17 + * Routines used by ia64 machines with contiguous (or virtually contiguous)
    8.18 + * memory.
    8.19 + */
    8.20 +#include <linux/config.h>
    8.21 +#include <linux/bootmem.h>
    8.22 +#include <linux/efi.h>
    8.23 +#include <linux/mm.h>
    8.24 +#include <linux/swap.h>
    8.25 +
    8.26 +#include <asm/meminit.h>
    8.27 +#include <asm/pgalloc.h>
    8.28 +#include <asm/pgtable.h>
    8.29 +#include <asm/sections.h>
    8.30 +#include <asm/mca.h>
    8.31 +
    8.32 +#ifdef CONFIG_VIRTUAL_MEM_MAP
    8.33 +static unsigned long num_dma_physpages;
    8.34 +#endif
    8.35 +
    8.36 +/**
    8.37 + * show_mem - display a memory statistics summary
    8.38 + *
    8.39 + * Just walks the pages in the system and describes where they're allocated.
    8.40 + */
    8.41 +#ifndef XEN
    8.42 +void
    8.43 +show_mem (void)
    8.44 +{
    8.45 +	int i, total = 0, reserved = 0;
    8.46 +	int shared = 0, cached = 0;
    8.47 +
    8.48 +	printk("Mem-info:\n");
    8.49 +	show_free_areas();
    8.50 +
    8.51 +	printk("Free swap:       %6ldkB\n", nr_swap_pages<<(PAGE_SHIFT-10));
    8.52 +	i = max_mapnr;
    8.53 +	while (i-- > 0) {
    8.54 +		if (!pfn_valid(i))
    8.55 +			continue;
    8.56 +		total++;
    8.57 +		if (PageReserved(mem_map+i))
    8.58 +			reserved++;
    8.59 +		else if (PageSwapCache(mem_map+i))
    8.60 +			cached++;
    8.61 +		else if (page_count(mem_map + i))
    8.62 +			shared += page_count(mem_map + i) - 1;
    8.63 +	}
    8.64 +	printk("%d pages of RAM\n", total);
    8.65 +	printk("%d reserved pages\n", reserved);
    8.66 +	printk("%d pages shared\n", shared);
    8.67 +	printk("%d pages swap cached\n", cached);
    8.68 +	printk("%ld pages in page table cache\n", pgtable_cache_size);
    8.69 +}
    8.70 +#endif
    8.71 +
    8.72 +/* physical address where the bootmem map is located */
    8.73 +unsigned long bootmap_start;
    8.74 +
    8.75 +/**
    8.76 + * find_max_pfn - adjust the maximum page number callback
    8.77 + * @start: start of range
    8.78 + * @end: end of range
    8.79 + * @arg: address of pointer to global max_pfn variable
    8.80 + *
    8.81 + * Passed as a callback function to efi_memmap_walk() to determine the highest
    8.82 + * available page frame number in the system.
    8.83 + */
    8.84 +int
    8.85 +find_max_pfn (unsigned long start, unsigned long end, void *arg)
    8.86 +{
    8.87 +	unsigned long *max_pfnp = arg, pfn;
    8.88 +
    8.89 +	pfn = (PAGE_ALIGN(end - 1) - PAGE_OFFSET) >> PAGE_SHIFT;
    8.90 +	if (pfn > *max_pfnp)
    8.91 +		*max_pfnp = pfn;
    8.92 +	return 0;
    8.93 +}
    8.94 +
    8.95 +/**
    8.96 + * find_bootmap_location - callback to find a memory area for the bootmap
    8.97 + * @start: start of region
    8.98 + * @end: end of region
    8.99 + * @arg: unused callback data
   8.100 + *
   8.101 + * Find a place to put the bootmap and return its starting address in
   8.102 + * bootmap_start.  This address must be page-aligned.
   8.103 + */
   8.104 +int
   8.105 +find_bootmap_location (unsigned long start, unsigned long end, void *arg)
   8.106 +{
   8.107 +	unsigned long needed = *(unsigned long *)arg;
   8.108 +	unsigned long range_start, range_end, free_start;
   8.109 +	int i;
   8.110 +
   8.111 +#if IGNORE_PFN0
   8.112 +	if (start == PAGE_OFFSET) {
   8.113 +		start += PAGE_SIZE;
   8.114 +		if (start >= end)
   8.115 +			return 0;
   8.116 +	}
   8.117 +#endif
   8.118 +
   8.119 +	free_start = PAGE_OFFSET;
   8.120 +
   8.121 +	for (i = 0; i < num_rsvd_regions; i++) {
   8.122 +		range_start = max(start, free_start);
   8.123 +		range_end   = min(end, rsvd_region[i].start & PAGE_MASK);
   8.124 +
   8.125 +		free_start = PAGE_ALIGN(rsvd_region[i].end);
   8.126 +
   8.127 +		if (range_end <= range_start)
   8.128 +			continue; /* skip over empty range */
   8.129 +
   8.130 +		if (range_end - range_start >= needed) {
   8.131 +			bootmap_start = __pa(range_start);
   8.132 +			return -1;	/* done */
   8.133 +		}
   8.134 +
   8.135 +		/* nothing more available in this segment */
   8.136 +		if (range_end == end)
   8.137 +			return 0;
   8.138 +	}
   8.139 +	return 0;
   8.140 +}
   8.141 +
   8.142 +/**
   8.143 + * find_memory - setup memory map
   8.144 + *
   8.145 + * Walk the EFI memory map and find usable memory for the system, taking
   8.146 + * into account reserved areas.
   8.147 + */
   8.148 +#ifndef XEN
   8.149 +void
   8.150 +find_memory (void)
   8.151 +{
   8.152 +	unsigned long bootmap_size;
   8.153 +
   8.154 +	reserve_memory();
   8.155 +
   8.156 +	/* first find highest page frame number */
   8.157 +	max_pfn = 0;
   8.158 +	efi_memmap_walk(find_max_pfn, &max_pfn);
   8.159 +
   8.160 +	/* how many bytes to cover all the pages */
   8.161 +	bootmap_size = bootmem_bootmap_pages(max_pfn) << PAGE_SHIFT;
   8.162 +
   8.163 +	/* look for a location to hold the bootmap */
   8.164 +	bootmap_start = ~0UL;
   8.165 +	efi_memmap_walk(find_bootmap_location, &bootmap_size);
   8.166 +	if (bootmap_start == ~0UL)
   8.167 +		panic("Cannot find %ld bytes for bootmap\n", bootmap_size);
   8.168 +
   8.169 +	bootmap_size = init_bootmem(bootmap_start >> PAGE_SHIFT, max_pfn);
   8.170 +
   8.171 +	/* Free all available memory, then mark bootmem-map as being in use. */
   8.172 +	efi_memmap_walk(filter_rsvd_memory, free_bootmem);
   8.173 +	reserve_bootmem(bootmap_start, bootmap_size);
   8.174 +
   8.175 +	find_initrd();
   8.176 +}
   8.177 +#endif
   8.178 +
   8.179 +#ifdef CONFIG_SMP
   8.180 +/**
   8.181 + * per_cpu_init - setup per-cpu variables
   8.182 + *
   8.183 + * Allocate and setup per-cpu data areas.
   8.184 + */
   8.185 +void *
   8.186 +per_cpu_init (void)
   8.187 +{
   8.188 +	void *cpu_data;
   8.189 +	int cpu;
   8.190 +
   8.191 +	/*
   8.192 +	 * get_free_pages() cannot be used before cpu_init() done.  BSP
   8.193 +	 * allocates "NR_CPUS" pages for all CPUs to avoid that AP calls
   8.194 +	 * get_zeroed_page().
   8.195 +	 */
   8.196 +	if (smp_processor_id() == 0) {
   8.197 +		cpu_data = __alloc_bootmem(PERCPU_PAGE_SIZE * NR_CPUS,
   8.198 +					   PERCPU_PAGE_SIZE, __pa(MAX_DMA_ADDRESS));
   8.199 +		for (cpu = 0; cpu < NR_CPUS; cpu++) {
   8.200 +			memcpy(cpu_data, __phys_per_cpu_start, __per_cpu_end - __per_cpu_start);
   8.201 +			__per_cpu_offset[cpu] = (char *) cpu_data - __per_cpu_start;
   8.202 +			cpu_data += PERCPU_PAGE_SIZE;
   8.203 +			per_cpu(local_per_cpu_offset, cpu) = __per_cpu_offset[cpu];
   8.204 +		}
   8.205 +	}
   8.206 +	return __per_cpu_start + __per_cpu_offset[smp_processor_id()];
   8.207 +}
   8.208 +#endif /* CONFIG_SMP */
   8.209 +
   8.210 +static int
   8.211 +count_pages (u64 start, u64 end, void *arg)
   8.212 +{
   8.213 +	unsigned long *count = arg;
   8.214 +
   8.215 +	*count += (end - start) >> PAGE_SHIFT;
   8.216 +	return 0;
   8.217 +}
   8.218 +
   8.219 +#ifdef CONFIG_VIRTUAL_MEM_MAP
   8.220 +static int
   8.221 +count_dma_pages (u64 start, u64 end, void *arg)
   8.222 +{
   8.223 +	unsigned long *count = arg;
   8.224 +
   8.225 +	if (start < MAX_DMA_ADDRESS)
   8.226 +		*count += (min(end, MAX_DMA_ADDRESS) - start) >> PAGE_SHIFT;
   8.227 +	return 0;
   8.228 +}
   8.229 +#endif
   8.230 +
   8.231 +/*
   8.232 + * Set up the page tables.
   8.233 + */
   8.234 +
   8.235 +#ifndef XEN
   8.236 +void
   8.237 +paging_init (void)
   8.238 +{
   8.239 +	unsigned long max_dma;
   8.240 +	unsigned long zones_size[MAX_NR_ZONES];
   8.241 +#ifdef CONFIG_VIRTUAL_MEM_MAP
   8.242 +	unsigned long zholes_size[MAX_NR_ZONES];
   8.243 +	unsigned long max_gap;
   8.244 +#endif
   8.245 +
   8.246 +	/* initialize mem_map[] */
   8.247 +
   8.248 +	memset(zones_size, 0, sizeof(zones_size));
   8.249 +
   8.250 +	num_physpages = 0;
   8.251 +	efi_memmap_walk(count_pages, &num_physpages);
   8.252 +
   8.253 +	max_dma = virt_to_phys((void *) MAX_DMA_ADDRESS) >> PAGE_SHIFT;
   8.254 +
   8.255 +#ifdef CONFIG_VIRTUAL_MEM_MAP
   8.256 +	memset(zholes_size, 0, sizeof(zholes_size));
   8.257 +
   8.258 +	num_dma_physpages = 0;
   8.259 +	efi_memmap_walk(count_dma_pages, &num_dma_physpages);
   8.260 +
   8.261 +	if (max_low_pfn < max_dma) {
   8.262 +		zones_size[ZONE_DMA] = max_low_pfn;
   8.263 +		zholes_size[ZONE_DMA] = max_low_pfn - num_dma_physpages;
   8.264 +	} else {
   8.265 +		zones_size[ZONE_DMA] = max_dma;
   8.266 +		zholes_size[ZONE_DMA] = max_dma - num_dma_physpages;
   8.267 +		if (num_physpages > num_dma_physpages) {
   8.268 +			zones_size[ZONE_NORMAL] = max_low_pfn - max_dma;
   8.269 +			zholes_size[ZONE_NORMAL] =
   8.270 +				((max_low_pfn - max_dma) -
   8.271 +				 (num_physpages - num_dma_physpages));
   8.272 +		}
   8.273 +	}
   8.274 +
   8.275 +	max_gap = 0;
   8.276 +	efi_memmap_walk(find_largest_hole, (u64 *)&max_gap);
   8.277 +	if (max_gap < LARGE_GAP) {
   8.278 +		vmem_map = (struct page *) 0;
   8.279 +		free_area_init_node(0, &contig_page_data, zones_size, 0,
   8.280 +				    zholes_size);
   8.281 +	} else {
   8.282 +		unsigned long map_size;
   8.283 +
   8.284 +		/* allocate virtual_mem_map */
   8.285 +
   8.286 +		map_size = PAGE_ALIGN(max_low_pfn * sizeof(struct page));
   8.287 +		vmalloc_end -= map_size;
   8.288 +		vmem_map = (struct page *) vmalloc_end;
   8.289 +		efi_memmap_walk(create_mem_map_page_table, NULL);
   8.290 +
   8.291 +		mem_map = contig_page_data.node_mem_map = vmem_map;
   8.292 +		free_area_init_node(0, &contig_page_data, zones_size,
   8.293 +				    0, zholes_size);
   8.294 +
   8.295 +		printk("Virtual mem_map starts at 0x%p\n", mem_map);
   8.296 +	}
   8.297 +#else /* !CONFIG_VIRTUAL_MEM_MAP */
   8.298 +	if (max_low_pfn < max_dma)
   8.299 +		zones_size[ZONE_DMA] = max_low_pfn;
   8.300 +	else {
   8.301 +		zones_size[ZONE_DMA] = max_dma;
   8.302 +		zones_size[ZONE_NORMAL] = max_low_pfn - max_dma;
   8.303 +	}
   8.304 +	free_area_init(zones_size);
   8.305 +#endif /* !CONFIG_VIRTUAL_MEM_MAP */
   8.306 +	zero_page_memmap_ptr = virt_to_page(ia64_imva(empty_zero_page));
   8.307 +}
   8.308 +#endif /* !CONFIG_XEN */
     9.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     9.2 +++ b/xen/arch/ia64/linux-xen/pal.S	Mon Aug 08 12:21:23 2005 -0700
     9.3 @@ -0,0 +1,310 @@
     9.4 +/*
     9.5 + * PAL Firmware support
     9.6 + * IA-64 Processor Programmers Reference Vol 2
     9.7 + *
     9.8 + * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
     9.9 + * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
    9.10 + * Copyright (C) 1999-2001, 2003 Hewlett-Packard Co
    9.11 + *	David Mosberger <davidm@hpl.hp.com>
    9.12 + *	Stephane Eranian <eranian@hpl.hp.com>
    9.13 + *
    9.14 + * 05/22/2000 eranian Added support for stacked register calls
    9.15 + * 05/24/2000 eranian Added support for physical mode static calls
    9.16 + */
    9.17 +
    9.18 +#include <asm/asmmacro.h>
    9.19 +#include <asm/processor.h>
    9.20 +
    9.21 +	.data
    9.22 +pal_entry_point:
    9.23 +	data8 ia64_pal_default_handler
    9.24 +	.text
    9.25 +
    9.26 +/*
    9.27 + * Set the PAL entry point address.  This could be written in C code, but we do it here
    9.28 + * to keep it all in one module (besides, it's so trivial that it's
    9.29 + * not a big deal).
    9.30 + *
    9.31 + * in0		Address of the PAL entry point (text address, NOT a function descriptor).
    9.32 + */
    9.33 +GLOBAL_ENTRY(ia64_pal_handler_init)
    9.34 +	alloc r3=ar.pfs,1,0,0,0
    9.35 +	movl r2=pal_entry_point
    9.36 +	;;
    9.37 +	st8 [r2]=in0
    9.38 +	br.ret.sptk.many rp
    9.39 +END(ia64_pal_handler_init)
    9.40 +
    9.41 +/*
    9.42 + * Default PAL call handler.  This needs to be coded in assembly because it uses
    9.43 + * the static calling convention, i.e., the RSE may not be used and calls are
    9.44 + * done via "br.cond" (not "br.call").
    9.45 + */
    9.46 +GLOBAL_ENTRY(ia64_pal_default_handler)
    9.47 +	mov r8=-1
    9.48 +	br.cond.sptk.many rp
    9.49 +END(ia64_pal_default_handler)
    9.50 +
    9.51 +/*
    9.52 + * Make a PAL call using the static calling convention.
    9.53 + *
    9.54 + * in0         Index of PAL service
    9.55 + * in1 - in3   Remaining PAL arguments
    9.56 + * in4	       1 ==> clear psr.ic,  0 ==> don't clear psr.ic
    9.57 + *
    9.58 + */
    9.59 +GLOBAL_ENTRY(ia64_pal_call_static)
    9.60 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(5)
    9.61 +	alloc loc1 = ar.pfs,5,5,0,0
    9.62 +	movl loc2 = pal_entry_point
    9.63 +1:	{
    9.64 +	  mov r28 = in0
    9.65 +	  mov r29 = in1
    9.66 +	  mov r8 = ip
    9.67 +	}
    9.68 +	;;
    9.69 +	ld8 loc2 = [loc2]		// loc2 <- entry point
    9.70 +	tbit.nz p6,p7 = in4, 0
    9.71 +	adds r8 = 1f-1b,r8
    9.72 +	mov loc4=ar.rsc			// save RSE configuration
    9.73 +	;;
    9.74 +	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
    9.75 +	mov loc3 = psr
    9.76 +	mov loc0 = rp
    9.77 +	.body
    9.78 +	mov r30 = in2
    9.79 +
    9.80 +(p6)	rsm psr.i | psr.ic
    9.81 +	mov r31 = in3
    9.82 +	mov b7 = loc2
    9.83 +
    9.84 +(p7)	rsm psr.i
    9.85 +	;;
    9.86 +(p6)	srlz.i
    9.87 +	mov rp = r8
    9.88 +	br.cond.sptk.many b7
    9.89 +1:	mov psr.l = loc3
    9.90 +	mov ar.rsc = loc4		// restore RSE configuration
    9.91 +	mov ar.pfs = loc1
    9.92 +	mov rp = loc0
    9.93 +	;;
    9.94 +	srlz.d				// seralize restoration of psr.l
    9.95 +	br.ret.sptk.many b0
    9.96 +END(ia64_pal_call_static)
    9.97 +
    9.98 +/*
    9.99 + * Make a PAL call using the stacked registers calling convention.
   9.100 + *
   9.101 + * Inputs:
   9.102 + * 	in0         Index of PAL service
   9.103 + * 	in2 - in3   Remaning PAL arguments
   9.104 + */
   9.105 +GLOBAL_ENTRY(ia64_pal_call_stacked)
   9.106 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(4)
   9.107 +	alloc loc1 = ar.pfs,4,4,4,0
   9.108 +	movl loc2 = pal_entry_point
   9.109 +
   9.110 +	mov r28  = in0			// Index MUST be copied to r28
   9.111 +	mov out0 = in0			// AND in0 of PAL function
   9.112 +	mov loc0 = rp
   9.113 +	.body
   9.114 +	;;
   9.115 +	ld8 loc2 = [loc2]		// loc2 <- entry point
   9.116 +	mov out1 = in1
   9.117 +	mov out2 = in2
   9.118 +	mov out3 = in3
   9.119 +	mov loc3 = psr
   9.120 +	;;
   9.121 +	rsm psr.i
   9.122 +	mov b7 = loc2
   9.123 +	;;
   9.124 +	br.call.sptk.many rp=b7		// now make the call
   9.125 +.ret0:	mov psr.l  = loc3
   9.126 +	mov ar.pfs = loc1
   9.127 +	mov rp = loc0
   9.128 +	;;
   9.129 +	srlz.d				// serialize restoration of psr.l
   9.130 +	br.ret.sptk.many b0
   9.131 +END(ia64_pal_call_stacked)
   9.132 +
   9.133 +/*
   9.134 + * Make a physical mode PAL call using the static registers calling convention.
   9.135 + *
   9.136 + * Inputs:
   9.137 + * 	in0         Index of PAL service
   9.138 + * 	in2 - in3   Remaning PAL arguments
   9.139 + *
   9.140 + * PSR_LP, PSR_TB, PSR_ID, PSR_DA are never set by the kernel.
   9.141 + * So we don't need to clear them.
   9.142 + */
   9.143 +#define PAL_PSR_BITS_TO_CLEAR							\
   9.144 +	(IA64_PSR_I | IA64_PSR_IT | IA64_PSR_DT  | IA64_PSR_DB | IA64_PSR_RT |	\
   9.145 +	 IA64_PSR_DD | IA64_PSR_SS | IA64_PSR_RI | IA64_PSR_ED |		\
   9.146 +	 IA64_PSR_DFL | IA64_PSR_DFH)
   9.147 +
   9.148 +#define PAL_PSR_BITS_TO_SET							\
   9.149 +	(IA64_PSR_BN)
   9.150 +
   9.151 +
   9.152 +GLOBAL_ENTRY(ia64_pal_call_phys_static)
   9.153 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(4)
   9.154 +	alloc loc1 = ar.pfs,4,7,0,0
   9.155 +	movl loc2 = pal_entry_point
   9.156 +1:	{
   9.157 +	  mov r28  = in0		// copy procedure index
   9.158 +	  mov r8   = ip			// save ip to compute branch
   9.159 +	  mov loc0 = rp			// save rp
   9.160 +	}
   9.161 +	.body
   9.162 +	;;
   9.163 +	ld8 loc2 = [loc2]		// loc2 <- entry point
   9.164 +	mov r29  = in1			// first argument
   9.165 +	mov r30  = in2			// copy arg2
   9.166 +	mov r31  = in3			// copy arg3
   9.167 +	;;
   9.168 +	mov loc3 = psr			// save psr
   9.169 +	adds r8  = 1f-1b,r8		// calculate return address for call
   9.170 +	;;
   9.171 +	mov loc4=ar.rsc			// save RSE configuration
   9.172 +#ifdef XEN
   9.173 +	dep.z loc2=loc2,0,60		// convert pal entry point to physical
   9.174 +#else // XEN
   9.175 +	dep.z loc2=loc2,0,61		// convert pal entry point to physical
   9.176 +#endif // XEN
   9.177 +	tpa r8=r8			// convert rp to physical
   9.178 +	;;
   9.179 +	mov b7 = loc2			// install target to branch reg
   9.180 +	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
   9.181 +	movl r16=PAL_PSR_BITS_TO_CLEAR
   9.182 +	movl r17=PAL_PSR_BITS_TO_SET
   9.183 +	;;
   9.184 +	or loc3=loc3,r17		// add in psr the bits to set
   9.185 +	;;
   9.186 +	andcm r16=loc3,r16		// removes bits to clear from psr
   9.187 +	br.call.sptk.many rp=ia64_switch_mode_phys
   9.188 +.ret1:	mov rp = r8			// install return address (physical)
   9.189 +	mov loc5 = r19
   9.190 +	mov loc6 = r20
   9.191 +	br.cond.sptk.many b7
   9.192 +1:
   9.193 +	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
   9.194 +	mov r16=loc3			// r16= original psr
   9.195 +	mov r19=loc5
   9.196 +	mov r20=loc6
   9.197 +	br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode
   9.198 +.ret2:
   9.199 +	mov psr.l = loc3		// restore init PSR
   9.200 +
   9.201 +	mov ar.pfs = loc1
   9.202 +	mov rp = loc0
   9.203 +	;;
   9.204 +	mov ar.rsc=loc4			// restore RSE configuration
   9.205 +	srlz.d				// seralize restoration of psr.l
   9.206 +	br.ret.sptk.many b0
   9.207 +END(ia64_pal_call_phys_static)
   9.208 +
   9.209 +/*
   9.210 + * Make a PAL call using the stacked registers in physical mode.
   9.211 + *
   9.212 + * Inputs:
   9.213 + * 	in0         Index of PAL service
   9.214 + * 	in2 - in3   Remaning PAL arguments
   9.215 + */
   9.216 +GLOBAL_ENTRY(ia64_pal_call_phys_stacked)
   9.217 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(5)
   9.218 +	alloc	loc1 = ar.pfs,5,7,4,0
   9.219 +	movl	loc2 = pal_entry_point
   9.220 +1:	{
   9.221 +	  mov r28  = in0		// copy procedure index
   9.222 +	  mov loc0 = rp		// save rp
   9.223 +	}
   9.224 +	.body
   9.225 +	;;
   9.226 +	ld8 loc2 = [loc2]		// loc2 <- entry point
   9.227 +	mov out0 = in0		// first argument
   9.228 +	mov out1 = in1		// copy arg2
   9.229 +	mov out2 = in2		// copy arg3
   9.230 +	mov out3 = in3		// copy arg3
   9.231 +	;;
   9.232 +	mov loc3 = psr		// save psr
   9.233 +	;;
   9.234 +	mov loc4=ar.rsc			// save RSE configuration
   9.235 +#ifdef XEN
   9.236 +	dep.z loc2=loc2,0,60		// convert pal entry point to physical
   9.237 +#else // XEN
   9.238 +	dep.z loc2=loc2,0,61		// convert pal entry point to physical
   9.239 +#endif // XEN
   9.240 +	;;
   9.241 +	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
   9.242 +	movl r16=PAL_PSR_BITS_TO_CLEAR
   9.243 +	movl r17=PAL_PSR_BITS_TO_SET
   9.244 +	;;
   9.245 +	or loc3=loc3,r17		// add in psr the bits to set
   9.246 +	mov b7 = loc2			// install target to branch reg
   9.247 +	;;
   9.248 +	andcm r16=loc3,r16		// removes bits to clear from psr
   9.249 +	br.call.sptk.many rp=ia64_switch_mode_phys
   9.250 +.ret6:
   9.251 +	mov loc5 = r19
   9.252 +	mov loc6 = r20
   9.253 +	br.call.sptk.many rp=b7		// now make the call
   9.254 +.ret7:
   9.255 +	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
   9.256 +	mov r16=loc3			// r16= original psr
   9.257 +	mov r19=loc5
   9.258 +	mov r20=loc6
   9.259 +	br.call.sptk.many rp=ia64_switch_mode_virt	// return to virtual mode
   9.260 +
   9.261 +.ret8:	mov psr.l  = loc3		// restore init PSR
   9.262 +	mov ar.pfs = loc1
   9.263 +	mov rp = loc0
   9.264 +	;;
   9.265 +	mov ar.rsc=loc4			// restore RSE configuration
   9.266 +	srlz.d				// seralize restoration of psr.l
   9.267 +	br.ret.sptk.many b0
   9.268 +END(ia64_pal_call_phys_stacked)
   9.269 +
   9.270 +/*
   9.271 + * Save scratch fp scratch regs which aren't saved in pt_regs already (fp10-fp15).
   9.272 + *
   9.273 + * NOTE: We need to do this since firmware (SAL and PAL) may use any of the scratch
   9.274 + * regs fp-low partition.
   9.275 + *
   9.276 + * Inputs:
   9.277 + *      in0	Address of stack storage for fp regs
   9.278 + */
   9.279 +GLOBAL_ENTRY(ia64_save_scratch_fpregs)
   9.280 +	alloc r3=ar.pfs,1,0,0,0
   9.281 +	add r2=16,in0
   9.282 +	;;
   9.283 +	stf.spill [in0] = f10,32
   9.284 +	stf.spill [r2]  = f11,32
   9.285 +	;;
   9.286 +	stf.spill [in0] = f12,32
   9.287 +	stf.spill [r2]  = f13,32
   9.288 +	;;
   9.289 +	stf.spill [in0] = f14,32
   9.290 +	stf.spill [r2]  = f15,32
   9.291 +	br.ret.sptk.many rp
   9.292 +END(ia64_save_scratch_fpregs)
   9.293 +
   9.294 +/*
   9.295 + * Load scratch fp scratch regs (fp10-fp15)
   9.296 + *
   9.297 + * Inputs:
   9.298 + *      in0	Address of stack storage for fp regs
   9.299 + */
   9.300 +GLOBAL_ENTRY(ia64_load_scratch_fpregs)
   9.301 +	alloc r3=ar.pfs,1,0,0,0
   9.302 +	add r2=16,in0
   9.303 +	;;
   9.304 +	ldf.fill  f10 = [in0],32
   9.305 +	ldf.fill  f11 = [r2],32
   9.306 +	;;
   9.307 +	ldf.fill  f12 = [in0],32
   9.308 +	ldf.fill  f13 = [r2],32
   9.309 +	;;
   9.310 +	ldf.fill  f14 = [in0],32
   9.311 +	ldf.fill  f15 = [r2],32
   9.312 +	br.ret.sptk.many rp
   9.313 +END(ia64_load_scratch_fpregs)
    10.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    10.2 +++ b/xen/arch/ia64/linux-xen/setup.c	Mon Aug 08 12:21:23 2005 -0700
    10.3 @@ -0,0 +1,773 @@
    10.4 +/*
    10.5 + * Architecture-specific setup.
    10.6 + *
    10.7 + * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
    10.8 + *	David Mosberger-Tang <davidm@hpl.hp.com>
    10.9 + *	Stephane Eranian <eranian@hpl.hp.com>
   10.10 + * Copyright (C) 2000, Rohit Seth <rohit.seth@intel.com>
   10.11 + * Copyright (C) 1999 VA Linux Systems
   10.12 + * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
   10.13 + *
   10.14 + * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
   10.15 + * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
   10.16 + * 03/31/00 R.Seth	cpu_initialized and current->processor fixes
   10.17 + * 02/04/00 D.Mosberger	some more get_cpuinfo fixes...
   10.18 + * 02/01/00 R.Seth	fixed get_cpuinfo for SMP
   10.19 + * 01/07/99 S.Eranian	added the support for command line argument
   10.20 + * 06/24/99 W.Drummond	added boot_cpu_data.
   10.21 + */
   10.22 +#include <linux/config.h>
   10.23 +#include <linux/module.h>
   10.24 +#include <linux/init.h>
   10.25 +
   10.26 +#include <linux/acpi.h>
   10.27 +#include <linux/bootmem.h>
   10.28 +#include <linux/console.h>
   10.29 +#include <linux/delay.h>
   10.30 +#include <linux/kernel.h>
   10.31 +#include <linux/reboot.h>
   10.32 +#include <linux/sched.h>
   10.33 +#include <linux/seq_file.h>
   10.34 +#include <linux/string.h>
   10.35 +#include <linux/threads.h>
   10.36 +#include <linux/tty.h>
   10.37 +#include <linux/serial.h>
   10.38 +#include <linux/serial_core.h>
   10.39 +#include <linux/efi.h>
   10.40 +#include <linux/initrd.h>
   10.41 +
   10.42 +#include <asm/ia32.h>
   10.43 +#include <asm/machvec.h>
   10.44 +#include <asm/mca.h>
   10.45 +#include <asm/meminit.h>
   10.46 +#include <asm/page.h>
   10.47 +#include <asm/patch.h>
   10.48 +#include <asm/pgtable.h>
   10.49 +#include <asm/processor.h>
   10.50 +#include <asm/sal.h>
   10.51 +#include <asm/sections.h>
   10.52 +#include <asm/serial.h>
   10.53 +#include <asm/setup.h>
   10.54 +#include <asm/smp.h>
   10.55 +#include <asm/system.h>
   10.56 +#include <asm/unistd.h>
   10.57 +#ifdef CONFIG_VTI
   10.58 +#include <asm/vmx.h>
   10.59 +#endif // CONFIG_VTI
   10.60 +#include <asm/io.h>
   10.61 +
   10.62 +#if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
   10.63 +# error "struct cpuinfo_ia64 too big!"
   10.64 +#endif
   10.65 +
   10.66 +#ifdef CONFIG_SMP
   10.67 +unsigned long __per_cpu_offset[NR_CPUS];
   10.68 +EXPORT_SYMBOL(__per_cpu_offset);
   10.69 +#endif
   10.70 +
   10.71 +DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
   10.72 +DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
   10.73 +DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8);
   10.74 +unsigned long ia64_cycles_per_usec;
   10.75 +struct ia64_boot_param *ia64_boot_param;
   10.76 +struct screen_info screen_info;
   10.77 +
   10.78 +unsigned long ia64_max_cacheline_size;
   10.79 +unsigned long ia64_iobase;	/* virtual address for I/O accesses */
   10.80 +EXPORT_SYMBOL(ia64_iobase);
   10.81 +struct io_space io_space[MAX_IO_SPACES];
   10.82 +EXPORT_SYMBOL(io_space);
   10.83 +unsigned int num_io_spaces;
   10.84 +
   10.85 +unsigned char aux_device_present = 0xaa;        /* XXX remove this when legacy I/O is gone */
   10.86 +
   10.87 +/*
   10.88 + * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1).  This
   10.89 + * mask specifies a mask of address bits that must be 0 in order for two buffers to be
   10.90 + * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
   10.91 + * address of the second buffer must be aligned to (merge_mask+1) in order to be
   10.92 + * mergeable).  By default, we assume there is no I/O MMU which can merge physically
   10.93 + * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
   10.94 + * page-size of 2^64.
   10.95 + */
   10.96 +unsigned long ia64_max_iommu_merge_mask = ~0UL;
   10.97 +EXPORT_SYMBOL(ia64_max_iommu_merge_mask);
   10.98 +
   10.99 +/*
  10.100 + * We use a special marker for the end of memory and it uses the extra (+1) slot
  10.101 + */
  10.102 +struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1];
  10.103 +int num_rsvd_regions;
  10.104 +
  10.105 +
  10.106 +/*
  10.107 + * Filter incoming memory segments based on the primitive map created from the boot
  10.108 + * parameters. Segments contained in the map are removed from the memory ranges. A
  10.109 + * caller-specified function is called with the memory ranges that remain after filtering.
  10.110 + * This routine does not assume the incoming segments are sorted.
  10.111 + */
  10.112 +int
  10.113 +filter_rsvd_memory (unsigned long start, unsigned long end, void *arg)
  10.114 +{
  10.115 +	unsigned long range_start, range_end, prev_start;
  10.116 +	void (*func)(unsigned long, unsigned long, int);
  10.117 +	int i;
  10.118 +
  10.119 +#if IGNORE_PFN0
  10.120 +	if (start == PAGE_OFFSET) {
  10.121 +		printk(KERN_WARNING "warning: skipping physical page 0\n");
  10.122 +		start += PAGE_SIZE;
  10.123 +		if (start >= end) return 0;
  10.124 +	}
  10.125 +#endif
  10.126 +	/*
  10.127 +	 * lowest possible address(walker uses virtual)
  10.128 +	 */
  10.129 +	prev_start = PAGE_OFFSET;
  10.130 +	func = arg;
  10.131 +
  10.132 +	for (i = 0; i < num_rsvd_regions; ++i) {
  10.133 +		range_start = max(start, prev_start);
  10.134 +		range_end   = min(end, rsvd_region[i].start);
  10.135 +
  10.136 +		if (range_start < range_end)
  10.137 +#ifdef XEN
  10.138 +		{
  10.139 +		/* init_boot_pages requires "ps, pe" */
  10.140 +			printk("Init boot pages: 0x%lx -> 0x%lx.\n",
  10.141 +				__pa(range_start), __pa(range_end));
  10.142 +			(*func)(__pa(range_start), __pa(range_end), 0);
  10.143 +		}
  10.144 +#else
  10.145 +			call_pernode_memory(__pa(range_start), range_end - range_start, func);
  10.146 +#endif
  10.147 +
  10.148 +		/* nothing more available in this segment */
  10.149 +		if (range_end == end) return 0;
  10.150 +
  10.151 +		prev_start = rsvd_region[i].end;
  10.152 +	}
  10.153 +	/* end of memory marker allows full processing inside loop body */
  10.154 +	return 0;
  10.155 +}
  10.156 +
  10.157 +static void
  10.158 +sort_regions (struct rsvd_region *rsvd_region, int max)
  10.159 +{
  10.160 +	int j;
  10.161 +
  10.162 +	/* simple bubble sorting */
  10.163 +	while (max--) {
  10.164 +		for (j = 0; j < max; ++j) {
  10.165 +			if (rsvd_region[j].start > rsvd_region[j+1].start) {
  10.166 +				struct rsvd_region tmp;
  10.167 +				tmp = rsvd_region[j];
  10.168 +				rsvd_region[j] = rsvd_region[j + 1];
  10.169 +				rsvd_region[j + 1] = tmp;
  10.170 +			}
  10.171 +		}
  10.172 +	}
  10.173 +}
  10.174 +
  10.175 +/**
  10.176 + * reserve_memory - setup reserved memory areas
  10.177 + *
  10.178 + * Setup the reserved memory areas set aside for the boot parameters,
  10.179 + * initrd, etc.  There are currently %IA64_MAX_RSVD_REGIONS defined,
  10.180 + * see include/asm-ia64/meminit.h if you need to define more.
  10.181 + */
  10.182 +void
  10.183 +reserve_memory (void)
  10.184 +{
  10.185 +	int n = 0;
  10.186 +
  10.187 +	/*
  10.188 +	 * none of the entries in this table overlap
  10.189 +	 */
  10.190 +	rsvd_region[n].start = (unsigned long) ia64_boot_param;
  10.191 +	rsvd_region[n].end   = rsvd_region[n].start + sizeof(*ia64_boot_param);
  10.192 +	n++;
  10.193 +
  10.194 +	rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
  10.195 +	rsvd_region[n].end   = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
  10.196 +	n++;
  10.197 +
  10.198 +	rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
  10.199 +	rsvd_region[n].end   = (rsvd_region[n].start
  10.200 +				+ strlen(__va(ia64_boot_param->command_line)) + 1);
  10.201 +	n++;
  10.202 +
  10.203 +	rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
  10.204 +#ifdef XEN
  10.205 +	/* Reserve xen image/bitmap/xen-heap */
  10.206 +	rsvd_region[n].end   = rsvd_region[n].start + xenheap_size;
  10.207 +#else
  10.208 +	rsvd_region[n].end   = (unsigned long) ia64_imva(_end);
  10.209 +#endif
  10.210 +	n++;
  10.211 +
  10.212 +#ifdef CONFIG_BLK_DEV_INITRD
  10.213 +	if (ia64_boot_param->initrd_start) {
  10.214 +		rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
  10.215 +		rsvd_region[n].end   = rsvd_region[n].start + ia64_boot_param->initrd_size;
  10.216 +		n++;
  10.217 +	}
  10.218 +#endif
  10.219 +
  10.220 +	/* end of memory marker */
  10.221 +	rsvd_region[n].start = ~0UL;
  10.222 +	rsvd_region[n].end   = ~0UL;
  10.223 +	n++;
  10.224 +
  10.225 +	num_rsvd_regions = n;
  10.226 +
  10.227 +	sort_regions(rsvd_region, num_rsvd_regions);
  10.228 +}
  10.229 +
  10.230 +/**
  10.231 + * find_initrd - get initrd parameters from the boot parameter structure
  10.232 + *
  10.233 + * Grab the initrd start and end from the boot parameter struct given us by
  10.234 + * the boot loader.
  10.235 + */
  10.236 +void
  10.237 +find_initrd (void)
  10.238 +{
  10.239 +#ifdef CONFIG_BLK_DEV_INITRD
  10.240 +	if (ia64_boot_param->initrd_start) {
  10.241 +		initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
  10.242 +		initrd_end   = initrd_start+ia64_boot_param->initrd_size;
  10.243 +
  10.244 +		printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
  10.245 +		       initrd_start, ia64_boot_param->initrd_size);
  10.246 +	}
  10.247 +#endif
  10.248 +}
  10.249 +
  10.250 +static void __init
  10.251 +io_port_init (void)
  10.252 +{
  10.253 +	extern unsigned long ia64_iobase;
  10.254 +	unsigned long phys_iobase;
  10.255 +
  10.256 +	/*
  10.257 +	 *  Set `iobase' to the appropriate address in region 6 (uncached access range).
  10.258 +	 *
  10.259 +	 *  The EFI memory map is the "preferred" location to get the I/O port space base,
  10.260 +	 *  rather the relying on AR.KR0. This should become more clear in future SAL
  10.261 +	 *  specs. We'll fall back to getting it out of AR.KR0 if no appropriate entry is
  10.262 +	 *  found in the memory map.
  10.263 +	 */
  10.264 +	phys_iobase = efi_get_iobase();
  10.265 +	if (phys_iobase)
  10.266 +		/* set AR.KR0 since this is all we use it for anyway */
  10.267 +		ia64_set_kr(IA64_KR_IO_BASE, phys_iobase);
  10.268 +	else {
  10.269 +		phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
  10.270 +		printk(KERN_INFO "No I/O port range found in EFI memory map, falling back "
  10.271 +		       "to AR.KR0\n");
  10.272 +		printk(KERN_INFO "I/O port base = 0x%lx\n", phys_iobase);
  10.273 +	}
  10.274 +	ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
  10.275 +
  10.276 +	/* setup legacy IO port space */
  10.277 +	io_space[0].mmio_base = ia64_iobase;
  10.278 +	io_space[0].sparse = 1;
  10.279 +	num_io_spaces = 1;
  10.280 +}
  10.281 +
  10.282 +/**
  10.283 + * early_console_setup - setup debugging console
  10.284 + *
  10.285 + * Consoles started here require little enough setup that we can start using
  10.286 + * them very early in the boot process, either right after the machine
  10.287 + * vector initialization, or even before if the drivers can detect their hw.
  10.288 + *
  10.289 + * Returns non-zero if a console couldn't be setup.
  10.290 + */
  10.291 +static inline int __init
  10.292 +early_console_setup (char *cmdline)
  10.293 +{
  10.294 +#ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
  10.295 +	{
  10.296 +		extern int sn_serial_console_early_setup(void);
  10.297 +		if (!sn_serial_console_early_setup())
  10.298 +			return 0;
  10.299 +	}
  10.300 +#endif
  10.301 +#ifdef CONFIG_EFI_PCDP
  10.302 +	if (!efi_setup_pcdp_console(cmdline))
  10.303 +		return 0;
  10.304 +#endif
  10.305 +#ifdef CONFIG_SERIAL_8250_CONSOLE
  10.306 +	if (!early_serial_console_init(cmdline))
  10.307 +		return 0;
  10.308 +#endif
  10.309 +
  10.310 +	return -1;
  10.311 +}
  10.312 +
  10.313 +static inline void
  10.314 +mark_bsp_online (void)
  10.315 +{
  10.316 +#ifdef CONFIG_SMP
  10.317 +	/* If we register an early console, allow CPU 0 to printk */
  10.318 +	cpu_set(smp_processor_id(), cpu_online_map);
  10.319 +#endif
  10.320 +}
  10.321 +
  10.322 +void __init
  10.323 +#ifdef XEN
  10.324 +early_setup_arch (char **cmdline_p)
  10.325 +#else
  10.326 +setup_arch (char **cmdline_p)
  10.327 +#endif
  10.328 +{
  10.329 +	unw_init();
  10.330 +
  10.331 +	ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
  10.332 +
  10.333 +	*cmdline_p = __va(ia64_boot_param->command_line);
  10.334 +#ifdef XEN
  10.335 +	efi_init();
  10.336 +#else
  10.337 +	strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE);
  10.338 +
  10.339 +	efi_init();
  10.340 +	io_port_init();
  10.341 +#endif
  10.342 +
  10.343 +#ifdef CONFIG_IA64_GENERIC
  10.344 +	{
  10.345 +		const char *mvec_name = strstr (*cmdline_p, "machvec=");
  10.346 +		char str[64];
  10.347 +
  10.348 +		if (mvec_name) {
  10.349 +			const char *end;
  10.350 +			size_t len;
  10.351 +
  10.352 +			mvec_name += 8;
  10.353 +			end = strchr (mvec_name, ' ');
  10.354 +			if (end)
  10.355 +				len = end - mvec_name;
  10.356 +			else
  10.357 +				len = strlen (mvec_name);
  10.358 +			len = min(len, sizeof (str) - 1);
  10.359 +			strncpy (str, mvec_name, len);
  10.360 +			str[len] = '\0';
  10.361 +			mvec_name = str;
  10.362 +		} else
  10.363 +			mvec_name = acpi_get_sysname();
  10.364 +		machvec_init(mvec_name);
  10.365 +	}
  10.366 +#endif
  10.367 +
  10.368 +#ifdef XEN
  10.369 +	early_cmdline_parse(cmdline_p);
  10.370 +	cmdline_parse(*cmdline_p);
  10.371 +#undef CONFIG_ACPI_BOOT
  10.372 +#endif
  10.373 +	if (early_console_setup(*cmdline_p) == 0)
  10.374 +		mark_bsp_online();
  10.375 +
  10.376 +#ifdef CONFIG_ACPI_BOOT
  10.377 +	/* Initialize the ACPI boot-time table parser */
  10.378 +	acpi_table_init();
  10.379 +# ifdef CONFIG_ACPI_NUMA
  10.380 +	acpi_numa_init();
  10.381 +# endif
  10.382 +#else
  10.383 +# ifdef CONFIG_SMP
  10.384 +	smp_build_cpu_map();	/* happens, e.g., with the Ski simulator */
  10.385 +# endif
  10.386 +#endif /* CONFIG_APCI_BOOT */
  10.387 +
  10.388 +#ifndef XEN
  10.389 +	find_memory();
  10.390 +#else
  10.391 +	io_port_init();
  10.392 +}
  10.393 +
  10.394 +void __init
  10.395 +late_setup_arch (char **cmdline_p)
  10.396 +{
  10.397 +#undef CONFIG_ACPI_BOOT
  10.398 +	acpi_table_init();
  10.399 +#endif
  10.400 +	/* process SAL system table: */
  10.401 +	ia64_sal_init(efi.sal_systab);
  10.402 +
  10.403 +#ifdef CONFIG_SMP
  10.404 +	cpu_physical_id(0) = hard_smp_processor_id();
  10.405 +#endif
  10.406 +
  10.407 +#ifdef CONFIG_VTI
  10.408 +	identify_vmx_feature();
  10.409 +#endif // CONFIG_VTI
  10.410 +
  10.411 +	cpu_init();	/* initialize the bootstrap CPU */
  10.412 +
  10.413 +#ifdef CONFIG_ACPI_BOOT
  10.414 +	acpi_boot_init();
  10.415 +#endif
  10.416 +
  10.417 +#ifdef CONFIG_VT
  10.418 +	if (!conswitchp) {
  10.419 +# if defined(CONFIG_DUMMY_CONSOLE)
  10.420 +		conswitchp = &dummy_con;
  10.421 +# endif
  10.422 +# if defined(CONFIG_VGA_CONSOLE)
  10.423 +		/*
  10.424 +		 * Non-legacy systems may route legacy VGA MMIO range to system
  10.425 +		 * memory.  vga_con probes the MMIO hole, so memory looks like
  10.426 +		 * a VGA device to it.  The EFI memory map can tell us if it's
  10.427 +		 * memory so we can avoid this problem.
  10.428 +		 */
  10.429 +		if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
  10.430 +			conswitchp = &vga_con;
  10.431 +# endif
  10.432 +	}
  10.433 +#endif
  10.434 +
  10.435 +	/* enable IA-64 Machine Check Abort Handling unless disabled */
  10.436 +	if (!strstr(saved_command_line, "nomca"))
  10.437 +		ia64_mca_init();
  10.438 +
  10.439 +	platform_setup(cmdline_p);
  10.440 +	paging_init();
  10.441 +}
  10.442 +
  10.443 +/*
  10.444 + * Display cpu info for all cpu's.
  10.445 + */
  10.446 +static int
  10.447 +show_cpuinfo (struct seq_file *m, void *v)
  10.448 +{
  10.449 +#ifdef CONFIG_SMP
  10.450 +#	define lpj	c->loops_per_jiffy
  10.451 +#	define cpunum	c->cpu
  10.452 +#else
  10.453 +#	define lpj	loops_per_jiffy
  10.454 +#	define cpunum	0
  10.455 +#endif
  10.456 +	static struct {
  10.457 +		unsigned long mask;
  10.458 +		const char *feature_name;
  10.459 +	} feature_bits[] = {
  10.460 +		{ 1UL << 0, "branchlong" },
  10.461 +		{ 1UL << 1, "spontaneous deferral"},
  10.462 +		{ 1UL << 2, "16-byte atomic ops" }
  10.463 +	};
  10.464 +	char family[32], features[128], *cp, sep;
  10.465 +	struct cpuinfo_ia64 *c = v;
  10.466 +	unsigned long mask;
  10.467 +	int i;
  10.468 +
  10.469 +	mask = c->features;
  10.470 +
  10.471 +	switch (c->family) {
  10.472 +	      case 0x07:	memcpy(family, "Itanium", 8); break;
  10.473 +	      case 0x1f:	memcpy(family, "Itanium 2", 10); break;
  10.474 +	      default:		sprintf(family, "%u", c->family); break;
  10.475 +	}
  10.476 +
  10.477 +	/* build the feature string: */
  10.478 +	memcpy(features, " standard", 10);
  10.479 +	cp = features;
  10.480 +	sep = 0;
  10.481 +	for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) {
  10.482 +		if (mask & feature_bits[i].mask) {
  10.483 +			if (sep)
  10.484 +				*cp++ = sep;
  10.485 +			sep = ',';
  10.486 +			*cp++ = ' ';
  10.487 +			strcpy(cp, feature_bits[i].feature_name);
  10.488 +			cp += strlen(feature_bits[i].feature_name);
  10.489 +			mask &= ~feature_bits[i].mask;
  10.490 +		}
  10.491 +	}
  10.492 +	if (mask) {
  10.493 +		/* print unknown features as a hex value: */
  10.494 +		if (sep)
  10.495 +			*cp++ = sep;
  10.496 +		sprintf(cp, " 0x%lx", mask);
  10.497 +	}
  10.498 +
  10.499 +	seq_printf(m,
  10.500 +		   "processor  : %d\n"
  10.501 +		   "vendor     : %s\n"
  10.502 +		   "arch       : IA-64\n"
  10.503 +		   "family     : %s\n"
  10.504 +		   "model      : %u\n"
  10.505 +		   "revision   : %u\n"
  10.506 +		   "archrev    : %u\n"
  10.507 +		   "features   :%s\n"	/* don't change this---it _is_ right! */
  10.508 +		   "cpu number : %lu\n"
  10.509 +		   "cpu regs   : %u\n"
  10.510 +		   "cpu MHz    : %lu.%06lu\n"
  10.511 +		   "itc MHz    : %lu.%06lu\n"
  10.512 +		   "BogoMIPS   : %lu.%02lu\n\n",
  10.513 +		   cpunum, c->vendor, family, c->model, c->revision, c->archrev,
  10.514 +		   features, c->ppn, c->number,
  10.515 +		   c->proc_freq / 1000000, c->proc_freq % 1000000,
  10.516 +		   c->itc_freq / 1000000, c->itc_freq % 1000000,
  10.517 +		   lpj*HZ/500000, (lpj*HZ/5000) % 100);
  10.518 +	return 0;
  10.519 +}
  10.520 +
  10.521 +static void *
  10.522 +c_start (struct seq_file *m, loff_t *pos)
  10.523 +{
  10.524 +#ifdef CONFIG_SMP
  10.525 +	while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map))
  10.526 +		++*pos;
  10.527 +#endif
  10.528 +	return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
  10.529 +}
  10.530 +
  10.531 +static void *
  10.532 +c_next (struct seq_file *m, void *v, loff_t *pos)
  10.533 +{
  10.534 +	++*pos;
  10.535 +	return c_start(m, pos);
  10.536 +}
  10.537 +
  10.538 +static void
  10.539 +c_stop (struct seq_file *m, void *v)
  10.540 +{
  10.541 +}
  10.542 +
  10.543 +#ifndef XEN
  10.544 +struct seq_operations cpuinfo_op = {
  10.545 +	.start =	c_start,
  10.546 +	.next =		c_next,
  10.547 +	.stop =		c_stop,
  10.548 +	.show =		show_cpuinfo
  10.549 +};
  10.550 +#endif
  10.551 +
  10.552 +void
  10.553 +identify_cpu (struct cpuinfo_ia64 *c)
  10.554 +{
  10.555 +	union {
  10.556 +		unsigned long bits[5];
  10.557 +		struct {
  10.558 +			/* id 0 & 1: */
  10.559 +			char vendor[16];
  10.560 +
  10.561 +			/* id 2 */
  10.562 +			u64 ppn;		/* processor serial number */
  10.563 +
  10.564 +			/* id 3: */
  10.565 +			unsigned number		:  8;
  10.566 +			unsigned revision	:  8;
  10.567 +			unsigned model		:  8;
  10.568 +			unsigned family		:  8;
  10.569 +			unsigned archrev	:  8;
  10.570 +			unsigned reserved	: 24;
  10.571 +
  10.572 +			/* id 4: */
  10.573 +			u64 features;
  10.574 +		} field;
  10.575 +	} cpuid;
  10.576 +	pal_vm_info_1_u_t vm1;
  10.577 +	pal_vm_info_2_u_t vm2;
  10.578 +	pal_status_t status;
  10.579 +	unsigned long impl_va_msb = 50, phys_addr_size = 44;	/* Itanium defaults */
  10.580 +	int i;
  10.581 +
  10.582 +	for (i = 0; i < 5; ++i)
  10.583 +		cpuid.bits[i] = ia64_get_cpuid(i);
  10.584 +
  10.585 +	memcpy(c->vendor, cpuid.field.vendor, 16);
  10.586 +#ifdef CONFIG_SMP
  10.587 +	c->cpu = smp_processor_id();
  10.588 +#endif
  10.589 +	c->ppn = cpuid.field.ppn;
  10.590 +	c->number = cpuid.field.number;
  10.591 +	c->revision = cpuid.field.revision;
  10.592 +	c->model = cpuid.field.model;
  10.593 +	c->family = cpuid.field.family;
  10.594 +	c->archrev = cpuid.field.archrev;
  10.595 +	c->features = cpuid.field.features;
  10.596 +
  10.597 +	status = ia64_pal_vm_summary(&vm1, &vm2);
  10.598 +	if (status == PAL_STATUS_SUCCESS) {
  10.599 +		impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
  10.600 +		phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
  10.601 +	}
  10.602 +	c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
  10.603 +	c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
  10.604 +
  10.605 +#ifdef CONFIG_VTI
  10.606 +	/* If vmx feature is on, do necessary initialization for vmx */
  10.607 +	if (vmx_enabled)
  10.608 +		vmx_init_env();
  10.609 +#endif
  10.610 +}
  10.611 +
  10.612 +void
  10.613 +setup_per_cpu_areas (void)
  10.614 +{
  10.615 +	/* start_kernel() requires this... */
  10.616 +}
  10.617 +
  10.618 +static void
  10.619 +get_max_cacheline_size (void)
  10.620 +{
  10.621 +	unsigned long line_size, max = 1;
  10.622 +	u64 l, levels, unique_caches;
  10.623 +        pal_cache_config_info_t cci;
  10.624 +        s64 status;
  10.625 +
  10.626 +        status = ia64_pal_cache_summary(&levels, &unique_caches);
  10.627 +        if (status != 0) {
  10.628 +                printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
  10.629 +                       __FUNCTION__, status);
  10.630 +                max = SMP_CACHE_BYTES;
  10.631 +		goto out;
  10.632 +        }
  10.633 +
  10.634 +	for (l = 0; l < levels; ++l) {
  10.635 +		status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2,
  10.636 +						    &cci);
  10.637 +		if (status != 0) {
  10.638 +			printk(KERN_ERR
  10.639 +			       "%s: ia64_pal_cache_config_info(l=%lu) failed (status=%ld)\n",
  10.640 +			       __FUNCTION__, l, status);
  10.641 +			max = SMP_CACHE_BYTES;
  10.642 +		}
  10.643 +		line_size = 1 << cci.pcci_line_size;
  10.644 +		if (line_size > max)
  10.645 +			max = line_size;
  10.646 +        }
  10.647 +  out:
  10.648 +	if (max > ia64_max_cacheline_size)
  10.649 +		ia64_max_cacheline_size = max;
  10.650 +}
  10.651 +
  10.652 +/*
  10.653 + * cpu_init() initializes state that is per-CPU.  This function acts
  10.654 + * as a 'CPU state barrier', nothing should get across.
  10.655 + */
  10.656 +void
  10.657 +cpu_init (void)
  10.658 +{
  10.659 +	extern void __devinit ia64_mmu_init (void *);
  10.660 +	unsigned long num_phys_stacked;
  10.661 +	pal_vm_info_2_u_t vmi;
  10.662 +	unsigned int max_ctx;
  10.663 +	struct cpuinfo_ia64 *cpu_info;
  10.664 +	void *cpu_data;
  10.665 +
  10.666 +	cpu_data = per_cpu_init();
  10.667 +
  10.668 +	/*
  10.669 +	 * We set ar.k3 so that assembly code in MCA handler can compute
  10.670 +	 * physical addresses of per cpu variables with a simple:
  10.671 +	 *   phys = ar.k3 + &per_cpu_var
  10.672 +	 */
  10.673 +	ia64_set_kr(IA64_KR_PER_CPU_DATA,
  10.674 +		    ia64_tpa(cpu_data) - (long) __per_cpu_start);
  10.675 +
  10.676 +	get_max_cacheline_size();
  10.677 +
  10.678 +	/*
  10.679 +	 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
  10.680 +	 * ia64_mmu_init() yet.  And we can't call ia64_mmu_init() first because it
  10.681 +	 * depends on the data returned by identify_cpu().  We break the dependency by
  10.682 +	 * accessing cpu_data() through the canonical per-CPU address.
  10.683 +	 */
  10.684 +	cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start);
  10.685 +	identify_cpu(cpu_info);
  10.686 +
  10.687 +#ifdef CONFIG_MCKINLEY
  10.688 +	{
  10.689 +#		define FEATURE_SET 16
  10.690 +		struct ia64_pal_retval iprv;
  10.691 +
  10.692 +		if (cpu_info->family == 0x1f) {
  10.693 +			PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
  10.694 +			if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
  10.695 +				PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
  10.696 +				              (iprv.v1 | 0x80), FEATURE_SET, 0);
  10.697 +		}
  10.698 +	}
  10.699 +#endif
  10.700 +
  10.701 +	/* Clear the stack memory reserved for pt_regs: */
  10.702 +	memset(ia64_task_regs(current), 0, sizeof(struct pt_regs));
  10.703 +
  10.704 +	ia64_set_kr(IA64_KR_FPU_OWNER, 0);
  10.705 +
  10.706 +	/*
  10.707 +	 * Initialize default control register to defer all speculative faults.  The
  10.708 +	 * kernel MUST NOT depend on a particular setting of these bits (in other words,
  10.709 +	 * the kernel must have recovery code for all speculative accesses).  Turn on
  10.710 +	 * dcr.lc as per recommendation by the architecture team.  Most IA-32 apps
  10.711 +	 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
  10.712 +	 * be fine).
  10.713 +	 */
  10.714 +	ia64_setreg(_IA64_REG_CR_DCR,  (  IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
  10.715 +					| IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
  10.716 +	atomic_inc(&init_mm.mm_count);
  10.717 +	current->active_mm = &init_mm;
  10.718 +#ifdef XEN
  10.719 +	if (current->domain->arch.mm)
  10.720 +#else
  10.721 +	if (current->mm)
  10.722 +#endif
  10.723 +		BUG();
  10.724 +
  10.725 +	ia64_mmu_init(ia64_imva(cpu_data));
  10.726 +	ia64_mca_cpu_init(ia64_imva(cpu_data));
  10.727 +
  10.728 +#ifdef CONFIG_IA32_SUPPORT
  10.729 +	ia32_cpu_init();
  10.730 +#endif
  10.731 +
  10.732 +	/* Clear ITC to eliminiate sched_clock() overflows in human time.  */
  10.733 +	ia64_set_itc(0);
  10.734 +
  10.735 +	/* disable all local interrupt sources: */
  10.736 +	ia64_set_itv(1 << 16);
  10.737 +	ia64_set_lrr0(1 << 16);
  10.738 +	ia64_set_lrr1(1 << 16);
  10.739 +	ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
  10.740 +	ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
  10.741 +
  10.742 +	/* clear TPR & XTP to enable all interrupt classes: */
  10.743 +	ia64_setreg(_IA64_REG_CR_TPR, 0);
  10.744 +#ifdef CONFIG_SMP
  10.745 +	normal_xtp();
  10.746 +#endif
  10.747 +
  10.748 +	/* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
  10.749 +	if (ia64_pal_vm_summary(NULL, &vmi) == 0)
  10.750 +		max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
  10.751 +	else {
  10.752 +		printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
  10.753 +		max_ctx = (1U << 15) - 1;	/* use architected minimum */
  10.754 +	}
  10.755 +	while (max_ctx < ia64_ctx.max_ctx) {
  10.756 +		unsigned int old = ia64_ctx.max_ctx;
  10.757 +		if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
  10.758 +			break;
  10.759 +	}
  10.760 +
  10.761 +	if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) {
  10.762 +		printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
  10.763 +		       "stacked regs\n");
  10.764 +		num_phys_stacked = 96;
  10.765 +	}
  10.766 +	/* size of physical stacked register partition plus 8 bytes: */
  10.767 +	__get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8;
  10.768 +	platform_cpu_init();
  10.769 +}
  10.770 +
  10.771 +void
  10.772 +check_bugs (void)
  10.773 +{
  10.774 +	ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
  10.775 +			       (unsigned long) __end___mckinley_e9_bundles);
  10.776 +}
    11.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    11.2 +++ b/xen/arch/ia64/linux-xen/time.c	Mon Aug 08 12:21:23 2005 -0700
    11.3 @@ -0,0 +1,264 @@
    11.4 +/*
    11.5 + * linux/arch/ia64/kernel/time.c
    11.6 + *
    11.7 + * Copyright (C) 1998-2003 Hewlett-Packard Co
    11.8 + *	Stephane Eranian <eranian@hpl.hp.com>
    11.9 + *	David Mosberger <davidm@hpl.hp.com>
   11.10 + * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
   11.11 + * Copyright (C) 1999-2000 VA Linux Systems
   11.12 + * Copyright (C) 1999-2000 Walt Drummond <drummond@valinux.com>
   11.13 + */
   11.14 +#include <linux/config.h>
   11.15 +
   11.16 +#include <linux/cpu.h>
   11.17 +#include <linux/init.h>
   11.18 +#include <linux/kernel.h>
   11.19 +#include <linux/module.h>
   11.20 +#include <linux/profile.h>
   11.21 +#include <linux/sched.h>
   11.22 +#include <linux/time.h>
   11.23 +#include <linux/interrupt.h>
   11.24 +#include <linux/efi.h>
   11.25 +#include <linux/profile.h>
   11.26 +#include <linux/timex.h>
   11.27 +
   11.28 +#include <asm/machvec.h>
   11.29 +#include <asm/delay.h>
   11.30 +#include <asm/hw_irq.h>
   11.31 +#include <asm/ptrace.h>
   11.32 +#include <asm/sal.h>
   11.33 +#include <asm/sections.h>
   11.34 +#include <asm/system.h>
   11.35 +#ifdef XEN
   11.36 +#include <linux/jiffies.h>	// not included by xen/sched.h
   11.37 +#endif
   11.38 +
   11.39 +extern unsigned long wall_jiffies;
   11.40 +
   11.41 +u64 jiffies_64 __cacheline_aligned_in_smp = INITIAL_JIFFIES;
   11.42 +
   11.43 +EXPORT_SYMBOL(jiffies_64);
   11.44 +
   11.45 +#define TIME_KEEPER_ID	0	/* smp_processor_id() of time-keeper */
   11.46 +
   11.47 +#ifdef CONFIG_IA64_DEBUG_IRQ
   11.48 +
   11.49 +unsigned long last_cli_ip;
   11.50 +EXPORT_SYMBOL(last_cli_ip);
   11.51 +
   11.52 +#endif
   11.53 +
   11.54 +#ifndef XEN
   11.55 +static struct time_interpolator itc_interpolator = {
   11.56 +	.shift = 16,
   11.57 +	.mask = 0xffffffffffffffffLL,
   11.58 +	.source = TIME_SOURCE_CPU
   11.59 +};
   11.60 +
   11.61 +static irqreturn_t
   11.62 +timer_interrupt (int irq, void *dev_id, struct pt_regs *regs)
   11.63 +{
   11.64 +	unsigned long new_itm;
   11.65 +
   11.66 +	if (unlikely(cpu_is_offline(smp_processor_id()))) {
   11.67 +		return IRQ_HANDLED;
   11.68 +	}
   11.69 +
   11.70 +	platform_timer_interrupt(irq, dev_id, regs);
   11.71 +
   11.72 +	new_itm = local_cpu_data->itm_next;
   11.73 +
   11.74 +	if (!time_after(ia64_get_itc(), new_itm))
   11.75 +		printk(KERN_ERR "Oops: timer tick before it's due (itc=%lx,itm=%lx)\n",
   11.76 +		       ia64_get_itc(), new_itm);
   11.77 +
   11.78 +	profile_tick(CPU_PROFILING, regs);
   11.79 +
   11.80 +	while (1) {
   11.81 +		update_process_times(user_mode(regs));
   11.82 +
   11.83 +		new_itm += local_cpu_data->itm_delta;
   11.84 +
   11.85 +		if (smp_processor_id() == TIME_KEEPER_ID) {
   11.86 +			/*
   11.87 +			 * Here we are in the timer irq handler. We have irqs locally
   11.88 +			 * disabled, but we don't know if the timer_bh is running on
   11.89 +			 * another CPU. We need to avoid to SMP race by acquiring the
   11.90 +			 * xtime_lock.
   11.91 +			 */
   11.92 +			write_seqlock(&xtime_lock);
   11.93 +			do_timer(regs);
   11.94 +			local_cpu_data->itm_next = new_itm;
   11.95 +			write_sequnlock(&xtime_lock);
   11.96 +		} else
   11.97 +			local_cpu_data->itm_next = new_itm;
   11.98 +
   11.99 +		if (time_after(new_itm, ia64_get_itc()))
  11.100 +			break;
  11.101 +	}
  11.102 +
  11.103 +	do {
  11.104 +		/*
  11.105 +		 * If we're too close to the next clock tick for
  11.106 +		 * comfort, we increase the safety margin by
  11.107 +		 * intentionally dropping the next tick(s).  We do NOT
  11.108 +		 * update itm.next because that would force us to call
  11.109 +		 * do_timer() which in turn would let our clock run
  11.110 +		 * too fast (with the potentially devastating effect
  11.111 +		 * of losing monotony of time).
  11.112 +		 */
  11.113 +		while (!time_after(new_itm, ia64_get_itc() + local_cpu_data->itm_delta/2))
  11.114 +			new_itm += local_cpu_data->itm_delta;
  11.115 +		ia64_set_itm(new_itm);
  11.116 +		/* double check, in case we got hit by a (slow) PMI: */
  11.117 +	} while (time_after_eq(ia64_get_itc(), new_itm));
  11.118 +	return IRQ_HANDLED;
  11.119 +}
  11.120 +#endif
  11.121 +
  11.122 +/*
  11.123 + * Encapsulate access to the itm structure for SMP.
  11.124 + */
  11.125 +void
  11.126 +ia64_cpu_local_tick (void)
  11.127 +{
  11.128 +	int cpu = smp_processor_id();
  11.129 +	unsigned long shift = 0, delta;
  11.130 +
  11.131 +	/* arrange for the cycle counter to generate a timer interrupt: */
  11.132 +	ia64_set_itv(IA64_TIMER_VECTOR);
  11.133 +
  11.134 +	delta = local_cpu_data->itm_delta;
  11.135 +	/*
  11.136 +	 * Stagger the timer tick for each CPU so they don't occur all at (almost) the
  11.137 +	 * same time:
  11.138 +	 */
  11.139 +	if (cpu) {
  11.140 +		unsigned long hi = 1UL << ia64_fls(cpu);
  11.141 +		shift = (2*(cpu - hi) + 1) * delta/hi/2;
  11.142 +	}
  11.143 +	local_cpu_data->itm_next = ia64_get_itc() + delta + shift;
  11.144 +	ia64_set_itm(local_cpu_data->itm_next);
  11.145 +}
  11.146 +
  11.147 +static int nojitter;
  11.148 +
  11.149 +static int __init nojitter_setup(char *str)
  11.150 +{
  11.151 +	nojitter = 1;
  11.152 +	printk("Jitter checking for ITC timers disabled\n");
  11.153 +	return 1;
  11.154 +}
  11.155 +
  11.156 +__setup("nojitter", nojitter_setup);
  11.157 +
  11.158 +
  11.159 +void __devinit
  11.160 +ia64_init_itm (void)
  11.161 +{
  11.162 +	unsigned long platform_base_freq, itc_freq;
  11.163 +	struct pal_freq_ratio itc_ratio, proc_ratio;
  11.164 +	long status, platform_base_drift, itc_drift;
  11.165 +
  11.166 +	/*
  11.167 +	 * According to SAL v2.6, we need to use a SAL call to determine the platform base
  11.168 +	 * frequency and then a PAL call to determine the frequency ratio between the ITC
  11.169 +	 * and the base frequency.
  11.170 +	 */
  11.171 +	status = ia64_sal_freq_base(SAL_FREQ_BASE_PLATFORM,
  11.172 +				    &platform_base_freq, &platform_base_drift);
  11.173 +	if (status != 0) {
  11.174 +		printk(KERN_ERR "SAL_FREQ_BASE_PLATFORM failed: %s\n", ia64_sal_strerror(status));
  11.175 +	} else {
  11.176 +		status = ia64_pal_freq_ratios(&proc_ratio, NULL, &itc_ratio);
  11.177 +		if (status != 0)
  11.178 +			printk(KERN_ERR "PAL_FREQ_RATIOS failed with status=%ld\n", status);
  11.179 +	}
  11.180 +	if (status != 0) {
  11.181 +		/* invent "random" values */
  11.182 +		printk(KERN_ERR
  11.183 +		       "SAL/PAL failed to obtain frequency info---inventing reasonable values\n");
  11.184 +		platform_base_freq = 100000000;
  11.185 +		platform_base_drift = -1;	/* no drift info */
  11.186 +		itc_ratio.num = 3;
  11.187 +		itc_ratio.den = 1;
  11.188 +	}
  11.189 +	if (platform_base_freq < 40000000) {
  11.190 +		printk(KERN_ERR "Platform base frequency %lu bogus---resetting to 75MHz!\n",
  11.191 +		       platform_base_freq);
  11.192 +		platform_base_freq = 75000000;
  11.193 +		platform_base_drift = -1;
  11.194 +	}
  11.195 +	if (!proc_ratio.den)
  11.196 +		proc_ratio.den = 1;	/* avoid division by zero */
  11.197 +	if (!itc_ratio.den)
  11.198 +		itc_ratio.den = 1;	/* avoid division by zero */
  11.199 +
  11.200 +	itc_freq = (platform_base_freq*itc_ratio.num)/itc_ratio.den;
  11.201 +
  11.202 +	local_cpu_data->itm_delta = (itc_freq + HZ/2) / HZ;
  11.203 +	printk(KERN_DEBUG "CPU %d: base freq=%lu.%03luMHz, ITC ratio=%lu/%lu, "
  11.204 +	       "ITC freq=%lu.%03luMHz", smp_processor_id(),
  11.205 +	       platform_base_freq / 1000000, (platform_base_freq / 1000) % 1000,
  11.206 +	       itc_ratio.num, itc_ratio.den, itc_freq / 1000000, (itc_freq / 1000) % 1000);
  11.207 +
  11.208 +	if (platform_base_drift != -1) {
  11.209 +		itc_drift = platform_base_drift*itc_ratio.num/itc_ratio.den;
  11.210 +		printk("+/-%ldppm\n", itc_drift);
  11.211 +	} else {
  11.212 +		itc_drift = -1;
  11.213 +		printk("\n");
  11.214 +	}
  11.215 +
  11.216 +	local_cpu_data->proc_freq = (platform_base_freq*proc_ratio.num)/proc_ratio.den;
  11.217 +	local_cpu_data->itc_freq = itc_freq;
  11.218 +	local_cpu_data->cyc_per_usec = (itc_freq + USEC_PER_SEC/2) / USEC_PER_SEC;
  11.219 +	local_cpu_data->nsec_per_cyc = ((NSEC_PER_SEC<<IA64_NSEC_PER_CYC_SHIFT)
  11.220 +					+ itc_freq/2)/itc_freq;
  11.221 +
  11.222 +	if (!(sal_platform_features & IA64_SAL_PLATFORM_FEATURE_ITC_DRIFT)) {
  11.223 +#ifndef XEN
  11.224 +		itc_interpolator.frequency = local_cpu_data->itc_freq;
  11.225 +		itc_interpolator.drift = itc_drift;
  11.226 +#ifdef CONFIG_SMP
  11.227 +		/* On IA64 in an SMP configuration ITCs are never accurately synchronized.
  11.228 +		 * Jitter compensation requires a cmpxchg which may limit
  11.229 +		 * the scalability of the syscalls for retrieving time.
  11.230 +		 * The ITC synchronization is usually successful to within a few
  11.231 +		 * ITC ticks but this is not a sure thing. If you need to improve
  11.232 +		 * timer performance in SMP situations then boot the kernel with the
  11.233 +		 * "nojitter" option. However, doing so may result in time fluctuating (maybe
  11.234 +		 * even going backward) if the ITC offsets between the individual CPUs
  11.235 +		 * are too large.
  11.236 +		 */
  11.237 +		if (!nojitter) itc_interpolator.jitter = 1;
  11.238 +#endif
  11.239 +		register_time_interpolator(&itc_interpolator);
  11.240 +#endif
  11.241 +	}
  11.242 +
  11.243 +	/* Setup the CPU local timer tick */
  11.244 +	ia64_cpu_local_tick();
  11.245 +}
  11.246 +
  11.247 +#ifndef XEN
  11.248 +static struct irqaction timer_irqaction = {
  11.249 +	.handler =	timer_interrupt,
  11.250 +	.flags =	SA_INTERRUPT,
  11.251 +	.name =		"timer"
  11.252 +};
  11.253 +
  11.254 +void __init
  11.255 +time_init (void)
  11.256 +{
  11.257 +	register_percpu_irq(IA64_TIMER_VECTOR, &timer_irqaction);
  11.258 +	efi_gettimeofday(&xtime);
  11.259 +	ia64_init_itm();
  11.260 +
  11.261 +	/*
  11.262 +	 * Initialize wall_to_monotonic such that adding it to xtime will yield zero, the
  11.263 +	 * tv_nsec field must be normalized (i.e., 0 <= nsec < NSEC_PER_SEC).
  11.264 +	 */
  11.265 +	set_normalized_timespec(&wall_to_monotonic, -xtime.tv_sec, -xtime.tv_nsec);
  11.266 +}
  11.267 +#endif
    12.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    12.2 +++ b/xen/arch/ia64/linux-xen/tlb.c	Mon Aug 08 12:21:23 2005 -0700
    12.3 @@ -0,0 +1,199 @@
    12.4 +/*
    12.5 + * TLB support routines.
    12.6 + *
    12.7 + * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
    12.8 + *	David Mosberger-Tang <davidm@hpl.hp.com>
    12.9 + *
   12.10 + * 08/02/00 A. Mallick <asit.k.mallick@intel.com>
   12.11 + *		Modified RID allocation for SMP
   12.12 + *          Goutham Rao <goutham.rao@intel.com>
   12.13 + *              IPI based ptc implementation and A-step IPI implementation.
   12.14 + */
   12.15 +#include <linux/config.h>
   12.16 +#include <linux/module.h>
   12.17 +#include <linux/init.h>
   12.18 +#include <linux/kernel.h>
   12.19 +#include <linux/sched.h>
   12.20 +#include <linux/smp.h>
   12.21 +#include <linux/mm.h>
   12.22 +
   12.23 +#include <asm/delay.h>
   12.24 +#include <asm/mmu_context.h>
   12.25 +#include <asm/pgalloc.h>
   12.26 +#include <asm/pal.h>
   12.27 +#include <asm/tlbflush.h>
   12.28 +
   12.29 +static struct {
   12.30 +	unsigned long mask;	/* mask of supported purge page-sizes */
   12.31 +	unsigned long max_bits;	/* log2() of largest supported purge page-size */
   12.32 +} purge;
   12.33 +
   12.34 +struct ia64_ctx ia64_ctx = {
   12.35 +	.lock =		SPIN_LOCK_UNLOCKED,
   12.36 +	.next =		1,
   12.37 +	.limit =	(1 << 15) - 1,		/* start out with the safe (architected) limit */
   12.38 +	.max_ctx =	~0U
   12.39 +};
   12.40 +
   12.41 +DEFINE_PER_CPU(u8, ia64_need_tlb_flush);
   12.42 +
   12.43 +/*
   12.44 + * Acquire the ia64_ctx.lock before calling this function!
   12.45 + */
   12.46 +void
   12.47 +wrap_mmu_context (struct mm_struct *mm)
   12.48 +{
   12.49 +#ifdef XEN
   12.50 +printf("wrap_mmu_context: called, not implemented\n");
   12.51 +#else
   12.52 +	unsigned long tsk_context, max_ctx = ia64_ctx.max_ctx;
   12.53 +	struct task_struct *tsk;
   12.54 +	int i;
   12.55 +
   12.56 +	if (ia64_ctx.next > max_ctx)
   12.57 +		ia64_ctx.next = 300;	/* skip daemons */
   12.58 +	ia64_ctx.limit = max_ctx + 1;
   12.59 +
   12.60 +	/*
   12.61 +	 * Scan all the task's mm->context and set proper safe range
   12.62 +	 */
   12.63 +
   12.64 +	read_lock(&tasklist_lock);
   12.65 +  repeat:
   12.66 +	for_each_process(tsk) {
   12.67 +		if (!tsk->mm)
   12.68 +			continue;
   12.69 +		tsk_context = tsk->mm->context;
   12.70 +		if (tsk_context == ia64_ctx.next) {
   12.71 +			if (++ia64_ctx.next >= ia64_ctx.limit) {
   12.72 +				/* empty range: reset the range limit and start over */
   12.73 +				if (ia64_ctx.next > max_ctx)
   12.74 +					ia64_ctx.next = 300;
   12.75 +				ia64_ctx.limit = max_ctx + 1;
   12.76 +				goto repeat;
   12.77 +			}
   12.78 +		}
   12.79 +		if ((tsk_context > ia64_ctx.next) && (tsk_context < ia64_ctx.limit))
   12.80 +			ia64_ctx.limit = tsk_context;
   12.81 +	}
   12.82 +	read_unlock(&tasklist_lock);
   12.83 +	/* can't call flush_tlb_all() here because of race condition with O(1) scheduler [EF] */
   12.84 +	{
   12.85 +		int cpu = get_cpu(); /* prevent preemption/migration */
   12.86 +		for (i = 0; i < NR_CPUS; ++i)
   12.87 +			if (cpu_online(i) && (i != cpu))
   12.88 +				per_cpu(ia64_need_tlb_flush, i) = 1;
   12.89 +		put_cpu();
   12.90 +	}
   12.91 +	local_flush_tlb_all();
   12.92 +#endif
   12.93 +}
   12.94 +
   12.95 +void
   12.96 +ia64_global_tlb_purge (unsigned long start, unsigned long end, unsigned long nbits)
   12.97 +{
   12.98 +	static DEFINE_SPINLOCK(ptcg_lock);
   12.99 +
  12.100 +	/* HW requires global serialization of ptc.ga.  */
  12.101 +	spin_lock(&ptcg_lock);
  12.102 +	{
  12.103 +		do {
  12.104 +			/*
  12.105 +			 * Flush ALAT entries also.
  12.106 +			 */
  12.107 +			ia64_ptcga(start, (nbits<<2));
  12.108 +			ia64_srlz_i();
  12.109 +			start += (1UL << nbits);
  12.110 +		} while (start < end);
  12.111 +	}
  12.112 +	spin_unlock(&ptcg_lock);
  12.113 +}
  12.114 +
  12.115 +void
  12.116 +local_flush_tlb_all (void)
  12.117 +{
  12.118 +	unsigned long i, j, flags, count0, count1, stride0, stride1, addr;
  12.119 +
  12.120 +	addr    = local_cpu_data->ptce_base;
  12.121 +	count0  = local_cpu_data->ptce_count[0];
  12.122 +	count1  = local_cpu_data->ptce_count[1];
  12.123 +	stride0 = local_cpu_data->ptce_stride[0];
  12.124 +	stride1 = local_cpu_data->ptce_stride[1];
  12.125 +
  12.126 +	local_irq_save(flags);
  12.127 +	for (i = 0; i < count0; ++i) {
  12.128 +		for (j = 0; j < count1; ++j) {
  12.129 +			ia64_ptce(addr);
  12.130 +			addr += stride1;
  12.131 +		}
  12.132 +		addr += stride0;
  12.133 +	}
  12.134 +	local_irq_restore(flags);
  12.135 +	ia64_srlz_i();			/* srlz.i implies srlz.d */
  12.136 +}
  12.137 +EXPORT_SYMBOL(local_flush_tlb_all);
  12.138 +
  12.139 +void
  12.140 +flush_tlb_range (struct vm_area_struct *vma, unsigned long start, unsigned long end)
  12.141 +{
  12.142 +#ifdef XEN
  12.143 +printf("flush_tlb_range: called, not implemented\n");
  12.144 +#else
  12.145 +	struct mm_struct *mm = vma->vm_mm;
  12.146 +	unsigned long size = end - start;
  12.147 +	unsigned long nbits;
  12.148 +
  12.149 +	if (mm != current->active_mm) {
  12.150 +		/* this does happen, but perhaps it's not worth optimizing for? */
  12.151 +#ifdef CONFIG_SMP
  12.152 +		flush_tlb_all();
  12.153 +#else
  12.154 +		mm->context = 0;
  12.155 +#endif
  12.156 +		return;
  12.157 +	}
  12.158 +
  12.159 +	nbits = ia64_fls(size + 0xfff);
  12.160 +	while (unlikely (((1UL << nbits) & purge.mask) == 0) && (nbits < purge.max_bits))
  12.161 +		++nbits;
  12.162 +	if (nbits > purge.max_bits)
  12.163 +		nbits = purge.max_bits;
  12.164 +	start &= ~((1UL << nbits) - 1);
  12.165 +
  12.166 +# ifdef CONFIG_SMP
  12.167 +	platform_global_tlb_purge(start, end, nbits);
  12.168 +# else
  12.169 +	do {
  12.170 +		ia64_ptcl(start, (nbits<<2));
  12.171 +		start += (1UL << nbits);
  12.172 +	} while (start < end);
  12.173 +# endif
  12.174 +
  12.175 +	ia64_srlz_i();			/* srlz.i implies srlz.d */
  12.176 +#endif
  12.177 +}
  12.178 +EXPORT_SYMBOL(flush_tlb_range);
  12.179 +
  12.180 +void __devinit
  12.181 +ia64_tlb_init (void)
  12.182 +{
  12.183 +	ia64_ptce_info_t ptce_info;
  12.184 +	unsigned long tr_pgbits;
  12.185 +	long status;
  12.186 +
  12.187 +	if ((status = ia64_pal_vm_page_size(&tr_pgbits, &purge.mask)) != 0) {
  12.188 +		printk(KERN_ERR "PAL_VM_PAGE_SIZE failed with status=%ld;"
  12.189 +		       "defaulting to architected purge page-sizes.\n", status);
  12.190 +		purge.mask = 0x115557000UL;
  12.191 +	}
  12.192 +	purge.max_bits = ia64_fls(purge.mask);
  12.193 +
  12.194 +	ia64_get_ptce(&ptce_info);
  12.195 +	local_cpu_data->ptce_base = ptce_info.base;
  12.196 +	local_cpu_data->ptce_count[0] = ptce_info.count[0];
  12.197 +	local_cpu_data->ptce_count[1] = ptce_info.count[1];
  12.198 +	local_cpu_data->ptce_stride[0] = ptce_info.stride[0];
  12.199 +	local_cpu_data->ptce_stride[1] = ptce_info.stride[1];
  12.200 +
  12.201 +	local_flush_tlb_all();		/* nuke left overs from bootstrapping... */
  12.202 +}
    13.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    13.2 +++ b/xen/arch/ia64/linux-xen/unaligned.c	Mon Aug 08 12:21:23 2005 -0700
    13.3 @@ -0,0 +1,1653 @@
    13.4 +/*
    13.5 + * Architecture-specific unaligned trap handling.
    13.6 + *
    13.7 + * Copyright (C) 1999-2002, 2004 Hewlett-Packard Co
    13.8 + *	Stephane Eranian <eranian@hpl.hp.com>
    13.9 + *	David Mosberger-Tang <davidm@hpl.hp.com>
   13.10 + *
   13.11 + * 2002/12/09   Fix rotating register handling (off-by-1 error, missing fr-rotation).  Fix
   13.12 + *		get_rse_reg() to not leak kernel bits to user-level (reading an out-of-frame
   13.13 + *		stacked register returns an undefined value; it does NOT trigger a
   13.14 + *		"rsvd register fault").
   13.15 + * 2001/10/11	Fix unaligned access to rotating registers in s/w pipelined loops.
   13.16 + * 2001/08/13	Correct size of extended floats (float_fsz) from 16 to 10 bytes.
   13.17 + * 2001/01/17	Add support emulation of unaligned kernel accesses.
   13.18 + */
   13.19 +#include <linux/kernel.h>
   13.20 +#include <linux/sched.h>
   13.21 +#include <linux/smp_lock.h>
   13.22 +#include <linux/tty.h>
   13.23 +
   13.24 +#include <asm/intrinsics.h>
   13.25 +#include <asm/processor.h>
   13.26 +#include <asm/rse.h>
   13.27 +#include <asm/uaccess.h>
   13.28 +#include <asm/unaligned.h>
   13.29 +
   13.30 +extern void die_if_kernel(char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn));
   13.31 +
   13.32 +#undef DEBUG_UNALIGNED_TRAP
   13.33 +
   13.34 +#ifdef DEBUG_UNALIGNED_TRAP
   13.35 +# define DPRINT(a...)	do { printk("%s %u: ", __FUNCTION__, __LINE__); printk (a); } while (0)
   13.36 +# define DDUMP(str,vp,len)	dump(str, vp, len)
   13.37 +
   13.38 +static void
   13.39 +dump (const char *str, void *vp, size_t len)
   13.40 +{
   13.41 +	unsigned char *cp = vp;
   13.42 +	int i;
   13.43 +
   13.44 +	printk("%s", str);
   13.45 +	for (i = 0; i < len; ++i)
   13.46 +		printk (" %02x", *cp++);
   13.47 +	printk("\n");
   13.48 +}
   13.49 +#else
   13.50 +# define DPRINT(a...)
   13.51 +# define DDUMP(str,vp,len)
   13.52 +#endif
   13.53 +
   13.54 +#define IA64_FIRST_STACKED_GR	32
   13.55 +#define IA64_FIRST_ROTATING_FR	32
   13.56 +#define SIGN_EXT9		0xffffffffffffff00ul
   13.57 +
   13.58 +/*
   13.59 + * For M-unit:
   13.60 + *
   13.61 + *  opcode |   m  |   x6    |
   13.62 + * --------|------|---------|
   13.63 + * [40-37] | [36] | [35:30] |
   13.64 + * --------|------|---------|
   13.65 + *     4   |   1  |    6    | = 11 bits
   13.66 + * --------------------------
   13.67 + * However bits [31:30] are not directly useful to distinguish between
   13.68 + * load/store so we can use [35:32] instead, which gives the following
   13.69 + * mask ([40:32]) using 9 bits. The 'e' comes from the fact that we defer
   13.70 + * checking the m-bit until later in the load/store emulation.
   13.71 + */
   13.72 +#define IA64_OPCODE_MASK	0x1ef
   13.73 +#define IA64_OPCODE_SHIFT	32
   13.74 +
   13.75 +/*
   13.76 + * Table C-28 Integer Load/Store
   13.77 + *
   13.78 + * We ignore [35:32]= 0x6, 0x7, 0xE, 0xF
   13.79 + *
   13.80 + * ld8.fill, st8.fill  MUST be aligned because the RNATs are based on
   13.81 + * the address (bits [8:3]), so we must failed.
   13.82 + */
   13.83 +#define LD_OP            0x080
   13.84 +#define LDS_OP           0x081
   13.85 +#define LDA_OP           0x082
   13.86 +#define LDSA_OP          0x083
   13.87 +#define LDBIAS_OP        0x084
   13.88 +#define LDACQ_OP         0x085
   13.89 +/* 0x086, 0x087 are not relevant */
   13.90 +#define LDCCLR_OP        0x088
   13.91 +#define LDCNC_OP         0x089
   13.92 +#define LDCCLRACQ_OP     0x08a
   13.93 +#define ST_OP            0x08c
   13.94 +#define STREL_OP         0x08d
   13.95 +/* 0x08e,0x8f are not relevant */
   13.96 +
   13.97 +/*
   13.98 + * Table C-29 Integer Load +Reg
   13.99 + *
  13.100 + * we use the ld->m (bit [36:36]) field to determine whether or not we have
  13.101 + * a load/store of this form.
  13.102 + */
  13.103 +
  13.104 +/*
  13.105 + * Table C-30 Integer Load/Store +Imm
  13.106 + *
  13.107 + * We ignore [35:32]= 0x6, 0x7, 0xE, 0xF
  13.108 + *
  13.109 + * ld8.fill, st8.fill  must be aligned because the Nat register are based on
  13.110 + * the address, so we must fail and the program must be fixed.
  13.111 + */
  13.112 +#define LD_IMM_OP            0x0a0
  13.113 +#define LDS_IMM_OP           0x0a1
  13.114 +#define LDA_IMM_OP           0x0a2
  13.115 +#define LDSA_IMM_OP          0x0a3
  13.116 +#define LDBIAS_IMM_OP        0x0a4
  13.117 +#define LDACQ_IMM_OP         0x0a5
  13.118 +/* 0x0a6, 0xa7 are not relevant */
  13.119 +#define LDCCLR_IMM_OP        0x0a8
  13.120 +#define LDCNC_IMM_OP         0x0a9
  13.121 +#define LDCCLRACQ_IMM_OP     0x0aa
  13.122 +#define ST_IMM_OP            0x0ac
  13.123 +#define STREL_IMM_OP         0x0ad
  13.124 +/* 0x0ae,0xaf are not relevant */
  13.125 +
  13.126 +/*
  13.127 + * Table C-32 Floating-point Load/Store
  13.128 + */
  13.129 +#define LDF_OP           0x0c0
  13.130 +#define LDFS_OP          0x0c1
  13.131 +#define LDFA_OP          0x0c2
  13.132 +#define LDFSA_OP         0x0c3
  13.133 +/* 0x0c6 is irrelevant */
  13.134 +#define LDFCCLR_OP       0x0c8
  13.135 +#define LDFCNC_OP        0x0c9
  13.136 +/* 0x0cb is irrelevant  */
  13.137 +#define STF_OP           0x0cc
  13.138 +
  13.139 +/*
  13.140 + * Table C-33 Floating-point Load +Reg
  13.141 + *
  13.142 + * we use the ld->m (bit [36:36]) field to determine whether or not we have
  13.143 + * a load/store of this form.
  13.144 + */
  13.145 +
  13.146 +/*
  13.147 + * Table C-34 Floating-point Load/Store +Imm
  13.148 + */
  13.149 +#define LDF_IMM_OP       0x0e0
  13.150 +#define LDFS_IMM_OP      0x0e1
  13.151 +#define LDFA_IMM_OP      0x0e2
  13.152 +#define LDFSA_IMM_OP     0x0e3
  13.153 +/* 0x0e6 is irrelevant */
  13.154 +#define LDFCCLR_IMM_OP   0x0e8
  13.155 +#define LDFCNC_IMM_OP    0x0e9
  13.156 +#define STF_IMM_OP       0x0ec
  13.157 +
  13.158 +typedef struct {
  13.159 +	unsigned long	 qp:6;	/* [0:5]   */
  13.160 +	unsigned long    r1:7;	/* [6:12]  */
  13.161 +	unsigned long   imm:7;	/* [13:19] */
  13.162 +	unsigned long    r3:7;	/* [20:26] */
  13.163 +	unsigned long     x:1;  /* [27:27] */
  13.164 +	unsigned long  hint:2;	/* [28:29] */
  13.165 +	unsigned long x6_sz:2;	/* [30:31] */
  13.166 +	unsigned long x6_op:4;	/* [32:35], x6 = x6_sz|x6_op */
  13.167 +	unsigned long     m:1;	/* [36:36] */
  13.168 +	unsigned long    op:4;	/* [37:40] */
  13.169 +	unsigned long   pad:23; /* [41:63] */
  13.170 +} load_store_t;
  13.171 +
  13.172 +
  13.173 +typedef enum {
  13.174 +	UPD_IMMEDIATE,	/* ldXZ r1=[r3],imm(9) */
  13.175 +	UPD_REG		/* ldXZ r1=[r3],r2     */
  13.176 +} update_t;
  13.177 +
  13.178 +/*
  13.179 + * We use tables to keep track of the offsets of registers in the saved state.
  13.180 + * This way we save having big switch/case statements.
  13.181 + *
  13.182 + * We use bit 0 to indicate switch_stack or pt_regs.
  13.183 + * The offset is simply shifted by 1 bit.
  13.184 + * A 2-byte value should be enough to hold any kind of offset
  13.185 + *
  13.186 + * In case the calling convention changes (and thus pt_regs/switch_stack)
  13.187 + * simply use RSW instead of RPT or vice-versa.
  13.188 + */
  13.189 +
  13.190 +#define RPO(x)	((size_t) &((struct pt_regs *)0)->x)
  13.191 +#define RSO(x)	((size_t) &((struct switch_stack *)0)->x)
  13.192 +
  13.193 +#define RPT(x)		(RPO(x) << 1)
  13.194 +#define RSW(x)		(1| RSO(x)<<1)
  13.195 +
  13.196 +#define GR_OFFS(x)	(gr_info[x]>>1)
  13.197 +#define GR_IN_SW(x)	(gr_info[x] & 0x1)
  13.198 +
  13.199 +#define FR_OFFS(x)	(fr_info[x]>>1)
  13.200 +#define FR_IN_SW(x)	(fr_info[x] & 0x1)
  13.201 +
  13.202 +static u16 gr_info[32]={
  13.203 +	0,			/* r0 is read-only : WE SHOULD NEVER GET THIS */
  13.204 +
  13.205 +	RPT(r1), RPT(r2), RPT(r3),
  13.206 +
  13.207 +#ifdef  CONFIG_VTI
  13.208 +	RPT(r4), RPT(r5), RPT(r6), RPT(r7),
  13.209 +#else   //CONFIG_VTI
  13.210 +	RSW(r4), RSW(r5), RSW(r6), RSW(r7),
  13.211 +#endif  //CONFIG_VTI
  13.212 +
  13.213 +	RPT(r8), RPT(r9), RPT(r10), RPT(r11),
  13.214 +	RPT(r12), RPT(r13), RPT(r14), RPT(r15),
  13.215 +
  13.216 +	RPT(r16), RPT(r17), RPT(r18), RPT(r19),
  13.217 +	RPT(r20), RPT(r21), RPT(r22), RPT(r23),
  13.218 +	RPT(r24), RPT(r25), RPT(r26), RPT(r27),
  13.219 +	RPT(r28), RPT(r29), RPT(r30), RPT(r31)
  13.220 +};
  13.221 +
  13.222 +static u16 fr_info[32]={
  13.223 +	0,			/* constant : WE SHOULD NEVER GET THIS */
  13.224 +	0,			/* constant : WE SHOULD NEVER GET THIS */
  13.225 +
  13.226 +	RSW(f2), RSW(f3), RSW(f4), RSW(f5),
  13.227 +
  13.228 +	RPT(f6), RPT(f7), RPT(f8), RPT(f9),
  13.229 +	RPT(f10), RPT(f11),
  13.230 +
  13.231 +	RSW(f12), RSW(f13), RSW(f14),
  13.232 +	RSW(f15), RSW(f16), RSW(f17), RSW(f18), RSW(f19),
  13.233 +	RSW(f20), RSW(f21), RSW(f22), RSW(f23), RSW(f24),
  13.234 +	RSW(f25), RSW(f26), RSW(f27), RSW(f28), RSW(f29),
  13.235 +	RSW(f30), RSW(f31)
  13.236 +};
  13.237 +
  13.238 +/* Invalidate ALAT entry for integer register REGNO.  */
  13.239 +static void
  13.240 +invala_gr (int regno)
  13.241 +{
  13.242 +#	define F(reg)	case reg: ia64_invala_gr(reg); break
  13.243 +
  13.244 +	switch (regno) {
  13.245 +		F(  0); F(  1); F(  2); F(  3); F(  4); F(  5); F(  6); F(  7);
  13.246 +		F(  8); F(  9); F( 10); F( 11); F( 12); F( 13); F( 14); F( 15);
  13.247 +		F( 16); F( 17); F( 18); F( 19); F( 20); F( 21); F( 22); F( 23);
  13.248 +		F( 24); F( 25); F( 26); F( 27); F( 28); F( 29); F( 30); F( 31);
  13.249 +		F( 32); F( 33); F( 34); F( 35); F( 36); F( 37); F( 38); F( 39);
  13.250 +		F( 40); F( 41); F( 42); F( 43); F( 44); F( 45); F( 46); F( 47);
  13.251 +		F( 48); F( 49); F( 50); F( 51); F( 52); F( 53); F( 54); F( 55);
  13.252 +		F( 56); F( 57); F( 58); F( 59); F( 60); F( 61); F( 62); F( 63);
  13.253 +		F( 64); F( 65); F( 66); F( 67); F( 68); F( 69); F( 70); F( 71);
  13.254 +		F( 72); F( 73); F( 74); F( 75); F( 76); F( 77); F( 78); F( 79);
  13.255 +		F( 80); F( 81); F( 82); F( 83); F( 84); F( 85); F( 86); F( 87);
  13.256 +		F( 88); F( 89); F( 90); F( 91); F( 92); F( 93); F( 94); F( 95);
  13.257 +		F( 96); F( 97); F( 98); F( 99); F(100); F(101); F(102); F(103);
  13.258 +		F(104); F(105); F(106); F(107); F(108); F(109); F(110); F(111);
  13.259 +		F(112); F(113); F(114); F(115); F(116); F(117); F(118); F(119);
  13.260 +		F(120); F(121); F(122); F(123); F(124); F(125); F(126); F(127);
  13.261 +	}
  13.262 +#	undef F
  13.263 +}
  13.264 +
  13.265 +/* Invalidate ALAT entry for floating-point register REGNO.  */
  13.266 +static void
  13.267 +invala_fr (int regno)
  13.268 +{
  13.269 +#	define F(reg)	case reg: ia64_invala_fr(reg); break
  13.270 +
  13.271 +	switch (regno) {
  13.272 +		F(  0); F(  1); F(  2); F(  3); F(  4); F(  5); F(  6); F(  7);
  13.273 +		F(  8); F(  9); F( 10); F( 11); F( 12); F( 13); F( 14); F( 15);
  13.274 +		F( 16); F( 17); F( 18); F( 19); F( 20); F( 21); F( 22); F( 23);
  13.275 +		F( 24); F( 25); F( 26); F( 27); F( 28); F( 29); F( 30); F( 31);
  13.276 +		F( 32); F( 33); F( 34); F( 35); F( 36); F( 37); F( 38); F( 39);
  13.277 +		F( 40); F( 41); F( 42); F( 43); F( 44); F( 45); F( 46); F( 47);
  13.278 +		F( 48); F( 49); F( 50); F( 51); F( 52); F( 53); F( 54); F( 55);
  13.279 +		F( 56); F( 57); F( 58); F( 59); F( 60); F( 61); F( 62); F( 63);
  13.280 +		F( 64); F( 65); F( 66); F( 67); F( 68); F( 69); F( 70); F( 71);
  13.281 +		F( 72); F( 73); F( 74); F( 75); F( 76); F( 77); F( 78); F( 79);
  13.282 +		F( 80); F( 81); F( 82); F( 83); F( 84); F( 85); F( 86); F( 87);
  13.283 +		F( 88); F( 89); F( 90); F( 91); F( 92); F( 93); F( 94); F( 95);
  13.284 +		F( 96); F( 97); F( 98); F( 99); F(100); F(101); F(102); F(103);
  13.285 +		F(104); F(105); F(106); F(107); F(108); F(109); F(110); F(111);
  13.286 +		F(112); F(113); F(114); F(115); F(116); F(117); F(118); F(119);
  13.287 +		F(120); F(121); F(122); F(123); F(124); F(125); F(126); F(127);
  13.288 +	}
  13.289 +#	undef F
  13.290 +}
  13.291 +
  13.292 +static inline unsigned long
  13.293 +rotate_reg (unsigned long sor, unsigned long rrb, unsigned long reg)
  13.294 +{
  13.295 +	reg += rrb;
  13.296 +	if (reg >= sor)
  13.297 +		reg -= sor;
  13.298 +	return reg;
  13.299 +}
  13.300 +
  13.301 +#ifdef CONFIG_VTI
  13.302 +static void
  13.303 +set_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long val, unsigned long nat)
  13.304 +{
  13.305 +	struct switch_stack *sw = (struct switch_stack *) regs - 1;
  13.306 +	unsigned long *bsp, *bspstore, *addr, *rnat_addr, *ubs_end;
  13.307 +	unsigned long *kbs = (void *) current + IA64_RBS_OFFSET;
  13.308 +	unsigned long rnats, nat_mask;
  13.309 +    unsigned long old_rsc,new_rsc;
  13.310 +	unsigned long on_kbs,rnat;
  13.311 +	long sof = (regs->cr_ifs) & 0x7f;
  13.312 +	long sor = 8 * ((regs->cr_ifs >> 14) & 0xf);
  13.313 +	long rrb_gr = (regs->cr_ifs >> 18) & 0x7f;
  13.314 +	long ridx = r1 - 32;
  13.315 +
  13.316 +	if (ridx >= sof) {
  13.317 +		/* this should never happen, as the "rsvd register fault" has higher priority */
  13.318 +		DPRINT("ignoring write to r%lu; only %lu registers are allocated!\n", r1, sof);
  13.319 +		return;
  13.320 +	}
  13.321 +
  13.322 +	if (ridx < sor)
  13.323 +		ridx = rotate_reg(sor, rrb_gr, ridx);
  13.324 +
  13.325 +    old_rsc=ia64_get_rsc();
  13.326 +    new_rsc=old_rsc&(~0x3);
  13.327 +    ia64_set_rsc(new_rsc);
  13.328 +
  13.329 +    bspstore = ia64_get_bspstore();
  13.330 +    bsp =kbs + (regs->loadrs >> 19);//16+3
  13.331 +
  13.332 +	addr = ia64_rse_skip_regs(bsp, -sof + ridx);
  13.333 +    nat_mask = 1UL << ia64_rse_slot_num(addr);
  13.334 +	rnat_addr = ia64_rse_rnat_addr(addr);
  13.335 +
  13.336 +    if(addr >= bspstore){
  13.337 +
  13.338 +        ia64_flushrs ();
  13.339 +        ia64_mf ();
  13.340 +		*addr = val;
  13.341 +        bspstore = ia64_get_bspstore();
  13.342 +    	rnat = ia64_get_rnat ();
  13.343 +        if(bspstore < rnat_addr){
  13.344 +            rnat=rnat&(~nat_mask);
  13.345 +        }else{
  13.346 +            *rnat_addr = (*rnat_addr)&(~nat_mask);
  13.347 +        }
  13.348 +        ia64_mf();
  13.349 +        ia64_loadrs();
  13.350 +        ia64_set_rnat(rnat);
  13.351 +    }else{
  13.352 +
  13.353 +    	rnat = ia64_get_rnat ();
  13.354 +		*addr = val;
  13.355 +        if(bspstore < rnat_addr){
  13.356 +            rnat=rnat&(~nat_mask);
  13.357 +        }else{
  13.358 +            *rnat_addr = (*rnat_addr)&(~nat_mask);
  13.359 +        }
  13.360 +        ia64_set_bspstore (bspstore);
  13.361 +        ia64_set_rnat(rnat);
  13.362 +    }
  13.363 +    ia64_set_rsc(old_rsc);
  13.364 +}
  13.365 +
  13.366 +
  13.367 +static void
  13.368 +get_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long *val, unsigned long *nat)
  13.369 +{
  13.370 +	struct switch_stack *sw = (struct switch_stack *) regs - 1;
  13.371 +	unsigned long *bsp, *addr, *rnat_addr, *ubs_end, *bspstore;
  13.372 +	unsigned long *kbs = (void *) current + IA64_RBS_OFFSET;
  13.373 +	unsigned long rnats, nat_mask;
  13.374 +	unsigned long on_kbs;
  13.375 +    unsigned long old_rsc, new_rsc;
  13.376 +	long sof = (regs->cr_ifs) & 0x7f;
  13.377 +	long sor = 8 * ((regs->cr_ifs >> 14) & 0xf);
  13.378 +	long rrb_gr = (regs->cr_ifs >> 18) & 0x7f;
  13.379 +	long ridx = r1 - 32;
  13.380 +
  13.381 +	if (ridx >= sof) {
  13.382 +		/* read of out-of-frame register returns an undefined value; 0 in our case.  */
  13.383 +		DPRINT("ignoring read from r%lu; only %lu registers are allocated!\n", r1, sof);
  13.384 +		panic("wrong stack register number");
  13.385 +	}
  13.386 +
  13.387 +	if (ridx < sor)
  13.388 +		ridx = rotate_reg(sor, rrb_gr, ridx);
  13.389 +
  13.390 +    old_rsc=ia64_get_rsc();
  13.391 +    new_rsc=old_rsc&(~(0x3));
  13.392 +    ia64_set_rsc(new_rsc);
  13.393 +
  13.394 +    bspstore = ia64_get_bspstore();
  13.395 +    bsp =kbs + (regs->loadrs >> 19); //16+3;
  13.396 +
  13.397 +	addr = ia64_rse_skip_regs(bsp, -sof + ridx);
  13.398 +    nat_mask = 1UL << ia64_rse_slot_num(addr);
  13.399 +	rnat_addr = ia64_rse_rnat_addr(addr);
  13.400 +
  13.401 +    if(addr >= bspstore){
  13.402 +
  13.403 +        ia64_flushrs ();
  13.404 +        ia64_mf ();
  13.405 +        bspstore = ia64_get_bspstore();
  13.406 +    }
  13.407 +	*val=*addr;
  13.408 +    if(bspstore < rnat_addr){
  13.409 +        *nat=!!(ia64_get_rnat()&nat_mask);
  13.410 +    }else{
  13.411 +        *nat = !!((*rnat_addr)&nat_mask);
  13.412 +    }
  13.413 +    ia64_set_rsc(old_rsc);
  13.414 +}
  13.415 +#else // CONFIG_VTI
  13.416 +static void
  13.417 +set_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long val, int nat)
  13.418 +{
  13.419 +	struct switch_stack *sw = (struct switch_stack *) regs - 1;
  13.420 +	unsigned long *bsp, *bspstore, *addr, *rnat_addr, *ubs_end;
  13.421 +	unsigned long *kbs = (void *) current + IA64_RBS_OFFSET;
  13.422 +	unsigned long rnats, nat_mask;
  13.423 +	unsigned long on_kbs;
  13.424 +	long sof = (regs->cr_ifs) & 0x7f;
  13.425 +	long sor = 8 * ((regs->cr_ifs >> 14) & 0xf);
  13.426 +	long rrb_gr = (regs->cr_ifs >> 18) & 0x7f;
  13.427 +	long ridx = r1 - 32;
  13.428 +
  13.429 +	if (ridx >= sof) {
  13.430 +		/* this should never happen, as the "rsvd register fault" has higher priority */
  13.431 +		DPRINT("ignoring write to r%lu; only %lu registers are allocated!\n", r1, sof);
  13.432 +		return;
  13.433 +	}
  13.434 +
  13.435 +	if (ridx < sor)
  13.436 +		ridx = rotate_reg(sor, rrb_gr, ridx);
  13.437 +
  13.438 +	DPRINT("r%lu, sw.bspstore=%lx pt.bspstore=%lx sof=%ld sol=%ld ridx=%ld\n",
  13.439 +	       r1, sw->ar_bspstore, regs->ar_bspstore, sof, (regs->cr_ifs >> 7) & 0x7f, ridx);
  13.440 +
  13.441 +	on_kbs = ia64_rse_num_regs(kbs, (unsigned long *) sw->ar_bspstore);
  13.442 +	addr = ia64_rse_skip_regs((unsigned long *) sw->ar_bspstore, -sof + ridx);
  13.443 +	if (addr >= kbs) {
  13.444 +		/* the register is on the kernel backing store: easy... */
  13.445 +		rnat_addr = ia64_rse_rnat_addr(addr);
  13.446 +		if ((unsigned long) rnat_addr >= sw->ar_bspstore)
  13.447 +			rnat_addr = &sw->ar_rnat;
  13.448 +		nat_mask = 1UL << ia64_rse_slot_num(addr);
  13.449 +
  13.450 +		*addr = val;
  13.451 +		if (nat)
  13.452 +			*rnat_addr |=  nat_mask;
  13.453 +		else
  13.454 +			*rnat_addr &= ~nat_mask;
  13.455 +		return;
  13.456 +	}
  13.457 +
  13.458 +	if (!user_stack(current, regs)) {
  13.459 +		DPRINT("ignoring kernel write to r%lu; register isn't on the kernel RBS!", r1);
  13.460 +		return;
  13.461 +	}
  13.462 +
  13.463 +	bspstore = (unsigned long *)regs->ar_bspstore;
  13.464 +	ubs_end = ia64_rse_skip_regs(bspstore, on_kbs);
  13.465 +	bsp     = ia64_rse_skip_regs(ubs_end, -sof);
  13.466 +	addr    = ia64_rse_skip_regs(bsp, ridx);
  13.467 +
  13.468 +	DPRINT("ubs_end=%p bsp=%p addr=%p\n", (void *) ubs_end, (void *) bsp, (void *) addr);
  13.469 +
  13.470 +	ia64_poke(current, sw, (unsigned long) ubs_end, (unsigned long) addr, val);
  13.471 +
  13.472 +	rnat_addr = ia64_rse_rnat_addr(addr);
  13.473 +
  13.474 +	ia64_peek(current, sw, (unsigned long) ubs_end, (unsigned long) rnat_addr, &rnats);
  13.475 +	DPRINT("rnat @%p = 0x%lx nat=%d old nat=%ld\n",
  13.476 +	       (void *) rnat_addr, rnats, nat, (rnats >> ia64_rse_slot_num(addr)) & 1);
  13.477 +
  13.478 +	nat_mask = 1UL << ia64_rse_slot_num(addr);
  13.479 +	if (nat)
  13.480 +		rnats |=  nat_mask;
  13.481 +	else
  13.482 +		rnats &= ~nat_mask;
  13.483 +	ia64_poke(current, sw, (unsigned long) ubs_end, (unsigned long) rnat_addr, rnats);
  13.484 +
  13.485 +	DPRINT("rnat changed to @%p = 0x%lx\n", (void *) rnat_addr, rnats);
  13.486 +}
  13.487 +
  13.488 +
  13.489 +static void
  13.490 +get_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long *val, int *nat)
  13.491 +{
  13.492 +	struct switch_stack *sw = (struct switch_stack *) regs - 1;
  13.493 +	unsigned long *bsp, *addr, *rnat_addr, *ubs_end, *bspstore;
  13.494 +	unsigned long *kbs = (void *) current + IA64_RBS_OFFSET;
  13.495 +	unsigned long rnats, nat_mask;
  13.496 +	unsigned long on_kbs;
  13.497 +	long sof = (regs->cr_ifs) & 0x7f;
  13.498 +	long sor = 8 * ((regs->cr_ifs >> 14) & 0xf);
  13.499 +	long rrb_gr = (regs->cr_ifs >> 18) & 0x7f;
  13.500 +	long ridx = r1 - 32;
  13.501 +
  13.502 +	if (ridx >= sof) {
  13.503 +		/* read of out-of-frame register returns an undefined value; 0 in our case.  */
  13.504 +		DPRINT("ignoring read from r%lu; only %lu registers are allocated!\n", r1, sof);
  13.505 +		goto fail;
  13.506 +	}
  13.507 +
  13.508 +	if (ridx < sor)
  13.509 +		ridx = rotate_reg(sor, rrb_gr, ridx);
  13.510 +
  13.511 +	DPRINT("r%lu, sw.bspstore=%lx pt.bspstore=%lx sof=%ld sol=%ld ridx=%ld\n",
  13.512 +	       r1, sw->ar_bspstore, regs->ar_bspstore, sof, (regs->cr_ifs >> 7) & 0x7f, ridx);
  13.513 +
  13.514 +	on_kbs = ia64_rse_num_regs(kbs, (unsigned long *) sw->ar_bspstore);
  13.515 +	addr = ia64_rse_skip_regs((unsigned long *) sw->ar_bspstore, -sof + ridx);
  13.516 +	if (addr >= kbs) {
  13.517 +		/* the register is on the kernel backing store: easy... */
  13.518 +		*val = *addr;
  13.519 +		if (nat) {
  13.520 +			rnat_addr = ia64_rse_rnat_addr(addr);
  13.521 +			if ((unsigned long) rnat_addr >= sw->ar_bspstore)
  13.522 +				rnat_addr = &sw->ar_rnat;
  13.523 +			nat_mask = 1UL << ia64_rse_slot_num(addr);
  13.524 +			*nat = (*rnat_addr & nat_mask) != 0;
  13.525 +		}
  13.526 +		return;
  13.527 +	}
  13.528 +
  13.529 +	if (!user_stack(current, regs)) {
  13.530 +		DPRINT("ignoring kernel read of r%lu; register isn't on the RBS!", r1);
  13.531 +		goto fail;
  13.532 +	}
  13.533 +
  13.534 +	bspstore = (unsigned long *)regs->ar_bspstore;
  13.535 +	ubs_end = ia64_rse_skip_regs(bspstore, on_kbs);
  13.536 +	bsp     = ia64_rse_skip_regs(ubs_end, -sof);
  13.537 +	addr    = ia64_rse_skip_regs(bsp, ridx);
  13.538 +
  13.539 +	DPRINT("ubs_end=%p bsp=%p addr=%p\n", (void *) ubs_end, (void *) bsp, (void *) addr);
  13.540 +
  13.541 +	ia64_peek(current, sw, (unsigned long) ubs_end, (unsigned long) addr, val);
  13.542 +
  13.543 +	if (nat) {
  13.544 +		rnat_addr = ia64_rse_rnat_addr(addr);
  13.545 +		nat_mask = 1UL << ia64_rse_slot_num(addr);
  13.546 +
  13.547 +		DPRINT("rnat @%p = 0x%lx\n", (void *) rnat_addr, rnats);
  13.548 +
  13.549 +		ia64_peek(current, sw, (unsigned long) ubs_end, (unsigned long) rnat_addr, &rnats);
  13.550 +		*nat = (rnats & nat_mask) != 0;
  13.551 +	}
  13.552 +	return;
  13.553 +
  13.554 +  fail:
  13.555 +	*val = 0;
  13.556 +	if (nat)
  13.557 +		*nat = 0;
  13.558 +	return;
  13.559 +}
  13.560 +#endif // CONFIG_VTI
  13.561 +
  13.562 +
  13.563 +#ifdef XEN
  13.564 +void
  13.565 +#else
  13.566 +static void
  13.567 +#endif
  13.568 +setreg (unsigned long regnum, unsigned long val, int nat, struct pt_regs *regs)
  13.569 +{
  13.570 +	struct switch_stack *sw = (struct switch_stack *) regs - 1;
  13.571 +	unsigned long addr;
  13.572 +	unsigned long bitmask;
  13.573 +	unsigned long *unat;
  13.574 +
  13.575 +	/*
  13.576 +	 * First takes care of stacked registers
  13.577 +	 */
  13.578 +	if (regnum >= IA64_FIRST_STACKED_GR) {
  13.579 +		set_rse_reg(regs, regnum, val, nat);
  13.580 +		return;
  13.581 +	}
  13.582 +
  13.583 +	/*
  13.584 +	 * Using r0 as a target raises a General Exception fault which has higher priority
  13.585 +	 * than the Unaligned Reference fault.
  13.586 +	 */
  13.587 +
  13.588 +	/*
  13.589 +	 * Now look at registers in [0-31] range and init correct UNAT
  13.590 +	 */
  13.591 +	if (GR_IN_SW(regnum)) {
  13.592 +		addr = (unsigned long)sw;
  13.593 +		unat = &sw->ar_unat;
  13.594 +	} else {
  13.595 +		addr = (unsigned long)regs;
  13.596 +#ifdef CONFIG_VTI
  13.597 +		unat = &regs->eml_unat;
  13.598 +#else //CONFIG_VTI
  13.599 +		unat = &sw->caller_unat;
  13.600 +#endif  //CONFIG_VTI
  13.601 +	}
  13.602 +	DPRINT("tmp_base=%lx switch_stack=%s offset=%d\n",
  13.603 +	       addr, unat==&sw->ar_unat ? "yes":"no", GR_OFFS(regnum));
  13.604 +	/*
  13.605 +	 * add offset from base of struct
  13.606 +	 * and do it !
  13.607 +	 */
  13.608 +	addr += GR_OFFS(regnum);
  13.609 +
  13.610 +	*(unsigned long *)addr = val;
  13.611 +
  13.612 +	/*
  13.613 +	 * We need to clear the corresponding UNAT bit to fully emulate the load
  13.614 +	 * UNAT bit_pos = GR[r3]{8:3} form EAS-2.4
  13.615 +	 */
  13.616 +	bitmask   = 1UL << (addr >> 3 & 0x3f);
  13.617 +	DPRINT("*0x%lx=0x%lx NaT=%d prev_unat @%p=%lx\n", addr, val, nat, (void *) unat, *unat);
  13.618 +	if (nat) {
  13.619 +		*unat |= bitmask;
  13.620 +	} else {
  13.621 +		*unat &= ~bitmask;
  13.622 +	}
  13.623 +	DPRINT("*0x%lx=0x%lx NaT=%d new unat: %p=%lx\n", addr, val, nat, (void *) unat,*unat);
  13.624 +}
  13.625 +
  13.626 +/*
  13.627 + * Return the (rotated) index for floating point register REGNUM (REGNUM must be in the
  13.628 + * range from 32-127, result is in the range from 0-95.
  13.629 + */
  13.630 +static inline unsigned long
  13.631 +fph_index (struct pt_regs *regs, long regnum)
  13.632 +{
  13.633 +	unsigned long rrb_fr = (regs->cr_ifs >> 25) & 0x7f;
  13.634 +	return rotate_reg(96, rrb_fr, (regnum - IA64_FIRST_ROTATING_FR));
  13.635 +}
  13.636 +
  13.637 +static void
  13.638 +setfpreg (unsigned long regnum, struct ia64_fpreg *fpval, struct pt_regs *regs)
  13.639 +{
  13.640 +	struct switch_stack *sw = (struct switch_stack *)regs - 1;
  13.641 +	unsigned long addr;
  13.642 +
  13.643 +	/*
  13.644 +	 * From EAS-2.5: FPDisableFault has higher priority than Unaligned
  13.645 +	 * Fault. Thus, when we get here, we know the partition is enabled.
  13.646 +	 * To update f32-f127, there are three choices:
  13.647 +	 *
  13.648 +	 *	(1) save f32-f127 to thread.fph and update the values there
  13.649 +	 *	(2) use a gigantic switch statement to directly access the registers
  13.650 +	 *	(3) generate code on the fly to update the desired register
  13.651 +	 *
  13.652 +	 * For now, we are using approach (1).
  13.653 +	 */
  13.654 +	if (regnum >= IA64_FIRST_ROTATING_FR) {
  13.655 +		ia64_sync_fph(current);
  13.656 +#ifdef XEN
  13.657 +		current->arch._thread.fph[fph_index(regs, regnum)] = *fpval;
  13.658 +#else
  13.659 +		current->thread.fph[fph_index(regs, regnum)] = *fpval;
  13.660 +#endif
  13.661 +	} else {
  13.662 +		/*
  13.663 +		 * pt_regs or switch_stack ?
  13.664 +		 */
  13.665 +		if (FR_IN_SW(regnum)) {
  13.666 +			addr = (unsigned long)sw;
  13.667 +		} else {
  13.668 +			addr = (unsigned long)regs;
  13.669 +		}
  13.670 +
  13.671 +		DPRINT("tmp_base=%lx offset=%d\n", addr, FR_OFFS(regnum));
  13.672 +
  13.673 +		addr += FR_OFFS(regnum);
  13.674 +		*(struct ia64_fpreg *)addr = *fpval;
  13.675 +
  13.676 +		/*
  13.677 +		 * mark the low partition as being used now
  13.678 +		 *
  13.679 +		 * It is highly unlikely that this bit is not already set, but
  13.680 +		 * let's do it for safety.
  13.681 +		 */
  13.682 +		regs->cr_ipsr |= IA64_PSR_MFL;
  13.683 +	}
  13.684 +}
  13.685 +
  13.686 +/*
  13.687 + * Those 2 inline functions generate the spilled versions of the constant floating point
  13.688 + * registers which can be used with stfX
  13.689 + */
  13.690 +static inline void
  13.691 +float_spill_f0 (struct ia64_fpreg *final)
  13.692 +{
  13.693 +	ia64_stf_spill(final, 0);
  13.694 +}
  13.695 +
  13.696 +static inline void
  13.697 +float_spill_f1 (struct ia64_fpreg *final)
  13.698 +{
  13.699 +	ia64_stf_spill(final, 1);
  13.700 +}
  13.701 +
  13.702 +static void
  13.703 +getfpreg (unsigned long regnum, struct ia64_fpreg *fpval, struct pt_regs *regs)
  13.704 +{
  13.705 +	struct switch_stack *sw = (struct switch_stack *) regs - 1;
  13.706 +	unsigned long addr;
  13.707 +
  13.708 +	/*
  13.709 +	 * From EAS-2.5: FPDisableFault has higher priority than
  13.710 +	 * Unaligned Fault. Thus, when we get here, we know the partition is
  13.711 +	 * enabled.
  13.712 +	 *
  13.713 +	 * When regnum > 31, the register is still live and we need to force a save
  13.714 +	 * to current->thread.fph to get access to it.  See discussion in setfpreg()
  13.715 +	 * for reasons and other ways of doing this.
  13.716 +	 */
  13.717 +	if (regnum >= IA64_FIRST_ROTATING_FR) {
  13.718 +		ia64_flush_fph(current);
  13.719 +#ifdef XEN
  13.720 +		*fpval = current->arch._thread.fph[fph_index(regs, regnum)];
  13.721 +#else
  13.722 +		*fpval = current->thread.fph[fph_index(regs, regnum)];
  13.723 +#endif
  13.724 +	} else {
  13.725 +		/*
  13.726 +		 * f0 = 0.0, f1= 1.0. Those registers are constant and are thus
  13.727 +		 * not saved, we must generate their spilled form on the fly
  13.728 +		 */
  13.729 +		switch(regnum) {
  13.730 +		case 0:
  13.731 +			float_spill_f0(fpval);
  13.732 +			break;
  13.733 +		case 1:
  13.734 +			float_spill_f1(fpval);
  13.735 +			break;
  13.736 +		default:
  13.737 +			/*
  13.738 +			 * pt_regs or switch_stack ?
  13.739 +			 */
  13.740 +			addr =  FR_IN_SW(regnum) ? (unsigned long)sw
  13.741 +						 : (unsigned long)regs;
  13.742 +
  13.743 +			DPRINT("is_sw=%d tmp_base=%lx offset=0x%x\n",
  13.744 +			       FR_IN_SW(regnum), addr, FR_OFFS(regnum));
  13.745 +
  13.746 +			addr  += FR_OFFS(regnum);
  13.747 +			*fpval = *(struct ia64_fpreg *)addr;
  13.748 +		}
  13.749 +	}
  13.750 +}
  13.751 +
  13.752 +
  13.753 +#ifdef XEN
  13.754 +void
  13.755 +#else
  13.756 +static void
  13.757 +#endif
  13.758 +getreg (unsigned long regnum, unsigned long *val, int *nat, struct pt_regs *regs)
  13.759 +{
  13.760 +	struct switch_stack *sw = (struct switch_stack *) regs - 1;
  13.761 +	unsigned long addr, *unat;
  13.762 +
  13.763 +	if (regnum >= IA64_FIRST_STACKED_GR) {
  13.764 +		get_rse_reg(regs, regnum, val, nat);
  13.765 +		return;
  13.766 +	}
  13.767 +
  13.768 +	/*
  13.769 +	 * take care of r0 (read-only always evaluate to 0)
  13.770 +	 */
  13.771 +	if (regnum == 0) {
  13.772 +		*val = 0;
  13.773 +		if (nat)
  13.774 +			*nat = 0;
  13.775 +		return;
  13.776 +	}
  13.777 +
  13.778 +	/*
  13.779 +	 * Now look at registers in [0-31] range and init correct UNAT
  13.780 +	 */
  13.781 +	if (GR_IN_SW(regnum)) {
  13.782 +		addr = (unsigned long)sw;
  13.783 +		unat = &sw->ar_unat;
  13.784 +	} else {
  13.785 +		addr = (unsigned long)regs;
  13.786 +#ifdef  CONFIG_VTI
  13.787 +		unat = &regs->eml_unat;;
  13.788 +#else   //CONFIG_VTI
  13.789 +		unat = &sw->caller_unat;
  13.790 +#endif  //CONFIG_VTI
  13.791 +	}
  13.792 +
  13.793 +	DPRINT("addr_base=%lx offset=0x%x\n", addr,  GR_OFFS(regnum));
  13.794 +
  13.795 +	addr += GR_OFFS(regnum);
  13.796 +
  13.797 +	*val  = *(unsigned long *)addr;
  13.798 +
  13.799 +	/*
  13.800 +	 * do it only when requested
  13.801 +	 */
  13.802 +	if (nat)
  13.803 +		*nat  = (*unat >> (addr >> 3 & 0x3f)) & 0x1UL;
  13.804 +}
  13.805 +
  13.806 +static void
  13.807 +emulate_load_updates (update_t type, load_store_t ld, struct pt_regs *regs, unsigned long ifa)
  13.808 +{
  13.809 +	/*
  13.810 +	 * IMPORTANT:
  13.811 +	 * Given the way we handle unaligned speculative loads, we should
  13.812 +	 * not get to this point in the code but we keep this sanity check,
  13.813 +	 * just in case.
  13.814 +	 */
  13.815 +	if (ld.x6_op == 1 || ld.x6_op == 3) {
  13.816 +		printk(KERN_ERR "%s: register update on speculative load, error\n", __FUNCTION__);
  13.817 +		die_if_kernel("unaligned reference on speculative load with register update\n",
  13.818 +			      regs, 30);
  13.819 +	}
  13.820 +
  13.821 +
  13.822 +	/*
  13.823 +	 * at this point, we know that the base register to update is valid i.e.,
  13.824 +	 * it's not r0
  13.825 +	 */
  13.826 +	if (type == UPD_IMMEDIATE) {
  13.827 +		unsigned long imm;
  13.828 +
  13.829 +		/*
  13.830 +		 * Load +Imm: ldXZ r1=[r3],imm(9)
  13.831 +		 *
  13.832 +		 *
  13.833 +		 * form imm9: [13:19] contain the first 7 bits
  13.834 +		 */
  13.835 +		imm = ld.x << 7 | ld.imm;
  13.836 +
  13.837 +		/*
  13.838 +		 * sign extend (1+8bits) if m set
  13.839 +		 */
  13.840 +		if (ld.m) imm |= SIGN_EXT9;
  13.841 +
  13.842 +		/*
  13.843 +		 * ifa == r3 and we know that the NaT bit on r3 was clear so
  13.844 +		 * we can directly use ifa.
  13.845 +		 */
  13.846 +		ifa += imm;
  13.847 +
  13.848 +		setreg(ld.r3, ifa, 0, regs);
  13.849 +
  13.850 +		DPRINT("ld.x=%d ld.m=%d imm=%ld r3=0x%lx\n", ld.x, ld.m, imm, ifa);
  13.851 +
  13.852 +	} else if (ld.m) {
  13.853 +		unsigned long r2;
  13.854 +		int nat_r2;
  13.855 +
  13.856 +		/*
  13.857 +		 * Load +Reg Opcode: ldXZ r1=[r3],r2
  13.858 +		 *
  13.859 +		 * Note: that we update r3 even in the case of ldfX.a
  13.860 +		 * (where the load does not happen)
  13.861 +		 *
  13.862 +		 * The way the load algorithm works, we know that r3 does not
  13.863 +		 * have its NaT bit set (would have gotten NaT consumption
  13.864 +		 * before getting the unaligned fault). So we can use ifa
  13.865 +		 * which equals r3 at this point.
  13.866 +		 *
  13.867 +		 * IMPORTANT:
  13.868 +		 * The above statement holds ONLY because we know that we
  13.869 +		 * never reach this code when trying to do a ldX.s.
  13.870 +		 * If we ever make it to here on an ldfX.s then
  13.871 +		 */
  13.872 +		getreg(ld.imm, &r2, &nat_r2, regs);
  13.873 +
  13.874 +		ifa += r2;
  13.875 +
  13.876 +		/*
  13.877 +		 * propagate Nat r2 -> r3
  13.878 +		 */
  13.879 +		setreg(ld.r3, ifa, nat_r2, regs);
  13.880 +
  13.881 +		DPRINT("imm=%d r2=%ld r3=0x%lx nat_r2=%d\n",ld.imm, r2, ifa, nat_r2);
  13.882 +	}
  13.883 +}
  13.884 +
  13.885 +
  13.886 +static int
  13.887 +emulate_load_int (unsigned long ifa, load_store_t ld, struct pt_regs *regs)
  13.888 +{
  13.889 +	unsigned int len = 1 << ld.x6_sz;
  13.890 +	unsigned long val = 0;
  13.891 +
  13.892 +	/*
  13.893 +	 * r0, as target, doesn't need to be checked because Illegal Instruction
  13.894 +	 * faults have higher priority than unaligned faults.
  13.895 +	 *
  13.896 +	 * r0 cannot be found as the base as it would never generate an
  13.897 +	 * unaligned reference.
  13.898 +	 */
  13.899 +
  13.900 +	/*
  13.901 +	 * ldX.a we will emulate load and also invalidate the ALAT entry.
  13.902 +	 * See comment below for explanation on how we handle ldX.a
  13.903 +	 */
  13.904 +
  13.905 +	if (len != 2 && len != 4 && len != 8) {
  13.906 +		DPRINT("unknown size: x6=%d\n", ld.x6_sz);
  13.907 +		return -1;
  13.908 +	}
  13.909 +	/* this assumes little-endian byte-order: */
  13.910 +	if (copy_from_user(&val, (void __user *) ifa, len))
  13.911 +		return -1;
  13.912 +	setreg(ld.r1, val, 0, regs);
  13.913 +
  13.914 +	/*
  13.915 +	 * check for updates on any kind of loads
  13.916 +	 */
  13.917 +	if (ld.op == 0x5 || ld.m)
  13.918 +		emulate_load_updates(ld.op == 0x5 ? UPD_IMMEDIATE: UPD_REG, ld, regs, ifa);
  13.919 +
  13.920 +	/*
  13.921 +	 * handling of various loads (based on EAS2.4):
  13.922 +	 *
  13.923 +	 * ldX.acq (ordered load):
  13.924 +	 *	- acquire semantics would have been used, so force fence instead.
  13.925 +	 *
  13.926 +	 * ldX.c.clr (check load and clear):
  13.927 +	 *	- if we get to this handler, it's because the entry was not in the ALAT.
  13.928 +	 *	  Therefore the operation reverts to a normal load
  13.929 +	 *
  13.930 +	 * ldX.c.nc (check load no clear):
  13.931 +	 *	- same as previous one
  13.932 +	 *
  13.933 +	 * ldX.c.clr.acq (ordered check load and clear):
  13.934 +	 *	- same as above for c.clr part. The load needs to have acquire semantics. So
  13.935 +	 *	  we use the fence semantics which is stronger and thus ensures correctness.
  13.936 +	 *
  13.937 +	 * ldX.a (advanced load):
  13.938 +	 *	- suppose ldX.a r1=[r3]. If we get to the unaligned trap it's because the
  13.939 +	 *	  address doesn't match requested size alignment. This means that we would
  13.940 +	 *	  possibly need more than one load to get the result.
  13.941 +	 *
  13.942 +	 *	  The load part can be handled just like a normal load, however the difficult
  13.943 +	 *	  part is to get the right thing into the ALAT. The critical piece of information
  13.944 +	 *	  in the base address of the load & size. To do that, a ld.a must be executed,
  13.945 +	 *	  clearly any address can be pushed into the table by using ld1.a r1=[r3]. Now
  13.946 +	 *	  if we use the same target register, we will be okay for the check.a instruction.
  13.947 +	 *	  If we look at the store, basically a stX [r3]=r1 checks the ALAT  for any entry
  13.948 +	 *	  which would overlap within [r3,r3+X] (the size of the load was store in the
  13.949 +	 *	  ALAT). If such an entry is found the entry is invalidated. But this is not good
  13.950 +	 *	  enough, take the following example:
  13.951 +	 *		r3=3
  13.952 +	 *		ld4.a r1=[r3]
  13.953 +	 *
  13.954 +	 *	  Could be emulated by doing:
  13.955 +	 *		ld1.a r1=[r3],1
  13.956 +	 *		store to temporary;
  13.957 +	 *		ld1.a r1=[r3],1
  13.958 +	 *		store & shift to temporary;
  13.959 +	 *		ld1.a r1=[r3],1
  13.960 +	 *		store & shift to temporary;
  13.961 +	 *		ld1.a r1=[r3]
  13.962 +	 *		store & shift to temporary;
  13.963 +	 *		r1=temporary
  13.964 +	 *
  13.965 +	 *	  So in this case, you would get the right value is r1 but the wrong info in
  13.966 +	 *	  the ALAT.  Notice that you could do it in reverse to finish with address 3
  13.967 +	 *	  but you would still get the size wrong.  To get the size right, one needs to
  13.968 +	 *	  execute exactly the same kind of load. You could do it from a aligned
  13.969 +	 *	  temporary location, but you would get the address wrong.
  13.970 +	 *
  13.971 +	 *	  So no matter what, it is not possible to emulate an advanced load
  13.972 +	 *	  correctly. But is that really critical ?
  13.973 +	 *
  13.974 +	 *	  We will always convert ld.a into a normal load with ALAT invalidated.  This
  13.975 +	 *	  will enable compiler to do optimization where certain code path after ld.a
  13.976 +	 *	  is not required to have ld.c/chk.a, e.g., code path with no intervening stores.
  13.977 +	 *
  13.978 +	 *	  If there is a store after the advanced load, one must either do a ld.c.* or
  13.979 +	 *	  chk.a.* to reuse the value stored in the ALAT. Both can "fail" (meaning no
  13.980 +	 *	  entry found in ALAT), and that's perfectly ok because:
  13.981 +	 *
  13.982 +	 *		- ld.c.*, if the entry is not present a  normal load is executed
  13.983 +	 *		- chk.a.*, if the entry is not present, execution jumps to recovery code
  13.984 +	 *
  13.985 +	 *	  In either case, the load can be potentially retried in another form.
  13.986 +	 *
  13.987 +	 *	  ALAT must be invalidated for the register (so that chk.a or ld.c don't pick
  13.988 +	 *	  up a stale entry later). The register base update MUST also be performed.
  13.989 +	 */
  13.990 +
  13.991 +	/*
  13.992 +	 * when the load has the .acq completer then
  13.993 +	 * use ordering fence.
  13.994 +	 */
  13.995 +	if (ld.x6_op == 0x5 || ld.x6_op == 0xa)
  13.996 +		mb();
  13.997 +
  13.998 +	/*
  13.999 +	 * invalidate ALAT entry in case of advanced load
 13.1000 +	 */
 13.1001 +	if (ld.x6_op == 0x2)
 13.1002 +		invala_gr(ld.r1);
 13.1003 +
 13.1004 +	return 0;
 13.1005 +}
 13.1006 +
 13.1007 +static int
 13.1008 +emulate_store_int (unsigned long ifa, load_store_t ld, struct pt_regs *regs)
 13.1009 +{
 13.1010 +	unsigned long r2;
 13.1011 +	unsigned int len = 1 << ld.x6_sz;
 13.1012 +
 13.1013 +	/*
 13.1014 +	 * if we get to this handler, Nat bits on both r3 and r2 have already
 13.1015 +	 * been checked. so we don't need to do it
 13.1016 +	 *
 13.1017 +	 * extract the value to be stored
 13.1018 +	 */
 13.1019 +	getreg(ld.imm, &r2, NULL, regs);
 13.1020 +
 13.1021 +	/*
 13.1022 +	 * we rely on the macros in unaligned.h for now i.e.,
 13.1023 +	 * we let the compiler figure out how to read memory gracefully.
 13.1024 +	 *
 13.1025 +	 * We need this switch/case because the way the inline function
 13.1026 +	 * works. The code is optimized by the compiler and looks like
 13.1027 +	 * a single switch/case.
 13.1028 +	 */
 13.1029 +	DPRINT("st%d [%lx]=%lx\n", len, ifa, r2);
 13.1030 +
 13.1031 +	if (len != 2 && len != 4 && len != 8) {
 13.1032 +		DPRINT("unknown size: x6=%d\n", ld.x6_sz);
 13.1033 +		return -1;
 13.1034 +	}
 13.1035 +
 13.1036 +	/* this assumes little-endian byte-order: */
 13.1037 +	if (copy_to_user((void __user *) ifa, &r2, len))
 13.1038 +		return -1;
 13.1039 +
 13.1040 +	/*
 13.1041 +	 * stX [r3]=r2,imm(9)
 13.1042 +	 *
 13.1043 +	 * NOTE:
 13.1044 +	 * ld.r3 can never be r0, because r0 would not generate an
 13.1045 +	 * unaligned access.
 13.1046 +	 */
 13.1047 +	if (ld.op == 0x5) {
 13.1048 +		unsigned long imm;
 13.1049 +
 13.1050 +		/*
 13.1051 +		 * form imm9: [12:6] contain first 7bits
 13.1052 +		 */
 13.1053 +		imm = ld.x << 7 | ld.r1;
 13.1054 +		/*
 13.1055 +		 * sign extend (8bits) if m set
 13.1056 +		 */
 13.1057 +		if (ld.m) imm |= SIGN_EXT9;
 13.1058 +		/*
 13.1059 +		 * ifa == r3 (NaT is necessarily cleared)
 13.1060 +		 */
 13.1061 +		ifa += imm;
 13.1062 +
 13.1063 +		DPRINT("imm=%lx r3=%lx\n", imm, ifa);
 13.1064 +
 13.1065 +		setreg(ld.r3, ifa, 0, regs);
 13.1066 +	}
 13.1067 +	/*
 13.1068 +	 * we don't have alat_invalidate_multiple() so we need
 13.1069 +	 * to do the complete flush :-<<
 13.1070 +	 */
 13.1071 +	ia64_invala();
 13.1072 +
 13.1073 +	/*
 13.1074 +	 * stX.rel: use fence instead of release
 13.1075 +	 */
 13.1076 +	if (ld.x6_op == 0xd)
 13.1077 +		mb();
 13.1078 +
 13.1079 +	return 0;
 13.1080 +}
 13.1081 +
 13.1082 +/*
 13.1083 + * floating point operations sizes in bytes
 13.1084 + */
 13.1085 +static const unsigned char float_fsz[4]={
 13.1086 +	10, /* extended precision (e) */
 13.1087 +	8,  /* integer (8)            */
 13.1088 +	4,  /* single precision (s)   */
 13.1089 +	8   /* double precision (d)   */
 13.1090 +};
 13.1091 +
 13.1092 +static inline void
 13.1093 +mem2float_extended (struct ia64_fpreg *init, struct ia64_fpreg *final)
 13.1094 +{
 13.1095 +	ia64_ldfe(6, init);
 13.1096 +	ia64_stop();
 13.1097 +	ia64_stf_spill(final, 6);
 13.1098 +}
 13.1099 +
 13.1100 +static inline void
 13.1101 +mem2float_integer (struct ia64_fpreg *init, struct ia64_fpreg *final)
 13.1102 +{
 13.1103 +	ia64_ldf8(6, init);
 13.1104 +	ia64_stop();
 13.1105 +	ia64_stf_spill(final, 6);
 13.1106 +}
 13.1107 +
 13.1108 +static inline void
 13.1109 +mem2float_single (struct ia64_fpreg *init, struct ia64_fpreg *final)
 13.1110 +{
 13.1111 +	ia64_ldfs(6, init);
 13.1112 +	ia64_stop();
 13.1113 +	ia64_stf_spill(final, 6);
 13.1114 +}
 13.1115 +
 13.1116 +static inline void
 13.1117 +mem2float_double (struct ia64_fpreg *init, struct ia64_fpreg *final)
 13.1118 +{
 13.1119 +	ia64_ldfd(6, init);
 13.1120 +	ia64_stop();
 13.1121 +	ia64_stf_spill(final, 6);
 13.1122 +}
 13.1123 +
 13.1124 +static inline void
 13.1125 +float2mem_extended (struct ia64_fpreg *init, struct ia64_fpreg *final)
 13.1126 +{
 13.1127 +	ia64_ldf_fill(6, init);
 13.1128 +	ia64_stop();
 13.1129 +	ia64_stfe(final, 6);
 13.1130 +}
 13.1131 +
 13.1132 +static inline void
 13.1133 +float2mem_integer (struct ia64_fpreg *init, struct ia64_fpreg *final)
 13.1134 +{
 13.1135 +	ia64_ldf_fill(6, init);
 13.1136 +	ia64_stop();
 13.1137 +	ia64_stf8(final, 6);
 13.1138 +}
 13.1139 +
 13.1140 +static inline void
 13.1141 +float2mem_single (struct ia64_fpreg *init, struct ia64_fpreg *final)
 13.1142 +{
 13.1143 +	ia64_ldf_fill(6, init);
 13.1144 +	ia64_stop();
 13.1145 +	ia64_stfs(final, 6);
 13.1146 +}
 13.1147 +
 13.1148 +static inline void
 13.1149 +float2mem_double (struct ia64_fpreg *init, struct ia64_fpreg *final)
 13.1150 +{
 13.1151 +	ia64_ldf_fill(6, init);
 13.1152 +	ia64_stop();
 13.1153 +	ia64_stfd(final, 6);
 13.1154 +}
 13.1155 +
 13.1156 +static int
 13.1157 +emulate_load_floatpair (unsigned long ifa, load_store_t ld, struct pt_regs *regs)
 13.1158 +{
 13.1159 +	struct ia64_fpreg fpr_init[2];
 13.1160 +	struct ia64_fpreg fpr_final[2];
 13.1161 +	unsigned long len = float_fsz[ld.x6_sz];
 13.1162 +
 13.1163 +	/*
 13.1164 +	 * fr0 & fr1 don't need to be checked because Illegal Instruction faults have
 13.1165 +	 * higher priority than unaligned faults.
 13.1166 +	 *
 13.1167 +	 * r0 cannot be found as the base as it would never generate an unaligned
 13.1168 +	 * reference.
 13.1169 +	 */
 13.1170 +
 13.1171 +	/*
 13.1172 +	 * make sure we get clean buffers
 13.1173 +	 */
 13.1174 +	memset(&fpr_init, 0, sizeof(fpr_init));
 13.1175 +	memset(&fpr_final, 0, sizeof(fpr_final));
 13.1176 +
 13.1177 +	/*
 13.1178 +	 * ldfpX.a: we don't try to emulate anything but we must
 13.1179 +	 * invalidate the ALAT entry and execute updates, if any.
 13.1180 +	 */
 13.1181 +	if (ld.x6_op != 0x2) {
 13.1182 +		/*
 13.1183 +		 * This assumes little-endian byte-order.  Note that there is no "ldfpe"
 13.1184 +		 * instruction:
 13.1185 +		 */
 13.1186 +		if (copy_from_user(&fpr_init[0], (void __user *) ifa, len)
 13.1187 +		    || copy_from_user(&fpr_init[1], (void __user *) (ifa + len), len))
 13.1188 +			return -1;
 13.1189 +
 13.1190 +		DPRINT("ld.r1=%d ld.imm=%d x6_sz=%d\n", ld.r1, ld.imm, ld.x6_sz);
 13.1191 +		DDUMP("frp_init =", &fpr_init, 2*len);
 13.1192 +		/*
 13.1193 +		 * XXX fixme
 13.1194 +		 * Could optimize inlines by using ldfpX & 2 spills
 13.1195 +		 */
 13.1196 +		switch( ld.x6_sz ) {
 13.1197 +			case 0:
 13.1198 +				mem2float_extended(&fpr_init[0], &fpr_final[0]);
 13.1199 +				mem2float_extended(&fpr_init[1], &fpr_final[1]);
 13.1200 +				break;
 13.1201 +			case 1:
 13.1202 +				mem2float_integer(&fpr_init[0], &fpr_final[0]);
 13.1203 +				mem2float_integer(&fpr_init[1], &fpr_final[1]);
 13.1204 +				break;
 13.1205 +			case 2:
 13.1206 +				mem2float_single(&fpr_init[0], &fpr_final[0]);
 13.1207 +				mem2float_single(&fpr_init[1], &fpr_final[1]);
 13.1208 +				break;
 13.1209 +			case 3:
 13.1210 +				mem2float_double(&fpr_init[0], &fpr_final[0]);
 13.1211 +				mem2float_double(&fpr_init[1], &fpr_final[1]);
 13.1212 +				break;
 13.1213 +		}
 13.1214 +		DDUMP("fpr_final =", &fpr_final, 2*len);
 13.1215 +		/*
 13.1216 +		 * XXX fixme
 13.1217 +		 *
 13.1218 +		 * A possible optimization would be to drop fpr_final and directly
 13.1219 +		 * use the storage from the saved context i.e., the actual final
 13.1220 +		 * destination (pt_regs, switch_stack or thread structure).
 13.1221 +		 */
 13.1222 +		setfpreg(ld.r1, &fpr_final[0], regs);
 13.1223 +		setfpreg(ld.imm, &fpr_final[1], regs);
 13.1224 +	}
 13.1225 +
 13.1226 +	/*
 13.1227 +	 * Check for updates: only immediate updates are available for this
 13.1228 +	 * instruction.
 13.1229 +	 */
 13.1230 +	if (ld.m) {
 13.1231 +		/*
 13.1232 +		 * the immediate is implicit given the ldsz of the operation:
 13.1233 +		 * single: 8 (2x4) and for  all others it's 16 (2x8)
 13.1234 +		 */
 13.1235 +		ifa += len<<1;
 13.1236 +
 13.1237 +		/*
 13.1238 +		 * IMPORTANT:
 13.1239 +		 * the fact that we force the NaT of r3 to zero is ONLY valid
 13.1240 +		 * as long as we don't come here with a ldfpX.s.
 13.1241 +		 * For this reason we keep this sanity check
 13.1242 +		 */
 13.1243 +		if (ld.x6_op == 1 || ld.x6_op == 3)
 13.1244 +			printk(KERN_ERR "%s: register update on speculative load pair, error\n",
 13.1245 +			       __FUNCTION__);
 13.1246 +
 13.1247 +		setreg(ld.r3, ifa, 0, regs);
 13.1248 +	}
 13.1249 +
 13.1250 +	/*
 13.1251 +	 * Invalidate ALAT entries, if any, for both registers.
 13.1252 +	 */
 13.1253 +	if (ld.x6_op == 0x2) {
 13.1254 +		invala_fr(ld.r1);
 13.1255 +		invala_fr(ld.imm);
 13.1256 +	}
 13.1257 +	return 0;
 13.1258 +}
 13.1259 +
 13.1260 +
 13.1261 +static int
 13.1262 +emulate_load_float (unsigned long ifa, load_store_t ld, struct pt_regs *regs)
 13.1263 +{
 13.1264 +	struct ia64_fpreg fpr_init;
 13.1265 +	struct ia64_fpreg fpr_final;
 13.1266 +	unsigned long len = float_fsz[ld.x6_sz];
 13.1267 +
 13.1268 +	/*
 13.1269 +	 * fr0 & fr1 don't need to be checked because Illegal Instruction
 13.1270 +	 * faults have higher priority than unaligned faults.
 13.1271 +	 *
 13.1272 +	 * r0 cannot be found as the base as it would never generate an
 13.1273 +	 * unaligned reference.
 13.1274 +	 */
 13.1275 +
 13.1276 +	/*
 13.1277 +	 * make sure we get clean buffers
 13.1278 +	 */
 13.1279 +	memset(&fpr_init,0, sizeof(fpr_init));
 13.1280 +	memset(&fpr_final,0, sizeof(fpr_final));
 13.1281 +
 13.1282 +	/*
 13.1283 +	 * ldfX.a we don't try to emulate anything but we must
 13.1284 +	 * invalidate the ALAT entry.
 13.1285 +	 * See comments in ldX for descriptions on how the various loads are handled.
 13.1286 +	 */
 13.1287 +	if (ld.x6_op != 0x2) {
 13.1288 +		if (copy_from_user(&fpr_init, (void __user *) ifa, len))
 13.1289 +			return -1;
 13.1290 +
 13.1291 +		DPRINT("ld.r1=%d x6_sz=%d\n", ld.r1, ld.x6_sz);
 13.1292 +		DDUMP("fpr_init =", &fpr_init, len);
 13.1293 +		/*
 13.1294 +		 * we only do something for x6_op={0,8,9}
 13.1295 +		 */
 13.1296 +		switch( ld.x6_sz ) {
 13.1297 +			case 0:
 13.1298 +				mem2float_extended(&fpr_init, &fpr_final);
 13.1299 +				break;
 13.1300 +			case 1:
 13.1301 +				mem2float_integer(&fpr_init, &fpr_final);
 13.1302 +				break;
 13.1303 +			case 2:
 13.1304 +				mem2float_single(&fpr_init, &fpr_final);
 13.1305 +				break;
 13.1306 +			case 3:
 13.1307 +				mem2float_double(&fpr_init, &fpr_final);
 13.1308 +				break;
 13.1309 +		}
 13.1310 +		DDUMP("fpr_final =", &fpr_final, len);
 13.1311 +		/*
 13.1312 +		 * XXX fixme
 13.1313 +		 *
 13.1314 +		 * A possible optimization would be to drop fpr_final and directly
 13.1315 +		 * use the storage from the saved context i.e., the actual final
 13.1316 +		 * destination (pt_regs, switch_stack or thread structure).
 13.1317 +		 */
 13.1318 +		setfpreg(ld.r1, &fpr_final, regs);
 13.1319 +	}
 13.1320 +
 13.1321 +	/*
 13.1322 +	 * check for updates on any loads
 13.1323 +	 */
 13.1324 +	if (ld.op == 0x7 || ld.m)
 13.1325 +		emulate_load_updates(ld.op == 0x7 ? UPD_IMMEDIATE: UPD_REG, ld, regs, ifa);
 13.1326 +
 13.1327 +	/*
 13.1328 +	 * invalidate ALAT entry in case of advanced floating point loads
 13.1329 +	 */
 13.1330 +	if (ld.x6_op == 0x2)
 13.1331 +		invala_fr(ld.r1);
 13.1332 +
 13.1333 +	return 0;
 13.1334 +}
 13.1335 +
 13.1336 +
 13.1337 +static int
 13.1338 +emulate_store_float (unsigned long ifa, load_store_t ld, struct pt_regs *regs)
 13.1339 +{
 13.1340 +	struct ia64_fpreg fpr_init;
 13.1341 +	struct ia64_fpreg fpr_final;
 13.1342 +	unsigned long len = float_fsz[ld.x6_sz];
 13.1343 +
 13.1344 +	/*
 13.1345 +	 * make sure we get clean buffers
 13.1346 +	 */
 13.1347 +	memset(&fpr_init,0, sizeof(fpr_init));
 13.1348 +	memset(&fpr_final,0, sizeof(fpr_final));
 13.1349 +
 13.1350 +	/*
 13.1351 +	 * if we get to this handler, Nat bits on both r3 and r2 have already
 13.1352 +	 * been checked. so we don't need to do it
 13.1353 +	 *
 13.1354 +	 * extract the value to be stored
 13.1355 +	 */
 13.1356 +	getfpreg(ld.imm, &fpr_init, regs);
 13.1357 +	/*
 13.1358 +	 * during this step, we extract the spilled registers from the saved
 13.1359 +	 * context i.e., we refill. Then we store (no spill) to temporary
 13.1360 +	 * aligned location
 13.1361 +	 */
 13.1362 +	switch( ld.x6_sz ) {
 13.1363 +		case 0:
 13.1364 +			float2mem_extended(&fpr_init, &fpr_final);
 13.1365 +			break;
 13.1366 +		case 1:
 13.1367 +			float2mem_integer(&fpr_init, &fpr_final);
 13.1368 +			break;
 13.1369 +		case 2:
 13.1370 +			float2mem_single(&fpr_init, &fpr_final);
 13.1371 +			break;
 13.1372 +		case 3:
 13.1373 +			float2mem_double(&fpr_init, &fpr_final);
 13.1374 +			break;
 13.1375 +	}
 13.1376 +	DPRINT("ld.r1=%d x6_sz=%d\n", ld.r1, ld.x6_sz);
 13.1377 +	DDUMP("fpr_init =", &fpr_init, len);
 13.1378 +	DDUMP("fpr_final =", &fpr_final, len);
 13.1379 +
 13.1380 +	if (copy_to_user((void __user *) ifa, &fpr_final, len))
 13.1381 +		return -1;
 13.1382 +
 13.1383 +	/*
 13.1384 +	 * stfX [r3]=r2,imm(9)
 13.1385 +	 *
 13.1386 +	 * NOTE:
 13.1387 +	 * ld.r3 can never be r0, because r0 would not generate an
 13.1388 +	 * unaligned access.
 13.1389 +	 */
 13.1390 +	if (ld.op == 0x7) {
 13.1391 +		unsigned long imm;
 13.1392 +
 13.1393 +		/*
 13.1394 +		 * form imm9: [12:6] contain first 7bits
 13.1395 +		 */
 13.1396 +		imm = ld.x << 7 | ld.r1;
 13.1397 +		/*
 13.1398 +		 * sign extend (8bits) if m set
 13.1399 +		 */
 13.1400 +		if (ld.m)
 13.1401 +			imm |= SIGN_EXT9;
 13.1402 +		/*
 13.1403 +		 * ifa == r3 (NaT is necessarily cleared)
 13.1404 +		 */
 13.1405 +		ifa += imm;
 13.1406 +
 13.1407 +		DPRINT("imm=%lx r3=%lx\n", imm, ifa);
 13.1408 +
 13.1409 +		setreg(ld.r3, ifa, 0, regs);
 13.1410 +	}
 13.1411 +	/*
 13.1412 +	 * we don't have alat_invalidate_multiple() so we need
 13.1413 +	 * to do the complete flush :-<<
 13.1414 +	 */
 13.1415 +	ia64_invala();
 13.1416 +
 13.1417 +	return 0;
 13.1418 +}
 13.1419 +
 13.1420 +/*
 13.1421 + * Make sure we log the unaligned access, so that user/sysadmin can notice it and
 13.1422 + * eventually fix the program.  However, we don't want to do that for every access so we
 13.1423 + * pace it with jiffies.  This isn't really MP-safe, but it doesn't really have to be
 13.1424 + * either...
 13.1425 + */
 13.1426 +static int
 13.1427 +within_logging_rate_limit (void)
 13.1428 +{
 13.1429 +	static unsigned long count, last_time;
 13.1430 +
 13.1431 +	if (jiffies - last_time > 5*HZ)
 13.1432 +		count = 0;
 13.1433 +	if (++count < 5) {
 13.1434 +		last_time = jiffies;
 13.1435 +		return 1;
 13.1436 +	}
 13.1437 +	return 0;
 13.1438 +
 13.1439 +}
 13.1440 +
 13.1441 +void
 13.1442 +ia64_handle_unaligned (unsigned long ifa, struct pt_regs *regs)
 13.1443 +{
 13.1444 +#ifdef XEN
 13.1445 +printk("ia64_handle_unaligned: called, not working yet\n");
 13.1446 +#else
 13.1447 +	struct ia64_psr *ipsr = ia64_psr(regs);
 13.1448 +	mm_segment_t old_fs = get_fs();
 13.1449 +	unsigned long bundle[2];
 13.1450 +	unsigned long opcode;
 13.1451 +	struct siginfo si;
 13.1452 +	const struct exception_table_entry *eh = NULL;
 13.1453 +	union {
 13.1454 +		unsigned long l;
 13.1455 +		load_store_t insn;
 13.1456 +	} u;
 13.1457 +	int ret = -1;
 13.1458 +
 13.1459 +	if (ia64_psr(regs)->be) {
 13.1460 +		/* we don't support big-endian accesses */
 13.1461 +		die_if_kernel("big-endian unaligned accesses are not supported", regs, 0);
 13.1462 +		goto force_sigbus;
 13.1463 +	}
 13.1464 +
 13.1465 +	/*
 13.1466 +	 * Treat kernel accesses for which there is an exception handler entry the same as
 13.1467 +	 * user-level unaligned accesses.  Otherwise, a clever program could trick this
 13.1468 +	 * handler into reading an arbitrary kernel addresses...
 13.1469 +	 */
 13.1470 +	if (!user_mode(regs))
 13.1471 +		eh = search_exception_tables(regs->cr_iip + ia64_psr(regs)->ri);
 13.1472 +	if (user_mode(regs) || eh) {
 13.1473 +		if ((current->thread.flags & IA64_THREAD_UAC_SIGBUS) != 0)
 13.1474 +			goto force_sigbus;
 13.1475 +
 13.1476 +		if (!(current->thread.flags & IA64_THREAD_UAC_NOPRINT)
 13.1477 +		    && within_logging_rate_limit())
 13.1478 +		{
 13.1479 +			char buf[200];	/* comm[] is at most 16 bytes... */
 13.1480 +			size_t len;
 13.1481 +
 13.1482 +			len = sprintf(buf, "%s(%d): unaligned access to 0x%016lx, "
 13.1483 +				      "ip=0x%016lx\n\r", current->comm, current->pid,
 13.1484 +				      ifa, regs->cr_iip + ipsr->ri);
 13.1485 +			/*
 13.1486 +			 * Don't call tty_write_message() if we're in the kernel; we might
 13.1487 +			 * be holding locks...
 13.1488 +			 */
 13.1489 +			if (user_mode(regs))
 13.1490 +				tty_write_message(current->signal->tty, buf);
 13.1491 +			buf[len-1] = '\0';	/* drop '\r' */
 13.1492 +			printk(KERN_WARNING "%s", buf);	/* watch for command names containing %s */
 13.1493 +		}
 13.1494 +	} else {
 13.1495 +		if (within_logging_rate_limit())
 13.1496 +			printk(KERN_WARNING "kernel unaligned access to 0x%016lx, ip=0x%016lx\n",
 13.1497 +			       ifa, regs->cr_iip + ipsr->ri);
 13.1498 +		set_fs(KERNEL_DS);
 13.1499 +	}
 13.1500 +
 13.1501 +	DPRINT("iip=%lx ifa=%lx isr=%lx (ei=%d, sp=%d)\n",
 13.1502 +	       regs->cr_iip, ifa, regs->cr_ipsr, ipsr->ri, ipsr->it);
 13.1503 +
 13.1504 +	if (__copy_from_user(bundle, (void __user *) regs->cr_iip, 16))
 13.1505 +		goto failure;
 13.1506 +
 13.1507 +	/*
 13.1508 +	 * extract the instruction from the bundle given the slot number
 13.1509 +	 */
 13.1510 +	switch (ipsr->ri) {
 13.1511 +	      case 0: u.l = (bundle[0] >>  5); break;
 13.1512 +	      case 1: u.l = (bundle[0] >> 46) | (bundle[1] << 18); break;
 13.1513 +	      case 2: u.l = (bundle[1] >> 23); break;
 13.1514 +	}
 13.1515 +	opcode = (u.l >> IA64_OPCODE_SHIFT) & IA64_OPCODE_MASK;
 13.1516 +
 13.1517 +	DPRINT("opcode=%lx ld.qp=%d ld.r1=%d ld.imm=%d ld.r3=%d ld.x=%d ld.hint=%d "
 13.1518 +	       "ld.x6=0x%x ld.m=%d ld.op=%d\n", opcode, u.insn.qp, u.insn.r1, u.insn.imm,
 13.1519 +	       u.insn.r3, u.insn.x, u.insn.hint, u.insn.x6_sz, u.insn.m, u.insn.op);
 13.1520 +
 13.1521 +	/*
 13.1522 +	 * IMPORTANT:
 13.1523 +	 * Notice that the switch statement DOES not cover all possible instructions
 13.1524 +	 * that DO generate unaligned references. This is made on purpose because for some
 13.1525 +	 * instructions it DOES NOT make sense to try and emulate the access. Sometimes it
 13.1526 +	 * is WRONG to try and emulate. Here is a list of instruction we don't emulate i.e.,
 13.1527 +	 * the program will get a signal and die:
 13.1528 +	 *
 13.1529 +	 *	load/store:
 13.1530 +	 *		- ldX.spill
 13.1531 +	 *		- stX.spill
 13.1532 +	 *	Reason: RNATs are based on addresses
 13.1533 +	 *
 13.1534 +	 *	synchronization:
 13.1535 +	 *		- cmpxchg
 13.1536 +	 *		- fetchadd
 13.1537 +	 *		- xchg
 13.1538 +	 *	Reason: ATOMIC operations cannot be emulated properly using multiple
 13.1539 +	 *	        instructions.
 13.1540 +	 *
 13.1541 +	 *	speculative loads:
 13.1542 +	 *		- ldX.sZ
 13.1543 +	 *	Reason: side effects, code must be ready to deal with failure so simpler
 13.1544 +	 *		to let the load fail.
 13.1545 +	 * ---------------------------------------------------------------------------------
 13.1546 +	 * XXX fixme
 13.1547 +	 *
 13.1548 +	 * I would like to get rid of this switch case and do something
 13.1549 +	 * more elegant.
 13.1550 +	 */
 13.1551 +	switch (opcode) {
 13.1552 +	      case LDS_OP:
 13.1553 +	      case LDSA_OP:
 13.1554 +	      case LDS_IMM_OP:
 13.1555 +	      case LDSA_IMM_OP:
 13.1556 +	      case LDFS_OP:
 13.1557 +	      case LDFSA_OP:
 13.1558 +	      case LDFS_IMM_OP:
 13.1559 +		/*
 13.1560 +		 * The instruction will be retried with deferred exceptions turned on, and
 13.1561 +		 * we should get Nat bit installed
 13.1562 +		 *
 13.1563 +		 * IMPORTANT: When PSR_ED is set, the register & immediate update forms
 13.1564 +		 * are actually executed even though the operation failed. So we don't
 13.1565 +		 * need to take care of this.
 13.1566 +		 */
 13.1567 +		DPRINT("forcing PSR_ED\n");
 13.1568 +		regs->cr_ipsr |= IA64_PSR_ED;
 13.1569 +		goto done;
 13.1570 +
 13.1571 +	      case LD_OP:
 13.1572 +	      case LDA_OP:
 13.1573 +	      case LDBIAS_OP:
 13.1574 +	      case LDACQ_OP:
 13.1575 +	      case LDCCLR_OP:
 13.1576 +	      case LDCNC_OP:
 13.1577 +	      case LDCCLRACQ_OP:
 13.1578 +	      case LD_IMM_OP:
 13.1579 +	      case LDA_IMM_OP:
 13.1580 +	      case LDBIAS_IMM_OP:
 13.1581 +	      case LDACQ_IMM_OP:
 13.1582 +	      case LDCCLR_IMM_OP:
 13.1583 +	      case LDCNC_IMM_OP:
 13.1584 +	      case LDCCLRACQ_IMM_OP:
 13.1585 +		ret = emulate_load_int(ifa, u.insn, regs);
 13.1586 +		break;
 13.1587 +
 13.1588 +	      case ST_OP:
 13.1589 +	      case STREL_OP:
 13.1590 +	      case ST_IMM_OP:
 13.1591 +	      case STREL_IMM_OP:
 13.1592 +		ret = emulate_store_int(ifa, u.insn, regs);
 13.1593 +		break;
 13.1594 +
 13.1595 +	      case LDF_OP:
 13.1596 +	      case LDFA_OP:
 13.1597 +	      case LDFCCLR_OP:
 13.1598 +	      case LDFCNC_OP:
 13.1599 +	      case LDF_IMM_OP:
 13.1600 +	      case LDFA_IMM_OP:
 13.1601 +	      case LDFCCLR_IMM_OP:
 13.1602 +	      case LDFCNC_IMM_OP:
 13.1603 +		if (u.insn.x)
 13.1604 +			ret = emulate_load_floatpair(ifa, u.insn, regs);
 13.1605 +		else
 13.1606 +			ret = emulate_load_float(ifa, u.insn, regs);
 13.1607 +		break;
 13.1608 +
 13.1609 +	      case STF_OP:
 13.1610 +	      case STF_IMM_OP:
 13.1611 +		ret = emulate_store_float(ifa, u.insn, regs);
 13.1612 +		break;
 13.1613 +
 13.1614 +	      default:
 13.1615 +		goto failure;
 13.1616 +	}
 13.1617 +	DPRINT("ret=%d\n", ret);
 13.1618 +	if (ret)
 13.1619 +		goto failure;
 13.1620 +
 13.1621 +	if (ipsr->ri == 2)
 13.1622 +		/*
 13.1623 +		 * given today's architecture this case is not likely to happen because a
 13.1624 +		 * memory access instruction (M) can never be in the last slot of a
 13.1625 +		 * bundle. But let's keep it for now.
 13.1626 +		 */
 13.1627 +		regs->cr_iip += 16;
 13.1628 +	ipsr->ri = (ipsr->ri + 1) & 0x3;
 13.1629 +
 13.1630 +	DPRINT("ipsr->ri=%d iip=%lx\n", ipsr->ri, regs->cr_iip);
 13.1631 +  done:
 13.1632 +	set_fs(old_fs);		/* restore original address limit */
 13.1633 +	return;
 13.1634 +
 13.1635 +  failure:
 13.1636 +	/* something went wrong... */
 13.1637 +	if (!user_mode(regs)) {
 13.1638 +		if (eh) {
 13.1639 +			ia64_handle_exception(regs, eh);
 13.1640 +			goto done;
 13.1641 +		}
 13.1642 +		die_if_kernel("error during unaligned kernel access\n", regs, ret);
 13.1643 +		/* NOT_REACHED */
 13.1644 +	}
 13.1645 +  force_sigbus:
 13.1646 +	si.si_signo = SIGBUS;
 13.1647 +	si.si_errno = 0;
 13.1648 +	si.si_code = BUS_ADRALN;
 13.1649 +	si.si_addr = (void __user *) ifa;
 13.1650 +	si.si_flags = 0;
 13.1651 +	si.si_isr = 0;
 13.1652 +	si.si_imm = 0;
 13.1653 +	force_sig_info(SIGBUS, &si, current);
 13.1654 +	goto done;
 13.1655 +#endif
 13.1656 +}
    14.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    14.2 +++ b/xen/arch/ia64/linux/cmdline.c	Mon Aug 08 12:21:23 2005 -0700
    14.3 @@ -0,0 +1,120 @@
    14.4 +/*
    14.5 + * linux/lib/cmdline.c
    14.6 + * Helper functions generally used for parsing kernel command line
    14.7 + * and module options.
    14.8 + *
    14.9 + * Code and copyrights come from init/main.c and arch/i386/kernel/setup.c.
   14.10 + *
   14.11 + * This source code is licensed under the GNU General Public License,
   14.12 + * Version 2.  See the file COPYING for more details.
   14.13 + *
   14.14 + * GNU Indent formatting options for this file: -kr -i8 -npsl -pcs
   14.15 + *
   14.16 + */
   14.17 +
   14.18 +#include <linux/module.h>
   14.19 +#include <linux/kernel.h>
   14.20 +#include <linux/string.h>
   14.21 +
   14.22 +
   14.23 +/**
   14.24 + *	get_option - Parse integer from an option string
   14.25 + *	@str: option string
   14.26 + *	@pint: (output) integer value parsed from @str
   14.27 + *
   14.28 + *	Read an int from an option string; if available accept a subsequent
   14.29 + *	comma as well.
   14.30 + *
   14.31 + *	Return values:
   14.32 + *	0 : no int in string
   14.33 + *	1 : int found, no subsequent comma
   14.34 + *	2 : int found including a subsequent comma
   14.35 + */
   14.36 +
   14.37 +int get_option (char **str, int *pint)
   14.38 +{
   14.39 +	char *cur = *str;
   14.40 +
   14.41 +	if (!cur || !(*cur))
   14.42 +		return 0;
   14.43 +	*pint = simple_strtol (cur, str, 0);
   14.44 +	if (cur == *str)
   14.45 +		return 0;
   14.46 +	if (**str == ',') {
   14.47 +		(*str)++;
   14.48 +		return 2;
   14.49 +	}
   14.50 +
   14.51 +	return 1;
   14.52 +}
   14.53 +
   14.54 +/**
   14.55 + *	get_options - Parse a string into a list of integers
   14.56 + *	@str: String to be parsed
   14.57 + *	@nints: size of integer array
   14.58 + *	@ints: integer array
   14.59 + *
   14.60 + *	This function parses a string containing a comma-separated
   14.61 + *	list of integers.  The parse halts when the array is
   14.62 + *	full, or when no more numbers can be retrieved from the
   14.63 + *	string.
   14.64 + *
   14.65 + *	Return value is the character in the string which caused
   14.66 + *	the parse to end (typically a null terminator, if @str is
   14.67 + *	completely parseable).
   14.68 + */
   14.69 + 
   14.70 +char *get_options(const char *str, int nints, int *ints)
   14.71 +{
   14.72 +	int res, i = 1;
   14.73 +
   14.74 +	while (i < nints) {
   14.75 +		res = get_option ((char **)&str, ints + i);
   14.76 +		if (res == 0)
   14.77 +			break;
   14.78 +		i++;
   14.79 +		if (res == 1)
   14.80 +			break;
   14.81 +	}
   14.82 +	ints[0] = i - 1;
   14.83 +	return (char *)str;
   14.84 +}
   14.85 +
   14.86 +/**
   14.87 + *	memparse - parse a string with mem suffixes into a number
   14.88 + *	@ptr: Where parse begins
   14.89 + *	@retptr: (output) Pointer to next char after parse completes
   14.90 + *
   14.91 + *	Parses a string into a number.  The number stored at @ptr is
   14.92 + *	potentially suffixed with %K (for kilobytes, or 1024 bytes),
   14.93 + *	%M (for megabytes, or 1048576 bytes), or %G (for gigabytes, or
   14.94 + *	1073741824).  If the number is suffixed with K, M, or G, then
   14.95 + *	the return value is the number multiplied by one kilobyte, one
   14.96 + *	megabyte, or one gigabyte, respectively.
   14.97 + */
   14.98 +
   14.99 +unsigned long long memparse (char *ptr, char **retptr)
  14.100 +{
  14.101 +	unsigned long long ret = simple_strtoull (ptr, retptr, 0);
  14.102 +
  14.103 +	switch (**retptr) {
  14.104 +	case 'G':
  14.105 +	case 'g':
  14.106 +		ret <<= 10;
  14.107 +	case 'M':
  14.108 +	case 'm':
  14.109 +		ret <<= 10;
  14.110 +	case 'K':
  14.111 +	case 'k':
  14.112 +		ret <<= 10;
  14.113 +		(*retptr)++;
  14.114 +	default:
  14.115 +		break;
  14.116 +	}
  14.117 +	return ret;
  14.118 +}
  14.119 +
  14.120 +
  14.121 +EXPORT_SYMBOL(memparse);
  14.122 +EXPORT_SYMBOL(get_option);
  14.123 +EXPORT_SYMBOL(get_options);
    15.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    15.2 +++ b/xen/arch/ia64/linux/efi_stub.S	Mon Aug 08 12:21:23 2005 -0700
    15.3 @@ -0,0 +1,86 @@
    15.4 +/*
    15.5 + * EFI call stub.
    15.6 + *
    15.7 + * Copyright (C) 1999-2001 Hewlett-Packard Co
    15.8 + *	David Mosberger <davidm@hpl.hp.com>
    15.9 + *
   15.10 + * This stub allows us to make EFI calls in physical mode with interrupts
   15.11 + * turned off.  We need this because we can't call SetVirtualMap() until
   15.12 + * the kernel has booted far enough to allow allocation of struct vma_struct
   15.13 + * entries (which we would need to map stuff with memory attributes other
   15.14 + * than uncached or writeback...).  Since the GetTime() service gets called
   15.15 + * earlier than that, we need to be able to make physical mode EFI calls from
   15.16 + * the kernel.
   15.17 + */
   15.18 +
   15.19 +/*
   15.20 + * PSR settings as per SAL spec (Chapter 8 in the "IA-64 System
   15.21 + * Abstraction Layer Specification", revision 2.6e).  Note that
   15.22 + * psr.dfl and psr.dfh MUST be cleared, despite what this manual says.
   15.23 + * Otherwise, SAL dies whenever it's trying to do an IA-32 BIOS call
   15.24 + * (the br.ia instruction fails unless psr.dfl and psr.dfh are
   15.25 + * cleared).  Fortunately, SAL promises not to touch the floating
   15.26 + * point regs, so at least we don't have to save f2-f127.
   15.27 + */
   15.28 +#define PSR_BITS_TO_CLEAR						\
   15.29 +	(IA64_PSR_I | IA64_PSR_IT | IA64_PSR_DT | IA64_PSR_RT |		\
   15.30 +	 IA64_PSR_DD | IA64_PSR_SS | IA64_PSR_RI | IA64_PSR_ED |	\
   15.31 +	 IA64_PSR_DFL | IA64_PSR_DFH)
   15.32 +
   15.33 +#define PSR_BITS_TO_SET							\
   15.34 +	(IA64_PSR_BN)
   15.35 +
   15.36 +#include <asm/processor.h>
   15.37 +#include <asm/asmmacro.h>
   15.38 +
   15.39 +/*
   15.40 + * Inputs:
   15.41 + *	in0 = address of function descriptor of EFI routine to call
   15.42 + *	in1..in7 = arguments to routine
   15.43 + *
   15.44 + * Outputs:
   15.45 + *	r8 = EFI_STATUS returned by called function
   15.46 + */
   15.47 +
   15.48 +GLOBAL_ENTRY(efi_call_phys)
   15.49 +	.prologue ASM_UNW_PRLG_RP|ASM_UNW_PRLG_PFS, ASM_UNW_PRLG_GRSAVE(8)
   15.50 +	alloc loc1=ar.pfs,8,7,7,0
   15.51 +	ld8 r2=[in0],8			// load EFI function's entry point
   15.52 +	mov loc0=rp
   15.53 +	.body
   15.54 +	;;
   15.55 +	mov loc2=gp			// save global pointer
   15.56 +	mov loc4=ar.rsc			// save RSE configuration
   15.57 +	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
   15.58 +	;;
   15.59 +	ld8 gp=[in0]			// load EFI function's global pointer
   15.60 +	movl r16=PSR_BITS_TO_CLEAR
   15.61 +	mov loc3=psr			// save processor status word
   15.62 +	movl r17=PSR_BITS_TO_SET
   15.63 +	;;
   15.64 +	or loc3=loc3,r17
   15.65 +	mov b6=r2
   15.66 +	;;
   15.67 +	andcm r16=loc3,r16		// get psr with IT, DT, and RT bits cleared
   15.68 +	br.call.sptk.many rp=ia64_switch_mode_phys
   15.69 +.ret0:	mov out4=in5
   15.70 +	mov out0=in1
   15.71 +	mov out1=in2
   15.72 +	mov out2=in3
   15.73 +	mov out3=in4
   15.74 +	mov out5=in6
   15.75 +	mov out6=in7
   15.76 +	mov loc5=r19
   15.77 +	mov loc6=r20
   15.78 +	br.call.sptk.many rp=b6		// call the EFI function
   15.79 +.ret1:	mov ar.rsc=0			// put RSE in enforced lazy, LE mode
   15.80 +	mov r16=loc3
   15.81 +	mov r19=loc5
   15.82 +	mov r20=loc6
   15.83 +	br.call.sptk.many rp=ia64_switch_mode_virt // return to virtual mode
   15.84 +.ret2:	mov ar.rsc=loc4			// restore RSE configuration
   15.85 +	mov ar.pfs=loc1
   15.86 +	mov rp=loc0
   15.87 +	mov gp=loc2
   15.88 +	br.ret.sptk.many rp
   15.89 +END(efi_call_phys)
    16.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    16.2 +++ b/xen/arch/ia64/linux/extable.c	Mon Aug 08 12:21:23 2005 -0700
    16.3 @@ -0,0 +1,93 @@
    16.4 +/*
    16.5 + * Kernel exception handling table support.  Derived from arch/alpha/mm/extable.c.
    16.6 + *
    16.7 + * Copyright (C) 1998, 1999, 2001-2002, 2004 Hewlett-Packard Co
    16.8 + *	David Mosberger-Tang <davidm@hpl.hp.com>
    16.9 + */
   16.10 +
   16.11 +#include <linux/config.h>
   16.12 +
   16.13 +#include <asm/uaccess.h>
   16.14 +#include <asm/module.h>
   16.15 +
   16.16 +static inline int
   16.17 +compare_entries (struct exception_table_entry *l, struct exception_table_entry *r)
   16.18 +{
   16.19 +	u64 lip = (u64) &l->addr + l->addr;
   16.20 +	u64 rip = (u64) &r->addr + r->addr;
   16.21 +
   16.22 +	if (lip < rip)
   16.23 +		return -1;
   16.24 +	if (lip == rip)
   16.25 +		return 0;
   16.26 +	else
   16.27 +		return 1;
   16.28 +}
   16.29 +
   16.30 +static inline void
   16.31 +swap_entries (struct exception_table_entry *l, struct exception_table_entry *r)
   16.32 +{
   16.33 +	u64 delta = (u64) r - (u64) l;
   16.34 +	struct exception_table_entry tmp;
   16.35 +
   16.36 +	tmp = *l;
   16.37 +	l->addr = r->addr + delta;
   16.38 +	l->cont = r->cont + delta;
   16.39 +	r->addr = tmp.addr - delta;
   16.40 +	r->cont = tmp.cont - delta;
   16.41 +}
   16.42 +
   16.43 +/*
   16.44 + * Sort the exception table.  It's usually already sorted, but there may be unordered
   16.45 + * entries due to multiple text sections (such as the .init text section).  Note that the
   16.46 + * exception-table-entries contain location-relative addresses, which requires a bit of
   16.47 + * care during sorting to avoid overflows in the offset members (e.g., it would not be
   16.48 + * safe to make a temporary copy of an exception-table entry on the stack, because the
   16.49 + * stack may be more than 2GB away from the exception-table).
   16.50 + */
   16.51 +void
   16.52 +sort_extable (struct exception_table_entry *start, struct exception_table_entry *finish)
   16.53 +{
   16.54 +	struct exception_table_entry *p, *q;
   16.55 +
   16.56 + 	/* insertion sort */
   16.57 +	for (p = start + 1; p < finish; ++p)
   16.58 +		/* start .. p-1 is sorted; push p down to it's proper place */
   16.59 +		for (q = p; q > start && compare_entries(&q[0], &q[-1]) < 0; --q)
   16.60 +			swap_entries(&q[0], &q[-1]);
   16.61 +}
   16.62 +
   16.63 +const struct exception_table_entry *
   16.64 +search_extable (const struct exception_table_entry *first,
   16.65 +		const struct exception_table_entry *last,
   16.66 +		unsigned long ip)
   16.67 +{
   16.68 +	const struct exception_table_entry *mid;
   16.69 +	unsigned long mid_ip;
   16.70 +	long diff;
   16.71 +
   16.72 +        while (first <= last) {
   16.73 +		mid = &first[(last - first)/2];
   16.74 +		mid_ip = (u64) &mid->addr + mid->addr;
   16.75 +		diff = mid_ip - ip;
   16.76 +                if (diff == 0)
   16.77 +                        return mid;
   16.78 +                else if (diff < 0)
   16.79 +                        first = mid + 1;
   16.80 +                else
   16.81 +                        last = mid - 1;
   16.82 +        }
   16.83 +        return NULL;
   16.84 +}
   16.85 +
   16.86 +void
   16.87 +ia64_handle_exception (struct pt_regs *regs, const struct exception_table_entry *e)
   16.88 +{
   16.89 +	long fix = (u64) &e->cont + e->cont;
   16.90 +
   16.91 +	regs->r8 = -EFAULT;
   16.92 +	if (fix & 4)
   16.93 +		regs->r9 = 0;
   16.94 +	regs->cr_iip = fix & ~0xf;
   16.95 +	ia64_psr(regs)->ri = fix & 0x3;		/* set continuation slot number */
   16.96 +}
    17.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    17.2 +++ b/xen/arch/ia64/linux/hpsim.S	Mon Aug 08 12:21:23 2005 -0700
    17.3 @@ -0,0 +1,10 @@
    17.4 +#include <asm/asmmacro.h>
    17.5 +
    17.6 +/*
    17.7 + * Simulator system call.
    17.8 + */
    17.9 +GLOBAL_ENTRY(ia64_ssc)
   17.10 +	mov r15=r36
   17.11 +	break 0x80001
   17.12 +	br.ret.sptk.many rp
   17.13 +END(ia64_ssc)
    18.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    18.2 +++ b/xen/arch/ia64/linux/ia64_ksyms.c	Mon Aug 08 12:21:23 2005 -0700
    18.3 @@ -0,0 +1,127 @@
    18.4 +/*
    18.5 + * Architecture-specific kernel symbols
    18.6 + *
    18.7 + * Don't put any exports here unless it's defined in an assembler file.
    18.8 + * All other exports should be put directly after the definition.
    18.9 + */
   18.10 +
   18.11 +#include <linux/config.h>
   18.12 +#include <linux/module.h>
   18.13 +
   18.14 +#include <linux/string.h>
   18.15 +EXPORT_SYMBOL(memset);
   18.16 +EXPORT_SYMBOL(memchr);
   18.17 +EXPORT_SYMBOL(memcmp);
   18.18 +EXPORT_SYMBOL(memcpy);
   18.19 +EXPORT_SYMBOL(memmove);
   18.20 +EXPORT_SYMBOL(memscan);
   18.21 +EXPORT_SYMBOL(strcat);
   18.22 +EXPORT_SYMBOL(strchr);
   18.23 +EXPORT_SYMBOL(strcmp);
   18.24 +EXPORT_SYMBOL(strcpy);
   18.25 +EXPORT_SYMBOL(strlen);
   18.26 +EXPORT_SYMBOL(strncat);
   18.27 +EXPORT_SYMBOL(strncmp);
   18.28 +EXPORT_SYMBOL(strncpy);
   18.29 +EXPORT_SYMBOL(strnlen);
   18.30 +EXPORT_SYMBOL(strrchr);
   18.31 +EXPORT_SYMBOL(strstr);
   18.32 +EXPORT_SYMBOL(strpbrk);
   18.33 +
   18.34 +#include <asm/checksum.h>
   18.35 +EXPORT_SYMBOL(ip_fast_csum);		/* hand-coded assembly */
   18.36 +
   18.37 +#include <asm/semaphore.h>
   18.38 +EXPORT_SYMBOL(__down);
   18.39 +EXPORT_SYMBOL(__down_interruptible);
   18.40 +EXPORT_SYMBOL(__down_trylock);
   18.41 +EXPORT_SYMBOL(__up);
   18.42 +
   18.43 +#include <asm/page.h>
   18.44 +EXPORT_SYMBOL(clear_page);
   18.45 +
   18.46 +#ifdef CONFIG_VIRTUAL_MEM_MAP
   18.47 +#include <linux/bootmem.h>
   18.48 +EXPORT_SYMBOL(max_low_pfn);	/* defined by bootmem.c, but not exported by generic code */
   18.49 +#endif
   18.50 +
   18.51 +#include <asm/processor.h>
   18.52 +EXPORT_SYMBOL(per_cpu__cpu_info);
   18.53 +#ifdef CONFIG_SMP
   18.54 +EXPORT_SYMBOL(per_cpu__local_per_cpu_offset);
   18.55 +#endif
   18.56 +
   18.57 +#include <asm/uaccess.h>
   18.58 +EXPORT_SYMBOL(__copy_user);
   18.59 +EXPORT_SYMBOL(__do_clear_user);
   18.60 +EXPORT_SYMBOL(__strlen_user);
   18.61 +EXPORT_SYMBOL(__strncpy_from_user);
   18.62 +EXPORT_SYMBOL(__strnlen_user);
   18.63 +
   18.64 +#include <asm/unistd.h>
   18.65 +EXPORT_SYMBOL(__ia64_syscall);
   18.66 +
   18.67 +/* from arch/ia64/lib */
   18.68 +extern void __divsi3(void);
   18.69 +extern void __udivsi3(void);
   18.70 +extern void __modsi3(void);
   18.71 +extern void __umodsi3(void);
   18.72 +extern void __divdi3(void);
   18.73 +extern void __udivdi3(void);
   18.74 +extern void __moddi3(void);
   18.75 +extern void __umoddi3(void);
   18.76 +
   18.77 +EXPORT_SYMBOL(__divsi3);
   18.78 +EXPORT_SYMBOL(__udivsi3);
   18.79 +EXPORT_SYMBOL(__modsi3);
   18.80 +EXPORT_SYMBOL(__umodsi3);
   18.81 +EXPORT_SYMBOL(__divdi3);
   18.82 +EXPORT_SYMBOL(__udivdi3);
   18.83 +EXPORT_SYMBOL(__moddi3);
   18.84 +EXPORT_SYMBOL(__umoddi3);
   18.85 +
   18.86 +#if defined(CONFIG_MD_RAID5) || defined(CONFIG_MD_RAID5_MODULE)
   18.87 +extern void xor_ia64_2(void);
   18.88 +extern void xor_ia64_3(void);
   18.89 +extern void xor_ia64_4(void);
   18.90 +extern void xor_ia64_5(void);
   18.91 +
   18.92 +EXPORT_SYMBOL(xor_ia64_2);
   18.93 +EXPORT_SYMBOL(xor_ia64_3);
   18.94 +EXPORT_SYMBOL(xor_ia64_4);
   18.95 +EXPORT_SYMBOL(xor_ia64_5);
   18.96 +#endif
   18.97 +
   18.98 +#include <asm/pal.h>
   18.99 +EXPORT_SYMBOL(ia64_pal_call_phys_stacked);
  18.100 +EXPORT_SYMBOL(ia64_pal_call_phys_static);
  18.101 +EXPORT_SYMBOL(ia64_pal_call_stacked);
  18.102 +EXPORT_SYMBOL(ia64_pal_call_static);
  18.103 +EXPORT_SYMBOL(ia64_load_scratch_fpregs);
  18.104 +EXPORT_SYMBOL(ia64_save_scratch_fpregs);
  18.105 +
  18.106 +#include <asm/unwind.h>
  18.107 +EXPORT_SYMBOL(unw_init_running);
  18.108 +
  18.109 +#ifdef ASM_SUPPORTED
  18.110 +# ifdef CONFIG_SMP
  18.111 +#  if __GNUC__ < 3 || (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
  18.112 +/*
  18.113 + * This is not a normal routine and we don't want a function descriptor for it, so we use
  18.114 + * a fake declaration here.
  18.115 + */
  18.116 +extern char ia64_spinlock_contention_pre3_4;
  18.117 +EXPORT_SYMBOL(ia64_spinlock_contention_pre3_4);
  18.118 +#  else
  18.119 +/*
  18.120 + * This is not a normal routine and we don't want a function descriptor for it, so we use
  18.121 + * a fake declaration here.
  18.122 + */
  18.123 +extern char ia64_spinlock_contention;
  18.124 +EXPORT_SYMBOL(ia64_spinlock_contention);
  18.125 +#  endif
  18.126 +# endif
  18.127 +#endif
  18.128 +
  18.129 +extern char ia64_ivt[];
  18.130 +EXPORT_SYMBOL(ia64_ivt);
    19.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    19.2 +++ b/xen/arch/ia64/linux/irq_lsapic.c	Mon Aug 08 12:21:23 2005 -0700
    19.3 @@ -0,0 +1,37 @@
    19.4 +/*
    19.5 + * LSAPIC Interrupt Controller
    19.6 + *
    19.7 + * This takes care of interrupts that are generated by the CPU's
    19.8 + * internal Streamlined Advanced Programmable Interrupt Controller
    19.9 + * (LSAPIC), such as the ITC and IPI interrupts.
   19.10 +    *
   19.11 + * Copyright (C) 1999 VA Linux Systems
   19.12 + * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
   19.13 + * Copyright (C) 2000 Hewlett-Packard Co
   19.14 + * Copyright (C) 2000 David Mosberger-Tang <davidm@hpl.hp.com>
   19.15 + */
   19.16 +
   19.17 +#include <linux/sched.h>
   19.18 +#include <linux/irq.h>
   19.19 +
   19.20 +static unsigned int
   19.21 +lsapic_noop_startup (unsigned int irq)
   19.22 +{
   19.23 +	return 0;
   19.24 +}
   19.25 +
   19.26 +static void
   19.27 +lsapic_noop (unsigned int irq)
   19.28 +{
   19.29 +	/* nuthing to do... */
   19.30 +}
   19.31 +
   19.32 +struct hw_interrupt_type irq_type_ia64_lsapic = {
   19.33 +	.typename =	"LSAPIC",
   19.34 +	.startup =	lsapic_noop_startup,
   19.35 +	.shutdown =	lsapic_noop,
   19.36 +	.enable =	lsapic_noop,
   19.37 +	.disable =	lsapic_noop,
   19.38 +	.ack =		lsapic_noop,
   19.39 +	.end =		lsapic_noop
   19.40 +};
    20.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    20.2 +++ b/xen/arch/ia64/linux/lib/Makefile	Mon Aug 08 12:21:23 2005 -0700
    20.3 @@ -0,0 +1,44 @@
    20.4 +#
    20.5 +# Makefile for ia64-specific library routines..
    20.6 +#
    20.7 +
    20.8 +include $(BASEDIR)/Rules.mk
    20.9 +
   20.10 +OBJS := __divsi3.o __udivsi3.o __modsi3.o __umodsi3.o			\
   20.11 +	__divdi3.o __udivdi3.o __moddi3.o __umoddi3.o			\
   20.12 +	bitop.o checksum.o clear_page.o csum_partial_copy.o copy_page.o	\
   20.13 +	clear_user.o strncpy_from_user.o strlen_user.o strnlen_user.o	\
   20.14 +	flush.o ip_fast_csum.o do_csum.o copy_user.o			\
   20.15 +	memset.o strlen.o memcpy.o 
   20.16 +
   20.17 +default: $(OBJS)
   20.18 +	$(LD) -r -o ia64lib.o $(OBJS)
   20.19 +
   20.20 +AFLAGS += -I$(BASEDIR)/include -D__ASSEMBLY__
   20.21 +
   20.22 +__divdi3.o: idiv64.S
   20.23 +	$(CC) $(AFLAGS) $(AFLAGS_KERNEL) -c -o $@ $<
   20.24 +
   20.25 +__udivdi3.o: idiv64.S
   20.26 +	$(CC) $(AFLAGS) $(AFLAGS_KERNEL) -c -DUNSIGNED -c -o $@ $<
   20.27 +
   20.28 +__moddi3.o: idiv64.S
   20.29 +	$(CC) $(AFLAGS) $(AFLAGS_KERNEL) -c -DMODULO -c -o $@ $<
   20.30 +
   20.31 +__umoddi3.o: idiv64.S
   20.32 +	$(CC) $(AFLAGS) $(AFLAGS_KERNEL) -c -DMODULO -DUNSIGNED -c -o $@ $<
   20.33 +
   20.34 +__divsi3.o: idiv32.S
   20.35 +	$(CC) $(AFLAGS) $(AFLAGS_KERNEL) -c -o $@ $<
   20.36 +
   20.37 +__udivsi3.o: idiv32.S
   20.38 +	$(CC) $(AFLAGS) $(AFLAGS_KERNEL) -c -DUNSIGNED -c -o $@ $<
   20.39 +
   20.40 +__modsi3.o: idiv32.S
   20.41 +	$(CC) $(AFLAGS) $(AFLAGS_KERNEL) -c -DMODULO -c -o $@ $<
   20.42 +
   20.43 +__umodsi3.o: idiv32.S
   20.44 +	$(CC) $(AFLAGS) $(AFLAGS_KERNEL) -c -DMODULO -DUNSIGNED -c -o $@ $<
   20.45 +
   20.46 +clean:
   20.47 +	rm -f *.o *~
    21.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    21.2 +++ b/xen/arch/ia64/linux/lib/bitop.c	Mon Aug 08 12:21:23 2005 -0700
    21.3 @@ -0,0 +1,88 @@
    21.4 +#include <linux/compiler.h>
    21.5 +#include <linux/types.h>
    21.6 +#include <asm/intrinsics.h>
    21.7 +#include <linux/module.h>
    21.8 +#include <linux/bitops.h>
    21.9 +
   21.10 +/*
   21.11 + * Find next zero bit in a bitmap reasonably efficiently..
   21.12 + */
   21.13 +
   21.14 +int __find_next_zero_bit (const void *addr, unsigned long size, unsigned long offset)
   21.15 +{
   21.16 +	unsigned long *p = ((unsigned long *) addr) + (offset >> 6);
   21.17 +	unsigned long result = offset & ~63UL;
   21.18 +	unsigned long tmp;
   21.19 +
   21.20 +	if (offset >= size)
   21.21 +		return size;
   21.22 +	size -= result;
   21.23 +	offset &= 63UL;
   21.24 +	if (offset) {
   21.25 +		tmp = *(p++);
   21.26 +		tmp |= ~0UL >> (64-offset);
   21.27 +		if (size < 64)
   21.28 +			goto found_first;
   21.29 +		if (~tmp)
   21.30 +			goto found_middle;
   21.31 +		size -= 64;
   21.32 +		result += 64;
   21.33 +	}
   21.34 +	while (size & ~63UL) {
   21.35 +		if (~(tmp = *(p++)))
   21.36 +			goto found_middle;
   21.37 +		result += 64;
   21.38 +		size -= 64;
   21.39 +	}
   21.40 +	if (!size)
   21.41 +		return result;
   21.42 +	tmp = *p;
   21.43 +found_first:
   21.44 +	tmp |= ~0UL << size;
   21.45 +	if (tmp == ~0UL)		/* any bits zero? */
   21.46 +		return result + size;	/* nope */
   21.47 +found_middle:
   21.48 +	return result + ffz(tmp);
   21.49 +}
   21.50 +EXPORT_SYMBOL(__find_next_zero_bit);
   21.51 +
   21.52 +/*
   21.53 + * Find next bit in a bitmap reasonably efficiently..
   21.54 + */
   21.55 +int __find_next_bit(const void *addr, unsigned long size, unsigned long offset)
   21.56 +{
   21.57 +	unsigned long *p = ((unsigned long *) addr) + (offset >> 6);
   21.58 +	unsigned long result = offset & ~63UL;
   21.59 +	unsigned long tmp;
   21.60 +
   21.61 +	if (offset >= size)
   21.62 +		return size;
   21.63 +	size -= result;
   21.64 +	offset &= 63UL;
   21.65 +	if (offset) {
   21.66 +		tmp = *(p++);
   21.67 +		tmp &= ~0UL << offset;
   21.68 +		if (size < 64)
   21.69 +			goto found_first;
   21.70 +		if (tmp)
   21.71 +			goto found_middle;
   21.72 +		size -= 64;
   21.73 +		result += 64;
   21.74 +	}
   21.75 +	while (size & ~63UL) {
   21.76 +		if ((tmp = *(p++)))
   21.77 +			goto found_middle;
   21.78 +		result += 64;
   21.79 +		size -= 64;
   21.80 +	}
   21.81 +	if (!size)
   21.82 +		return result;
   21.83 +	tmp = *p;
   21.84 +  found_first:
   21.85 +	tmp &= ~0UL >> (64-size);
   21.86 +	if (tmp == 0UL)		/* Are any bits set? */
   21.87 +		return result + size; /* Nope. */
   21.88 +  found_middle:
   21.89 +	return result + __ffs(tmp);
   21.90 +}
   21.91 +EXPORT_SYMBOL(__find_next_bit);
    22.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    22.2 +++ b/xen/arch/ia64/linux/lib/carta_random.S	Mon Aug 08 12:21:23 2005 -0700
    22.3 @@ -0,0 +1,54 @@
    22.4 +/*
    22.5 + * Fast, simple, yet decent quality random number generator based on
    22.6 + * a paper by David G. Carta ("Two Fast Implementations of the
    22.7 + * `Minimal Standard' Random Number Generator," Communications of the
    22.8 + * ACM, January, 1990).
    22.9 + *
   22.10 + * Copyright (C) 2002 Hewlett-Packard Co
   22.11 + *	David Mosberger-Tang <davidm@hpl.hp.com>
   22.12 + */
   22.13 +
   22.14 +#include <asm/asmmacro.h>
   22.15 +
   22.16 +#define a	r2
   22.17 +#define m	r3
   22.18 +#define lo	r8
   22.19 +#define hi	r9
   22.20 +#define t0	r16
   22.21 +#define t1	r17
   22.22 +#define	seed	r32
   22.23 +
   22.24 +GLOBAL_ENTRY(carta_random32)
   22.25 +	movl	a = (16807 << 16) | 16807
   22.26 +	;;
   22.27 +	pmpyshr2.u t0 = a, seed, 0
   22.28 +	pmpyshr2.u t1 = a, seed, 16
   22.29 +	;;
   22.30 +	unpack2.l t0 = t1, t0
   22.31 +	dep	m = -1, r0, 0, 31
   22.32 +	;;
   22.33 +	zxt4	lo = t0
   22.34 +	shr.u	hi = t0, 32
   22.35 +	;;
   22.36 +	dep	t0 = 0, hi, 15, 49	// t0 = (hi & 0x7fff)
   22.37 +	;;
   22.38 +	shl	t0 = t0, 16		// t0 = (hi & 0x7fff) << 16
   22.39 +	shr	t1 = hi, 15		// t1 = (hi >> 15)
   22.40 +	;;
   22.41 +	add	lo = lo, t0
   22.42 +	;;
   22.43 +	cmp.gtu	p6, p0 = lo, m
   22.44 +	;;
   22.45 +(p6)	and	lo = lo, m
   22.46 +	;;
   22.47 +(p6)	add	lo = 1, lo
   22.48 +	;;
   22.49 +	add	lo = lo, t1
   22.50 +	;;
   22.51 +	cmp.gtu p6, p0 = lo, m
   22.52 +	;;
   22.53 +(p6)	and	lo = lo, m
   22.54 +	;;
   22.55 +(p6)	add	lo = 1, lo
   22.56 +	br.ret.sptk.many rp
   22.57 +END(carta_random32)
    23.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    23.2 +++ b/xen/arch/ia64/linux/lib/checksum.c	Mon Aug 08 12:21:23 2005 -0700
    23.3 @@ -0,0 +1,102 @@
    23.4 +/*
    23.5 + * Network checksum routines
    23.6 + *
    23.7 + * Copyright (C) 1999, 2003 Hewlett-Packard Co
    23.8 + *	Stephane Eranian <eranian@hpl.hp.com>
    23.9 + *
   23.10 + * Most of the code coming from arch/alpha/lib/checksum.c
   23.11 + *
   23.12 + * This file contains network checksum routines that are better done
   23.13 + * in an architecture-specific manner due to speed..
   23.14 + */
   23.15 +
   23.16 +#include <linux/module.h>
   23.17 +#include <linux/string.h>
   23.18 +
   23.19 +#include <asm/byteorder.h>
   23.20 +
   23.21 +static inline unsigned short
   23.22 +from64to16 (unsigned long x)
   23.23 +{
   23.24 +	/* add up 32-bit words for 33 bits */
   23.25 +	x = (x & 0xffffffff) + (x >> 32);
   23.26 +	/* add up 16-bit and 17-bit words for 17+c bits */
   23.27 +	x = (x & 0xffff) + (x >> 16);
   23.28 +	/* add up 16-bit and 2-bit for 16+c bit */
   23.29 +	x = (x & 0xffff) + (x >> 16);
   23.30 +	/* add up carry.. */
   23.31 +	x = (x & 0xffff) + (x >> 16);
   23.32 +	return x;
   23.33 +}
   23.34 +
   23.35 +/*
   23.36 + * computes the checksum of the TCP/UDP pseudo-header
   23.37 + * returns a 16-bit checksum, already complemented.
   23.38 + */
   23.39 +unsigned short int
   23.40 +csum_tcpudp_magic (unsigned long saddr, unsigned long daddr, unsigned short len,
   23.41 +		   unsigned short proto, unsigned int sum)
   23.42 +{
   23.43 +	return ~from64to16(saddr + daddr + sum + ((unsigned long) ntohs(len) << 16) +
   23.44 +			   ((unsigned long) proto << 8));
   23.45 +}
   23.46 +
   23.47 +EXPORT_SYMBOL(csum_tcpudp_magic);
   23.48 +
   23.49 +unsigned int
   23.50 +csum_tcpudp_nofold (unsigned long saddr, unsigned long daddr, unsigned short len,
   23.51 +		    unsigned short proto, unsigned int sum)
   23.52 +{
   23.53 +	unsigned long result;
   23.54 +
   23.55 +	result = (saddr + daddr + sum +
   23.56 +		  ((unsigned long) ntohs(len) << 16) +
   23.57 +		  ((unsigned long) proto << 8));
   23.58 +
   23.59 +	/* Fold down to 32-bits so we don't lose in the typedef-less network stack.  */
   23.60 +	/* 64 to 33 */
   23.61 +	result = (result & 0xffffffff) + (result >> 32);
   23.62 +	/* 33 to 32 */
   23.63 +	result = (result & 0xffffffff) + (result >> 32);
   23.64 +	return result;
   23.65 +}
   23.66 +
   23.67 +extern unsigned long do_csum (const unsigned char *, long);
   23.68 +
   23.69 +/*
   23.70 + * computes the checksum of a memory block at buff, length len,
   23.71 + * and adds in "sum" (32-bit)
   23.72 + *
   23.73 + * returns a 32-bit number suitable for feeding into itself
   23.74 + * or csum_tcpudp_magic
   23.75 + *
   23.76 + * this function must be called with even lengths, except
   23.77 + * for the last fragment, which may be odd
   23.78 + *
   23.79 + * it's best to have buff aligned on a 32-bit boundary
   23.80 + */
   23.81 +unsigned int
   23.82 +csum_partial (const unsigned char * buff, int len, unsigned int sum)
   23.83 +{
   23.84 +	unsigned long result = do_csum(buff, len);
   23.85 +
   23.86 +	/* add in old sum, and carry.. */
   23.87 +	result += sum;
   23.88 +	/* 32+c bits -> 32 bits */
   23.89 +	result = (result & 0xffffffff) + (result >> 32);
   23.90 +	return result;
   23.91 +}
   23.92 +
   23.93 +EXPORT_SYMBOL(csum_partial);
   23.94 +
   23.95 +/*
   23.96 + * this routine is used for miscellaneous IP-like checksums, mainly
   23.97 + * in icmp.c
   23.98 + */
   23.99 +unsigned short
  23.100 +ip_compute_csum (unsigned char * buff, int len)
  23.101 +{
  23.102 +	return ~do_csum(buff,len);
  23.103 +}
  23.104 +
  23.105 +EXPORT_SYMBOL(ip_compute_csum);
    24.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    24.2 +++ b/xen/arch/ia64/linux/lib/clear_page.S	Mon Aug 08 12:21:23 2005 -0700
    24.3 @@ -0,0 +1,77 @@
    24.4 +/*
    24.5 + * Copyright (C) 1999-2002 Hewlett-Packard Co
    24.6 + *	Stephane Eranian <eranian@hpl.hp.com>
    24.7 + *	David Mosberger-Tang <davidm@hpl.hp.com>
    24.8 + * Copyright (C) 2002 Ken Chen <kenneth.w.chen@intel.com>
    24.9 + *
   24.10 + * 1/06/01 davidm	Tuned for Itanium.
   24.11 + * 2/12/02 kchen	Tuned for both Itanium and McKinley
   24.12 + * 3/08/02 davidm	Some more tweaking
   24.13 + */
   24.14 +#include <linux/config.h>
   24.15 +
   24.16 +#include <asm/asmmacro.h>
   24.17 +#include <asm/page.h>
   24.18 +
   24.19 +#ifdef CONFIG_ITANIUM
   24.20 +# define L3_LINE_SIZE	64	// Itanium L3 line size
   24.21 +# define PREFETCH_LINES	9	// magic number
   24.22 +#else
   24.23 +# define L3_LINE_SIZE	128	// McKinley L3 line size
   24.24 +# define PREFETCH_LINES	12	// magic number
   24.25 +#endif
   24.26 +
   24.27 +#define saved_lc	r2
   24.28 +#define dst_fetch	r3
   24.29 +#define dst1		r8
   24.30 +#define dst2		r9
   24.31 +#define dst3		r10
   24.32 +#define dst4		r11
   24.33 +
   24.34 +#define dst_last	r31
   24.35 +
   24.36 +GLOBAL_ENTRY(clear_page)
   24.37 +	.prologue
   24.38 +	.regstk 1,0,0,0
   24.39 +	mov r16 = PAGE_SIZE/L3_LINE_SIZE-1	// main loop count, -1=repeat/until
   24.40 +	.save ar.lc, saved_lc
   24.41 +	mov saved_lc = ar.lc
   24.42 +
   24.43 +	.body
   24.44 +	mov ar.lc = (PREFETCH_LINES - 1)
   24.45 +	mov dst_fetch = in0
   24.46 +	adds dst1 = 16, in0
   24.47 +	adds dst2 = 32, in0
   24.48 +	;;
   24.49 +.fetch:	stf.spill.nta [dst_fetch] = f0, L3_LINE_SIZE
   24.50 +	adds dst3 = 48, in0		// executing this multiple times is harmless
   24.51 +	br.cloop.sptk.few .fetch
   24.52 +	;;
   24.53 +	addl dst_last = (PAGE_SIZE - PREFETCH_LINES*L3_LINE_SIZE), dst_fetch
   24.54 +	mov ar.lc = r16			// one L3 line per iteration
   24.55 +	adds dst4 = 64, in0
   24.56 +	;;
   24.57 +#ifdef CONFIG_ITANIUM
   24.58 +	// Optimized for Itanium
   24.59 +1:	stf.spill.nta [dst1] = f0, 64
   24.60 +	stf.spill.nta [dst2] = f0, 64
   24.61 +	cmp.lt p8,p0=dst_fetch, dst_last
   24.62 +	;;
   24.63 +#else
   24.64 +	// Optimized for McKinley
   24.65 +1:	stf.spill.nta [dst1] = f0, 64
   24.66 +	stf.spill.nta [dst2] = f0, 64
   24.67 +	stf.spill.nta [dst3] = f0, 64
   24.68 +	stf.spill.nta [dst4] = f0, 128
   24.69 +	cmp.lt p8,p0=dst_fetch, dst_last
   24.70 +	;;
   24.71 +	stf.spill.nta [dst1] = f0, 64
   24.72 +	stf.spill.nta [dst2] = f0, 64
   24.73 +#endif
   24.74 +	stf.spill.nta [dst3] = f0, 64
   24.75 +(p8)	stf.spill.nta [dst_fetch] = f0, L3_LINE_SIZE
   24.76 +	br.cloop.sptk.few 1b
   24.77 +	;;
   24.78 +	mov ar.lc = saved_lc		// restore lc
   24.79 +	br.ret.sptk.many rp
   24.80 +END(clear_page)
    25.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    25.2 +++ b/xen/arch/ia64/linux/lib/clear_user.S	Mon Aug 08 12:21:23 2005 -0700
    25.3 @@ -0,0 +1,209 @@
    25.4 +/*
    25.5 + * This routine clears to zero a linear memory buffer in user space.
    25.6 + *
    25.7 + * Inputs:
    25.8 + *	in0:	address of buffer
    25.9 + *	in1:	length of buffer in bytes
   25.10 + * Outputs:
   25.11 + *	r8:	number of bytes that didn't get cleared due to a fault
   25.12 + *
   25.13 + * Copyright (C) 1998, 1999, 2001 Hewlett-Packard Co
   25.14 + *	Stephane Eranian <eranian@hpl.hp.com>
   25.15 + */
   25.16 +
   25.17 +#include <asm/asmmacro.h>
   25.18 +
   25.19 +//
   25.20 +// arguments
   25.21 +//
   25.22 +#define buf		r32
   25.23 +#define len		r33
   25.24 +
   25.25 +//
   25.26 +// local registers
   25.27 +//
   25.28 +#define cnt		r16
   25.29 +#define buf2		r17
   25.30 +#define saved_lc	r18
   25.31 +#define saved_pfs	r19
   25.32 +#define tmp		r20
   25.33 +#define len2		r21
   25.34 +#define len3		r22
   25.35 +
   25.36 +//
   25.37 +// Theory of operations:
   25.38 +//	- we check whether or not the buffer is small, i.e., less than 17
   25.39 +//	  in which case we do the byte by byte loop.
   25.40 +//
   25.41 +//	- Otherwise we go progressively from 1 byte store to 8byte store in
   25.42 +//	  the head part, the body is a 16byte store loop and we finish we the
   25.43 +//	  tail for the last 15 bytes.
   25.44 +//	  The good point about this breakdown is that the long buffer handling
   25.45 +//	  contains only 2 branches.
   25.46 +//
   25.47 +//	The reason for not using shifting & masking for both the head and the
   25.48 +//	tail is to stay semantically correct. This routine is not supposed
   25.49 +//	to write bytes outside of the buffer. While most of the time this would
   25.50 +//	be ok, we can't tolerate a mistake. A classical example is the case
   25.51 +//	of multithreaded code were to the extra bytes touched is actually owned
   25.52 +//	by another thread which runs concurrently to ours. Another, less likely,
   25.53 +//	example is with device drivers where reading an I/O mapped location may
   25.54 +//	have side effects (same thing for writing).
   25.55 +//
   25.56 +
   25.57 +GLOBAL_ENTRY(__do_clear_user)
   25.58 +	.prologue
   25.59 +	.save ar.pfs, saved_pfs
   25.60 +	alloc	saved_pfs=ar.pfs,2,0,0,0
   25.61 +	cmp.eq p6,p0=r0,len		// check for zero length
   25.62 +	.save ar.lc, saved_lc
   25.63 +	mov saved_lc=ar.lc		// preserve ar.lc (slow)
   25.64 +	.body
   25.65 +	;;				// avoid WAW on CFM
   25.66 +	adds tmp=-1,len			// br.ctop is repeat/until
   25.67 +	mov ret0=len			// return value is length at this point
   25.68 +(p6)	br.ret.spnt.many rp
   25.69 +	;;
   25.70 +	cmp.lt p6,p0=16,len		// if len > 16 then long memset
   25.71 +	mov ar.lc=tmp			// initialize lc for small count
   25.72 +(p6)	br.cond.dptk .long_do_clear
   25.73 +	;;				// WAR on ar.lc
   25.74 +	//
   25.75 +	// worst case 16 iterations, avg 8 iterations
   25.76 +	//
   25.77 +	// We could have played with the predicates to use the extra
   25.78 +	// M slot for 2 stores/iteration but the cost the initialization
   25.79 +	// the various counters compared to how long the loop is supposed
   25.80 +	// to last on average does not make this solution viable.
   25.81 +	//
   25.82 +1:
   25.83 +	EX( .Lexit1, st1 [buf]=r0,1 )
   25.84 +	adds len=-1,len			// countdown length using len
   25.85 +	br.cloop.dptk 1b
   25.86 +	;;				// avoid RAW on ar.lc
   25.87 +	//
   25.88 +	// .Lexit4: comes from byte by byte loop
   25.89 +	//	    len contains bytes left
   25.90 +.Lexit1:
   25.91 +	mov ret0=len			// faster than using ar.lc
   25.92 +	mov ar.lc=saved_lc
   25.93 +	br.ret.sptk.many rp		// end of short clear_user
   25.94 +
   25.95 +
   25.96 +	//
   25.97 +	// At this point we know we have more than 16 bytes to copy
   25.98 +	// so we focus on alignment (no branches required)
   25.99 +	//
  25.100 +	// The use of len/len2 for countdown of the number of bytes left
  25.101 +	// instead of ret0 is due to the fact that the exception code
  25.102 +	// changes the values of r8.
  25.103 +	//
  25.104 +.long_do_clear:
  25.105 +	tbit.nz p6,p0=buf,0		// odd alignment (for long_do_clear)
  25.106 +	;;
  25.107 +	EX( .Lexit3, (p6) st1 [buf]=r0,1 )	// 1-byte aligned
  25.108 +(p6)	adds len=-1,len;;		// sync because buf is modified
  25.109 +	tbit.nz p6,p0=buf,1
  25.110 +	;;
  25.111 +	EX( .Lexit3, (p6) st2 [buf]=r0,2 )	// 2-byte aligned
  25.112 +(p6)	adds len=-2,len;;
  25.113 +	tbit.nz p6,p0=buf,2
  25.114 +	;;
  25.115 +	EX( .Lexit3, (p6) st4 [buf]=r0,4 )	// 4-byte aligned
  25.116 +(p6)	adds len=-4,len;;
  25.117 +	tbit.nz p6,p0=buf,3
  25.118 +	;;
  25.119 +	EX( .Lexit3, (p6) st8 [buf]=r0,8 )	// 8-byte aligned
  25.120 +(p6)	adds len=-8,len;;
  25.121 +	shr.u cnt=len,4		// number of 128-bit (2x64bit) words
  25.122 +	;;
  25.123 +	cmp.eq p6,p0=r0,cnt
  25.124 +	adds tmp=-1,cnt
  25.125 +(p6)	br.cond.dpnt .dotail		// we have less than 16 bytes left
  25.126 +	;;
  25.127 +	adds buf2=8,buf			// setup second base pointer
  25.128 +	mov ar.lc=tmp
  25.129 +	;;
  25.130 +
  25.131 +	//
  25.132 +	// 16bytes/iteration core loop
  25.133 +	//
  25.134 +	// The second store can never generate a fault because
  25.135 +	// we come into the loop only when we are 16-byte aligned.
  25.136 +	// This means that if we cross a page then it will always be
  25.137 +	// in the first store and never in the second.
  25.138 +	//
  25.139 +	//
  25.140 +	// We need to keep track of the remaining length. A possible (optimistic)
  25.141 +	// way would be to use ar.lc and derive how many byte were left by
  25.142 +	// doing : left= 16*ar.lc + 16.  this would avoid the addition at
  25.143 +	// every iteration.
  25.144 +	// However we need to keep the synchronization point. A template
  25.145 +	// M;;MB does not exist and thus we can keep the addition at no
  25.146 +	// extra cycle cost (use a nop slot anyway). It also simplifies the
  25.147 +	// (unlikely)  error recovery code
  25.148 +	//
  25.149 +
  25.150 +2:	EX(.Lexit3, st8 [buf]=r0,16 )
  25.151 +	;;				// needed to get len correct when error
  25.152 +	st8 [buf2]=r0,16
  25.153 +	adds len=-16,len
  25.154 +	br.cloop.dptk 2b
  25.155 +	;;
  25.156 +	mov ar.lc=saved_lc
  25.157 +	//
  25.158 +	// tail correction based on len only
  25.159 +	//
  25.160 +	// We alternate the use of len3,len2 to allow parallelism and correct
  25.161 +	// error handling. We also reuse p6/p7 to return correct value.
  25.162 +	// The addition of len2/len3 does not cost anything more compared to
  25.163 +	// the regular memset as we had empty slots.
  25.164 +	//
  25.165 +.dotail:
  25.166 +	mov len2=len			// for parallelization of error handling
  25.167 +	mov len3=len
  25.168 +	tbit.nz p6,p0=len,3
  25.169 +	;;
  25.170 +	EX( .Lexit2, (p6) st8 [buf]=r0,8 )	// at least 8 bytes
  25.171 +(p6)	adds len3=-8,len2
  25.172 +	tbit.nz p7,p6=len,2
  25.173 +	;;
  25.174 +	EX( .Lexit2, (p7) st4 [buf]=r0,4 )	// at least 4 bytes
  25.175 +(p7)	adds len2=-4,len3
  25.176 +	tbit.nz p6,p7=len,1
  25.177 +	;;
  25.178 +	EX( .Lexit2, (p6) st2 [buf]=r0,2 )	// at least 2 bytes
  25.179 +(p6)	adds len3=-2,len2
  25.180 +	tbit.nz p7,p6=len,0
  25.181 +	;;
  25.182 +	EX( .Lexit2, (p7) st1 [buf]=r0 )	// only 1 byte left
  25.183 +	mov ret0=r0				// success
  25.184 +	br.ret.sptk.many rp			// end of most likely path
  25.185 +
  25.186 +	//
  25.187 +	// Outlined error handling code
  25.188 +	//
  25.189 +
  25.190 +	//
  25.191 +	// .Lexit3: comes from core loop, need restore pr/lc
  25.192 +	//	    len contains bytes left
  25.193 +	//
  25.194 +	//
  25.195 +	// .Lexit2:
  25.196 +	//	if p6 -> coming from st8 or st2 : len2 contains what's left
  25.197 +	//	if p7 -> coming from st4 or st1 : len3 contains what's left
  25.198 +	// We must restore lc/pr even though might not have been used.
  25.199 +.Lexit2:
  25.200 +	.pred.rel "mutex", p6, p7
  25.201 +(p6)	mov len=len2
  25.202 +(p7)	mov len=len3
  25.203 +	;;
  25.204 +	//
  25.205 +	// .Lexit4: comes from head, need not restore pr/lc
  25.206 +	//	    len contains bytes left
  25.207 +	//
  25.208 +.Lexit3:
  25.209 +	mov ret0=len
  25.210 +	mov ar.lc=saved_lc
  25.211 +	br.ret.sptk.many rp
  25.212 +END(__do_clear_user)
    26.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    26.2 +++ b/xen/arch/ia64/linux/lib/copy_page.S	Mon Aug 08 12:21:23 2005 -0700
    26.3 @@ -0,0 +1,98 @@
    26.4 +/*
    26.5 + *
    26.6 + * Optimized version of the standard copy_page() function
    26.7 + *
    26.8 + * Inputs:
    26.9 + *	in0:	address of target page
   26.10 + *	in1:	address of source page
   26.11 + * Output:
   26.12 + *	no return value
   26.13 + *
   26.14 + * Copyright (C) 1999, 2001 Hewlett-Packard Co
   26.15 + *	Stephane Eranian <eranian@hpl.hp.com>
   26.16 + *	David Mosberger <davidm@hpl.hp.com>
   26.17 + *
   26.18 + * 4/06/01 davidm	Tuned to make it perform well both for cached and uncached copies.
   26.19 + */
   26.20 +#include <asm/asmmacro.h>
   26.21 +#include <asm/page.h>
   26.22 +
   26.23 +#define PIPE_DEPTH	3
   26.24 +#define EPI		p[PIPE_DEPTH-1]
   26.25 +
   26.26 +#define lcount		r16
   26.27 +#define saved_pr	r17
   26.28 +#define saved_lc	r18
   26.29 +#define saved_pfs	r19
   26.30 +#define src1		r20
   26.31 +#define src2		r21
   26.32 +#define tgt1		r22
   26.33 +#define tgt2		r23
   26.34 +#define srcf		r24
   26.35 +#define tgtf		r25
   26.36 +#define tgt_last	r26
   26.37 +
   26.38 +#define Nrot		((8*PIPE_DEPTH+7)&~7)
   26.39 +
   26.40 +GLOBAL_ENTRY(copy_page)
   26.41 +	.prologue
   26.42 +	.save ar.pfs, saved_pfs
   26.43 +	alloc saved_pfs=ar.pfs,3,Nrot-3,0,Nrot
   26.44 +
   26.45 +	.rotr t1[PIPE_DEPTH], t2[PIPE_DEPTH], t3[PIPE_DEPTH], t4[PIPE_DEPTH], \
   26.46 +	      t5[PIPE_DEPTH], t6[PIPE_DEPTH], t7[PIPE_DEPTH], t8[PIPE_DEPTH]
   26.47 +	.rotp p[PIPE_DEPTH]
   26.48 +
   26.49 +	.save ar.lc, saved_lc
   26.50 +	mov saved_lc=ar.lc
   26.51 +	mov ar.ec=PIPE_DEPTH
   26.52 +
   26.53 +	mov lcount=PAGE_SIZE/64-1
   26.54 +	.save pr, saved_pr
   26.55 +	mov saved_pr=pr
   26.56 +	mov pr.rot=1<<16
   26.57 +
   26.58 +	.body
   26.59 +
   26.60 +	mov src1=in1
   26.61 +	adds src2=8,in1
   26.62 +	mov tgt_last = PAGE_SIZE
   26.63 +	;;
   26.64 +	adds tgt2=8,in0
   26.65 +	add srcf=512,in1
   26.66 +	mov ar.lc=lcount
   26.67 +	mov tgt1=in0
   26.68 +	add tgtf=512,in0
   26.69 +	add tgt_last = tgt_last, in0
   26.70 +	;;
   26.71 +1:
   26.72 +(p[0])	ld8 t1[0]=[src1],16
   26.73 +(EPI)	st8 [tgt1]=t1[PIPE_DEPTH-1],16
   26.74 +(p[0])	ld8 t2[0]=[src2],16
   26.75 +(EPI)	st8 [tgt2]=t2[PIPE_DEPTH-1],16
   26.76 +	cmp.ltu p6,p0 = tgtf, tgt_last
   26.77 +	;;
   26.78 +(p[0])	ld8 t3[0]=[src1],16
   26.79 +(EPI)	st8 [tgt1]=t3[PIPE_DEPTH-1],16
   26.80 +(p[0])	ld8 t4[0]=[src2],16
   26.81 +(EPI)	st8 [tgt2]=t4[PIPE_DEPTH-1],16
   26.82 +	;;
   26.83 +(p[0])	ld8 t5[0]=[src1],16
   26.84 +(EPI)	st8 [tgt1]=t5[PIPE_DEPTH-1],16
   26.85 +(p[0])	ld8 t6[0]=[src2],16
   26.86 +(EPI)	st8 [tgt2]=t6[PIPE_DEPTH-1],16
   26.87 +	;;
   26.88 +(p[0])	ld8 t7[0]=[src1],16
   26.89 +(EPI)	st8 [tgt1]=t7[PIPE_DEPTH-1],16
   26.90 +(p[0])	ld8 t8[0]=[src2],16
   26.91 +(EPI)	st8 [tgt2]=t8[PIPE_DEPTH-1],16
   26.92 +
   26.93 +(p6)	lfetch [srcf], 64
   26.94 +(p6)	lfetch [tgtf], 64
   26.95 +	br.ctop.sptk.few 1b
   26.96 +	;;
   26.97 +	mov pr=saved_pr,0xffffffffffff0000	// restore predicates
   26.98 +	mov ar.pfs=saved_pfs
   26.99 +	mov ar.lc=saved_lc
  26.100 +	br.ret.sptk.many rp
  26.101 +END(copy_page)
    27.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    27.2 +++ b/xen/arch/ia64/linux/lib/copy_page_mck.S	Mon Aug 08 12:21:23 2005 -0700
    27.3 @@ -0,0 +1,185 @@
    27.4 +/*
    27.5 + * McKinley-optimized version of copy_page().
    27.6 + *
    27.7 + * Copyright (C) 2002 Hewlett-Packard Co
    27.8 + *	David Mosberger <davidm@hpl.hp.com>
    27.9 + *
   27.10 + * Inputs:
   27.11 + *	in0:	address of target page
   27.12 + *	in1:	address of source page
   27.13 + * Output:
   27.14 + *	no return value
   27.15 + *
   27.16 + * General idea:
   27.17 + *	- use regular loads and stores to prefetch data to avoid consuming M-slot just for
   27.18 + *	  lfetches => good for in-cache performance
   27.19 + *	- avoid l2 bank-conflicts by not storing into the same 16-byte bank within a single
   27.20 + *	  cycle
   27.21 + *
   27.22 + * Principle of operation:
   27.23 + *	First, note that L1 has a line-size of 64 bytes and L2 a line-size of 128 bytes.
   27.24 + *	To avoid secondary misses in L2, we prefetch both source and destination with a line-size
   27.25 + *	of 128 bytes.  When both of these lines are in the L2 and the first half of the
   27.26 + *	source line is in L1, we start copying the remaining words.  The second half of the
   27.27 + *	source line is prefetched in an earlier iteration, so that by the time we start
   27.28 + *	accessing it, it's also present in the L1.
   27.29 + *
   27.30 + *	We use a software-pipelined loop to control the overall operation.  The pipeline
   27.31 + *	has 2*PREFETCH_DIST+K stages.  The first PREFETCH_DIST stages are used for prefetching
   27.32 + *	source cache-lines.  The second PREFETCH_DIST stages are used for prefetching destination
   27.33 + *	cache-lines, the last K stages are used to copy the cache-line words not copied by
   27.34 + *	the prefetches.  The four relevant points in the pipelined are called A, B, C, D:
   27.35 + *	p[A] is TRUE if a source-line should be prefetched, p[B] is TRUE if a destination-line
   27.36 + *	should be prefetched, p[C] is TRUE if the second half of an L2 line should be brought
   27.37 + *	into L1D and p[D] is TRUE if a cacheline needs to be copied.
   27.38 + *
   27.39 + *	This all sounds very complicated, but thanks to the modulo-scheduled loop support,
   27.40 + *	the resulting code is very regular and quite easy to follow (once you get the idea).
   27.41 + *
   27.42 + *	As a secondary optimization, the first 2*PREFETCH_DIST iterations are implemented
   27.43 + *	as the separate .prefetch_loop.  Logically, this loop performs exactly like the
   27.44 + *	main-loop (.line_copy), but has all known-to-be-predicated-off instructions removed,
   27.45 + *	so that each loop iteration is faster (again, good for cached case).
   27.46 + *
   27.47 + *	When reading the code, it helps to keep the following picture in mind:
   27.48 + *
   27.49 + *	       word 0 word 1
   27.50 + *            +------+------+---
   27.51 + *	      |	v[x] | 	t1  | ^
   27.52 + *	      |	t2   |	t3  | |
   27.53 + *	      |	t4   |	t5  | |
   27.54 + *	      |	t6   |	t7  | | 128 bytes
   27.55 + *     	      |	n[y] | 	t9  | |	(L2 cache line)
   27.56 + *	      |	t10  | 	t11 | |
   27.57 + *	      |	t12  | 	t13 | |
   27.58 + *	      |	t14  | 	t15 | v
   27.59 + *	      +------+------+---
   27.60 + *
   27.61 + *	Here, v[x] is copied by the (memory) prefetch.  n[y] is loaded at p[C]
   27.62 + *	to fetch the second-half of the L2 cache line into L1, and the tX words are copied in
   27.63 + *	an order that avoids bank conflicts.
   27.64 + */
   27.65 +#include <asm/asmmacro.h>
   27.66 +#include <asm/page.h>
   27.67 +
   27.68 +#define PREFETCH_DIST	8		// McKinley sustains 16 outstanding L2 misses (8 ld, 8 st)
   27.69 +
   27.70 +#define src0		r2
   27.71 +#define src1		r3
   27.72 +#define dst0		r9
   27.73 +#define dst1		r10
   27.74 +#define src_pre_mem	r11
   27.75 +#define dst_pre_mem	r14
   27.76 +#define src_pre_l2	r15
   27.77 +#define dst_pre_l2	r16
   27.78 +#define t1		r17
   27.79 +#define t2		r18
   27.80 +#define t3		r19
   27.81 +#define t4		r20
   27.82 +#define t5		t1	// alias!
   27.83 +#define t6		t2	// alias!
   27.84 +#define t7		t3	// alias!
   27.85 +#define t9		t5	// alias!
   27.86 +#define t10		t4	// alias!
   27.87 +#define t11		t7	// alias!
   27.88 +#define t12		t6	// alias!
   27.89 +#define t14		t10	// alias!
   27.90 +#define t13		r21
   27.91 +#define t15		r22
   27.92 +
   27.93 +#define saved_lc	r23
   27.94 +#define saved_pr	r24
   27.95 +
   27.96 +#define	A	0
   27.97 +#define B	(PREFETCH_DIST)
   27.98 +#define C	(B + PREFETCH_DIST)
   27.99 +#define D	(C + 3)
  27.100 +#define N	(D + 1)
  27.101 +#define Nrot	((N + 7) & ~7)
  27.102 +
  27.103 +GLOBAL_ENTRY(copy_page)
  27.104 +	.prologue
  27.105 +	alloc r8 = ar.pfs, 2, Nrot-2, 0, Nrot
  27.106 +
  27.107 +	.rotr v[2*PREFETCH_DIST], n[D-C+1]
  27.108 +	.rotp p[N]
  27.109 +
  27.110 +	.save ar.lc, saved_lc
  27.111 +	mov saved_lc = ar.lc
  27.112 +	.save pr, saved_pr
  27.113 +	mov saved_pr = pr
  27.114 +	.body
  27.115 +
  27.116 +	mov src_pre_mem = in1
  27.117 +	mov pr.rot = 0x10000
  27.118 +	mov ar.ec = 1				// special unrolled loop
  27.119 +
  27.120 +	mov dst_pre_mem = in0
  27.121 +	mov ar.lc = 2*PREFETCH_DIST - 1
  27.122 +
  27.123 +	add src_pre_l2 = 8*8, in1
  27.124 +	add dst_pre_l2 = 8*8, in0
  27.125 +	add src0 = 8, in1			// first t1 src
  27.126 +	add src1 = 3*8, in1			// first t3 src
  27.127 +	add dst0 = 8, in0			// first t1 dst
  27.128 +	add dst1 = 3*8, in0			// first t3 dst
  27.129 +	mov t1 = (PAGE_SIZE/128) - (2*PREFETCH_DIST) - 1
  27.130 +	nop.m 0
  27.131 +	nop.i 0
  27.132 +	;;
  27.133 +	// same as .line_copy loop, but with all predicated-off instructions removed:
  27.134 +.prefetch_loop:
  27.135 +(p[A])	ld8 v[A] = [src_pre_mem], 128		// M0
  27.136 +(p[B])	st8 [dst_pre_mem] = v[B], 128		// M2
  27.137 +	br.ctop.sptk .prefetch_loop
  27.138 +	;;
  27.139 +	cmp.eq p16, p0 = r0, r0			// reset p16 to 1 (br.ctop cleared it to zero)
  27.140 +	mov ar.lc = t1				// with 64KB pages, t1 is too big to fit in 8 bits!
  27.141 +	mov ar.ec = N				// # of stages in pipeline
  27.142 +	;;
  27.143 +.line_copy:
  27.144 +(p[D])	ld8 t2 = [src0], 3*8			// M0
  27.145 +(p[D])	ld8 t4 = [src1], 3*8			// M1
  27.146 +(p[B])	st8 [dst_pre_mem] = v[B], 128		// M2 prefetch dst from memory
  27.147 +(p[D])	st8 [dst_pre_l2] = n[D-C], 128		// M3 prefetch dst from L2
  27.148 +	;;
  27.149 +(p[A])	ld8 v[A] = [src_pre_mem], 128		// M0 prefetch src from memory
  27.150 +(p[C])	ld8 n[0] = [src_pre_l2], 128		// M1 prefetch src from L2
  27.151 +(p[D])	st8 [dst0] =  t1, 8			// M2
  27.152 +(p[D])	st8 [dst1] =  t3, 8			// M3
  27.153 +	;;
  27.154 +(p[D])	ld8  t5 = [src0], 8
  27.155 +(p[D])	ld8  t7 = [src1], 3*8
  27.156 +(p[D])	st8 [dst0] =  t2, 3*8
  27.157 +(p[D])	st8 [dst1] =  t4, 3*8
  27.158 +	;;
  27.159 +(p[D])	ld8  t6 = [src0], 3*8
  27.160 +(p[D])	ld8 t10 = [src1], 8
  27.161 +(p[D])	st8 [dst0] =  t5, 8
  27.162 +(p[D])	st8 [dst1] =  t7, 3*8
  27.163 +	;;
  27.164 +(p[D])	ld8  t9 = [src0], 3*8
  27.165 +(p[D])	ld8 t11 = [src1], 3*8
  27.166 +(p[D])	st8 [dst0] =  t6, 3*8
  27.167 +(p[D])	st8 [dst1] = t10, 8
  27.168 +	;;
  27.169 +(p[D])	ld8 t12 = [src0], 8
  27.170 +(p[D])	ld8 t14 = [src1], 8
  27.171 +(p[D])	st8 [dst0] =  t9, 3*8
  27.172 +(p[D])	st8 [dst1] = t11, 3*8
  27.173 +	;;
  27.174 +(p[D])	ld8 t13 = [src0], 4*8
  27.175 +(p[D])	ld8 t15 = [src1], 4*8
  27.176 +(p[D])	st8 [dst0] = t12, 8
  27.177 +(p[D])	st8 [dst1] = t14, 8
  27.178 +	;;
  27.179 +(p[D-1])ld8  t1 = [src0], 8
  27.180 +(p[D-1])ld8  t3 = [src1], 8
  27.181 +(p[D])	st8 [dst0] = t13, 4*8
  27.182 +(p[D])	st8 [dst1] = t15, 4*8
  27.183 +	br.ctop.sptk .line_copy
  27.184 +	;;
  27.185 +	mov ar.lc = saved_lc
  27.186 +	mov pr = saved_pr, -1
  27.187 +	br.ret.sptk.many rp
  27.188 +END(copy_page)
    28.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    28.2 +++ b/xen/arch/ia64/linux/lib/copy_user.S	Mon Aug 08 12:21:23 2005 -0700
    28.3 @@ -0,0 +1,610 @@
    28.4 +/*
    28.5 + *
    28.6 + * Optimized version of the copy_user() routine.
    28.7 + * It is used to copy date across the kernel/user boundary.
    28.8 + *
    28.9 + * The source and destination are always on opposite side of
   28.10 + * the boundary. When reading from user space we must catch
   28.11 + * faults on loads. When writing to user space we must catch
   28.12 + * errors on stores. Note that because of the nature of the copy
   28.13 + * we don't need to worry about overlapping regions.
   28.14 + *
   28.15 + *
   28.16 + * Inputs:
   28.17 + *	in0	address of source buffer
   28.18 + *	in1	address of destination buffer
   28.19 + *	in2	number of bytes to copy
   28.20 + *
   28.21 + * Outputs:
   28.22 + *	ret0	0 in case of success. The number of bytes NOT copied in
   28.23 + *		case of error.
   28.24 + *
   28.25 + * Copyright (C) 2000-2001 Hewlett-Packard Co
   28.26 + *	Stephane Eranian <eranian@hpl.hp.com>
   28.27 + *
   28.28 + * Fixme:
   28.29 + *	- handle the case where we have more than 16 bytes and the alignment
   28.30 + *	  are different.
   28.31 + *	- more benchmarking
   28.32 + *	- fix extraneous stop bit introduced by the EX() macro.
   28.33 + */
   28.34 +
   28.35 +#include <asm/asmmacro.h>
   28.36 +
   28.37 +//
   28.38 +// Tuneable parameters
   28.39 +//
   28.40 +#define COPY_BREAK	16	// we do byte copy below (must be >=16)
   28.41 +#define PIPE_DEPTH	21	// pipe depth
   28.42 +
   28.43 +#define EPI		p[PIPE_DEPTH-1]
   28.44 +
   28.45 +//
   28.46 +// arguments
   28.47 +//
   28.48 +#define dst		in0
   28.49 +#define src		in1
   28.50 +#define len		in2
   28.51 +
   28.52 +//
   28.53 +// local registers
   28.54 +//
   28.55 +#define t1		r2	// rshift in bytes
   28.56 +#define t2		r3	// lshift in bytes
   28.57 +#define rshift		r14	// right shift in bits
   28.58 +#define lshift		r15	// left shift in bits
   28.59 +#define word1		r16
   28.60 +#define word2		r17
   28.61 +#define cnt		r18
   28.62 +#define len2		r19
   28.63 +#define saved_lc	r20
   28.64 +#define saved_pr	r21
   28.65 +#define tmp		r22
   28.66 +#define val		r23
   28.67 +#define src1		r24
   28.68 +#define dst1		r25
   28.69 +#define src2		r26
   28.70 +#define dst2		r27
   28.71 +#define len1		r28
   28.72 +#define enddst		r29
   28.73 +#define endsrc		r30
   28.74 +#define saved_pfs	r31
   28.75 +
   28.76 +GLOBAL_ENTRY(__copy_user)
   28.77 +	.prologue
   28.78 +	.save ar.pfs, saved_pfs
   28.79 +	alloc saved_pfs=ar.pfs,3,((2*PIPE_DEPTH+7)&~7),0,((2*PIPE_DEPTH+7)&~7)
   28.80 +
   28.81 +	.rotr val1[PIPE_DEPTH],val2[PIPE_DEPTH]
   28.82 +	.rotp p[PIPE_DEPTH]
   28.83 +
   28.84 +	adds len2=-1,len	// br.ctop is repeat/until
   28.85 +	mov ret0=r0
   28.86 +
   28.87 +	;;			// RAW of cfm when len=0
   28.88 +	cmp.eq p8,p0=r0,len	// check for zero length
   28.89 +	.save ar.lc, saved_lc
   28.90 +	mov saved_lc=ar.lc	// preserve ar.lc (slow)
   28.91 +(p8)	br.ret.spnt.many rp	// empty mempcy()
   28.92 +	;;
   28.93 +	add enddst=dst,len	// first byte after end of source
   28.94 +	add endsrc=src,len	// first byte after end of destination
   28.95 +	.save pr, saved_pr
   28.96 +	mov saved_pr=pr		// preserve predicates
   28.97 +
   28.98 +	.body
   28.99 +
  28.100 +	mov dst1=dst		// copy because of rotation
  28.101 +	mov ar.ec=PIPE_DEPTH
  28.102 +	mov pr.rot=1<<16	// p16=true all others are false
  28.103 +
  28.104 +	mov src1=src		// copy because of rotation
  28.105 +	mov ar.lc=len2		// initialize lc for small count
  28.106 +	cmp.lt p10,p7=COPY_BREAK,len	// if len > COPY_BREAK then long copy
  28.107 +
  28.108 +	xor tmp=src,dst		// same alignment test prepare
  28.109 +(p10)	br.cond.dptk .long_copy_user
  28.110 +	;;			// RAW pr.rot/p16 ?
  28.111 +	//
  28.112 +	// Now we do the byte by byte loop with software pipeline
  28.113 +	//
  28.114 +	// p7 is necessarily false by now
  28.115 +1:
  28.116 +	EX(.failure_in_pipe1,(p16) ld1 val1[0]=[src1],1)
  28.117 +	EX(.failure_out,(EPI) st1 [dst1]=val1[PIPE_DEPTH-1],1)
  28.118 +	br.ctop.dptk.few 1b
  28.119 +	;;
  28.120 +	mov ar.lc=saved_lc
  28.121 +	mov pr=saved_pr,0xffffffffffff0000
  28.122 +	mov ar.pfs=saved_pfs		// restore ar.ec
  28.123 +	br.ret.sptk.many rp		// end of short memcpy
  28.124 +
  28.125 +	//
  28.126 +	// Not 8-byte aligned
  28.127 +	//
  28.128 +.diff_align_copy_user:
  28.129 +	// At this point we know we have more than 16 bytes to copy
  28.130 +	// and also that src and dest do _not_ have the same alignment.
  28.131 +	and src2=0x7,src1				// src offset
  28.132 +	and dst2=0x7,dst1				// dst offset
  28.133 +	;;
  28.134 +	// The basic idea is that we copy byte-by-byte at the head so
  28.135 +	// that we can reach 8-byte alignment for both src1 and dst1.
  28.136 +	// Then copy the body using software pipelined 8-byte copy,
  28.137 +	// shifting the two back-to-back words right and left, then copy
  28.138 +	// the tail by copying byte-by-byte.
  28.139 +	//
  28.140 +	// Fault handling. If the byte-by-byte at the head fails on the
  28.141 +	// load, then restart and finish the pipleline by copying zeros
  28.142 +	// to the dst1. Then copy zeros for the rest of dst1.
  28.143 +	// If 8-byte software pipeline fails on the load, do the same as
  28.144 +	// failure_in3 does. If the byte-by-byte at the tail fails, it is
  28.145 +	// handled simply by failure_in_pipe1.
  28.146 +	//
  28.147 +	// The case p14 represents the source has more bytes in the
  28.148 +	// the first word (by the shifted part), whereas the p15 needs to
  28.149 +	// copy some bytes from the 2nd word of the source that has the
  28.150 +	// tail of the 1st of the destination.
  28.151 +	//
  28.152 +
  28.153 +	//
  28.154 +	// Optimization. If dst1 is 8-byte aligned (quite common), we don't need
  28.155 +	// to copy the head to dst1, to start 8-byte copy software pipeline.
  28.156 +	// We know src1 is not 8-byte aligned in this case.
  28.157 +	//
  28.158 +	cmp.eq p14,p15=r0,dst2
  28.159 +(p15)	br.cond.spnt 1f
  28.160 +	;;
  28.161 +	sub t1=8,src2
  28.162 +	mov t2=src2
  28.163 +	;;
  28.164 +	shl rshift=t2,3
  28.165 +	sub len1=len,t1					// set len1
  28.166 +	;;
  28.167 +	sub lshift=64,rshift
  28.168 +	;;
  28.169 +	br.cond.spnt .word_copy_user
  28.170 +	;;
  28.171 +1:
  28.172 +	cmp.leu	p14,p15=src2,dst2
  28.173 +	sub t1=dst2,src2
  28.174 +	;;
  28.175 +	.pred.rel "mutex", p14, p15
  28.176 +(p14)	sub word1=8,src2				// (8 - src offset)
  28.177 +(p15)	sub t1=r0,t1					// absolute value
  28.178 +(p15)	sub word1=8,dst2				// (8 - dst offset)
  28.179 +	;;
  28.180 +	// For the case p14, we don't need to copy the shifted part to
  28.181 +	// the 1st word of destination.
  28.182 +	sub t2=8,t1
  28.183 +(p14)	sub word1=word1,t1
  28.184 +	;;
  28.185 +	sub len1=len,word1				// resulting len
  28.186 +(p15)	shl rshift=t1,3					// in bits
  28.187 +(p14)	shl rshift=t2,3
  28.188 +	;;
  28.189 +(p14)	sub len1=len1,t1
  28.190 +	adds cnt=-1,word1
  28.191 +	;;
  28.192 +	sub lshift=64,rshift
  28.193 +	mov ar.ec=PIPE_DEPTH
  28.194 +	mov pr.rot=1<<16	// p16=true all others are false
  28.195 +	mov ar.lc=cnt
  28.196 +	;;
  28.197 +2:
  28.198 +	EX(.failure_in_pipe2,(p16) ld1 val1[0]=[src1],1)
  28.199 +	EX(.failure_out,(EPI) st1 [dst1]=val1[PIPE_DEPTH-1],1)
  28.200 +	br.ctop.dptk.few 2b
  28.201 +	;;
  28.202 +	clrrrb
  28.203 +	;;
  28.204 +.word_copy_user:
  28.205 +	cmp.gtu p9,p0=16,len1
  28.206 +(p9)	br.cond.spnt 4f			// if (16 > len1) skip 8-byte copy
  28.207 +	;;
  28.208 +	shr.u cnt=len1,3		// number of 64-bit words
  28.209 +	;;
  28.210 +	adds cnt=-1,cnt
  28.211 +	;;
  28.212 +	.pred.rel "mutex", p14, p15
  28.213 +(p14)	sub src1=src1,t2
  28.214 +(p15)	sub src1=src1,t1
  28.215 +	//
  28.216 +	// Now both src1 and dst1 point to an 8-byte aligned address. And
  28.217 +	// we have more than 8 bytes to copy.
  28.218 +	//
  28.219 +	mov ar.lc=cnt
  28.220 +	mov ar.ec=PIPE_DEPTH
  28.221 +	mov pr.rot=1<<16	// p16=true all others are false
  28.222 +	;;
  28.223 +3:
  28.224 +	//
  28.225 +	// The pipleline consists of 3 stages:
  28.226 +	// 1 (p16):	Load a word from src1
  28.227 +	// 2 (EPI_1):	Shift right pair, saving to tmp
  28.228 +	// 3 (EPI):	Store tmp to dst1
  28.229 +	//
  28.230 +	// To make it simple, use at least 2 (p16) loops to set up val1[n]
  28.231 +	// because we need 2 back-to-back val1[] to get tmp.
  28.232 +	// Note that this implies EPI_2 must be p18 or greater.
  28.233 +	//
  28.234 +
  28.235 +#define EPI_1		p[PIPE_DEPTH-2]
  28.236 +#define SWITCH(pred, shift)	cmp.eq pred,p0=shift,rshift
  28.237 +#define CASE(pred, shift)	\
  28.238 +	(pred)	br.cond.spnt .copy_user_bit##shift
  28.239 +#define BODY(rshift)						\
  28.240 +.copy_user_bit##rshift:						\
  28.241 +1:								\
  28.242 +	EX(.failure_out,(EPI) st8 [dst1]=tmp,8);		\
  28.243 +(EPI_1) shrp tmp=val1[PIPE_DEPTH-2],val1[PIPE_DEPTH-1],rshift;	\
  28.244 +	EX(3f,(p16) ld8 val1[1]=[src1],8);			\
  28.245 +(p16)	mov val1[0]=r0;						\
  28.246 +	br.ctop.dptk 1b;					\
  28.247 +	;;							\
  28.248 +	br.cond.sptk.many .diff_align_do_tail;			\
  28.249 +2:								\
  28.250 +(EPI)	st8 [dst1]=tmp,8;					\
  28.251 +(EPI_1)	shrp tmp=val1[PIPE_DEPTH-2],val1[PIPE_DEPTH-1],rshift;	\
  28.252 +3:								\
  28.253 +(p16)	mov val1[1]=r0;						\
  28.254 +(p16)	mov val1[0]=r0;						\
  28.255 +	br.ctop.dptk 2b;					\
  28.256 +	;;							\
  28.257 +	br.cond.sptk.many .failure_in2
  28.258 +
  28.259 +	//
  28.260 +	// Since the instruction 'shrp' requires a fixed 128-bit value
  28.261 +	// specifying the bits to shift, we need to provide 7 cases
  28.262 +	// below.
  28.263 +	//
  28.264 +	SWITCH(p6, 8)
  28.265 +	SWITCH(p7, 16)
  28.266 +	SWITCH(p8, 24)
  28.267 +	SWITCH(p9, 32)
  28.268 +	SWITCH(p10, 40)
  28.269 +	SWITCH(p11, 48)
  28.270 +	SWITCH(p12, 56)
  28.271 +	;;
  28.272 +	CASE(p6, 8)
  28.273 +	CASE(p7, 16)
  28.274 +	CASE(p8, 24)
  28.275 +	CASE(p9, 32)
  28.276 +	CASE(p10, 40)
  28.277 +	CASE(p11, 48)
  28.278 +	CASE(p12, 56)
  28.279 +	;;
  28.280 +	BODY(8)
  28.281 +	BODY(16)
  28.282 +	BODY(24)
  28.283 +	BODY(32)
  28.284 +	BODY(40)
  28.285 +	BODY(48)
  28.286 +	BODY(56)
  28.287 +	;;
  28.288 +.diff_align_do_tail:
  28.289 +	.pred.rel "mutex", p14, p15
  28.290 +(p14)	sub src1=src1,t1
  28.291 +(p14)	adds dst1=-8,dst1
  28.292 +(p15)	sub dst1=dst1,t1
  28.293 +	;;
  28.294 +4:
  28.295 +	// Tail correction.
  28.296 +	//
  28.297 +	// The problem with this piplelined loop is that the last word is not
  28.298 +	// loaded and thus parf of the last word written is not correct.
  28.299 +	// To fix that, we simply copy the tail byte by byte.
  28.300 +
  28.301 +	sub len1=endsrc,src1,1
  28.302 +	clrrrb
  28.303 +	;;
  28.304 +	mov ar.ec=PIPE_DEPTH
  28.305 +	mov pr.rot=1<<16	// p16=true all others are false
  28.306 +	mov ar.lc=len1
  28.307 +	;;
  28.308 +5:
  28.309 +	EX(.failure_in_pipe1,(p16) ld1 val1[0]=[src1],1)
  28.310 +	EX(.failure_out,(EPI) st1 [dst1]=val1[PIPE_DEPTH-1],1)
  28.311 +	br.ctop.dptk.few 5b
  28.312 +	;;
  28.313 +	mov ar.lc=saved_lc
  28.314 +	mov pr=saved_pr,0xffffffffffff0000
  28.315 +	mov ar.pfs=saved_pfs
  28.316 +	br.ret.sptk.many rp
  28.317 +
  28.318 +	//
  28.319 +	// Beginning of long mempcy (i.e. > 16 bytes)
  28.320 +	//
  28.321 +.long_copy_user:
  28.322 +	tbit.nz p6,p7=src1,0	// odd alignment
  28.323 +	and tmp=7,tmp
  28.324 +	;;
  28.325 +	cmp.eq p10,p8=r0,tmp
  28.326 +	mov len1=len		// copy because of rotation
  28.327 +(p8)	br.cond.dpnt .diff_align_copy_user
  28.328 +	;;
  28.329 +	// At this point we know we have more than 16 bytes to copy
  28.330 +	// and also that both src and dest have the same alignment
  28.331 +	// which may not be the one we want. So for now we must move
  28.332 +	// forward slowly until we reach 16byte alignment: no need to
  28.333 +	// worry about reaching the end of buffer.
  28.334 +	//
  28.335 +	EX(.failure_in1,(p6) ld1 val1[0]=[src1],1)	// 1-byte aligned
  28.336 +(p6)	adds len1=-1,len1;;
  28.337 +	tbit.nz p7,p0=src1,1
  28.338 +	;;
  28.339 +	EX(.failure_in1,(p7) ld2 val1[1]=[src1],2)	// 2-byte aligned
  28.340 +(p7)	adds len1=-2,len1;;
  28.341 +	tbit.nz p8,p0=src1,2
  28.342 +	;;
  28.343 +	//
  28.344 +	// Stop bit not required after ld4 because if we fail on ld4
  28.345 +	// we have never executed the ld1, therefore st1 is not executed.
  28.346 +	//
  28.347 +	EX(.failure_in1,(p8) ld4 val2[0]=[src1],4)	// 4-byte aligned
  28.348 +	;;
  28.349 +	EX(.failure_out,(p6) st1 [dst1]=val1[0],1)
  28.350 +	tbit.nz p9,p0=src1,3
  28.351 +	;;
  28.352 +	//
  28.353 +	// Stop bit not required after ld8 because if we fail on ld8
  28.354 +	// we have never executed the ld2, therefore st2 is not executed.
  28.355 +	//
  28.356 +	EX(.failure_in1,(p9) ld8 val2[1]=[src1],8)	// 8-byte aligned
  28.357 +	EX(.failure_out,(p7) st2 [dst1]=val1[1],2)
  28.358 +(p8)	adds len1=-4,len1
  28.359 +	;;
  28.360 +	EX(.failure_out, (p8) st4 [dst1]=val2[0],4)
  28.361 +(p9)	adds len1=-8,len1;;
  28.362 +	shr.u cnt=len1,4		// number of 128-bit (2x64bit) words
  28.363 +	;;
  28.364 +	EX(.failure_out, (p9) st8 [dst1]=val2[1],8)
  28.365 +	tbit.nz p6,p0=len1,3
  28.366 +	cmp.eq p7,p0=r0,cnt
  28.367 +	adds tmp=-1,cnt			// br.ctop is repeat/until
  28.368 +(p7)	br.cond.dpnt .dotail		// we have less than 16 bytes left
  28.369 +	;;
  28.370 +	adds src2=8,src1
  28.371 +	adds dst2=8,dst1
  28.372 +	mov ar.lc=tmp
  28.373 +	;;
  28.374 +	//
  28.375 +	// 16bytes/iteration
  28.376 +	//
  28.377 +2:
  28.378 +	EX(.failure_in3,(p16) ld8 val1[0]=[src1],16)
  28.379 +(p16)	ld8 val2[0]=[src2],16
  28.380 +
  28.381 +	EX(.failure_out, (EPI)	st8 [dst1]=val1[PIPE_DEPTH-1],16)
  28.382 +(EPI)	st8 [dst2]=val2[PIPE_DEPTH-1],16
  28.383 +	br.ctop.dptk 2b
  28.384 +	;;			// RAW on src1 when fall through from loop
  28.385 +	//
  28.386 +	// Tail correction based on len only
  28.387 +	//
  28.388 +	// No matter where we come from (loop or test) the src1 pointer
  28.389 +	// is 16 byte aligned AND we have less than 16 bytes to copy.
  28.390 +	//
  28.391 +.dotail:
  28.392 +	EX(.failure_in1,(p6) ld8 val1[0]=[src1],8)	// at least 8 bytes
  28.393 +	tbit.nz p7,p0=len1,2
  28.394 +	;;
  28.395 +	EX(.failure_in1,(p7) ld4 val1[1]=[src1],4)	// at least 4 bytes
  28.396 +	tbit.nz p8,p0=len1,1
  28.397 +	;;
  28.398 +	EX(.failure_in1,(p8) ld2 val2[0]=[src1],2)	// at least 2 bytes
  28.399 +	tbit.nz p9,p0=len1,0
  28.400 +	;;
  28.401 +	EX(.failure_out, (p6) st8 [dst1]=val1[0],8)
  28.402 +	;;
  28.403 +	EX(.failure_in1,(p9) ld1 val2[1]=[src1])	// only 1 byte left
  28.404 +	mov ar.lc=saved_lc
  28.405 +	;;
  28.406 +	EX(.failure_out,(p7) st4 [dst1]=val1[1],4)
  28.407 +	mov pr=saved_pr,0xffffffffffff0000
  28.408 +	;;
  28.409 +	EX(.failure_out, (p8)	st2 [dst1]=val2[0],2)
  28.410 +	mov ar.pfs=saved_pfs
  28.411 +	;;
  28.412 +	EX(.failure_out, (p9)	st1 [dst1]=val2[1])
  28.413 +	br.ret.sptk.many rp
  28.414 +
  28.415 +
  28.416 +	//
  28.417 +	// Here we handle the case where the byte by byte copy fails
  28.418 +	// on the load.
  28.419 +	// Several factors make the zeroing of the rest of the buffer kind of
  28.420 +	// tricky:
  28.421 +	//	- the pipeline: loads/stores are not in sync (pipeline)
  28.422 +	//
  28.423 +	//	  In the same loop iteration, the dst1 pointer does not directly
  28.424 +	//	  reflect where the faulty load was.
  28.425 +	//
  28.426 +	//	- pipeline effect
  28.427 +	//	  When you get a fault on load, you may have valid data from
  28.428 +	//	  previous loads not yet store in transit. Such data must be
  28.429 +	//	  store normally before moving onto zeroing the rest.
  28.430 +	//
  28.431 +	//	- single/multi dispersal independence.
  28.432 +	//
  28.433 +	// solution:
  28.434 +	//	- we don't disrupt the pipeline, i.e. data in transit in
  28.435 +	//	  the software pipeline will be eventually move to memory.
  28.436 +	//	  We simply replace the load with a simple mov and keep the
  28.437 +	//	  pipeline going. We can't really do this inline because
  28.438 +	//	  p16 is always reset to 1 when lc > 0.
  28.439 +	//
  28.440 +.failure_in_pipe1:
  28.441 +	sub ret0=endsrc,src1	// number of bytes to zero, i.e. not copied
  28.442 +1:
  28.443 +(p16)	mov val1[0]=r0
  28.444 +(EPI)	st1 [dst1]=val1[PIPE_DEPTH-1],1
  28.445 +	br.ctop.dptk 1b
  28.446 +	;;
  28.447 +	mov pr=saved_pr,0xffffffffffff0000
  28.448 +	mov ar.lc=saved_lc
  28.449 +	mov ar.pfs=saved_pfs
  28.450 +	br.ret.sptk.many rp
  28.451 +
  28.452 +	//
  28.453 +	// This is the case where the byte by byte copy fails on the load
  28.454 +	// when we copy the head. We need to finish the pipeline and copy
  28.455 +	// zeros for the rest of the destination. Since this happens
  28.456 +	// at the top we still need to fill the body and tail.
  28.457 +.failure_in_pipe2:
  28.458 +	sub ret0=endsrc,src1	// number of bytes to zero, i.e. not copied
  28.459 +2:
  28.460 +(p16)	mov val1[0]=r0
  28.461 +(EPI)	st1 [dst1]=val1[PIPE_DEPTH-1],1
  28.462 +	br.ctop.dptk 2b
  28.463 +	;;
  28.464 +	sub len=enddst,dst1,1		// precompute len
  28.465 +	br.cond.dptk.many .failure_in1bis
  28.466 +	;;
  28.467 +
  28.468 +	//
  28.469 +	// Here we handle the head & tail part when we check for alignment.
  28.470 +	// The following code handles only the load failures. The
  28.471 +	// main diffculty comes from the fact that loads/stores are
  28.472 +	// scheduled. So when you fail on a load, the stores corresponding
  28.473 +	// to previous successful loads must be executed.
  28.474 +	//
  28.475 +	// However some simplifications are possible given the way
  28.476 +	// things work.
  28.477 +	//
  28.478 +	// 1) HEAD
  28.479 +	// Theory of operation:
  28.480 +	//
  28.481 +	//  Page A   | Page B
  28.482 +	//  ---------|-----
  28.483 +	//          1|8 x
  28.484 +	//	  1 2|8 x
  28.485 +	//	    4|8 x
  28.486 +	//	  1 4|8 x
  28.487 +	//        2 4|8 x
  28.488 +	//      1 2 4|8 x
  28.489 +	//	     |1
  28.490 +	//	     |2 x
  28.491 +	//	     |4 x
  28.492 +	//
  28.493 +	// page_size >= 4k (2^12).  (x means 4, 2, 1)
  28.494 +	// Here we suppose Page A exists and Page B does not.
  28.495 +	//
  28.496 +	// As we move towards eight byte alignment we may encounter faults.
  28.497 +	// The numbers on each page show the size of the load (current alignment).
  28.498 +	//
  28.499 +	// Key point:
  28.500 +	//	- if you fail on 1, 2, 4 then you have never executed any smaller
  28.501 +	//	  size loads, e.g. failing ld4 means no ld1 nor ld2 executed
  28.502 +	//	  before.
  28.503 +	//
  28.504 +	// This allows us to simplify the cleanup code, because basically you
  28.505 +	// only have to worry about "pending" stores in the case of a failing
  28.506 +	// ld8(). Given the way the code is written today, this means only
  28.507 +	// worry about st2, st4. There we can use the information encapsulated
  28.508 +	// into the predicates.
  28.509 +	//
  28.510 +	// Other key point:
  28.511 +	//	- if you fail on the ld8 in the head, it means you went straight
  28.512 +	//	  to it, i.e. 8byte alignment within an unexisting page.
  28.513 +	// Again this comes from the fact that if you crossed just for the ld8 then
  28.514 +	// you are 8byte aligned but also 16byte align, therefore you would
  28.515 +	// either go for the 16byte copy loop OR the ld8 in the tail part.
  28.516 +	// The combination ld1, ld2, ld4, ld8 where you fail on ld8 is impossible
  28.517 +	// because it would mean you had 15bytes to copy in which case you
  28.518 +	// would have defaulted to the byte by byte copy.
  28.519 +	//
  28.520 +	//
  28.521 +	// 2) TAIL
  28.522 +	// Here we now we have less than 16 bytes AND we are either 8 or 16 byte
  28.523 +	// aligned.
  28.524 +	//
  28.525 +	// Key point:
  28.526 +	// This means that we either:
  28.527 +	//		- are right on a page boundary
  28.528 +	//	OR
  28.529 +	//		- are at more than 16 bytes from a page boundary with
  28.530 +	//		  at most 15 bytes to copy: no chance of crossing.
  28.531 +	//
  28.532 +	// This allows us to assume that if we fail on a load we haven't possibly
  28.533 +	// executed any of the previous (tail) ones, so we don't need to do
  28.534 +	// any stores. For instance, if we fail on ld2, this means we had
  28.535 +	// 2 or 3 bytes left to copy and we did not execute the ld8 nor ld4.
  28.536 +	//
  28.537 +	// This means that we are in a situation similar the a fault in the
  28.538 +	// head part. That's nice!
  28.539 +	//
  28.540 +.failure_in1:
  28.541 +	sub ret0=endsrc,src1	// number of bytes to zero, i.e. not copied
  28.542 +	sub len=endsrc,src1,1
  28.543 +	//
  28.544 +	// we know that ret0 can never be zero at this point
  28.545 +	// because we failed why trying to do a load, i.e. there is still
  28.546 +	// some work to do.
  28.547 +	// The failure_in1bis and length problem is taken care of at the
  28.548 +	// calling side.
  28.549 +	//
  28.550 +	;;
  28.551 +.failure_in1bis:		// from (.failure_in3)
  28.552 +	mov ar.lc=len		// Continue with a stupid byte store.
  28.553 +	;;
  28.554 +5:
  28.555 +	st1 [dst1]=r0,1
  28.556 +	br.cloop.dptk 5b
  28.557 +	;;
  28.558 +	mov pr=saved_pr,0xffffffffffff0000
  28.559 +	mov ar.lc=saved_lc
  28.560 +	mov ar.pfs=saved_pfs
  28.561 +	br.ret.sptk.many rp
  28.562 +
  28.563 +	//
  28.564 +	// Here we simply restart the loop but instead
  28.565 +	// of doing loads we fill the pipeline with zeroes
  28.566 +	// We can't simply store r0 because we may have valid
  28.567 +	// data in transit in the pipeline.
  28.568 +	// ar.lc and ar.ec are setup correctly at this point
  28.569 +	//
  28.570 +	// we MUST use src1/endsrc here and not dst1/enddst because
  28.571 +	// of the pipeline effect.
  28.572 +	//
  28.573 +.failure_in3:
  28.574 +	sub ret0=endsrc,src1	// number of bytes to zero, i.e. not copied
  28.575 +	;;
  28.576 +2:
  28.577 +(p16)	mov val1[0]=r0
  28.578 +(p16)	mov val2[0]=r0
  28.579 +(EPI)	st8 [dst1]=val1[PIPE_DEPTH-1],16
  28.580 +(EPI)	st8 [dst2]=val2[PIPE_DEPTH-1],16
  28.581 +	br.ctop.dptk 2b
  28.582 +	;;
  28.583 +	cmp.ne p6,p0=dst1,enddst	// Do we need to finish the tail ?
  28.584 +	sub len=enddst,dst1,1		// precompute len
  28.585 +(p6)	br.cond.dptk .failure_in1bis
  28.586 +	;;
  28.587 +	mov pr=saved_pr,0xffffffffffff0000
  28.588 +	mov ar.lc=saved_lc
  28.589 +	mov ar.pfs=saved_pfs
  28.590 +	br.ret.sptk.many rp
  28.591 +
  28.592 +.failure_in2:
  28.593 +	sub ret0=endsrc,src1
  28.594 +	cmp.ne p6,p0=dst1,enddst	// Do we need to finish the tail ?
  28.595 +	sub len=enddst,dst1,1		// precompute len
  28.596 +(p6)	br.cond.dptk .failure_in1bis
  28.597 +	;;
  28.598 +	mov pr=saved_pr,0xffffffffffff0000
  28.599 +	mov ar.lc=saved_lc
  28.600 +	mov ar.pfs=saved_pfs
  28.601 +	br.ret.sptk.many rp
  28.602 +
  28.603 +	//
  28.604 +	// handling of failures on stores: that's the easy part
  28.605 +	//
  28.606 +.failure_out:
  28.607 +	sub ret0=enddst,dst1
  28.608 +	mov pr=saved_pr,0xffffffffffff0000
  28.609 +	mov ar.lc=saved_lc
  28.610 +
  28.611 +	mov ar.pfs=saved_pfs
  28.612 +	br.ret.sptk.many rp
  28.613 +END(__copy_user)
    29.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    29.2 +++ b/xen/arch/ia64/linux/lib/csum_partial_copy.c	Mon Aug 08 12:21:23 2005 -0700
    29.3 @@ -0,0 +1,151 @@
    29.4 +/*
    29.5 + * Network Checksum & Copy routine
    29.6 + *
    29.7 + * Copyright (C) 1999, 2003-2004 Hewlett-Packard Co
    29.8 + *	Stephane Eranian <eranian@hpl.hp.com>
    29.9 + *
   29.10 + * Most of the code has been imported from Linux/Alpha
   29.11 + */
   29.12 +
   29.13 +#include <linux/module.h>
   29.14 +#include <linux/types.h>
   29.15 +#include <linux/string.h>
   29.16 +
   29.17 +#include <asm/uaccess.h>
   29.18 +
   29.19 +/*
   29.20 + * XXX Fixme: those 2 inlines are meant for debugging and will go away
   29.21 + */
   29.22 +static inline unsigned
   29.23 +short from64to16(unsigned long x)
   29.24 +{
   29.25 +	/* add up 32-bit words for 33 bits */
   29.26 +	x = (x & 0xffffffff) + (x >> 32);
   29.27 +	/* add up 16-bit and 17-bit words for 17+c bits */
   29.28 +	x = (x & 0xffff) + (x >> 16);
   29.29 +	/* add up 16-bit and 2-bit for 16+c bit */
   29.30 +	x = (x & 0xffff) + (x >> 16);
   29.31 +	/* add up carry.. */
   29.32 +	x = (x & 0xffff) + (x >> 16);
   29.33 +	return x;
   29.34 +}
   29.35 +
   29.36 +static inline
   29.37 +unsigned long do_csum_c(const unsigned char * buff, int len, unsigned int psum)
   29.38 +{
   29.39 +	int odd, count;
   29.40 +	unsigned long result = (unsigned long)psum;
   29.41 +
   29.42 +	if (len <= 0)
   29.43 +		goto out;
   29.44 +	odd = 1 & (unsigned long) buff;
   29.45 +	if (odd) {
   29.46 +		result = *buff << 8;
   29.47 +		len--;
   29.48 +		buff++;
   29.49 +	}
   29.50 +	count = len >> 1;		/* nr of 16-bit words.. */
   29.51 +	if (count) {
   29.52 +		if (2 & (unsigned long) buff) {
   29.53 +			result += *(unsigned short *) buff;
   29.54 +			count--;
   29.55 +			len -= 2;
   29.56 +			buff += 2;
   29.57 +		}
   29.58 +		count >>= 1;		/* nr of 32-bit words.. */
   29.59 +		if (count) {
   29.60 +			if (4 & (unsigned long) buff) {
   29.61 +				result += *(unsigned int *) buff;
   29.62 +				count--;
   29.63 +				len -= 4;
   29.64 +				buff += 4;
   29.65 +			}
   29.66 +			count >>= 1;	/* nr of 64-bit words.. */
   29.67 +			if (count) {
   29.68 +				unsigned long carry = 0;
   29.69 +				do {
   29.70 +					unsigned long w = *(unsigned long *) buff;
   29.71 +					count--;
   29.72 +					buff += 8;
   29.73 +					result += carry;
   29.74 +					result += w;
   29.75 +					carry = (w > result);
   29.76 +				} while (count);
   29.77 +				result += carry;
   29.78 +				result = (result & 0xffffffff) + (result >> 32);
   29.79 +			}
   29.80 +			if (len & 4) {
   29.81 +				result += *(unsigned int *) buff;
   29.82 +				buff += 4;
   29.83 +			}
   29.84 +		}
   29.85 +		if (len & 2) {
   29.86 +			result += *(unsigned short *) buff;
   29.87 +			buff += 2;
   29.88 +		}
   29.89 +	}
   29.90 +	if (len & 1)
   29.91 +		result += *buff;
   29.92 +
   29.93 +	result = from64to16(result);
   29.94 +
   29.95 +	if (odd)
   29.96 +		result = ((result >> 8) & 0xff) | ((result & 0xff) << 8);
   29.97 +
   29.98 +out:
   29.99 +	return result;
  29.100 +}
  29.101 +
  29.102 +/*
  29.103 + * XXX Fixme
  29.104 + *
  29.105 + * This is very ugly but temporary. THIS NEEDS SERIOUS ENHANCEMENTS.
  29.106 + * But it's very tricky to get right even in C.
  29.107 + */
  29.108 +extern unsigned long do_csum(const unsigned char *, long);
  29.109 +
  29.110 +static unsigned int
  29.111 +do_csum_partial_copy_from_user (const unsigned char __user *src, unsigned char *dst,
  29.112 +				int len, unsigned int psum, int *errp)
  29.113 +{
  29.114 +	unsigned long result;
  29.115 +
  29.116 +	/* XXX Fixme
  29.117 +	 * for now we separate the copy from checksum for obvious
  29.118 +	 * alignment difficulties. Look at the Alpha code and you'll be
  29.119 +	 * scared.
  29.120 +	 */
  29.121 +
  29.122 +	if (__copy_from_user(dst, src, len) != 0 && errp)
  29.123 +		*errp = -EFAULT;
  29.124 +
  29.125 +	result = do_csum(dst, len);
  29.126 +
  29.127 +	/* add in old sum, and carry.. */
  29.128 +	result += psum;
  29.129 +	/* 32+c bits -> 32 bits */
  29.130 +	result = (result & 0xffffffff) + (result >> 32);
  29.131 +	return result;
  29.132 +}
  29.133 +
  29.134 +unsigned int
  29.135 +csum_partial_copy_from_user (const unsigned char __user *src, unsigned char *dst,
  29.136 +			     int len, unsigned int sum, int *errp)
  29.137 +{
  29.138 +	if (!access_ok(VERIFY_READ, src, len)) {
  29.139 +		*errp = -EFAULT;
  29.140 +		memset(dst, 0, len);
  29.141 +		return sum;
  29.142 +	}
  29.143 +
  29.144 +	return do_csum_partial_copy_from_user(src, dst, len, sum, errp);
  29.145 +}
  29.146 +
  29.147 +unsigned int
  29.148 +csum_partial_copy_nocheck(const unsigned char __user *src, unsigned char *dst,
  29.149 +			  int len, unsigned int sum)
  29.150 +{
  29.151 +	return do_csum_partial_copy_from_user(src, dst, len, sum, NULL);
  29.152 +}
  29.153 +
  29.154 +EXPORT_SYMBOL(csum_partial_copy_nocheck);
    30.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    30.2 +++ b/xen/arch/ia64/linux/lib/dec_and_lock.c	Mon Aug 08 12:21:23 2005 -0700
    30.3 @@ -0,0 +1,42 @@
    30.4 +/*
    30.5 + * Copyright (C) 2003 Jerome Marchand, Bull S.A.
    30.6 + *	Cleaned up by David Mosberger-Tang <davidm@hpl.hp.com>
    30.7 + *
    30.8 + * This file is released under the GPLv2, or at your option any later version.
    30.9 + *
   30.10 + * ia64 version of "atomic_dec_and_lock()" using the atomic "cmpxchg" instruction.  This
   30.11 + * code is an adaptation of the x86 version of "atomic_dec_and_lock()".
   30.12 + */
   30.13 +
   30.14 +#include <linux/compiler.h>
   30.15 +#include <linux/module.h>
   30.16 +#include <linux/spinlock.h>
   30.17 +#include <asm/atomic.h>
   30.18 +
   30.19 +/*
   30.20 + * Decrement REFCOUNT and if the count reaches zero, acquire the spinlock.  Both of these
   30.21 + * operations have to be done atomically, so that the count doesn't drop to zero without
   30.22 + * acquiring the spinlock first.
   30.23 + */
   30.24 +int
   30.25 +_atomic_dec_and_lock (atomic_t *refcount, spinlock_t *lock)
   30.26 +{
   30.27 +	int old, new;
   30.28 +
   30.29 +	do {
   30.30 +		old = atomic_read(refcount);
   30.31 +		new = old - 1;
   30.32 +
   30.33 +		if (unlikely (old == 1)) {
   30.34 +			/* oops, we may be decrementing to zero, do it the slow way... */
   30.35 +			spin_lock(lock);
   30.36 +			if (atomic_dec_and_test(refcount))
   30.37 +				return 1;
   30.38 +			spin_unlock(lock);
   30.39 +			return 0;
   30.40 +		}
   30.41 +	} while (cmpxchg(&refcount->counter, old, new) != old);
   30.42 +	return 0;
   30.43 +}
   30.44 +
   30.45 +EXPORT_SYMBOL(_atomic_dec_and_lock);
    31.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    31.2 +++ b/xen/arch/ia64/linux/lib/do_csum.S	Mon Aug 08 12:21:23 2005 -0700
    31.3 @@ -0,0 +1,323 @@
    31.4 +/*
    31.5 + *
    31.6 + * Optmized version of the standard do_csum() function
    31.7 + *
    31.8 + * Return: a 64bit quantity containing the 16bit Internet checksum
    31.9 + *
   31.10 + * Inputs:
   31.11 + *	in0: address of buffer to checksum (char *)
   31.12 + *	in1: length of the buffer (int)
   31.13 + *
   31.14 + * Copyright (C) 1999, 2001-2002 Hewlett-Packard Co
   31.15 + *	Stephane Eranian <eranian@hpl.hp.com>
   31.16 + *
   31.17 + * 02/04/22	Ken Chen <kenneth.w.chen@intel.com>
   31.18 + *		Data locality study on the checksum buffer.
   31.19 + *		More optimization cleanup - remove excessive stop bits.
   31.20 + * 02/04/08	David Mosberger <davidm@hpl.hp.com>
   31.21 + *		More cleanup and tuning.
   31.22 + * 01/04/18	Jun Nakajima <jun.nakajima@intel.com>
   31.23 + *		Clean up and optimize and the software pipeline, loading two
   31.24 + *		back-to-back 8-byte words per loop. Clean up the initialization
   31.25 + *		for the loop. Support the cases where load latency = 1 or 2.
   31.26 + *		Set CONFIG_IA64_LOAD_LATENCY to 1 or 2 (default).
   31.27 + */
   31.28 +
   31.29 +#include <asm/asmmacro.h>
   31.30 +
   31.31 +//
   31.32 +// Theory of operations:
   31.33 +//	The goal is to go as quickly as possible to the point where
   31.34 +//	we can checksum 16 bytes/loop. Before reaching that point we must
   31.35 +//	take care of incorrect alignment of first byte.
   31.36 +//
   31.37 +//	The code hereafter also takes care of the "tail" part of the buffer
   31.38 +//	before entering the core loop, if any. The checksum is a sum so it
   31.39 +//	allows us to commute operations. So we do the "head" and "tail"
   31.40 +//	first to finish at full speed in the body. Once we get the head and
   31.41 +//	tail values, we feed them into the pipeline, very handy initialization.
   31.42 +//
   31.43 +//	Of course we deal with the special case where the whole buffer fits
   31.44 +//	into one 8 byte word. In this case we have only one entry in the pipeline.
   31.45 +//
   31.46 +//	We use a (LOAD_LATENCY+2)-stage pipeline in the loop to account for
   31.47 +//	possible load latency and also to accommodate for head and tail.
   31.48 +//
   31.49 +//	The end of the function deals with folding the checksum from 64bits
   31.50 +//	down to 16bits taking care of the carry.
   31.51 +//
   31.52 +//	This version avoids synchronization in the core loop by also using a
   31.53 +//	pipeline for the accumulation of the checksum in resultx[] (x=1,2).
   31.54 +//
   31.55 +//	 wordx[] (x=1,2)
   31.56 +//	|---|
   31.57 +//      |   | 0			: new value loaded in pipeline
   31.58 +//	|---|
   31.59 +//      |   | -			: in transit data
   31.60 +//	|---|
   31.61 +//      |   | LOAD_LATENCY	: current value to add to checksum
   31.62 +//	|---|
   31.63 +//      |   | LOAD_LATENCY+1	: previous value added to checksum
   31.64 +//      |---|			(previous iteration)
   31.65 +//
   31.66 +//	resultx[] (x=1,2)
   31.67 +//	|---|
   31.68 +//      |   | 0			: initial value
   31.69 +//	|---|
   31.70 +//      |   | LOAD_LATENCY-1	: new checksum
   31.71 +//	|---|
   31.72 +//      |   | LOAD_LATENCY	: previous value of checksum
   31.73 +//	|---|
   31.74 +//      |   | LOAD_LATENCY+1	: final checksum when out of the loop
   31.75 +//      |---|
   31.76 +//
   31.77 +//
   31.78 +//	See RFC1071 "Computing the Internet Checksum" for various techniques for
   31.79 +//	calculating the Internet checksum.
   31.80 +//
   31.81 +// NOT YET DONE:
   31.82 +//	- Maybe another algorithm which would take care of the folding at the
   31.83 +//	  end in a different manner
   31.84 +//	- Work with people more knowledgeable than me on the network stack
   31.85 +//	  to figure out if we could not split the function depending on the
   31.86 +//	  type of packet or alignment we get. Like the ip_fast_csum() routine
   31.87 +//	  where we know we have at least 20bytes worth of data to checksum.
   31.88 +//	- Do a better job of handling small packets.
   31.89 +//	- Note on prefetching: it was found that under various load, i.e. ftp read/write,
   31.90 +//	  nfs read/write, the L1 cache hit rate is at 60% and L2 cache hit rate is at 99.8%
   31.91 +//	  on the data that buffer points to (partly because the checksum is often preceded by
   31.92 +//	  a copy_from_user()).  This finding indiate that lfetch will not be beneficial since
   31.93 +//	  the data is already in the cache.
   31.94 +//
   31.95 +
   31.96 +#define saved_pfs	r11
   31.97 +#define hmask		r16
   31.98 +#define tmask		r17
   31.99 +#define first1		r18
  31.100 +#define firstval	r19
  31.101 +#define firstoff	r20
  31.102 +#define last		r21
  31.103 +#define lastval		r22
  31.104 +#define lastoff		r23
  31.105 +#define saved_lc	r24
  31.106 +#define saved_pr	r25
  31.107 +#define tmp1		r26
  31.108 +#define tmp2		r27
  31.109 +#define tmp3		r28
  31.110 +#define carry1		r29
  31.111 +#define carry2		r30
  31.112 +#define first2		r31
  31.113 +
  31.114 +#define buf		in0
  31.115 +#define len		in1
  31.116 +
  31.117 +#define LOAD_LATENCY	2	// XXX fix me
  31.118 +
  31.119 +#if (LOAD_LATENCY != 1) && (LOAD_LATENCY != 2)
  31.120 +# error "Only 1 or 2 is supported/tested for LOAD_LATENCY."
  31.121 +#endif
  31.122 +
  31.123 +#define PIPE_DEPTH			(LOAD_LATENCY+2)
  31.124 +#define ELD	p[LOAD_LATENCY]		// end of load
  31.125 +#define ELD_1	p[LOAD_LATENCY+1]	// and next stage
  31.126 +
  31.127 +// unsigned long do_csum(unsigned char *buf,long len)
  31.128 +
  31.129 +GLOBAL_ENTRY(do_csum)
  31.130 +	.prologue
  31.131 +	.save ar.pfs, saved_pfs
  31.132 +	alloc saved_pfs=ar.pfs,2,16,0,16
  31.133 +	.rotr word1[4], word2[4],result1[LOAD_LATENCY+2],result2[LOAD_LATENCY+2]
  31.134 +	.rotp p[PIPE_DEPTH], pC1[2], pC2[2]
  31.135 +	mov ret0=r0		// in case we have zero length
  31.136 +	cmp.lt p0,p6=r0,len	// check for zero length or negative (32bit len)
  31.137 +	;;
  31.138 +	add tmp1=buf,len	// last byte's address
  31.139 +	.save pr, saved_pr
  31.140 +	mov saved_pr=pr		// preserve predicates (rotation)
  31.141 +(p6)	br.ret.spnt.many rp	// return if zero or negative length
  31.142 +
  31.143 +	mov hmask=-1		// initialize head mask
  31.144 +	tbit.nz p15,p0=buf,0	// is buf an odd address?
  31.145 +	and first1=-8,buf	// 8-byte align down address of first1 element
  31.146 +
  31.147 +	and firstoff=7,buf	// how many bytes off for first1 element
  31.148 +	mov tmask=-1		// initialize tail mask
  31.149 +
  31.150 +	;;
  31.151 +	adds tmp2=-1,tmp1	// last-1
  31.152 +	and lastoff=7,tmp1	// how many bytes off for last element
  31.153 +	;;