ia64/xen-unstable

changeset 18096:1e7a371cee11

[IA64] Don't perform implicit sync when vps_save/restore

When calling vps_save/restore, pass 1 as the third parameter not to
perform implicit sync.

The third parameter of vps_save/restore is used to indidate whether
vps_save/restore do implicit vps_read_sync/vps_write_sync.
When the third parameter is 1, it doesn't perform implicit sync.
This parameter adds flexibility of vps_save/restore.
This feature was newly introduced by SDM specification update June 2008.

Signed-off-by: Anthony Xu <anthony.xu@intel.com>
author Isaku Yamahata <yamahata@valinux.co.jp>
date Wed Jul 23 11:21:47 2008 +0900 (2008-07-23)
parents 2fd648307ad1
children 1970781956c7
files xen/arch/ia64/vmx/vmx_init.c
line diff
     1.1 --- a/xen/arch/ia64/vmx/vmx_init.c	Tue Jul 22 12:15:02 2008 +0900
     1.2 +++ b/xen/arch/ia64/vmx/vmx_init.c	Wed Jul 23 11:21:47 2008 +0900
     1.3 @@ -335,7 +335,7 @@ vmx_save_state(struct vcpu *v)
     1.4  {
     1.5  	BUG_ON(v != current);
     1.6  	
     1.7 -	ia64_call_vsa(PAL_VPS_SAVE, (u64)v->arch.privregs, 0, 0, 0, 0, 0, 0);
     1.8 +	ia64_call_vsa(PAL_VPS_SAVE, (u64)v->arch.privregs, 1, 0, 0, 0, 0, 0);
     1.9  
    1.10  	/* Need to save KR when domain switch, though HV itself doesn;t
    1.11  	 * use them.
    1.12 @@ -359,7 +359,7 @@ vmx_load_state(struct vcpu *v)
    1.13  	vmx_load_all_rr(v);
    1.14  
    1.15  	/* vmx_load_all_rr() pins down v->arch.privregs with both dtr/itr*/
    1.16 -	ia64_call_vsa(PAL_VPS_RESTORE, (u64)v->arch.privregs, 0, 0, 0, 0, 0, 0);
    1.17 +	ia64_call_vsa(PAL_VPS_RESTORE, (u64)v->arch.privregs, 1, 0, 0, 0, 0, 0);
    1.18  
    1.19  	ia64_set_kr(0, v->arch.arch_vmx.vkr[0]);
    1.20  	ia64_set_kr(1, v->arch.arch_vmx.vkr[1]);