ia64/xen-unstable

changeset 13436:1d72428a0fab

[IA64] Remove dorfirfi completely

Signed-off-by: Anthony Xu <anthony.xu@intel.com>
author awilliam@xenbuild2.aw
date Tue Jan 16 11:48:43 2007 -0700 (2007-01-16)
parents 24ce556e3049
children 7a2c224a9252
files xen/arch/ia64/xen/faults.c xen/arch/ia64/xen/hyperprivop.S xen/arch/ia64/xen/vcpu.c xen/arch/ia64/xen/xenasm.S xen/include/asm-ia64/vcpu.h
line diff
     1.1 --- a/xen/arch/ia64/xen/faults.c	Tue Jan 16 11:22:44 2007 -0700
     1.2 +++ b/xen/arch/ia64/xen/faults.c	Tue Jan 16 11:48:43 2007 -0700
     1.3 @@ -136,11 +136,6 @@ void reflect_event(void)
     1.4  
     1.5  	regs = vcpu_regs(v);
     1.6  
     1.7 -	// can't inject event, when XEN is emulating rfi 
     1.8 -	// and both PSCB(v, ifs) and regs->ifs are valid
     1.9 -	if (regs->cr_iip == *(unsigned long *)dorfirfi)
    1.10 -		return;
    1.11 -
    1.12  	isr = regs->cr_ipsr & IA64_PSR_RI;
    1.13  
    1.14  	if (!PSCB(v, interrupt_collection_enabled))
     2.1 --- a/xen/arch/ia64/xen/hyperprivop.S	Tue Jan 16 11:22:44 2007 -0700
     2.2 +++ b/xen/arch/ia64/xen/hyperprivop.S	Tue Jan 16 11:48:43 2007 -0700
     2.3 @@ -81,9 +81,6 @@
     2.4  //	r19 == vpsr.ic
     2.5  //	r31 == pr
     2.6  GLOBAL_ENTRY(fast_hyperprivop)
     2.7 -#ifndef FAST_HYPERPRIVOPS // see beginning of file
     2.8 -	br.sptk.many dispatch_break_fault ;;
     2.9 -#endif
    2.10  	// HYPERPRIVOP_SSM_I?
    2.11  	// assumes domain interrupts pending, so just do it
    2.12  	cmp.eq p7,p6=HYPERPRIVOP_SSM_I,r17
    2.13 @@ -102,7 +99,9 @@ GLOBAL_ENTRY(fast_hyperprivop)
    2.14  	cmp.eq p7,p6=HYPERPRIVOP_RFI,r17
    2.15  (p7)	br.sptk.many hyper_rfi
    2.16  	;;
    2.17 -
    2.18 +#ifndef FAST_HYPERPRIVOPS // see beginning of file
    2.19 +	br.sptk.many dispatch_break_fault ;;
    2.20 +#endif
    2.21  	// if event enabled and there are pending events
    2.22  	cmp.ne p7,p0=r20,r0
    2.23  	;;
    2.24 @@ -1010,10 +1009,22 @@ 1:	extr.u r25=r17,61,3;;
    2.25  #endif
    2.26  END(fast_tlb_miss_reflect)
    2.27  
    2.28 +ENTRY(slow_vcpu_rfi)
    2.29 +	adds r22=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18;;
    2.30 +	ld8 r22=[r22];;
    2.31 +	tbit.z p6,p0=r22,63
    2.32 +(p6)	br.spnt.few dispatch_break_fault ;;
    2.33 +	// if vips is valid, discard current register frame
    2.34 +	// don't need dorfirfi any more
    2.35 +	alloc r22=ar.pfs,0,0,0,0
    2.36 +	br.spnt.few dispatch_break_fault
    2.37 +	;;
    2.38 +END(slow_vcpu_rfi)    
    2.39 +
    2.40  // ensure that, if giving up, registers at entry to fast_hyperprivop unchanged
    2.41  ENTRY(hyper_rfi)
    2.42  #ifndef FAST_RFI
    2.43 -	br.spnt.few dispatch_break_fault ;;
    2.44 +	br.spnt.few slow_vcpu_rfi ;;
    2.45  #endif
    2.46  	// if no interrupts pending, proceed
    2.47  	mov r30=r0
    2.48 @@ -1027,7 +1038,7 @@ ENTRY(hyper_rfi)
    2.49  	// r30 determines whether we might deliver an immediate extint
    2.50  #ifndef RFI_TO_INTERRUPT // see beginning of file
    2.51  	cmp.ne p6,p0=r30,r0
    2.52 -(p6)	br.cond.spnt.few dispatch_break_fault ;;
    2.53 +(p6)	br.cond.spnt.few slow_vcpu_rfi ;;
    2.54  #endif
    2.55  1:
    2.56  	adds r20=XSI_IPSR_OFS-XSI_PSR_IC_OFS,r18 ;;
    2.57 @@ -1035,25 +1046,25 @@ 1:
    2.58  	extr.u r22=r21,IA64_PSR_BE_BIT,1 ;;
    2.59  	// if turning on psr.be, give up for now and do it the slow way
    2.60  	cmp.ne p7,p0=r22,r0
    2.61 -(p7)	br.spnt.few dispatch_break_fault ;;
    2.62 +(p7)	br.spnt.few slow_vcpu_rfi ;;
    2.63  	// if (!(vpsr.dt && vpsr.rt && vpsr.it)), do it the slow way
    2.64  	movl r20=(IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_IT);;
    2.65  	and r22=r20,r21
    2.66  	;;
    2.67  	cmp.ne p7,p0=r22,r20
    2.68 -(p7)	br.spnt.few dispatch_break_fault ;;
    2.69 +(p7)	br.spnt.few slow_vcpu_rfi ;;
    2.70  	// if was in metaphys mode, do it the slow way (FIXME later?)
    2.71  	adds r20=XSI_METAPHYS_OFS-XSI_PSR_IC_OFS,r18 ;;
    2.72  	ld4 r20=[r20];;
    2.73  	cmp.ne p7,p0=r20,r0
    2.74 -(p7)	br.spnt.few dispatch_break_fault ;;
    2.75 +(p7)	br.spnt.few slow_vcpu_rfi ;;
    2.76  	// if domain hasn't already done virtual bank switch
    2.77  	//  do it the slow way (FIXME later?)
    2.78  #if 0
    2.79  	adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
    2.80  	ld4 r20=[r20];;
    2.81  	cmp.eq p7,p0=r20,r0
    2.82 -(p7)	br.spnt.few dispatch_break_fault ;;
    2.83 +(p7)	br.spnt.few slow_vcpu_rfi ;;
    2.84  #endif
    2.85  	// validate vcr.iip, if in Xen range, do it the slow way
    2.86  	adds r20=XSI_IIP_OFS-XSI_PSR_IC_OFS,r18 ;;
    2.87 @@ -1062,7 +1073,7 @@ 1:
    2.88  	movl r24=HYPERVISOR_VIRT_END;;
    2.89  	cmp.ltu p0,p7=r22,r23 ;;	// if !(iip<low) &&
    2.90  (p7)	cmp.geu p0,p7=r22,r24 ;;	//    !(iip>=high)
    2.91 -(p7)	br.spnt.few dispatch_break_fault ;;
    2.92 +(p7)	br.spnt.few slow_vcpu_rfi ;;
    2.93  
    2.94  1:	// OK now, let's do an rfi.
    2.95  #ifdef FAST_HYPERPRIVOP_CNT
     3.1 --- a/xen/arch/ia64/xen/vcpu.c	Tue Jan 16 11:22:44 2007 -0700
     3.2 +++ b/xen/arch/ia64/xen/vcpu.c	Tue Jan 16 11:48:43 2007 -0700
     3.3 @@ -1336,8 +1336,7 @@ IA64FAULT vcpu_rfi(VCPU * vcpu)
     3.4  {
     3.5  	// TODO: Only allowed for current vcpu
     3.6  	PSR psr;
     3.7 -	u64 int_enable, regspsr = 0;
     3.8 -	u64 ifs;
     3.9 +	u64 int_enable, ifs;
    3.10  	REGS *regs = vcpu_regs(vcpu);
    3.11  
    3.12  	psr.i64 = PSCB(vcpu, ipsr);
    3.13 @@ -1363,26 +1362,11 @@ IA64FAULT vcpu_rfi(VCPU * vcpu)
    3.14  	}
    3.15  
    3.16  	ifs = PSCB(vcpu, ifs);
    3.17 -	if (ifs > 0x8000000000000000UL) {
    3.18 -		if (regs->cr_ifs > 0x8000000000000000UL) {
    3.19 -			// TODO: validate PSCB(vcpu,iip)
    3.20 -			// TODO: PSCB(vcpu,ipsr) = psr;
    3.21 -			PSCB(vcpu, ipsr) = psr.i64;
    3.22 -			// now set up the trampoline
    3.23 -			regs->cr_iip = *(unsigned long *)dorfirfi; // func ptr!
    3.24 -			__asm__ __volatile("mov %0=psr;;":"=r"(regspsr)
    3.25 -			                   ::"memory");
    3.26 -			regs->cr_ipsr = regspsr & ~(IA64_PSR_I | IA64_PSR_IC |
    3.27 -			                            IA64_PSR_BN);
    3.28 -		} else {
    3.29 -			regs->cr_ifs = ifs;
    3.30 -			regs->cr_ipsr = psr.i64;
    3.31 -			regs->cr_iip = PSCB(vcpu, iip);
    3.32 -		}
    3.33 -	} else {
    3.34 -		regs->cr_ipsr = psr.i64;
    3.35 -		regs->cr_iip = PSCB(vcpu, iip);
    3.36 -	}
    3.37 +	if (ifs & 0x8000000000000000UL) 
    3.38 +		regs->cr_ifs = ifs;
    3.39 +
    3.40 +	regs->cr_ipsr = psr.i64;
    3.41 +	regs->cr_iip = PSCB(vcpu, iip);
    3.42  	PSCB(vcpu, interrupt_collection_enabled) = 1;
    3.43  	vcpu_bsw1(vcpu);
    3.44  	vcpu->vcpu_info->evtchn_upcall_mask = !int_enable;
     4.1 --- a/xen/arch/ia64/xen/xenasm.S	Tue Jan 16 11:22:44 2007 -0700
     4.2 +++ b/xen/arch/ia64/xen/xenasm.S	Tue Jan 16 11:48:43 2007 -0700
     4.3 @@ -256,28 +256,6 @@ GLOBAL_ENTRY(__get_domain_bundle)
     4.4  	;;
     4.5  END(__get_domain_bundle)
     4.6  
     4.7 -GLOBAL_ENTRY(dorfirfi)
     4.8 -	// Read current vcpu shared info
     4.9 -	movl r16=THIS_CPU(current_psr_ic_addr)
    4.10 -	;;
    4.11 -	ld8 r19 = [r16]
    4.12 -	;;
    4.13 -	add r16 = XSI_IIP_OFS - XSI_PSR_IC_OFS, r19
    4.14 -	add r17 = XSI_IPSR_OFS - XSI_PSR_IC_OFS, r19
    4.15 -	add r18 = XSI_IFS_OFS - XSI_PSR_IC_OFS, r19
    4.16 -	;;
    4.17 -	ld8 r16 = [r16]
    4.18 -	ld8 r17 = [r17]
    4.19 -	ld8 r18 = [r18]
    4.20 -	;;
    4.21 -	mov cr.iip=r16
    4.22 -	mov cr.ipsr=r17
    4.23 -	mov cr.ifs=r18
    4.24 -	;;
    4.25 -	rfi
    4.26 -	;;
    4.27 -END(dorfirfi)
    4.28 -
    4.29  /* derived from linux/arch/ia64/hp/sim/boot/boot_head.S */
    4.30  GLOBAL_ENTRY(pal_emulator_static)
    4.31  	mov r8=-1
     5.1 --- a/xen/include/asm-ia64/vcpu.h	Tue Jan 16 11:22:44 2007 -0700
     5.2 +++ b/xen/include/asm-ia64/vcpu.h	Tue Jan 16 11:48:43 2007 -0700
     5.3 @@ -23,8 +23,6 @@ extern u64 cycle_to_ns(u64 cycle);
     5.4  
     5.5  #define SPURIOUS_VECTOR 0xf
     5.6  
     5.7 -extern void dorfirfi(void);
     5.8 -
     5.9  /* general registers */
    5.10  extern u64 vcpu_get_gr(VCPU * vcpu, unsigned long reg);
    5.11  extern IA64FAULT vcpu_get_gr_nat(VCPU * vcpu, unsigned long reg, u64 * val);