ia64/xen-unstable

changeset 18057:1c22d42043bb

x86: platform-timer read function returns 64 bits.
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Tue Jul 15 13:36:22 2008 +0100 (2008-07-15)
parents 750eee596adf
children bd6d194199e5
files xen/arch/x86/time.c
line diff
     1.1 --- a/xen/arch/x86/time.c	Tue Jul 15 13:19:26 2008 +0100
     1.2 +++ b/xen/arch/x86/time.c	Tue Jul 15 13:36:22 2008 +0100
     1.3 @@ -54,14 +54,14 @@ struct cpu_time {
     1.4      s_time_t stime_local_stamp;
     1.5      s_time_t stime_master_stamp;
     1.6      struct time_scale tsc_scale;
     1.7 -    u32 cstate_plt_count_stamp;
     1.8 +    u64 cstate_plt_count_stamp;
     1.9      struct timer calibration_timer;
    1.10  };
    1.11  
    1.12  struct platform_timesource {
    1.13      char *name;
    1.14      u64 frequency;
    1.15 -    u32 (*read_counter)(void);
    1.16 +    u64 (*read_counter)(void);
    1.17      int counter_bits;
    1.18  };
    1.19  
    1.20 @@ -340,7 +340,7 @@ static char *freq_string(u64 freq)
    1.21   * PLATFORM TIMER 1: PROGRAMMABLE INTERVAL TIMER (LEGACY PIT)
    1.22   */
    1.23  
    1.24 -static u32 read_pit_count(void)
    1.25 +static u64 read_pit_count(void)
    1.26  {
    1.27      u16 count16;
    1.28      u32 count32;
    1.29 @@ -372,7 +372,7 @@ static void init_pit(struct platform_tim
    1.30   * PLATFORM TIMER 2: HIGH PRECISION EVENT TIMER (HPET)
    1.31   */
    1.32  
    1.33 -static u32 read_hpet_count(void)
    1.34 +static u64 read_hpet_count(void)
    1.35  {
    1.36      return hpet_read32(HPET_COUNTER);
    1.37  }
    1.38 @@ -412,7 +412,7 @@ int use_cyclone;
    1.39  /* Cyclone MPMC0 register. */
    1.40  static volatile u32 *cyclone_timer;
    1.41  
    1.42 -static u32 read_cyclone_count(void)
    1.43 +static u64 read_cyclone_count(void)
    1.44  {
    1.45      return *cyclone_timer;
    1.46  }
    1.47 @@ -462,7 +462,7 @@ u32 pmtmr_ioport;
    1.48  /* ACPI PM timer ticks at 3.579545 MHz. */
    1.49  #define ACPI_PM_FREQUENCY 3579545
    1.50  
    1.51 -static u32 read_pmtimer_count(void)
    1.52 +static u64 read_pmtimer_count(void)
    1.53  {
    1.54      return inl(pmtmr_ioport);
    1.55  }
    1.56 @@ -485,7 +485,7 @@ static int init_pmtimer(struct platform_
    1.57   */
    1.58  
    1.59  static struct platform_timesource plt_src; /* details of chosen timesource  */
    1.60 -static u32 plt_mask;             /* hardware-width mask                     */
    1.61 +static u64 plt_mask;             /* hardware-width mask                     */
    1.62  static u64 plt_overflow_period;  /* ns between calls to plt_overflow()      */
    1.63  static struct time_scale plt_scale; /* scale: platform counter -> nanosecs  */
    1.64  
    1.65 @@ -494,12 +494,12 @@ static DEFINE_SPINLOCK(platform_timer_lo
    1.66  static s_time_t stime_platform_stamp; /* System time at below platform time */
    1.67  static u64 platform_timer_stamp;      /* Platform time at above system time */
    1.68  static u64 plt_stamp64;          /* 64-bit platform counter stamp           */
    1.69 -static u32 plt_stamp;            /* hardware-width platform counter stamp   */
    1.70 +static u64 plt_stamp;            /* hardware-width platform counter stamp   */
    1.71  static struct timer plt_overflow_timer;
    1.72  
    1.73  static void plt_overflow(void *unused)
    1.74  {
    1.75 -    u32 count;
    1.76 +    u64 count;
    1.77  
    1.78      spin_lock(&platform_timer_lock);
    1.79      count = plt_src.read_counter();
    1.80 @@ -578,7 +578,7 @@ static void init_platform_timer(void)
    1.81           !init_pmtimer(pts) )
    1.82          init_pit(pts);
    1.83  
    1.84 -    plt_mask = (u32)~0u >> (32 - pts->counter_bits);
    1.85 +    plt_mask = (u64)~0ull >> (64 - pts->counter_bits);
    1.86  
    1.87      set_time_scale(&plt_scale, pts->frequency);
    1.88  
    1.89 @@ -597,31 +597,25 @@ void cstate_save_tsc(void)
    1.90  {
    1.91      struct cpu_time *t = &this_cpu(cpu_time);
    1.92  
    1.93 -    if (!tsc_invariant){
    1.94 -        t->cstate_plt_count_stamp = plt_src.read_counter();
    1.95 -        rdtscll(t->cstate_tsc_stamp);
    1.96 -    }
    1.97 +    if ( tsc_invariant )
    1.98 +        return;
    1.99 +
   1.100 +    t->cstate_plt_count_stamp = plt_src.read_counter();
   1.101 +    rdtscll(t->cstate_tsc_stamp);
   1.102  }
   1.103  
   1.104  void cstate_restore_tsc(void)
   1.105  {
   1.106 -    struct cpu_time *t;
   1.107 -    u32    plt_count_delta;
   1.108 -    u64    tsc_delta;
   1.109 -
   1.110 -    if (!tsc_invariant){
   1.111 -        t = &this_cpu(cpu_time);
   1.112 +    struct cpu_time *t = &this_cpu(cpu_time);
   1.113 +    u64 plt_count_delta, tsc_delta;
   1.114  
   1.115 -        /* if platform counter overflow happens, interrupt will bring CPU from
   1.116 -           C state to working state, so the platform counter won't wrap the
   1.117 -           cstate_plt_count_stamp, and the 32 bit unsigned platform counter
   1.118 -           is enough for delta calculation
   1.119 -         */
   1.120 -        plt_count_delta = 
   1.121 -            (plt_src.read_counter() - t->cstate_plt_count_stamp) & plt_mask;
   1.122 -        tsc_delta = scale_delta(plt_count_delta, &plt_scale)*cpu_khz/1000000UL;
   1.123 -        wrmsrl(MSR_IA32_TSC,  t->cstate_tsc_stamp + tsc_delta);
   1.124 -    }
   1.125 +    if ( tsc_invariant )
   1.126 +        return;
   1.127 +
   1.128 +    plt_count_delta = (plt_src.read_counter() -
   1.129 +                       t->cstate_plt_count_stamp) & plt_mask;
   1.130 +    tsc_delta = scale_delta(plt_count_delta, &plt_scale) * cpu_khz/1000000UL;
   1.131 +    wrmsrl(MSR_IA32_TSC, t->cstate_tsc_stamp + tsc_delta);
   1.132  }
   1.133  
   1.134  /***************************************************************************