ia64/xen-unstable

changeset 17645:1b7042d60351

Intel vmx: To correctly detect default1 vmx features which may
actually be switched to 0, we must check VMX_BASIC_MSR[55] and
possibly check a set of 'true' feature MSRs.

Signed-off-by: Jun Nakajima <jun.nakajima@intel.com>
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Tue May 13 10:40:49 2008 +0100 (2008-05-13)
parents 5d9430d492e3
children 5e1a0dc74a35
files xen/arch/x86/hvm/vmx/vmcs.c xen/include/asm-x86/msr-index.h
line diff
     1.1 --- a/xen/arch/x86/hvm/vmx/vmcs.c	Tue May 13 10:19:54 2008 +0100
     1.2 +++ b/xen/arch/x86/hvm/vmx/vmcs.c	Tue May 13 10:40:49 2008 +0100
     1.3 @@ -72,13 +72,15 @@ static u32 adjust_vmx_controls(u32 ctl_m
     1.4  
     1.5  static void vmx_init_vmcs_config(void)
     1.6  {
     1.7 -    u32 vmx_msr_low, vmx_msr_high, min, opt;
     1.8 +    u32 vmx_basic_msr_low, vmx_basic_msr_high, min, opt;
     1.9      u32 _vmx_pin_based_exec_control;
    1.10      u32 _vmx_cpu_based_exec_control;
    1.11      u32 _vmx_secondary_exec_control = 0;
    1.12      u32 _vmx_vmexit_control;
    1.13      u32 _vmx_vmentry_control;
    1.14  
    1.15 +    rdmsr(MSR_IA32_VMX_BASIC, vmx_basic_msr_low, vmx_basic_msr_high);
    1.16 +
    1.17      min = (PIN_BASED_EXT_INTR_MASK |
    1.18             PIN_BASED_NMI_EXITING);
    1.19      opt = PIN_BASED_VIRTUAL_NMIS;
    1.20 @@ -122,9 +124,14 @@ static void vmx_init_vmcs_config(void)
    1.21  
    1.22      if ( _vmx_secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT )
    1.23      {
    1.24 -        /* To use EPT we expect to be able to clear certain intercepts. */
    1.25 -        uint32_t must_be_one, must_be_zero;
    1.26 -        rdmsr(MSR_IA32_VMX_PROCBASED_CTLS, must_be_one, must_be_zero);
    1.27 +        /*
    1.28 +         * To use EPT we expect to be able to clear certain intercepts.
    1.29 +         * We check VMX_BASIC_MSR[55] to correctly handle default1 controls.
    1.30 +         */
    1.31 +        uint32_t must_be_one, must_be_zero, msr = MSR_IA32_VMX_PROCBASED_CTLS;
    1.32 +        if ( vmx_basic_msr_high & (1u << 23) )
    1.33 +            msr = MSR_IA32_VMX_TRUE_PROCBASED_CTLS;
    1.34 +        rdmsr(msr, must_be_one, must_be_zero);
    1.35          if ( must_be_one & (CPU_BASED_INVLPG_EXITING |
    1.36                              CPU_BASED_CR3_LOAD_EXITING |
    1.37                              CPU_BASED_CR3_STORE_EXITING) )
    1.38 @@ -150,41 +157,40 @@ static void vmx_init_vmcs_config(void)
    1.39      _vmx_vmentry_control = adjust_vmx_controls(
    1.40          min, opt, MSR_IA32_VMX_ENTRY_CTLS);
    1.41  
    1.42 -    rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
    1.43 -
    1.44      if ( !vmx_pin_based_exec_control )
    1.45      {
    1.46          /* First time through. */
    1.47 -        vmcs_revision_id = vmx_msr_low;
    1.48 +        vmcs_revision_id = vmx_basic_msr_low;
    1.49          vmx_pin_based_exec_control = _vmx_pin_based_exec_control;
    1.50          vmx_cpu_based_exec_control = _vmx_cpu_based_exec_control;
    1.51          vmx_secondary_exec_control = _vmx_secondary_exec_control;
    1.52          vmx_vmexit_control         = _vmx_vmexit_control;
    1.53          vmx_vmentry_control        = _vmx_vmentry_control;
    1.54 -        cpu_has_vmx_ins_outs_instr_info = !!(vmx_msr_high & (1U<<22));
    1.55 +        cpu_has_vmx_ins_outs_instr_info = !!(vmx_basic_msr_high & (1U<<22));
    1.56      }
    1.57      else
    1.58      {
    1.59          /* Globals are already initialised: re-check them. */
    1.60 -        BUG_ON(vmcs_revision_id != vmx_msr_low);
    1.61 +        BUG_ON(vmcs_revision_id != vmx_basic_msr_low);
    1.62          BUG_ON(vmx_pin_based_exec_control != _vmx_pin_based_exec_control);
    1.63          BUG_ON(vmx_cpu_based_exec_control != _vmx_cpu_based_exec_control);
    1.64          BUG_ON(vmx_secondary_exec_control != _vmx_secondary_exec_control);
    1.65          BUG_ON(vmx_vmexit_control != _vmx_vmexit_control);
    1.66          BUG_ON(vmx_vmentry_control != _vmx_vmentry_control);
    1.67 -        BUG_ON(cpu_has_vmx_ins_outs_instr_info != !!(vmx_msr_high & (1U<<22)));
    1.68 +        BUG_ON(cpu_has_vmx_ins_outs_instr_info !=
    1.69 +               !!(vmx_basic_msr_high & (1U<<22)));
    1.70      }
    1.71  
    1.72      /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
    1.73 -    BUG_ON((vmx_msr_high & 0x1fff) > PAGE_SIZE);
    1.74 +    BUG_ON((vmx_basic_msr_high & 0x1fff) > PAGE_SIZE);
    1.75  
    1.76  #ifdef __x86_64__
    1.77      /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
    1.78 -    BUG_ON(vmx_msr_high & (1u<<16));
    1.79 +    BUG_ON(vmx_basic_msr_high & (1u<<16));
    1.80  #endif
    1.81  
    1.82      /* Require Write-Back (WB) memory type for VMCS accesses. */
    1.83 -    BUG_ON(((vmx_msr_high >> 18) & 15) != 6);
    1.84 +    BUG_ON(((vmx_basic_msr_high >> 18) & 15) != 6);
    1.85  }
    1.86  
    1.87  static struct vmcs_struct *vmx_alloc_vmcs(void)
     2.1 --- a/xen/include/asm-x86/msr-index.h	Tue May 13 10:19:54 2008 +0100
     2.2 +++ b/xen/include/asm-x86/msr-index.h	Tue May 13 10:40:49 2008 +0100
     2.3 @@ -135,6 +135,10 @@
     2.4  #define MSR_IA32_VMX_CR4_FIXED0                 0x488
     2.5  #define MSR_IA32_VMX_CR4_FIXED1                 0x489
     2.6  #define MSR_IA32_VMX_PROCBASED_CTLS2            0x48b
     2.7 +#define MSR_IA32_VMX_TRUE_PINBASED_CTLS         0x48d
     2.8 +#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS        0x48e
     2.9 +#define MSR_IA32_VMX_TRUE_EXIT_CTLS             0x48f
    2.10 +#define MSR_IA32_VMX_TRUE_ENTRY_CTLS            0x490
    2.11  #define IA32_FEATURE_CONTROL_MSR                0x3a
    2.12  #define IA32_FEATURE_CONTROL_MSR_LOCK                     0x0001
    2.13  #define IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_INSIDE_SMX  0x0002