ia64/xen-unstable

changeset 10195:18b087bafac6

[IA64] VTI: simple format cleanup

Signed-off-by: Anthony Xu <anthony.xu@intel.com>
author awilliam@xenbuild.aw
date Tue May 30 08:46:21 2006 -0600 (2006-05-30)
parents c073ebdbde8c
children 166073f830a3
files xen/arch/ia64/vmx/vmmu.c xen/arch/ia64/vmx/vmx_ivt.S xen/arch/ia64/vmx/vmx_process.c xen/include/asm-ia64/vmmu.h xen/include/asm-ia64/vmx_vcpu.h
line diff
     1.1 --- a/xen/arch/ia64/vmx/vmmu.c	Fri May 26 13:41:49 2006 -0600
     1.2 +++ b/xen/arch/ia64/vmx/vmmu.c	Tue May 30 08:46:21 2006 -0600
     1.3 @@ -319,17 +319,17 @@ fetch_code(VCPU *vcpu, u64 gip, u64 *cod
     1.4  //        if( tlb == NULL )
     1.5  //             tlb = vtlb_lookup(vcpu, gip, DSIDE_TLB );
     1.6          if (tlb)
     1.7 -	        gpip = (tlb->ppn >>(tlb->ps-12)<<tlb->ps) | ( gip & (PSIZE(tlb->ps)-1) );
     1.8 +            gpip = (tlb->ppn >>(tlb->ps-12)<<tlb->ps) | ( gip & (PSIZE(tlb->ps)-1) );
     1.9      }
    1.10      if( gpip){
    1.11 -	 mfn = gmfn_to_mfn(vcpu->domain, gpip >>PAGE_SHIFT);
    1.12 -    	if( mfn == INVALID_MFN )  panic_domain(vcpu_regs(vcpu),"fetch_code: invalid memory\n");
    1.13 -    	vpa =(u64 *)__va( (gip & (PAGE_SIZE-1)) | (mfn<<PAGE_SHIFT));
    1.14 +        mfn = gmfn_to_mfn(vcpu->domain, gpip >>PAGE_SHIFT);
    1.15 +        if( mfn == INVALID_MFN )  panic_domain(vcpu_regs(vcpu),"fetch_code: invalid memory\n");
    1.16 +        vpa =(u64 *)__va( (gip & (PAGE_SIZE-1)) | (mfn<<PAGE_SHIFT));
    1.17      }else{
    1.18 -	tlb = vhpt_lookup(gip);
    1.19 -	if( tlb == NULL)
    1.20 -	    panic_domain(vcpu_regs(vcpu),"No entry found in ITLB and DTLB\n");
    1.21 -	vpa =(u64 *)__va((tlb->ppn>>(PAGE_SHIFT-ARCH_PAGE_SHIFT)<<PAGE_SHIFT)|(gip&(PAGE_SIZE-1)));
    1.22 +        tlb = vhpt_lookup(gip);
    1.23 +        if( tlb == NULL)
    1.24 +            panic_domain(vcpu_regs(vcpu),"No entry found in ITLB and DTLB\n");
    1.25 +        vpa =(u64 *)__va((tlb->ppn>>(PAGE_SHIFT-ARCH_PAGE_SHIFT)<<PAGE_SHIFT)|(gip&(PAGE_SIZE-1)));
    1.26      }
    1.27      *code1 = *vpa++;
    1.28      *code2 = *vpa;
    1.29 @@ -530,7 +530,7 @@ IA64FAULT vmx_vcpu_tpa(VCPU *vcpu, UINT6
    1.30      visr.ir=pt_isr.ir;
    1.31      vpsr.val = vmx_vcpu_get_psr(vcpu);
    1.32      if(vpsr.ic==0){
    1.33 -         visr.ni=1;
    1.34 +        visr.ni=1;
    1.35      }
    1.36      visr.na=1;
    1.37      data = vtlb_lookup(vcpu, vadr, DSIDE_TLB);
    1.38 @@ -648,14 +648,14 @@ IA64FAULT vmx_vcpu_tak(VCPU *vcpu, UINT6
    1.39  long
    1.40  __domain_va_to_ma(unsigned long va, unsigned long* ma, unsigned long *len)
    1.41  {
    1.42 -    unsigned long 	mpfn, gpfn, m, n = *len;
    1.43 -    unsigned long	end;	/* end of the area mapped by current entry */
    1.44 -    thash_data_t	*entry;
    1.45 +    unsigned long  mpfn, gpfn, m, n = *len;
    1.46 +    unsigned long  end;   /* end of the area mapped by current entry */
    1.47 +    thash_data_t   *entry;
    1.48      struct vcpu *v = current;
    1.49  
    1.50      entry = vtlb_lookup(v, va, DSIDE_TLB);
    1.51      if (entry == NULL)
    1.52 -	return -EFAULT;
    1.53 +        return -EFAULT;
    1.54  
    1.55      gpfn =(entry->ppn>>(PAGE_SHIFT-12));
    1.56      gpfn =PAGEALIGN(gpfn,(entry->ps-PAGE_SHIFT));
    1.57 @@ -668,7 +668,7 @@ long
    1.58      /*end = PAGEALIGN(m, entry->ps) + PSIZE(entry->ps);*/
    1.59      /* Current entry can't map all requested area */
    1.60      if ((m + n) > end)
    1.61 -	n = end - m;
    1.62 +        n = end - m;
    1.63  
    1.64      *ma = m;
    1.65      *len = n;
     2.1 --- a/xen/arch/ia64/vmx/vmx_ivt.S	Fri May 26 13:41:49 2006 -0600
     2.2 +++ b/xen/arch/ia64/vmx/vmx_ivt.S	Tue May 30 08:46:21 2006 -0600
     2.3 @@ -2,10 +2,10 @@
     2.4   * arch/ia64/kernel/vmx_ivt.S
     2.5   *
     2.6   * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
     2.7 - *	Stephane Eranian <eranian@hpl.hp.com>
     2.8 - *	David Mosberger <davidm@hpl.hp.com>
     2.9 + *      Stephane Eranian <eranian@hpl.hp.com>
    2.10 + *      David Mosberger <davidm@hpl.hp.com>
    2.11   * Copyright (C) 2000, 2002-2003 Intel Co
    2.12 - *	Asit Mallick <asit.k.mallick@intel.com>
    2.13 + *      Asit Mallick <asit.k.mallick@intel.com>
    2.14   *      Suresh Siddha <suresh.b.siddha@intel.com>
    2.15   *      Kenneth Chen <kenneth.w.chen@intel.com>
    2.16   *      Fenghua Yu <fenghua.yu@intel.com>
    2.17 @@ -31,7 +31,7 @@
    2.18   *
    2.19   *  For each entry, the comment is as follows:
    2.20   *
    2.21 - *		// 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
    2.22 + *              // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
    2.23   *  entry offset ----/     /         /                  /          /
    2.24   *  entry number ---------/         /                  /          /
    2.25   *  size of the entry -------------/                  /          /
    2.26 @@ -96,13 +96,13 @@ vmx_fault_##n:;          \
    2.27      ;;                  \
    2.28  
    2.29  
    2.30 -#define VMX_REFLECT(n)				\
    2.31 -	mov r31=pr;									\
    2.32 -	mov r19=n;			/* prepare to save predicates */		\
    2.33 -    mov r29=cr.ipsr;        \
    2.34 +#define VMX_REFLECT(n)    \
    2.35 +    mov r31=pr;           \
    2.36 +    mov r19=n;       /* prepare to save predicates */ \
    2.37 +    mov r29=cr.ipsr;      \
    2.38      ;;      \
    2.39      tbit.z p6,p7=r29,IA64_PSR_VM_BIT;       \
    2.40 -(p7) br.sptk.many vmx_dispatch_reflection;        \
    2.41 +(p7)br.sptk.many vmx_dispatch_reflection;        \
    2.42      VMX_FAULT(n);            \
    2.43  
    2.44  
    2.45 @@ -115,10 +115,10 @@ END(vmx_panic)
    2.46  
    2.47  
    2.48  
    2.49 -	.section .text.ivt,"ax"
    2.50 +    .section .text.ivt,"ax"
    2.51  
    2.52 -	.align 32768	// align on 32KB boundary
    2.53 -	.global vmx_ia64_ivt
    2.54 +    .align 32768    // align on 32KB boundary
    2.55 +    .global vmx_ia64_ivt
    2.56  vmx_ia64_ivt:
    2.57  /////////////////////////////////////////////////////////////////////////////////////////
    2.58  // 0x0000 Entry 0 (size 64 bundles) VHPT Translation (8,20,47)
    2.59 @@ -127,7 +127,7 @@ ENTRY(vmx_vhpt_miss)
    2.60      VMX_FAULT(0)
    2.61  END(vmx_vhpt_miss)
    2.62  
    2.63 -	.org vmx_ia64_ivt+0x400
    2.64 +    .org vmx_ia64_ivt+0x400
    2.65  /////////////////////////////////////////////////////////////////////////////////////////
    2.66  // 0x0400 Entry 1 (size 64 bundles) ITLB (21)
    2.67  ENTRY(vmx_itlb_miss)
    2.68 @@ -410,52 +410,52 @@ ENTRY(vmx_nested_dtlb_miss)
    2.69      VMX_FAULT(5)
    2.70  END(vmx_nested_dtlb_miss)
    2.71  
    2.72 -	.org vmx_ia64_ivt+0x1800
    2.73 +    .org vmx_ia64_ivt+0x1800
    2.74  /////////////////////////////////////////////////////////////////////////////////////////
    2.75  // 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24)
    2.76  ENTRY(vmx_ikey_miss)
    2.77      VMX_DBG_FAULT(6)
    2.78 -	VMX_REFLECT(6)
    2.79 +    VMX_REFLECT(6)
    2.80  END(vmx_ikey_miss)
    2.81  
    2.82 -	.org vmx_ia64_ivt+0x1c00
    2.83 +    .org vmx_ia64_ivt+0x1c00
    2.84  /////////////////////////////////////////////////////////////////////////////////////////
    2.85  // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
    2.86  ENTRY(vmx_dkey_miss)
    2.87      VMX_DBG_FAULT(7)
    2.88 -	VMX_REFLECT(7)
    2.89 +    VMX_REFLECT(7)
    2.90  END(vmx_dkey_miss)
    2.91  
    2.92 -	.org vmx_ia64_ivt+0x2000
    2.93 +    .org vmx_ia64_ivt+0x2000
    2.94  /////////////////////////////////////////////////////////////////////////////////////////
    2.95  // 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54)
    2.96  ENTRY(vmx_dirty_bit)
    2.97      VMX_DBG_FAULT(8)
    2.98 -	VMX_REFLECT(8)
    2.99 +    VMX_REFLECT(8)
   2.100  END(vmx_dirty_bit)
   2.101  
   2.102 -	.org vmx_ia64_ivt+0x2400
   2.103 +    .org vmx_ia64_ivt+0x2400
   2.104  /////////////////////////////////////////////////////////////////////////////////////////
   2.105  // 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27)
   2.106  ENTRY(vmx_iaccess_bit)
   2.107      VMX_DBG_FAULT(9)
   2.108 -	VMX_REFLECT(9)
   2.109 +    VMX_REFLECT(9)
   2.110  END(vmx_iaccess_bit)
   2.111  
   2.112 -	.org vmx_ia64_ivt+0x2800
   2.113 +    .org vmx_ia64_ivt+0x2800
   2.114  /////////////////////////////////////////////////////////////////////////////////////////
   2.115  // 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55)
   2.116  ENTRY(vmx_daccess_bit)
   2.117      VMX_DBG_FAULT(10)
   2.118 -	VMX_REFLECT(10)
   2.119 +    VMX_REFLECT(10)
   2.120  END(vmx_daccess_bit)
   2.121  
   2.122 -	.org vmx_ia64_ivt+0x2c00
   2.123 +    .org vmx_ia64_ivt+0x2c00
   2.124  /////////////////////////////////////////////////////////////////////////////////////////
   2.125  // 0x2c00 Entry 11 (size 64 bundles) Break instruction (33)
   2.126  ENTRY(vmx_break_fault)
   2.127      VMX_DBG_FAULT(11)
   2.128 -	mov r31=pr
   2.129 +    mov r31=pr
   2.130      mov r19=11
   2.131      mov r30=cr.iim
   2.132      movl r29=0x1100
   2.133 @@ -473,12 +473,12 @@ ENTRY(vmx_break_fault)
   2.134      VMX_FAULT(11);
   2.135  END(vmx_break_fault)
   2.136  
   2.137 -	.org vmx_ia64_ivt+0x3000
   2.138 +    .org vmx_ia64_ivt+0x3000
   2.139  /////////////////////////////////////////////////////////////////////////////////////////
   2.140  // 0x3000 Entry 12 (size 64 bundles) External Interrupt (4)
   2.141  ENTRY(vmx_interrupt)
   2.142  //    VMX_DBG_FAULT(12)
   2.143 -	mov r31=pr		// prepare to save predicates
   2.144 +    mov r31=pr		// prepare to save predicates
   2.145      mov r19=12
   2.146      mov r29=cr.ipsr
   2.147      ;;
   2.148 @@ -487,58 +487,58 @@ ENTRY(vmx_interrupt)
   2.149      ;;
   2.150  (p7) br.sptk vmx_dispatch_interrupt
   2.151      ;;
   2.152 -	mov r27=ar.rsc			/* M */
   2.153 -	mov r20=r1			/* A */
   2.154 -	mov r25=ar.unat		/* M */
   2.155 -	mov r26=ar.pfs			/* I */
   2.156 -	mov r28=cr.iip			/* M */
   2.157 -	cover               /* B (or nothing) */
   2.158 -	;;
   2.159 -	mov r1=sp
   2.160 -	;;
   2.161 -	invala				/* M */
   2.162 -	mov r30=cr.ifs
   2.163 -	;;
   2.164 +    mov r27=ar.rsc		/* M */
   2.165 +    mov r20=r1			/* A */
   2.166 +    mov r25=ar.unat		/* M */
   2.167 +    mov r26=ar.pfs		/* I */
   2.168 +    mov r28=cr.iip		/* M */
   2.169 +    cover			/* B (or nothing) */
   2.170 +    ;;
   2.171 +    mov r1=sp
   2.172 +    ;;
   2.173 +    invala			/* M */
   2.174 +    mov r30=cr.ifs
   2.175 +    ;;
   2.176      addl r1=-IA64_PT_REGS_SIZE,r1
   2.177      ;;
   2.178 -	adds r17=2*L1_CACHE_BYTES,r1		/* really: biggest cache-line size */
   2.179 -	adds r16=PT(CR_IPSR),r1
   2.180 -	;;
   2.181 -	lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES
   2.182 -	st8 [r16]=r29		/* save cr.ipsr */
   2.183 -	;;
   2.184 -	lfetch.fault.excl.nt1 [r17]
   2.185 -	mov r29=b0
   2.186 -	;;
   2.187 -	adds r16=PT(R8),r1  	/* initialize first base pointer */
   2.188 -	adds r17=PT(R9),r1  	/* initialize second base pointer */
   2.189 -	mov r18=r0      		/* make sure r18 isn't NaT */
   2.190 -	;;
   2.191 +    adds r17=2*L1_CACHE_BYTES,r1	/* really: biggest cache-line size */
   2.192 +    adds r16=PT(CR_IPSR),r1
   2.193 +    ;;
   2.194 +    lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES
   2.195 +    st8 [r16]=r29			/* save cr.ipsr */
   2.196 +    ;;
   2.197 +    lfetch.fault.excl.nt1 [r17]
   2.198 +    mov r29=b0
   2.199 +    ;;
   2.200 +    adds r16=PT(R8),r1  	/* initialize first base pointer */
   2.201 +    adds r17=PT(R9),r1  	/* initialize second base pointer */
   2.202 +    mov r18=r0      		/* make sure r18 isn't NaT */
   2.203 +    ;;
   2.204  .mem.offset 0,0; st8.spill [r16]=r8,16
   2.205  .mem.offset 8,0; st8.spill [r17]=r9,16
   2.206          ;;
   2.207  .mem.offset 0,0; st8.spill [r16]=r10,24
   2.208  .mem.offset 8,0; st8.spill [r17]=r11,24
   2.209          ;;
   2.210 -	st8 [r16]=r28,16	/* save cr.iip */
   2.211 -	st8 [r17]=r30,16	/* save cr.ifs */
   2.212 -	mov r8=ar.fpsr		/* M */
   2.213 -	mov r9=ar.csd
   2.214 -	mov r10=ar.ssd
   2.215 -	movl r11=FPSR_DEFAULT   /* L-unit */
   2.216 -	;;
   2.217 -	st8 [r16]=r25,16	/* save ar.unat */
   2.218 -	st8 [r17]=r26,16	/* save ar.pfs */
   2.219 -	shl r18=r18,16		/* compute ar.rsc to be used for "loadrs" */
   2.220 -	;;
   2.221 -    st8 [r16]=r27,16   /* save ar.rsc */
   2.222 -    adds r17=16,r17    /* skip over ar_rnat field */
   2.223 -    ;;          /* avoid RAW on r16 & r17 */
   2.224 -    st8 [r17]=r31,16   /* save predicates */
   2.225 -    adds r16=16,r16    /* skip over ar_bspstore field */
   2.226 +    st8 [r16]=r28,16		/* save cr.iip */
   2.227 +    st8 [r17]=r30,16		/* save cr.ifs */
   2.228 +    mov r8=ar.fpsr		/* M */
   2.229 +    mov r9=ar.csd
   2.230 +    mov r10=ar.ssd
   2.231 +    movl r11=FPSR_DEFAULT	/* L-unit */
   2.232      ;;
   2.233 -    st8 [r16]=r29,16   /* save b0 */
   2.234 -    st8 [r17]=r18,16   /* save ar.rsc value for "loadrs" */
   2.235 +    st8 [r16]=r25,16		/* save ar.unat */
   2.236 +    st8 [r17]=r26,16		/* save ar.pfs */
   2.237 +    shl r18=r18,16		/* compute ar.rsc to be used for "loadrs" */
   2.238 +    ;;
   2.239 +    st8 [r16]=r27,16		/* save ar.rsc */
   2.240 +    adds r17=16,r17		/* skip over ar_rnat field */
   2.241 +    ;;
   2.242 +    st8 [r17]=r31,16		/* save predicates */
   2.243 +    adds r16=16,r16		/* skip over ar_bspstore field */
   2.244 +    ;;
   2.245 +    st8 [r16]=r29,16		/* save b0 */
   2.246 +    st8 [r17]=r18,16		/* save ar.rsc value for "loadrs" */
   2.247      ;;
   2.248  .mem.offset 0,0; st8.spill [r16]=r20,16    /* save original r1 */
   2.249  .mem.offset 8,0; st8.spill [r17]=r12,16
   2.250 @@ -561,18 +561,18 @@ ENTRY(vmx_interrupt)
   2.251      ;;                                          \
   2.252      bsw.1
   2.253      ;;
   2.254 -	alloc r14=ar.pfs,0,0,2,0 // must be first in an insn group
   2.255 -	mov out0=cr.ivr		// pass cr.ivr as first arg
   2.256 -	add out1=16,sp		// pass pointer to pt_regs as second arg
   2.257 +    alloc r14=ar.pfs,0,0,2,0	// must be first in an insn group
   2.258 +    mov out0=cr.ivr		// pass cr.ivr as first arg
   2.259 +    add out1=16,sp		// pass pointer to pt_regs as second arg
   2.260  
   2.261 -	ssm psr.ic
   2.262 +    ssm psr.ic
   2.263      ;;
   2.264      srlz.i
   2.265 -	;;
   2.266 +    ;;
   2.267      (p15) ssm psr.i
   2.268 -	adds r3=8,r2		// set up second base pointer for SAVE_REST
   2.269 -	srlz.i			// ensure everybody knows psr.ic is back on
   2.270 -	;;
   2.271 +    adds r3=8,r2		// set up second base pointer for SAVE_REST
   2.272 +    srlz.i			// ensure everybody knows psr.ic is back on
   2.273 +    ;;
   2.274  .mem.offset 0,0; st8.spill [r2]=r16,16
   2.275  .mem.offset 8,0; st8.spill [r3]=r17,16
   2.276      ;;
   2.277 @@ -599,8 +599,8 @@ ENTRY(vmx_interrupt)
   2.278  .mem.offset 0,0; st8.spill [r2]=r30,16
   2.279  .mem.offset 8,0; st8.spill [r3]=r31,32
   2.280      ;;
   2.281 -    mov ar.fpsr=r11     /* M-unit */
   2.282 -    st8 [r2]=r8,8      /* ar.ccv */
   2.283 +    mov ar.fpsr=r11       /* M-unit */
   2.284 +    st8 [r2]=r8,8         /* ar.ccv */
   2.285      adds r24=PT(B6)-PT(F7),r3
   2.286      ;;
   2.287      stf.spill [r2]=f6,32
   2.288 @@ -619,95 +619,95 @@ ENTRY(vmx_interrupt)
   2.289      st8 [r24]=r9           /* ar.csd */
   2.290      st8 [r25]=r10          /* ar.ssd */
   2.291      ;;
   2.292 -	srlz.d			// make sure we see the effect of cr.ivr
   2.293 -	movl r14=ia64_leave_nested
   2.294 -	;;
   2.295 -	mov rp=r14
   2.296 -	br.call.sptk.many b6=ia64_handle_irq
   2.297 -	;;
   2.298 +    srlz.d		// make sure we see the effect of cr.ivr
   2.299 +    movl r14=ia64_leave_nested
   2.300 +    ;;
   2.301 +    mov rp=r14
   2.302 +    br.call.sptk.many b6=ia64_handle_irq
   2.303 +    ;;
   2.304  END(vmx_interrupt)
   2.305  
   2.306 -	.org vmx_ia64_ivt+0x3400
   2.307 +    .org vmx_ia64_ivt+0x3400
   2.308  /////////////////////////////////////////////////////////////////////////////////////////
   2.309  // 0x3400 Entry 13 (size 64 bundles) Reserved
   2.310  ENTRY(vmx_virtual_exirq)
   2.311 -	VMX_DBG_FAULT(13)
   2.312 -	mov r31=pr
   2.313 -        mov r19=13
   2.314 -        br.sptk vmx_dispatch_vexirq
   2.315 +    VMX_DBG_FAULT(13)
   2.316 +    mov r31=pr
   2.317 +    mov r19=13
   2.318 +    br.sptk vmx_dispatch_vexirq
   2.319  END(vmx_virtual_exirq)
   2.320  
   2.321 -	.org vmx_ia64_ivt+0x3800
   2.322 +    .org vmx_ia64_ivt+0x3800
   2.323  /////////////////////////////////////////////////////////////////////////////////////////
   2.324  // 0x3800 Entry 14 (size 64 bundles) Reserved
   2.325      VMX_DBG_FAULT(14)
   2.326 -	VMX_FAULT(14)
   2.327 +    VMX_FAULT(14)
   2.328  
   2.329  
   2.330 -	.org vmx_ia64_ivt+0x3c00
   2.331 +    .org vmx_ia64_ivt+0x3c00
   2.332  /////////////////////////////////////////////////////////////////////////////////////////
   2.333  // 0x3c00 Entry 15 (size 64 bundles) Reserved
   2.334      VMX_DBG_FAULT(15)
   2.335 -	VMX_FAULT(15)
   2.336 +    VMX_FAULT(15)
   2.337  
   2.338  
   2.339 -	.org vmx_ia64_ivt+0x4000
   2.340 +    .org vmx_ia64_ivt+0x4000
   2.341  /////////////////////////////////////////////////////////////////////////////////////////
   2.342  // 0x4000 Entry 16 (size 64 bundles) Reserved
   2.343      VMX_DBG_FAULT(16)
   2.344 -	VMX_FAULT(16)
   2.345 +    VMX_FAULT(16)
   2.346  
   2.347 -	.org vmx_ia64_ivt+0x4400
   2.348 +    .org vmx_ia64_ivt+0x4400
   2.349  /////////////////////////////////////////////////////////////////////////////////////////
   2.350  // 0x4400 Entry 17 (size 64 bundles) Reserved
   2.351      VMX_DBG_FAULT(17)
   2.352 -	VMX_FAULT(17)
   2.353 +    VMX_FAULT(17)
   2.354  
   2.355 -	.org vmx_ia64_ivt+0x4800
   2.356 +    .org vmx_ia64_ivt+0x4800
   2.357  /////////////////////////////////////////////////////////////////////////////////////////
   2.358  // 0x4800 Entry 18 (size 64 bundles) Reserved
   2.359      VMX_DBG_FAULT(18)
   2.360 -	VMX_FAULT(18)
   2.361 +    VMX_FAULT(18)
   2.362  
   2.363 -	.org vmx_ia64_ivt+0x4c00
   2.364 +    .org vmx_ia64_ivt+0x4c00
   2.365  /////////////////////////////////////////////////////////////////////////////////////////
   2.366  // 0x4c00 Entry 19 (size 64 bundles) Reserved
   2.367      VMX_DBG_FAULT(19)
   2.368 -	VMX_FAULT(19)
   2.369 +    VMX_FAULT(19)
   2.370  
   2.371      .org vmx_ia64_ivt+0x5000
   2.372  /////////////////////////////////////////////////////////////////////////////////////////
   2.373  // 0x5000 Entry 20 (size 16 bundles) Page Not Present
   2.374  ENTRY(vmx_page_not_present)
   2.375 -	VMX_DBG_FAULT(20)
   2.376 -	VMX_REFLECT(20)
   2.377 +    VMX_DBG_FAULT(20)
   2.378 +    VMX_REFLECT(20)
   2.379  END(vmx_page_not_present)
   2.380  
   2.381      .org vmx_ia64_ivt+0x5100
   2.382  /////////////////////////////////////////////////////////////////////////////////////////
   2.383  // 0x5100 Entry 21 (size 16 bundles) Key Permission vector
   2.384  ENTRY(vmx_key_permission)
   2.385 -	VMX_DBG_FAULT(21)
   2.386 -	VMX_REFLECT(21)
   2.387 +    VMX_DBG_FAULT(21)
   2.388 +    VMX_REFLECT(21)
   2.389  END(vmx_key_permission)
   2.390  
   2.391      .org vmx_ia64_ivt+0x5200
   2.392  /////////////////////////////////////////////////////////////////////////////////////////
   2.393  // 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26)
   2.394  ENTRY(vmx_iaccess_rights)
   2.395 -	VMX_DBG_FAULT(22)
   2.396 -	VMX_REFLECT(22)
   2.397 +    VMX_DBG_FAULT(22)
   2.398 +    VMX_REFLECT(22)
   2.399  END(vmx_iaccess_rights)
   2.400  
   2.401 -	.org vmx_ia64_ivt+0x5300
   2.402 +    .org vmx_ia64_ivt+0x5300
   2.403  /////////////////////////////////////////////////////////////////////////////////////////
   2.404  // 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53)
   2.405  ENTRY(vmx_daccess_rights)
   2.406 -	VMX_DBG_FAULT(23)
   2.407 -	VMX_REFLECT(23)
   2.408 +    VMX_DBG_FAULT(23)
   2.409 +    VMX_REFLECT(23)
   2.410  END(vmx_daccess_rights)
   2.411  
   2.412 -	.org vmx_ia64_ivt+0x5400
   2.413 +    .org vmx_ia64_ivt+0x5400
   2.414  /////////////////////////////////////////////////////////////////////////////////////////
   2.415  // 0x5400 Entry 24 (size 16 bundles) General Exception (5,32,34,36,38,39)
   2.416  ENTRY(vmx_general_exception)
   2.417 @@ -716,106 +716,106 @@ ENTRY(vmx_general_exception)
   2.418  //    VMX_FAULT(24)
   2.419  END(vmx_general_exception)
   2.420  
   2.421 -	.org vmx_ia64_ivt+0x5500
   2.422 +    .org vmx_ia64_ivt+0x5500
   2.423  /////////////////////////////////////////////////////////////////////////////////////////
   2.424  // 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35)
   2.425  ENTRY(vmx_disabled_fp_reg)
   2.426 -	VMX_DBG_FAULT(25)
   2.427 -	VMX_REFLECT(25)
   2.428 +    VMX_DBG_FAULT(25)
   2.429 +    VMX_REFLECT(25)
   2.430  END(vmx_disabled_fp_reg)
   2.431  
   2.432 -	.org vmx_ia64_ivt+0x5600
   2.433 +    .org vmx_ia64_ivt+0x5600
   2.434  /////////////////////////////////////////////////////////////////////////////////////////
   2.435  // 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50)
   2.436  ENTRY(vmx_nat_consumption)
   2.437 -	VMX_DBG_FAULT(26)
   2.438 -	VMX_REFLECT(26)
   2.439 +    VMX_DBG_FAULT(26)
   2.440 +    VMX_REFLECT(26)
   2.441  END(vmx_nat_consumption)
   2.442  
   2.443 -	.org vmx_ia64_ivt+0x5700
   2.444 +    .org vmx_ia64_ivt+0x5700
   2.445  /////////////////////////////////////////////////////////////////////////////////////////
   2.446  // 0x5700 Entry 27 (size 16 bundles) Speculation (40)
   2.447  ENTRY(vmx_speculation_vector)
   2.448 -	VMX_DBG_FAULT(27)
   2.449 -	VMX_REFLECT(27)
   2.450 +    VMX_DBG_FAULT(27)
   2.451 +    VMX_REFLECT(27)
   2.452  END(vmx_speculation_vector)
   2.453  
   2.454 -	.org vmx_ia64_ivt+0x5800
   2.455 +    .org vmx_ia64_ivt+0x5800
   2.456  /////////////////////////////////////////////////////////////////////////////////////////
   2.457  // 0x5800 Entry 28 (size 16 bundles) Reserved
   2.458      VMX_DBG_FAULT(28)
   2.459 -	VMX_FAULT(28)
   2.460 +    VMX_FAULT(28)
   2.461  
   2.462 -	.org vmx_ia64_ivt+0x5900
   2.463 +    .org vmx_ia64_ivt+0x5900
   2.464  /////////////////////////////////////////////////////////////////////////////////////////
   2.465  // 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56)
   2.466  ENTRY(vmx_debug_vector)
   2.467      VMX_DBG_FAULT(29)
   2.468 -	VMX_FAULT(29)
   2.469 +    VMX_FAULT(29)
   2.470  END(vmx_debug_vector)
   2.471  
   2.472 -	.org vmx_ia64_ivt+0x5a00
   2.473 +    .org vmx_ia64_ivt+0x5a00
   2.474  /////////////////////////////////////////////////////////////////////////////////////////
   2.475  // 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57)
   2.476  ENTRY(vmx_unaligned_access)
   2.477 -	VMX_DBG_FAULT(30)
   2.478 -	VMX_REFLECT(30)
   2.479 +    VMX_DBG_FAULT(30)
   2.480 +    VMX_REFLECT(30)
   2.481  END(vmx_unaligned_access)
   2.482  
   2.483 -	.org vmx_ia64_ivt+0x5b00
   2.484 +    .org vmx_ia64_ivt+0x5b00
   2.485  /////////////////////////////////////////////////////////////////////////////////////////
   2.486  // 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57)
   2.487  ENTRY(vmx_unsupported_data_reference)
   2.488 -	VMX_DBG_FAULT(31)
   2.489 -	VMX_REFLECT(31)
   2.490 +    VMX_DBG_FAULT(31)
   2.491 +    VMX_REFLECT(31)
   2.492  END(vmx_unsupported_data_reference)
   2.493  
   2.494 -	.org vmx_ia64_ivt+0x5c00
   2.495 +    .org vmx_ia64_ivt+0x5c00
   2.496  /////////////////////////////////////////////////////////////////////////////////////////
   2.497  // 0x5c00 Entry 32 (size 16 bundles) Floating-Point Fault (64)
   2.498  ENTRY(vmx_floating_point_fault)
   2.499 -	VMX_DBG_FAULT(32)
   2.500 -	VMX_REFLECT(32)
   2.501 +    VMX_DBG_FAULT(32)
   2.502 +    VMX_REFLECT(32)
   2.503  END(vmx_floating_point_fault)
   2.504  
   2.505 -	.org vmx_ia64_ivt+0x5d00
   2.506 +    .org vmx_ia64_ivt+0x5d00
   2.507  /////////////////////////////////////////////////////////////////////////////////////////
   2.508  // 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66)
   2.509  ENTRY(vmx_floating_point_trap)
   2.510 -	VMX_DBG_FAULT(33)
   2.511 -	VMX_REFLECT(33)
   2.512 +    VMX_DBG_FAULT(33)
   2.513 +    VMX_REFLECT(33)
   2.514  END(vmx_floating_point_trap)
   2.515  
   2.516 -	.org vmx_ia64_ivt+0x5e00
   2.517 +    .org vmx_ia64_ivt+0x5e00
   2.518  /////////////////////////////////////////////////////////////////////////////////////////
   2.519  // 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Transfer Trap (66)
   2.520  ENTRY(vmx_lower_privilege_trap)
   2.521 -	VMX_DBG_FAULT(34)
   2.522 -	VMX_REFLECT(34)
   2.523 +    VMX_DBG_FAULT(34)
   2.524 +    VMX_REFLECT(34)
   2.525  END(vmx_lower_privilege_trap)
   2.526  
   2.527 -	.org vmx_ia64_ivt+0x5f00
   2.528 +    .org vmx_ia64_ivt+0x5f00
   2.529  /////////////////////////////////////////////////////////////////////////////////////////
   2.530  // 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68)
   2.531  ENTRY(vmx_taken_branch_trap)
   2.532 -	VMX_DBG_FAULT(35)
   2.533 -	VMX_REFLECT(35)
   2.534 +    VMX_DBG_FAULT(35)
   2.535 +    VMX_REFLECT(35)
   2.536  END(vmx_taken_branch_trap)
   2.537  
   2.538 -	.org vmx_ia64_ivt+0x6000
   2.539 +    .org vmx_ia64_ivt+0x6000
   2.540  /////////////////////////////////////////////////////////////////////////////////////////
   2.541  // 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69)
   2.542  ENTRY(vmx_single_step_trap)
   2.543 -	VMX_DBG_FAULT(36)
   2.544 -	VMX_REFLECT(36)
   2.545 +    VMX_DBG_FAULT(36)
   2.546 +    VMX_REFLECT(36)
   2.547  END(vmx_single_step_trap)
   2.548  
   2.549 -	.org vmx_ia64_ivt+0x6100
   2.550 +    .org vmx_ia64_ivt+0x6100
   2.551  /////////////////////////////////////////////////////////////////////////////////////////
   2.552  // 0x6100 Entry 37 (size 16 bundles) Virtualization Fault
   2.553  ENTRY(vmx_virtualization_fault)
   2.554  //    VMX_DBG_FAULT(37)
   2.555 -	mov r31=pr
   2.556 +    mov r31=pr
   2.557      mov r19=37
   2.558      adds r16 = IA64_VCPU_CAUSE_OFFSET,r21
   2.559      adds r17 = IA64_VCPU_OPCODE_OFFSET,r21
   2.560 @@ -826,197 +826,197 @@ ENTRY(vmx_virtualization_fault)
   2.561      br.sptk vmx_dispatch_virtualization_fault
   2.562  END(vmx_virtualization_fault)
   2.563  
   2.564 -	.org vmx_ia64_ivt+0x6200
   2.565 +    .org vmx_ia64_ivt+0x6200
   2.566  /////////////////////////////////////////////////////////////////////////////////////////
   2.567  // 0x6200 Entry 38 (size 16 bundles) Reserved
   2.568 -	VMX_DBG_FAULT(38)
   2.569 -	VMX_FAULT(38)
   2.570 +    VMX_DBG_FAULT(38)
   2.571 +    VMX_FAULT(38)
   2.572  
   2.573 -	.org vmx_ia64_ivt+0x6300
   2.574 +    .org vmx_ia64_ivt+0x6300
   2.575  /////////////////////////////////////////////////////////////////////////////////////////
   2.576  // 0x6300 Entry 39 (size 16 bundles) Reserved
   2.577 -	VMX_DBG_FAULT(39)
   2.578 -	VMX_FAULT(39)
   2.579 +    VMX_DBG_FAULT(39)
   2.580 +    VMX_FAULT(39)
   2.581  
   2.582 -	.org vmx_ia64_ivt+0x6400
   2.583 +    .org vmx_ia64_ivt+0x6400
   2.584  /////////////////////////////////////////////////////////////////////////////////////////
   2.585  // 0x6400 Entry 40 (size 16 bundles) Reserved
   2.586 -	VMX_DBG_FAULT(40)
   2.587 -	VMX_FAULT(40)
   2.588 +    VMX_DBG_FAULT(40)
   2.589 +    VMX_FAULT(40)
   2.590  
   2.591 -	.org vmx_ia64_ivt+0x6500
   2.592 +    .org vmx_ia64_ivt+0x6500
   2.593  /////////////////////////////////////////////////////////////////////////////////////////
   2.594  // 0x6500 Entry 41 (size 16 bundles) Reserved
   2.595 -	VMX_DBG_FAULT(41)
   2.596 -	VMX_FAULT(41)
   2.597 +    VMX_DBG_FAULT(41)
   2.598 +    VMX_FAULT(41)
   2.599  
   2.600 -	.org vmx_ia64_ivt+0x6600
   2.601 +    .org vmx_ia64_ivt+0x6600
   2.602  /////////////////////////////////////////////////////////////////////////////////////////
   2.603  // 0x6600 Entry 42 (size 16 bundles) Reserved
   2.604 -	VMX_DBG_FAULT(42)
   2.605 -	VMX_FAULT(42)
   2.606 +    VMX_DBG_FAULT(42)
   2.607 +    VMX_FAULT(42)
   2.608  
   2.609 -	.org vmx_ia64_ivt+0x6700
   2.610 +    .org vmx_ia64_ivt+0x6700
   2.611  /////////////////////////////////////////////////////////////////////////////////////////
   2.612  // 0x6700 Entry 43 (size 16 bundles) Reserved
   2.613 -	VMX_DBG_FAULT(43)
   2.614 -	VMX_FAULT(43)
   2.615 +    VMX_DBG_FAULT(43)
   2.616 +    VMX_FAULT(43)
   2.617  
   2.618 -	.org vmx_ia64_ivt+0x6800
   2.619 +    .org vmx_ia64_ivt+0x6800
   2.620  /////////////////////////////////////////////////////////////////////////////////////////
   2.621  // 0x6800 Entry 44 (size 16 bundles) Reserved
   2.622 -	VMX_DBG_FAULT(44)
   2.623 -	VMX_FAULT(44)
   2.624 +    VMX_DBG_FAULT(44)
   2.625 +    VMX_FAULT(44)
   2.626  
   2.627 -	.org vmx_ia64_ivt+0x6900
   2.628 +    .org vmx_ia64_ivt+0x6900
   2.629  /////////////////////////////////////////////////////////////////////////////////////////
   2.630  // 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,44,58,60,61,62,72,73,75,76,77)
   2.631  ENTRY(vmx_ia32_exception)
   2.632 -	VMX_DBG_FAULT(45)
   2.633 -	VMX_FAULT(45)
   2.634 +    VMX_DBG_FAULT(45)
   2.635 +    VMX_FAULT(45)
   2.636  END(vmx_ia32_exception)
   2.637  
   2.638 -	.org vmx_ia64_ivt+0x6a00
   2.639 +    .org vmx_ia64_ivt+0x6a00
   2.640  /////////////////////////////////////////////////////////////////////////////////////////
   2.641  // 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept  (30,31,59,70,71)
   2.642  ENTRY(vmx_ia32_intercept)
   2.643 -	VMX_DBG_FAULT(46)
   2.644 -	VMX_FAULT(46)
   2.645 +    VMX_DBG_FAULT(46)
   2.646 +    VMX_FAULT(46)
   2.647  END(vmx_ia32_intercept)
   2.648  
   2.649 -	.org vmx_ia64_ivt+0x6b00
   2.650 +    .org vmx_ia64_ivt+0x6b00
   2.651  /////////////////////////////////////////////////////////////////////////////////////////
   2.652  // 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt  (74)
   2.653  ENTRY(vmx_ia32_interrupt)
   2.654 -	VMX_DBG_FAULT(47)
   2.655 -	VMX_FAULT(47)
   2.656 +    VMX_DBG_FAULT(47)
   2.657 +    VMX_FAULT(47)
   2.658  END(vmx_ia32_interrupt)
   2.659  
   2.660 -	.org vmx_ia64_ivt+0x6c00
   2.661 +    .org vmx_ia64_ivt+0x6c00
   2.662  /////////////////////////////////////////////////////////////////////////////////////////
   2.663  // 0x6c00 Entry 48 (size 16 bundles) Reserved
   2.664 -	VMX_DBG_FAULT(48)
   2.665 -	VMX_FAULT(48)
   2.666 +    VMX_DBG_FAULT(48)
   2.667 +    VMX_FAULT(48)
   2.668  
   2.669 -	.org vmx_ia64_ivt+0x6d00
   2.670 +    .org vmx_ia64_ivt+0x6d00
   2.671  /////////////////////////////////////////////////////////////////////////////////////////
   2.672  // 0x6d00 Entry 49 (size 16 bundles) Reserved
   2.673 -	VMX_DBG_FAULT(49)
   2.674 -	VMX_FAULT(49)
   2.675 +    VMX_DBG_FAULT(49)
   2.676 +    VMX_FAULT(49)
   2.677  
   2.678 -	.org vmx_ia64_ivt+0x6e00
   2.679 +    .org vmx_ia64_ivt+0x6e00
   2.680  /////////////////////////////////////////////////////////////////////////////////////////
   2.681  // 0x6e00 Entry 50 (size 16 bundles) Reserved
   2.682 -	VMX_DBG_FAULT(50)
   2.683 -	VMX_FAULT(50)
   2.684 +    VMX_DBG_FAULT(50)
   2.685 +    VMX_FAULT(50)
   2.686  
   2.687 -	.org vmx_ia64_ivt+0x6f00
   2.688 +    .org vmx_ia64_ivt+0x6f00
   2.689  /////////////////////////////////////////////////////////////////////////////////////////
   2.690  // 0x6f00 Entry 51 (size 16 bundles) Reserved
   2.691 -	VMX_DBG_FAULT(51)
   2.692 -	VMX_FAULT(51)
   2.693 +    VMX_DBG_FAULT(51)
   2.694 +    VMX_FAULT(51)
   2.695  
   2.696 -	.org vmx_ia64_ivt+0x7000
   2.697 +    .org vmx_ia64_ivt+0x7000
   2.698  /////////////////////////////////////////////////////////////////////////////////////////
   2.699  // 0x7000 Entry 52 (size 16 bundles) Reserved
   2.700 -	VMX_DBG_FAULT(52)
   2.701 -	VMX_FAULT(52)
   2.702 +    VMX_DBG_FAULT(52)
   2.703 +    VMX_FAULT(52)
   2.704  
   2.705 -	.org vmx_ia64_ivt+0x7100
   2.706 +    .org vmx_ia64_ivt+0x7100
   2.707  /////////////////////////////////////////////////////////////////////////////////////////
   2.708  // 0x7100 Entry 53 (size 16 bundles) Reserved
   2.709 -	VMX_DBG_FAULT(53)
   2.710 -	VMX_FAULT(53)
   2.711 +    VMX_DBG_FAULT(53)
   2.712 +    VMX_FAULT(53)
   2.713  
   2.714 -	.org vmx_ia64_ivt+0x7200
   2.715 +    .org vmx_ia64_ivt+0x7200
   2.716  /////////////////////////////////////////////////////////////////////////////////////////
   2.717  // 0x7200 Entry 54 (size 16 bundles) Reserved
   2.718 -	VMX_DBG_FAULT(54)
   2.719 -	VMX_FAULT(54)
   2.720 +    VMX_DBG_FAULT(54)
   2.721 +    VMX_FAULT(54)
   2.722  
   2.723 -	.org vmx_ia64_ivt+0x7300
   2.724 +    .org vmx_ia64_ivt+0x7300
   2.725  /////////////////////////////////////////////////////////////////////////////////////////
   2.726  // 0x7300 Entry 55 (size 16 bundles) Reserved
   2.727 -	VMX_DBG_FAULT(55)
   2.728 -	VMX_FAULT(55)
   2.729 +    VMX_DBG_FAULT(55)
   2.730 +    VMX_FAULT(55)
   2.731  
   2.732 -	.org vmx_ia64_ivt+0x7400
   2.733 +    .org vmx_ia64_ivt+0x7400
   2.734  /////////////////////////////////////////////////////////////////////////////////////////
   2.735  // 0x7400 Entry 56 (size 16 bundles) Reserved
   2.736 -	VMX_DBG_FAULT(56)
   2.737 -	VMX_FAULT(56)
   2.738 +    VMX_DBG_FAULT(56)
   2.739 +    VMX_FAULT(56)
   2.740  
   2.741 -	.org vmx_ia64_ivt+0x7500
   2.742 +    .org vmx_ia64_ivt+0x7500
   2.743  /////////////////////////////////////////////////////////////////////////////////////////
   2.744  // 0x7500 Entry 57 (size 16 bundles) Reserved
   2.745 -	VMX_DBG_FAULT(57)
   2.746 -	VMX_FAULT(57)
   2.747 +    VMX_DBG_FAULT(57)
   2.748 +    VMX_FAULT(57)
   2.749  
   2.750 -	.org vmx_ia64_ivt+0x7600
   2.751 +    .org vmx_ia64_ivt+0x7600
   2.752  /////////////////////////////////////////////////////////////////////////////////////////
   2.753  // 0x7600 Entry 58 (size 16 bundles) Reserved
   2.754 -	VMX_DBG_FAULT(58)
   2.755 -	VMX_FAULT(58)
   2.756 +    VMX_DBG_FAULT(58)
   2.757 +    VMX_FAULT(58)
   2.758  
   2.759 -	.org vmx_ia64_ivt+0x7700
   2.760 +    .org vmx_ia64_ivt+0x7700
   2.761  /////////////////////////////////////////////////////////////////////////////////////////
   2.762  // 0x7700 Entry 59 (size 16 bundles) Reserved
   2.763 -	VMX_DBG_FAULT(59)
   2.764 -	VMX_FAULT(59)
   2.765 +    VMX_DBG_FAULT(59)
   2.766 +    VMX_FAULT(59)
   2.767  
   2.768 -	.org vmx_ia64_ivt+0x7800
   2.769 +    .org vmx_ia64_ivt+0x7800
   2.770  /////////////////////////////////////////////////////////////////////////////////////////
   2.771  // 0x7800 Entry 60 (size 16 bundles) Reserved
   2.772 -	VMX_DBG_FAULT(60)
   2.773 -	VMX_FAULT(60)
   2.774 +    VMX_DBG_FAULT(60)
   2.775 +    VMX_FAULT(60)
   2.776  
   2.777 -	.org vmx_ia64_ivt+0x7900
   2.778 +    .org vmx_ia64_ivt+0x7900
   2.779  /////////////////////////////////////////////////////////////////////////////////////////
   2.780  // 0x7900 Entry 61 (size 16 bundles) Reserved
   2.781 -	VMX_DBG_FAULT(61)
   2.782 -	VMX_FAULT(61)
   2.783 +    VMX_DBG_FAULT(61)
   2.784 +    VMX_FAULT(61)
   2.785  
   2.786 -	.org vmx_ia64_ivt+0x7a00
   2.787 +    .org vmx_ia64_ivt+0x7a00
   2.788  /////////////////////////////////////////////////////////////////////////////////////////
   2.789  // 0x7a00 Entry 62 (size 16 bundles) Reserved
   2.790 -	VMX_DBG_FAULT(62)
   2.791 -	VMX_FAULT(62)
   2.792 +    VMX_DBG_FAULT(62)
   2.793 +    VMX_FAULT(62)
   2.794  
   2.795 -	.org vmx_ia64_ivt+0x7b00
   2.796 +    .org vmx_ia64_ivt+0x7b00
   2.797  /////////////////////////////////////////////////////////////////////////////////////////
   2.798  // 0x7b00 Entry 63 (size 16 bundles) Reserved
   2.799 -	VMX_DBG_FAULT(63)
   2.800 -	VMX_FAULT(63)
   2.801 +    VMX_DBG_FAULT(63)
   2.802 +    VMX_FAULT(63)
   2.803  
   2.804 -	.org vmx_ia64_ivt+0x7c00
   2.805 +    .org vmx_ia64_ivt+0x7c00
   2.806  /////////////////////////////////////////////////////////////////////////////////////////
   2.807  // 0x7c00 Entry 64 (size 16 bundles) Reserved
   2.808      VMX_DBG_FAULT(64)
   2.809 -	VMX_FAULT(64)
   2.810 +    VMX_FAULT(64)
   2.811  
   2.812 -	.org vmx_ia64_ivt+0x7d00
   2.813 +    .org vmx_ia64_ivt+0x7d00
   2.814  /////////////////////////////////////////////////////////////////////////////////////////
   2.815  // 0x7d00 Entry 65 (size 16 bundles) Reserved
   2.816 -	VMX_DBG_FAULT(65)
   2.817 -	VMX_FAULT(65)
   2.818 +    VMX_DBG_FAULT(65)
   2.819 +    VMX_FAULT(65)
   2.820  
   2.821 -	.org vmx_ia64_ivt+0x7e00
   2.822 +    .org vmx_ia64_ivt+0x7e00
   2.823  /////////////////////////////////////////////////////////////////////////////////////////
   2.824  // 0x7e00 Entry 66 (size 16 bundles) Reserved
   2.825 -	VMX_DBG_FAULT(66)
   2.826 -	VMX_FAULT(66)
   2.827 +    VMX_DBG_FAULT(66)
   2.828 +    VMX_FAULT(66)
   2.829  
   2.830 -	.org vmx_ia64_ivt+0x7f00
   2.831 +    .org vmx_ia64_ivt+0x7f00
   2.832  /////////////////////////////////////////////////////////////////////////////////////////
   2.833  // 0x7f00 Entry 67 (size 16 bundles) Reserved
   2.834 -	VMX_DBG_FAULT(67)
   2.835 -	VMX_FAULT(67)
   2.836 +    VMX_DBG_FAULT(67)
   2.837 +    VMX_FAULT(67)
   2.838  
   2.839 -	.org vmx_ia64_ivt+0x8000
   2.840 -    // There is no particular reason for this code to be here, other than that
   2.841 -    // there happens to be space here that would go unused otherwise.  If this
   2.842 -    // fault ever gets "unreserved", simply moved the following code to a more
   2.843 -    // suitable spot...
   2.844 +    .org vmx_ia64_ivt+0x8000
   2.845 +// There is no particular reason for this code to be here, other than that
   2.846 +// there happens to be space here that would go unused otherwise.  If this
   2.847 +// fault ever gets "unreserved", simply moved the following code to a more
   2.848 +// suitable spot...
   2.849  
   2.850  
   2.851  ENTRY(vmx_dispatch_reflection)
   2.852 @@ -1165,24 +1165,24 @@ END(vmx_hypercall_dispatch)
   2.853  
   2.854  
   2.855  ENTRY(vmx_dispatch_interrupt)
   2.856 -	VMX_SAVE_MIN_WITH_COVER_R19	// uses r31; defines r2 and r3
   2.857 -	;;
   2.858 -	alloc r14=ar.pfs,0,0,2,0 // must be first in an insn group
   2.859 -	mov out0=cr.ivr		// pass cr.ivr as first arg
   2.860 -	adds r3=8,r2		// set up second base pointer for SAVE_REST
   2.861 +    VMX_SAVE_MIN_WITH_COVER_R19	// uses r31; defines r2 and r3
   2.862      ;;
   2.863 -	ssm psr.ic
   2.864 -	;;
   2.865 +    alloc r14=ar.pfs,0,0,2,0 // must be first in an insn group
   2.866 +    mov out0=cr.ivr		// pass cr.ivr as first arg
   2.867 +    adds r3=8,r2		// set up second base pointer for SAVE_REST
   2.868 +    ;;
   2.869 +    ssm psr.ic
   2.870 +    ;;
   2.871      srlz.i
   2.872      ;;
   2.873      (p15) ssm psr.i
   2.874 -	movl r14=ia64_leave_hypervisor
   2.875 -	;;
   2.876 -	VMX_SAVE_REST
   2.877 -	mov rp=r14
   2.878 -	;;
   2.879 -	add out1=16,sp		// pass pointer to pt_regs as second arg
   2.880 -	br.call.sptk.many b6=ia64_handle_irq
   2.881 +    movl r14=ia64_leave_hypervisor
   2.882 +    ;;
   2.883 +    VMX_SAVE_REST
   2.884 +    mov rp=r14
   2.885 +    ;;
   2.886 +    add out1=16,sp		// pass pointer to pt_regs as second arg
   2.887 +    br.call.sptk.many b6=ia64_handle_irq
   2.888  END(vmx_dispatch_interrupt)
   2.889  
   2.890  
     3.1 --- a/xen/arch/ia64/vmx/vmx_process.c	Fri May 26 13:41:49 2006 -0600
     3.2 +++ b/xen/arch/ia64/vmx/vmx_process.c	Tue May 30 08:46:21 2006 -0600
     3.3 @@ -183,12 +183,12 @@ vmx_ia64_handle_break (unsigned long ifa
     3.4      struct vcpu *v = current;
     3.5  
     3.6  #ifdef CRASH_DEBUG
     3.7 -	if ((iim == 0 || iim == CDB_BREAK_NUM) && !user_mode(regs) &&
     3.8 +    if ((iim == 0 || iim == CDB_BREAK_NUM) && !user_mode(regs) &&
     3.9          IS_VMM_ADDRESS(regs->cr_iip)) {
    3.10 -		if (iim == 0)
    3.11 -			show_registers(regs);
    3.12 -		debugger_trap_fatal(0 /* don't care */, regs);
    3.13 -	} else
    3.14 +        if (iim == 0)
    3.15 +            show_registers(regs);
    3.16 +        debugger_trap_fatal(0 /* don't care */, regs);
    3.17 +    } else
    3.18  #endif
    3.19      {
    3.20          if (iim == 0) 
    3.21 @@ -247,45 +247,45 @@ void save_banked_regs_to_vpd(VCPU *v, RE
    3.22  // NEVER successful if already reflecting a trap/fault because psr.i==0
    3.23  void leave_hypervisor_tail(struct pt_regs *regs)
    3.24  {
    3.25 -	struct domain *d = current->domain;
    3.26 -	struct vcpu *v = current;
    3.27 -	// FIXME: Will this work properly if doing an RFI???
    3.28 -	if (!is_idle_domain(d) ) {	// always comes from guest
    3.29 -	        extern void vmx_dorfirfi(void);
    3.30 -		struct pt_regs *user_regs = vcpu_regs(current);
    3.31 - 		if (local_softirq_pending())
    3.32 - 			do_softirq();
    3.33 -		local_irq_disable();
    3.34 - 
    3.35 -		if (user_regs != regs)
    3.36 -			printk("WARNING: checking pending interrupt in nested interrupt!!!\n");
    3.37 +    struct domain *d = current->domain;
    3.38 +    struct vcpu *v = current;
    3.39 +    // FIXME: Will this work properly if doing an RFI???
    3.40 +    if (!is_idle_domain(d) ) {	// always comes from guest
    3.41 +        extern void vmx_dorfirfi(void);
    3.42 +        struct pt_regs *user_regs = vcpu_regs(current);
    3.43 +        if (local_softirq_pending())
    3.44 +            do_softirq();
    3.45 +        local_irq_disable();
    3.46  
    3.47 -		/* VMX Domain N has other interrupt source, saying DM  */
    3.48 -                if (test_bit(ARCH_VMX_INTR_ASSIST, &v->arch.arch_vmx.flags))
    3.49 +        if (user_regs != regs)
    3.50 +            printk("WARNING: checking pending interrupt in nested interrupt!!!\n");
    3.51 +
    3.52 +        /* VMX Domain N has other interrupt source, saying DM  */
    3.53 +        if (test_bit(ARCH_VMX_INTR_ASSIST, &v->arch.arch_vmx.flags))
    3.54                        vmx_intr_assist(v);
    3.55  
    3.56 - 		/* FIXME: Check event pending indicator, and set
    3.57 - 		 * pending bit if necessary to inject back to guest.
    3.58 - 		 * Should be careful about window between this check
    3.59 - 		 * and above assist, since IOPACKET_PORT shouldn't be
    3.60 - 		 * injected into vmx domain.
    3.61 - 		 *
    3.62 - 		 * Now hardcode the vector as 0x10 temporarily
    3.63 - 		 */
    3.64 -// 		if (event_pending(v)&&(!(VLSAPIC_INSVC(v,0)&(1UL<<0x10)))) {
    3.65 -// 			VCPU(v, irr[0]) |= 1UL << 0x10;
    3.66 -// 			v->arch.irq_new_pending = 1;
    3.67 -// 		}
    3.68 +        /* FIXME: Check event pending indicator, and set
    3.69 +         * pending bit if necessary to inject back to guest.
    3.70 +         * Should be careful about window between this check
    3.71 +         * and above assist, since IOPACKET_PORT shouldn't be
    3.72 +         * injected into vmx domain.
    3.73 +         *
    3.74 +         * Now hardcode the vector as 0x10 temporarily
    3.75 +         */
    3.76 +//       if (event_pending(v)&&(!(VLSAPIC_INSVC(v,0)&(1UL<<0x10)))) {
    3.77 +//           VCPU(v, irr[0]) |= 1UL << 0x10;
    3.78 +//           v->arch.irq_new_pending = 1;
    3.79 +//       }
    3.80  
    3.81 - 		if ( v->arch.irq_new_pending ) {
    3.82 - 			v->arch.irq_new_pending = 0;
    3.83 - 			vmx_check_pending_irq(v);
    3.84 - 		}
    3.85 +        if ( v->arch.irq_new_pending ) {
    3.86 +            v->arch.irq_new_pending = 0;
    3.87 +            vmx_check_pending_irq(v);
    3.88 +        }
    3.89  //        if (VCPU(v,vac).a_bsw){
    3.90  //            save_banked_regs_to_vpd(v,regs);
    3.91  //        }
    3.92  
    3.93 -	}
    3.94 +    }
    3.95  }
    3.96  
    3.97  extern ia64_rr vmx_vcpu_rr(VCPU *vcpu,UINT64 vadr);
     4.1 --- a/xen/include/asm-ia64/vmmu.h	Fri May 26 13:41:49 2006 -0600
     4.2 +++ b/xen/include/asm-ia64/vmmu.h	Tue May 30 08:46:21 2006 -0600
     4.3 @@ -23,15 +23,15 @@
     4.4  #ifndef XEN_TLBthash_H
     4.5  #define XEN_TLBthash_H
     4.6  
     4.7 -#define         MAX_CCN_DEPTH           15       // collision chain depth
     4.8 -#define         VCPU_VTLB_SHIFT          (20)    // 1M for VTLB
     4.9 -#define         VCPU_VTLB_SIZE           (1UL<<VCPU_VTLB_SHIFT)
    4.10 -#define         VCPU_VTLB_ORDER          (VCPU_VTLB_SHIFT - PAGE_SHIFT)
    4.11 -#define         VCPU_VHPT_SHIFT          (24)    // 16M for VTLB
    4.12 -#define         VCPU_VHPT_SIZE           (1UL<<VCPU_VHPT_SHIFT)
    4.13 -#define         VCPU_VHPT_ORDER          (VCPU_VHPT_SHIFT - PAGE_SHIFT)
    4.14 -#define		VTLB(v,_x)		(v->arch.vtlb._x)
    4.15 -#define		VHPT(v,_x)		(v->arch.vhpt._x)
    4.16 +#define     MAX_CCN_DEPTH       (15)       // collision chain depth
    4.17 +#define     VCPU_VTLB_SHIFT     (20)    // 1M for VTLB
    4.18 +#define     VCPU_VTLB_SIZE      (1UL<<VCPU_VTLB_SHIFT)
    4.19 +#define     VCPU_VTLB_ORDER     (VCPU_VTLB_SHIFT - PAGE_SHIFT)
    4.20 +#define     VCPU_VHPT_SHIFT     (24)    // 16M for VTLB
    4.21 +#define     VCPU_VHPT_SIZE      (1UL<<VCPU_VHPT_SHIFT)
    4.22 +#define     VCPU_VHPT_ORDER     (VCPU_VHPT_SHIFT - PAGE_SHIFT)
    4.23 +#define     VTLB(v,_x)          (v->arch.vtlb._x)
    4.24 +#define     VHPT(v,_x)          (v->arch.vhpt._x)
    4.25  #ifndef __ASSEMBLY__
    4.26  
    4.27  #include <xen/config.h>
    4.28 @@ -60,18 +60,18 @@
    4.29  #define LOW_32BITS(x)   bits(x,0,31)
    4.30  
    4.31  typedef union search_section {
    4.32 -        struct {
    4.33 -                u32 tr : 1;
    4.34 -                u32 tc : 1;
    4.35 -                u32 rsv: 30;
    4.36 -        };
    4.37 -        u32     v;
    4.38 +    struct {
    4.39 +        u32 tr : 1;
    4.40 +        u32 tc : 1;
    4.41 +        u32 rsv: 30;
    4.42 +    };
    4.43 +    u32     v;
    4.44  } search_section_t;
    4.45  
    4.46  
    4.47  enum {
    4.48 -        ISIDE_TLB=0,
    4.49 -        DSIDE_TLB=1
    4.50 +    ISIDE_TLB=0,
    4.51 +    DSIDE_TLB=1
    4.52  };
    4.53  #define VTLB_PTE_P_BIT      0
    4.54  #define VTLB_PTE_IO_BIT     60
    4.55 @@ -93,16 +93,15 @@ typedef struct thash_data {
    4.56              u64 ig1  :  3; // 53-63
    4.57          };
    4.58          struct {
    4.59 -            u64 __rv1 : 53;	// 0-52
    4.60 +            u64 __rv1 : 53;     // 0-52
    4.61              u64 contiguous : 1; //53
    4.62 -            u64 tc : 1;     // 54 TR or TC
    4.63 -            u64 cl : 1; // 55 I side or D side cache line
    4.64 -            // next extension to ig1, only for TLB instance
    4.65 -            u64 len  :  4; // 56-59
    4.66 +            u64 tc : 1;         // 54 TR or TC
    4.67 +            u64 cl : 1;         // 55 I side or D side cache line
    4.68 +            u64 len  :  4;      // 56-59
    4.69              u64 io  : 1;	// 60 entry is for io or not
    4.70 -            u64 nomap : 1;   // 61 entry cann't be inserted into machine TLB.
    4.71 -            u64 checked : 1; // 62 for VTLB/VHPT sanity check
    4.72 -            u64 invalid : 1; // 63 invalid entry
    4.73 +            u64 nomap : 1;      // 61 entry cann't be inserted into machine TLB.
    4.74 +            u64 checked : 1;    // 62 for VTLB/VHPT sanity check
    4.75 +            u64 invalid : 1;    // 63 invalid entry
    4.76          };
    4.77          u64 page_flags;
    4.78      };                  // same for VHPT and TLB
    4.79 @@ -114,12 +113,6 @@ typedef struct thash_data {
    4.80              u64 key  : 24; // 8-31
    4.81              u64 rv4  : 32; // 32-63
    4.82          };
    4.83 -//        struct {
    4.84 -//            u64 __rv3  : 32; // 0-31
    4.85 -            // next extension to rv4
    4.86 -//            u64 rid  : 24;  // 32-55
    4.87 -//            u64 __rv4  : 8; // 56-63
    4.88 -//        };
    4.89          u64 itir;
    4.90      };
    4.91      union {
    4.92 @@ -176,8 +169,8 @@ static inline u64 xen_to_arch_ppn(u64 xp
    4.93  }
    4.94  
    4.95  typedef enum {
    4.96 -        THASH_TLB=0,
    4.97 -        THASH_VHPT
    4.98 +    THASH_TLB=0,
    4.99 +    THASH_VHPT
   4.100  } THASH_TYPE;
   4.101  
   4.102  struct thash_cb;
     5.1 --- a/xen/include/asm-ia64/vmx_vcpu.h	Fri May 26 13:41:49 2006 -0600
     5.2 +++ b/xen/include/asm-ia64/vmx_vcpu.h	Tue May 30 08:46:21 2006 -0600
     5.3 @@ -44,7 +44,6 @@
     5.4  #define VRN7    0x7UL
     5.5  // for vlsapic
     5.6  #define  VLSAPIC_INSVC(vcpu, i) ((vcpu)->arch.insvc[i])
     5.7 -//#define	VMX_VPD(x,y)	((x)->arch.arch_vmx.vpd->y)
     5.8  
     5.9  #define VMX(x,y)  ((x)->arch.arch_vmx.y)
    5.10  
    5.11 @@ -228,7 +227,8 @@ IA64FAULT vmx_vcpu_get_lrr0(VCPU *vcpu, 
    5.12  }
    5.13  static inline
    5.14  IA64FAULT vmx_vcpu_get_lrr1(VCPU *vcpu, UINT64 *pval)
    5.15 -{    *pval = VCPU(vcpu,lrr1);
    5.16 +{
    5.17 +    *pval = VCPU(vcpu,lrr1);
    5.18      return (IA64_NO_FAULT);
    5.19  }
    5.20  static inline