ia64/xen-unstable
changeset 236:170eb7974e43
bitkeeper revision 1.94 (3e5a4f5fzVaxemjfCt0N0OH8PYPiuw)
Rename xen-2.4.16 to just "xen" to reflect that it hasn't got any
relation to the Linux kernel version.
Rename xen-2.4.16 to just "xen" to reflect that it hasn't got any
relation to the Linux kernel version.
author | iap10@labyrinth.cl.cam.ac.uk |
---|---|
date | Mon Feb 24 16:59:11 2003 +0000 (2003-02-24) |
parents | d7d0a23b2e07 |
children | 22ebe9dcd444 |
files | .rootkeys xen-2.4.16/Makefile xen-2.4.16/README xen-2.4.16/Rules.mk xen-2.4.16/arch/i386/Makefile xen-2.4.16/arch/i386/Rules.mk xen-2.4.16/arch/i386/acpitable.c xen-2.4.16/arch/i386/acpitable.h xen-2.4.16/arch/i386/apic.c xen-2.4.16/arch/i386/boot/boot.S xen-2.4.16/arch/i386/delay.c xen-2.4.16/arch/i386/entry.S xen-2.4.16/arch/i386/extable.c xen-2.4.16/arch/i386/i387.c xen-2.4.16/arch/i386/i8259.c xen-2.4.16/arch/i386/idle0_task.c xen-2.4.16/arch/i386/io_apic.c xen-2.4.16/arch/i386/ioremap.c xen-2.4.16/arch/i386/irq.c xen-2.4.16/arch/i386/mm.c xen-2.4.16/arch/i386/mpparse.c xen-2.4.16/arch/i386/pci-dma.c xen-2.4.16/arch/i386/pci-i386.c xen-2.4.16/arch/i386/pci-i386.h xen-2.4.16/arch/i386/pci-irq.c xen-2.4.16/arch/i386/pci-pc.c xen-2.4.16/arch/i386/process.c xen-2.4.16/arch/i386/rwlock.c xen-2.4.16/arch/i386/setup.c xen-2.4.16/arch/i386/smp.c xen-2.4.16/arch/i386/smpboot.c xen-2.4.16/arch/i386/time.c xen-2.4.16/arch/i386/trampoline.S xen-2.4.16/arch/i386/traps.c xen-2.4.16/arch/i386/usercopy.c xen-2.4.16/arch/i386/xeno.lds xen-2.4.16/common/Makefile xen-2.4.16/common/ac_timer.c xen-2.4.16/common/block.c xen-2.4.16/common/brlock.c xen-2.4.16/common/dom0_ops.c xen-2.4.16/common/domain.c xen-2.4.16/common/domain_page.c xen-2.4.16/common/event.c xen-2.4.16/common/kernel.c xen-2.4.16/common/keyhandler.c xen-2.4.16/common/lib.c xen-2.4.16/common/memory.c xen-2.4.16/common/network.c xen-2.4.16/common/page_alloc.c xen-2.4.16/common/perfc.c xen-2.4.16/common/resource.c xen-2.4.16/common/schedule.c xen-2.4.16/common/slab.c xen-2.4.16/common/softirq.c xen-2.4.16/common/timer.c xen-2.4.16/common/vsprintf.c xen-2.4.16/drivers/Makefile xen-2.4.16/drivers/block/Makefile xen-2.4.16/drivers/block/blkpg.c xen-2.4.16/drivers/block/elevator.c xen-2.4.16/drivers/block/genhd.c xen-2.4.16/drivers/block/ll_rw_blk.c xen-2.4.16/drivers/block/xen_block.c xen-2.4.16/drivers/char/Makefile xen-2.4.16/drivers/char/xen_kbd.c xen-2.4.16/drivers/char/xen_serial.c xen-2.4.16/drivers/ide/Makefile xen-2.4.16/drivers/ide/ide-disk.c xen-2.4.16/drivers/ide/ide-dma.c xen-2.4.16/drivers/ide/ide-features.c xen-2.4.16/drivers/ide/ide-geometry.c xen-2.4.16/drivers/ide/ide-pci.c xen-2.4.16/drivers/ide/ide-probe.c xen-2.4.16/drivers/ide/ide-taskfile.c xen-2.4.16/drivers/ide/ide-xeno.c xen-2.4.16/drivers/ide/ide.c xen-2.4.16/drivers/ide/ide_modes.h xen-2.4.16/drivers/ide/piix.c xen-2.4.16/drivers/net/3c59x.c xen-2.4.16/drivers/net/Makefile xen-2.4.16/drivers/net/Space.c xen-2.4.16/drivers/net/e1000/LICENSE xen-2.4.16/drivers/net/e1000/Makefile xen-2.4.16/drivers/net/e1000/e1000.h xen-2.4.16/drivers/net/e1000/e1000_ethtool.c xen-2.4.16/drivers/net/e1000/e1000_hw.c xen-2.4.16/drivers/net/e1000/e1000_hw.h xen-2.4.16/drivers/net/e1000/e1000_main.c xen-2.4.16/drivers/net/e1000/e1000_osdep.h xen-2.4.16/drivers/net/e1000/e1000_param.c xen-2.4.16/drivers/net/ne/8390.c xen-2.4.16/drivers/net/ne/8390.h xen-2.4.16/drivers/net/ne/Makefile xen-2.4.16/drivers/net/ne/ne.c xen-2.4.16/drivers/net/net_init.c xen-2.4.16/drivers/net/setup.c xen-2.4.16/drivers/net/tg3.c xen-2.4.16/drivers/net/tg3.h xen-2.4.16/drivers/pci/Makefile xen-2.4.16/drivers/pci/compat.c xen-2.4.16/drivers/pci/gen-devlist.c xen-2.4.16/drivers/pci/names.c xen-2.4.16/drivers/pci/pci.c xen-2.4.16/drivers/pci/pci.ids xen-2.4.16/drivers/pci/proc.c xen-2.4.16/drivers/pci/quirks.c xen-2.4.16/drivers/pci/setup-bus.c xen-2.4.16/drivers/pci/setup-irq.c xen-2.4.16/drivers/pci/setup-res.c xen-2.4.16/drivers/pci/syscall.c xen-2.4.16/drivers/scsi/Makefile xen-2.4.16/drivers/scsi/aacraid/Makefile xen-2.4.16/drivers/scsi/aacraid/README xen-2.4.16/drivers/scsi/aacraid/TODO xen-2.4.16/drivers/scsi/aacraid/aachba.c xen-2.4.16/drivers/scsi/aacraid/aacraid.h xen-2.4.16/drivers/scsi/aacraid/commctrl.c xen-2.4.16/drivers/scsi/aacraid/comminit.c xen-2.4.16/drivers/scsi/aacraid/commsup.c xen-2.4.16/drivers/scsi/aacraid/dpcsup.c xen-2.4.16/drivers/scsi/aacraid/linit.c xen-2.4.16/drivers/scsi/aacraid/rx.c xen-2.4.16/drivers/scsi/aacraid/sa.c xen-2.4.16/drivers/scsi/constants.c xen-2.4.16/drivers/scsi/constants.h xen-2.4.16/drivers/scsi/hosts.c xen-2.4.16/drivers/scsi/hosts.h xen-2.4.16/drivers/scsi/scsi.c xen-2.4.16/drivers/scsi/scsi.h xen-2.4.16/drivers/scsi/scsi_dma.c xen-2.4.16/drivers/scsi/scsi_error.c xen-2.4.16/drivers/scsi/scsi_ioctl.c xen-2.4.16/drivers/scsi/scsi_lib.c xen-2.4.16/drivers/scsi/scsi_merge.c xen-2.4.16/drivers/scsi/scsi_module.c.inc xen-2.4.16/drivers/scsi/scsi_obsolete.h xen-2.4.16/drivers/scsi/scsi_proc.c xen-2.4.16/drivers/scsi/scsi_queue.c xen-2.4.16/drivers/scsi/scsi_scan.c xen-2.4.16/drivers/scsi/scsi_syms.c xen-2.4.16/drivers/scsi/scsicam.c xen-2.4.16/drivers/scsi/sd.c xen-2.4.16/drivers/scsi/sd.h xen-2.4.16/include/asm-i386/apic.h xen-2.4.16/include/asm-i386/apicdef.h xen-2.4.16/include/asm-i386/atomic.h xen-2.4.16/include/asm-i386/bitops.h xen-2.4.16/include/asm-i386/byteorder.h xen-2.4.16/include/asm-i386/cache.h xen-2.4.16/include/asm-i386/cpufeature.h xen-2.4.16/include/asm-i386/current.h xen-2.4.16/include/asm-i386/debugreg.h xen-2.4.16/include/asm-i386/delay.h xen-2.4.16/include/asm-i386/desc.h xen-2.4.16/include/asm-i386/dma.h xen-2.4.16/include/asm-i386/domain_page.h xen-2.4.16/include/asm-i386/elf.h xen-2.4.16/include/asm-i386/fixmap.h xen-2.4.16/include/asm-i386/flushtlb.h xen-2.4.16/include/asm-i386/hardirq.h xen-2.4.16/include/asm-i386/hdreg.h xen-2.4.16/include/asm-i386/i387.h xen-2.4.16/include/asm-i386/ide.h xen-2.4.16/include/asm-i386/io.h xen-2.4.16/include/asm-i386/io_apic.h xen-2.4.16/include/asm-i386/ioctl.h xen-2.4.16/include/asm-i386/irq.h xen-2.4.16/include/asm-i386/mc146818rtc.h xen-2.4.16/include/asm-i386/mpspec.h xen-2.4.16/include/asm-i386/msr.h xen-2.4.16/include/asm-i386/page.h xen-2.4.16/include/asm-i386/param.h xen-2.4.16/include/asm-i386/pci.h xen-2.4.16/include/asm-i386/pgalloc.h xen-2.4.16/include/asm-i386/processor.h xen-2.4.16/include/asm-i386/ptrace.h xen-2.4.16/include/asm-i386/rwlock.h xen-2.4.16/include/asm-i386/scatterlist.h xen-2.4.16/include/asm-i386/smp.h xen-2.4.16/include/asm-i386/smpboot.h xen-2.4.16/include/asm-i386/softirq.h xen-2.4.16/include/asm-i386/spinlock.h xen-2.4.16/include/asm-i386/system.h xen-2.4.16/include/asm-i386/time.h xen-2.4.16/include/asm-i386/timex.h xen-2.4.16/include/asm-i386/types.h xen-2.4.16/include/asm-i386/uaccess.h xen-2.4.16/include/asm-i386/unaligned.h xen-2.4.16/include/hypervisor-ifs/block.h xen-2.4.16/include/hypervisor-ifs/hypervisor-if.h xen-2.4.16/include/hypervisor-ifs/network.h xen-2.4.16/include/scsi/scsi.h xen-2.4.16/include/scsi/scsi_ioctl.h xen-2.4.16/include/scsi/scsicam.h xen-2.4.16/include/scsi/sg.h xen-2.4.16/include/stdarg.h xen-2.4.16/include/xeno/ac_timer.h xen-2.4.16/include/xeno/blk.h xen-2.4.16/include/xeno/blkdev.h xen-2.4.16/include/xeno/blkpg.h xen-2.4.16/include/xeno/block.h xen-2.4.16/include/xeno/brlock.h xen-2.4.16/include/xeno/byteorder/big_endian.h xen-2.4.16/include/xeno/byteorder/generic.h xen-2.4.16/include/xeno/byteorder/little_endian.h xen-2.4.16/include/xeno/byteorder/pdp_endian.h xen-2.4.16/include/xeno/byteorder/swab.h xen-2.4.16/include/xeno/byteorder/swabb.h xen-2.4.16/include/xeno/cache.h xen-2.4.16/include/xeno/config.h xen-2.4.16/include/xeno/ctype.h xen-2.4.16/include/xeno/delay.h xen-2.4.16/include/xeno/dom0_ops.h xen-2.4.16/include/xeno/elevator.h xen-2.4.16/include/xeno/errno.h xen-2.4.16/include/xeno/etherdevice.h xen-2.4.16/include/xeno/ethtool.h xen-2.4.16/include/xeno/event.h xen-2.4.16/include/xeno/genhd.h xen-2.4.16/include/xeno/hdreg.h xen-2.4.16/include/xeno/hdsmart.h xen-2.4.16/include/xeno/ide.h xen-2.4.16/include/xeno/if.h xen-2.4.16/include/xeno/if_ether.h xen-2.4.16/include/xeno/if_packet.h xen-2.4.16/include/xeno/if_vlan.h xen-2.4.16/include/xeno/in.h xen-2.4.16/include/xeno/init.h xen-2.4.16/include/xeno/interrupt.h xen-2.4.16/include/xeno/ioctl.h xen-2.4.16/include/xeno/ioport.h xen-2.4.16/include/xeno/irq.h xen-2.4.16/include/xeno/irq_cpustat.h xen-2.4.16/include/xeno/kdev_t.h xen-2.4.16/include/xeno/kernel.h xen-2.4.16/include/xeno/keyhandler.h xen-2.4.16/include/xeno/lib.h xen-2.4.16/include/xeno/list.h xen-2.4.16/include/xeno/major.h xen-2.4.16/include/xeno/mii.h xen-2.4.16/include/xeno/mm.h xen-2.4.16/include/xeno/module.h xen-2.4.16/include/xeno/multiboot.h xen-2.4.16/include/xeno/netdevice.h xen-2.4.16/include/xeno/notifier.h xen-2.4.16/include/xeno/pci.h xen-2.4.16/include/xeno/pci_ids.h xen-2.4.16/include/xeno/perfc.h xen-2.4.16/include/xeno/perfc_defn.h xen-2.4.16/include/xeno/prefetch.h xen-2.4.16/include/xeno/reboot.h xen-2.4.16/include/xeno/sched.h xen-2.4.16/include/xeno/skbuff.h xen-2.4.16/include/xeno/slab.h xen-2.4.16/include/xeno/smp.h xen-2.4.16/include/xeno/socket.h xen-2.4.16/include/xeno/sockios.h xen-2.4.16/include/xeno/spinlock.h xen-2.4.16/include/xeno/time.h xen-2.4.16/include/xeno/timer.h xen-2.4.16/include/xeno/timex.h xen-2.4.16/include/xeno/tqueue.h xen-2.4.16/include/xeno/types.h xen-2.4.16/include/xeno/vif.h xen-2.4.16/net/Makefile xen-2.4.16/net/dev.c xen-2.4.16/net/dev_mcast.c xen-2.4.16/net/devinit.c xen-2.4.16/net/eth.c xen-2.4.16/net/skbuff.c xen-2.4.16/tools/Makefile xen-2.4.16/tools/elf-reloc.c xen/Makefile xen/README xen/Rules.mk xen/arch/i386/Makefile xen/arch/i386/Rules.mk xen/arch/i386/acpitable.c xen/arch/i386/acpitable.h xen/arch/i386/apic.c xen/arch/i386/boot/boot.S xen/arch/i386/delay.c xen/arch/i386/entry.S xen/arch/i386/extable.c xen/arch/i386/i387.c xen/arch/i386/i8259.c xen/arch/i386/idle0_task.c xen/arch/i386/io_apic.c xen/arch/i386/ioremap.c xen/arch/i386/irq.c xen/arch/i386/mm.c xen/arch/i386/mpparse.c xen/arch/i386/pci-dma.c xen/arch/i386/pci-i386.c xen/arch/i386/pci-i386.h xen/arch/i386/pci-irq.c xen/arch/i386/pci-pc.c xen/arch/i386/process.c xen/arch/i386/rwlock.c xen/arch/i386/setup.c xen/arch/i386/smp.c xen/arch/i386/smpboot.c xen/arch/i386/time.c xen/arch/i386/trampoline.S xen/arch/i386/traps.c xen/arch/i386/usercopy.c xen/arch/i386/xeno.lds xen/common/Makefile xen/common/ac_timer.c xen/common/block.c xen/common/brlock.c xen/common/dom0_ops.c xen/common/domain.c xen/common/domain_page.c xen/common/event.c xen/common/kernel.c xen/common/keyhandler.c xen/common/lib.c xen/common/memory.c xen/common/network.c xen/common/page_alloc.c xen/common/perfc.c xen/common/resource.c xen/common/schedule.c xen/common/slab.c xen/common/softirq.c xen/common/timer.c xen/common/vsprintf.c xen/drivers/Makefile xen/drivers/block/Makefile xen/drivers/block/blkpg.c xen/drivers/block/elevator.c xen/drivers/block/genhd.c xen/drivers/block/ll_rw_blk.c xen/drivers/block/xen_block.c xen/drivers/char/Makefile xen/drivers/char/xen_kbd.c xen/drivers/char/xen_serial.c xen/drivers/ide/Makefile xen/drivers/ide/ide-disk.c xen/drivers/ide/ide-dma.c xen/drivers/ide/ide-features.c xen/drivers/ide/ide-geometry.c xen/drivers/ide/ide-pci.c xen/drivers/ide/ide-probe.c xen/drivers/ide/ide-taskfile.c xen/drivers/ide/ide-xeno.c xen/drivers/ide/ide.c xen/drivers/ide/ide_modes.h xen/drivers/ide/piix.c xen/drivers/net/3c59x.c xen/drivers/net/Makefile xen/drivers/net/Space.c xen/drivers/net/e1000/LICENSE xen/drivers/net/e1000/Makefile xen/drivers/net/e1000/e1000.h xen/drivers/net/e1000/e1000_ethtool.c xen/drivers/net/e1000/e1000_hw.c xen/drivers/net/e1000/e1000_hw.h xen/drivers/net/e1000/e1000_main.c xen/drivers/net/e1000/e1000_osdep.h xen/drivers/net/e1000/e1000_param.c xen/drivers/net/ne/8390.c xen/drivers/net/ne/8390.h xen/drivers/net/ne/Makefile xen/drivers/net/ne/ne.c xen/drivers/net/net_init.c xen/drivers/net/setup.c xen/drivers/net/tg3.c xen/drivers/net/tg3.h xen/drivers/pci/Makefile xen/drivers/pci/compat.c xen/drivers/pci/gen-devlist.c xen/drivers/pci/names.c xen/drivers/pci/pci.c xen/drivers/pci/pci.ids xen/drivers/pci/proc.c xen/drivers/pci/quirks.c xen/drivers/pci/setup-bus.c xen/drivers/pci/setup-irq.c xen/drivers/pci/setup-res.c xen/drivers/pci/syscall.c xen/drivers/scsi/Makefile xen/drivers/scsi/aacraid/Makefile xen/drivers/scsi/aacraid/README xen/drivers/scsi/aacraid/TODO xen/drivers/scsi/aacraid/aachba.c xen/drivers/scsi/aacraid/aacraid.h xen/drivers/scsi/aacraid/commctrl.c xen/drivers/scsi/aacraid/comminit.c xen/drivers/scsi/aacraid/commsup.c xen/drivers/scsi/aacraid/dpcsup.c xen/drivers/scsi/aacraid/linit.c xen/drivers/scsi/aacraid/rx.c xen/drivers/scsi/aacraid/sa.c xen/drivers/scsi/constants.c xen/drivers/scsi/constants.h xen/drivers/scsi/hosts.c xen/drivers/scsi/hosts.h xen/drivers/scsi/scsi.c xen/drivers/scsi/scsi.h xen/drivers/scsi/scsi_dma.c xen/drivers/scsi/scsi_error.c xen/drivers/scsi/scsi_ioctl.c xen/drivers/scsi/scsi_lib.c xen/drivers/scsi/scsi_merge.c xen/drivers/scsi/scsi_module.c.inc xen/drivers/scsi/scsi_obsolete.h xen/drivers/scsi/scsi_proc.c xen/drivers/scsi/scsi_queue.c xen/drivers/scsi/scsi_scan.c xen/drivers/scsi/scsi_syms.c xen/drivers/scsi/scsicam.c xen/drivers/scsi/sd.c xen/drivers/scsi/sd.h xen/include/asm-i386/apic.h xen/include/asm-i386/apicdef.h xen/include/asm-i386/atomic.h xen/include/asm-i386/bitops.h xen/include/asm-i386/byteorder.h xen/include/asm-i386/cache.h xen/include/asm-i386/cpufeature.h xen/include/asm-i386/current.h xen/include/asm-i386/debugreg.h xen/include/asm-i386/delay.h xen/include/asm-i386/desc.h xen/include/asm-i386/dma.h xen/include/asm-i386/domain_page.h xen/include/asm-i386/elf.h xen/include/asm-i386/fixmap.h xen/include/asm-i386/flushtlb.h xen/include/asm-i386/hardirq.h xen/include/asm-i386/hdreg.h xen/include/asm-i386/i387.h xen/include/asm-i386/ide.h xen/include/asm-i386/io.h xen/include/asm-i386/io_apic.h xen/include/asm-i386/ioctl.h xen/include/asm-i386/irq.h xen/include/asm-i386/mc146818rtc.h xen/include/asm-i386/mpspec.h xen/include/asm-i386/msr.h xen/include/asm-i386/page.h xen/include/asm-i386/param.h xen/include/asm-i386/pci.h xen/include/asm-i386/pgalloc.h xen/include/asm-i386/processor.h xen/include/asm-i386/ptrace.h xen/include/asm-i386/rwlock.h xen/include/asm-i386/scatterlist.h xen/include/asm-i386/smp.h xen/include/asm-i386/smpboot.h xen/include/asm-i386/softirq.h xen/include/asm-i386/spinlock.h xen/include/asm-i386/system.h xen/include/asm-i386/time.h xen/include/asm-i386/timex.h xen/include/asm-i386/types.h xen/include/asm-i386/uaccess.h xen/include/asm-i386/unaligned.h xen/include/hypervisor-ifs/block.h xen/include/hypervisor-ifs/hypervisor-if.h xen/include/hypervisor-ifs/network.h xen/include/scsi/scsi.h xen/include/scsi/scsi_ioctl.h xen/include/scsi/scsicam.h xen/include/scsi/sg.h xen/include/stdarg.h xen/include/xeno/ac_timer.h xen/include/xeno/blk.h xen/include/xeno/blkdev.h xen/include/xeno/blkpg.h xen/include/xeno/block.h xen/include/xeno/brlock.h xen/include/xeno/byteorder/big_endian.h xen/include/xeno/byteorder/generic.h xen/include/xeno/byteorder/little_endian.h xen/include/xeno/byteorder/pdp_endian.h xen/include/xeno/byteorder/swab.h xen/include/xeno/byteorder/swabb.h xen/include/xeno/cache.h xen/include/xeno/config.h xen/include/xeno/ctype.h xen/include/xeno/delay.h xen/include/xeno/dom0_ops.h xen/include/xeno/elevator.h xen/include/xeno/errno.h xen/include/xeno/etherdevice.h xen/include/xeno/ethtool.h xen/include/xeno/event.h xen/include/xeno/genhd.h xen/include/xeno/hdreg.h xen/include/xeno/hdsmart.h xen/include/xeno/ide.h xen/include/xeno/if.h xen/include/xeno/if_ether.h xen/include/xeno/if_packet.h xen/include/xeno/if_vlan.h xen/include/xeno/in.h xen/include/xeno/init.h xen/include/xeno/interrupt.h xen/include/xeno/ioctl.h xen/include/xeno/ioport.h xen/include/xeno/irq.h xen/include/xeno/irq_cpustat.h xen/include/xeno/kdev_t.h xen/include/xeno/kernel.h xen/include/xeno/keyhandler.h xen/include/xeno/lib.h xen/include/xeno/list.h xen/include/xeno/major.h xen/include/xeno/mii.h xen/include/xeno/mm.h xen/include/xeno/module.h xen/include/xeno/multiboot.h xen/include/xeno/netdevice.h xen/include/xeno/notifier.h xen/include/xeno/pci.h xen/include/xeno/pci_ids.h xen/include/xeno/perfc.h xen/include/xeno/perfc_defn.h xen/include/xeno/prefetch.h xen/include/xeno/reboot.h xen/include/xeno/sched.h xen/include/xeno/skbuff.h xen/include/xeno/slab.h xen/include/xeno/smp.h xen/include/xeno/socket.h xen/include/xeno/sockios.h xen/include/xeno/spinlock.h xen/include/xeno/time.h xen/include/xeno/timer.h xen/include/xeno/timex.h xen/include/xeno/tqueue.h xen/include/xeno/types.h xen/include/xeno/vif.h xen/net/Makefile xen/net/dev.c xen/net/dev_mcast.c xen/net/devinit.c xen/net/eth.c xen/net/skbuff.c xen/tools/Makefile xen/tools/elf-reloc.c |
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+3ddb79c0CLfAlJLg1ohdPD-Jjn-jxg xen/include/xeno/netdevice.h 1.523 +3e4540ccaugeWGdOuphJKj6WFw1jkw xen/include/xeno/notifier.h 1.524 +3ddb79c2Fg44_PBPVxHSC0gTOMq4Ow xen/include/xeno/pci.h 1.525 +3ddb79c0MOVXq8qZDQRGb6z64_xAwg xen/include/xeno/pci_ids.h 1.526 +3e54c38dlSCVdyVM4PKcrSfzLLxWUQ xen/include/xeno/perfc.h 1.527 +3e54c38de9SUSYSAwxDf_DwkpAnQFA xen/include/xeno/perfc_defn.h 1.528 +3ddb79c04nQVR3EYM5L4zxDV_MCo1g xen/include/xeno/prefetch.h 1.529 +3e4540ccU1sgCx8seIMGlahmMfv7yQ xen/include/xeno/reboot.h 1.530 +3ddb79c0LzqqS0LhAQ50ekgj4oGl7Q xen/include/xeno/sched.h 1.531 +3ddb79c0VDeD-Oft5eNfMneTU3D1dQ xen/include/xeno/skbuff.h 1.532 +3ddb79c14dXIhP7C2ahnoD08K90G_w xen/include/xeno/slab.h 1.533 +3ddb79c09xbS-xxfKxuV3JETIhBzmg xen/include/xeno/smp.h 1.534 +3ddb79c1-yIt89RT02wIPp2xDR8YjQ xen/include/xeno/socket.h 1.535 +3ddb79c2V2P9F2xMCzDJ9vbUofSg_Q xen/include/xeno/sockios.h 1.536 +3ddb79c2iIcESrDAB8samy_yAh6olQ xen/include/xeno/spinlock.h 1.537 +3ddb79c0BnA20PbgmuMPSGIBljNRQw xen/include/xeno/time.h 1.538 +3ddb79c2HFkXuRxi1CriJtSFmY6Ybw xen/include/xeno/timer.h 1.539 +3ddb79c2_m8lT9jDKse_tePj7zcnNQ xen/include/xeno/timex.h 1.540 +3ddb79c2e2C14HkndNEJlYwXaPrF5A xen/include/xeno/tqueue.h 1.541 +3ddb79c1-kVvF8cVa0k3ZHDdBMj01Q xen/include/xeno/types.h 1.542 +3ddb79c2Ae5KpzhC9LCYG7mP_Vi4Aw xen/include/xeno/vif.h 1.543 +3ddb79c4YQCQ6r0xNLLu0jfbM7pVmA xen/net/Makefile 1.544 +3ddb79c4AkfDkTCw0comx4L8wsUOMg xen/net/dev.c 1.545 +3ddb79c4x1L_soh8b-r_1jQW_37Icw xen/net/dev_mcast.c 1.546 +3ddb79c4KZhNxUuYJ7lul8cc-wRkyg xen/net/devinit.c 1.547 +3ddb79c4NSDwiQ-AmrYdxcRAwLPzwQ xen/net/eth.c 1.548 +3ddb79c4TZj1wXPKQt36O72SddtBNQ xen/net/skbuff.c 1.549 +3ddb79c4x8dvwPtzclghWAKFWpEBFA xen/tools/Makefile 1.550 +3ddb79c4yGZ7_22QAFFwPzqP4NSHwA xen/tools/elf-reloc.c 1.551 3e5a4e6589G-U42lFKs43plskXoFxQ xenolinux-2.4.21-pre4-sparse/Makefile 1.552 3e5a4e65IEPjnWPZ5w3TxS5scV8Ewg xenolinux-2.4.21-pre4-sparse/arch/xeno/Makefile 1.553 3e5a4e65n-KhsEAs-A4ULiStBp-r6w xenolinux-2.4.21-pre4-sparse/arch/xeno/boot/Makefile
2.1 --- a/xen-2.4.16/Makefile Mon Feb 24 16:55:07 2003 +0000 2.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 2.3 @@ -1,41 +0,0 @@ 2.4 - 2.5 -export BASEDIR := $(shell pwd) 2.6 - 2.7 -include Rules.mk 2.8 - 2.9 -default: $(TARGET) 2.10 - gzip -f -9 < $(TARGET) > $(TARGET).gz 2.11 -# objdump -D -S image >image.s 2.12 - 2.13 -install: $(TARGET) 2.14 - gzip -f -9 < $(TARGET) > $(TARGET).gz 2.15 - cp $(TARGET).gz ../../install/images/image 2.16 - 2.17 -clean: delete-links 2.18 - $(MAKE) -C tools clean 2.19 - $(MAKE) -C common clean 2.20 - $(MAKE) -C net clean 2.21 - $(MAKE) -C drivers clean 2.22 - $(MAKE) -C arch/$(ARCH) clean 2.23 - rm -f *.o $(TARGET)* *~ core 2.24 - 2.25 -$(TARGET): make-links 2.26 - $(MAKE) -C tools 2.27 - $(MAKE) -C common 2.28 - $(MAKE) -C net 2.29 - $(MAKE) -C drivers 2.30 - $(MAKE) -C arch/$(ARCH) 2.31 - 2.32 -make-links: 2.33 - ln -sf xeno include/linux 2.34 - ln -sf asm-$(ARCH) include/asm 2.35 - 2.36 -delete-links: 2.37 - rm -f include/linux include/asm 2.38 - 2.39 -SUBDIRS =arch common drivers net 2.40 -TAGS: 2.41 - etags `find include/asm-$(ARCH) -name '*.h'` 2.42 - find include -type d \( -name "asm-*" -o -name config \) -prune -o -name '*.h' -print | xargs etags -a 2.43 - find $(SUBDIRS) -name '*.[ch]' | xargs etags -a 2.44 -
3.1 --- a/xen-2.4.16/README Mon Feb 24 16:55:07 2003 +0000 3.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 3.3 @@ -1,145 +0,0 @@ 3.4 - 3.5 -***************************************************** 3.6 - Xeno Hypervisor (18/7/02) 3.7 - 3.8 -1) Tree layout 3.9 -Looks rather like a simplified Linux :-) 3.10 -Headers are in include/xeno and include asm-<arch>. 3.11 -At build time we create symlinks: 3.12 - include/linux -> include/xeno 3.13 - include/asm -> include/asm-<arch> 3.14 -In this way, Linux device drivers should need less tweaking of 3.15 -their #include lines. 3.16 - 3.17 -For source files, mapping between hypervisor and Linux is: 3.18 - Linux Hypervisor 3.19 - ----- ---------- 3.20 - kernel/init/mm/lib -> common 3.21 - net/* -> net/* 3.22 - drivers/* -> drivers/* 3.23 - arch/* -> arch/* 3.24 - 3.25 -Note that the use of #include <asm/...> and #include <linux/...> can 3.26 -lead to confusion, as such files will often exist on the system include 3.27 -path, even if a version doesn't exist within the hypervisor tree. 3.28 -Unfortunately '-nostdinc' cannot be specified to the compiler, as that 3.29 -prevents us using stdarg.h in the compiler's own header directory. 3.30 - 3.31 -We try to not modify things in driver/* as much as possible, so we can 3.32 -easily take updates from Linux. arch/* is basically straight from 3.33 -Linux, with fingers in Linux-specific pies hacked off. common/* has 3.34 -a lot of Linux code in it, but certain subsystems (task maintenance, 3.35 -low-level memory handling) have been replaced. net/* contains enough 3.36 -Linux-like gloop to get network drivers to work with little/no 3.37 -modification. 3.38 - 3.39 -2) Building 3.40 -'make': Builds ELF executable called 'image' in base directory 3.41 -'make install': gzip-compresses 'image' and copies it to TFTP server 3.42 -'make clean': removes *all* build and target files 3.43 - 3.44 - 3.45 -***************************************************** 3.46 -Random thoughts and stuff from here down... 3.47 - 3.48 -Todo list 3.49 ---------- 3.50 -* Hypervisor need only directly map its own memory pool 3.51 - (maybe 128MB, tops). That would need 0x08000000.... 3.52 - This would allow 512MB Linux with plenty room for vmalloc'ed areas. 3.53 -* Network device -- port drivers to hypervisor, implement virtual 3.54 - driver for xeno-linux. Looks like Ethernet. 3.55 - -- Hypervisor needs to do (at a minimum): 3.56 - - packet filtering on tx (unicast IP only) 3.57 - - packet demux on rx (unicast IP only) 3.58 - - provide DHCP [maybedo something simpler?] 3.59 - and ARP [at least for hypervisor IP address] 3.60 - 3.61 - 3.62 -Segment descriptor tables 3.63 -------------------------- 3.64 -We want to allow guest OSes to specify GDT and LDT tables using their 3.65 -own pages of memory (just like with page tables). So allow the following: 3.66 - * new_table_entry(ptr, val) 3.67 - [Allows insertion of a code, data, or LDT descriptor into given 3.68 - location. Can simply be checked then poked, with no need to look at 3.69 - page type.] 3.70 - * new_GDT() -- relevent virtual pages are resolved to frames. Either 3.71 - (i) page not present; or (ii) page is only mapped read-only and checks 3.72 - out okay (then marked as special page). Old table is resolved first, 3.73 - and the pages are unmarked (no longer special type). 3.74 - * new_LDT() -- same as for new_GDT(), with same special page type. 3.75 - 3.76 -Page table updates must be hooked, so we look for updates to virtual page 3.77 -addresses in the GDT/LDT range. If map to not present, then old physpage 3.78 -has type_count decremented. If map to present, ensure read-only, check the 3.79 -page, and set special type. 3.80 - 3.81 -Merge set_{LDT,GDT} into update_baseptr, by passing four args: 3.82 - update_baseptrs(mask, ptab, gdttab, ldttab); 3.83 -Update of ptab requires update of gtab (or set to internal default). 3.84 -Update of gtab requires update of ltab (or set to internal default). 3.85 - 3.86 - 3.87 -The hypervisor page cache 3.88 -------------------------- 3.89 -This will allow guest OSes to make use of spare pages in the system, but 3.90 -allow them to be immediately used for any new domains or memory requests. 3.91 -The idea is that, when a page is laundered and falls off Linux's clean_LRU 3.92 -list, rather than freeing it it becomes a candidate for passing down into 3.93 -the hypervisor. In return, xeno-linux may ask for one of its previously- 3.94 -cached pages back: 3.95 - (page, new_id) = cache_query(page, old_id); 3.96 -If the requested page couldn't be kept, a blank page is returned. 3.97 -When would Linux make the query? Whenever it wants a page back without 3.98 -the delay or going to disc. Also, whenever a page would otherwise be 3.99 -flushed to disc. 3.100 - 3.101 -To try and add to the cache: (blank_page, new_id) = cache_query(page, NULL); 3.102 - [NULL means "give me a blank page"]. 3.103 -To try and retrieve from the cache: (page, new_id) = cache_query(x_page, id) 3.104 - [we may request that x_page just be discarded, and therefore not impinge 3.105 - on this domain's cache quota]. 3.106 - 3.107 - 3.108 -Booting secondary processors 3.109 ----------------------------- 3.110 - 3.111 -start_of_day (i386/setup.c) 3.112 -smp_boot_cpus (i386/smpboot.c) 3.113 - * initialises boot CPU data 3.114 - * parses APIC tables 3.115 - * for each cpu: 3.116 - do_boot_cpu (i386/smpboot.c) 3.117 - * forks a new idle process 3.118 - * points initial stack inside new task struct 3.119 - * points initial EIP at a trampoline in very low memory 3.120 - * frobs remote APIC.... 3.121 - 3.122 -On other processor: 3.123 - * trampoline sets GDT and IDT 3.124 - * jumps at main boot address with magic register value 3.125 - * after setting proper page and descriptor tables, jumps at... 3.126 - initialize_secondary (i386/smpboot.c) 3.127 - * simply reads ESP/EIP out of the (new) idle task 3.128 - * this causes a jump to... 3.129 - start_secondary (i386/smpboot.c) 3.130 - * reset all processor state 3.131 - * barrier, then write bitmasks to signal back to boot cpu 3.132 - * then barrel into... 3.133 - cpu_idle (i386/process.c) 3.134 - [THIS IS PROBABLY REASONABLE -- BOOT CPU SHOULD KICK 3.135 - SECONDARIES TO GET WORK DONE] 3.136 - 3.137 - 3.138 -SMP capabilities 3.139 ----------------- 3.140 - 3.141 -Current intention is to allow hypervisor to schedule on all processors in 3.142 -SMP boxen, but to tie each domain to a single processor. This simplifies 3.143 -many SMP intricacies both in terms of correctness and efficiency (eg. 3.144 -TLB flushing, network packet delivery, ...). 3.145 - 3.146 -Clients can still make use of SMP by installing multiple domains on a single 3.147 -machine, and treating it as a fast cluster (at the very least, the 3.148 -hypervisor will have fast routing of locally-destined packets).
4.1 --- a/xen-2.4.16/Rules.mk Mon Feb 24 16:55:07 2003 +0000 4.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 4.3 @@ -1,36 +0,0 @@ 4.4 - 4.5 -ARCH := i386 4.6 - 4.7 -TARGET := $(BASEDIR)/image 4.8 -HDRS := $(wildcard $(BASEDIR)/include/xeno/*.h) 4.9 -HDRS += $(wildcard $(BASEDIR)/include/scsi/*.h) 4.10 -HDRS += $(wildcard $(BASEDIR)/include/hypervisor-ifs/*.h) 4.11 -HDRS += $(wildcard $(BASEDIR)/include/asm-$(ARCH)/*.h) 4.12 - 4.13 -C_SRCS := $(wildcard *.c) 4.14 -S_SRCS := $(wildcard *.S) 4.15 -OBJS := $(patsubst %.S,%.o,$(S_SRCS)) 4.16 -OBJS += $(patsubst %.c,%.o,$(C_SRCS)) 4.17 - 4.18 -# Note that link order matters! 4.19 -ALL_OBJS := $(BASEDIR)/common/common.o 4.20 -ALL_OBJS += $(BASEDIR)/net/network.o 4.21 -ALL_OBJS += $(BASEDIR)/drivers/char/driver.o 4.22 -ALL_OBJS += $(BASEDIR)/drivers/pci/driver.o 4.23 -ALL_OBJS += $(BASEDIR)/drivers/net/driver.o 4.24 -ALL_OBJS += $(BASEDIR)/drivers/block/driver.o 4.25 -ALL_OBJS += $(BASEDIR)/drivers/ide/driver.o 4.26 -#ALL_OBJS += $(BASEDIR)/drivers/scsi/driver.o 4.27 -ALL_OBJS += $(BASEDIR)/arch/$(ARCH)/arch.o 4.28 - 4.29 -HOSTCC = gcc 4.30 -HOSTCFLAGS = -Wall -Wstrict-prototypes -O2 -fomit-frame-pointer 4.31 - 4.32 -include $(BASEDIR)/arch/$(ARCH)/Rules.mk 4.33 - 4.34 -%.o: %.c $(HDRS) Makefile 4.35 - $(CC) -g $(CFLAGS) -c $< -o $@ 4.36 - 4.37 -%.o: %.S $(HDRS) Makefile 4.38 - $(CC) $(CFLAGS) -D__ASSEMBLY__ -c $< -o $@ 4.39 -
5.1 --- a/xen-2.4.16/arch/i386/Makefile Mon Feb 24 16:55:07 2003 +0000 5.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 5.3 @@ -1,17 +0,0 @@ 5.4 - 5.5 -include $(BASEDIR)/Rules.mk 5.6 - 5.7 -# What happens here? We link monitor object files together, starting 5.8 -# at MONITOR_BASE (a very high address). But bootloader cannot put 5.9 -# things there, so we initially load at LOAD_BASE. A hacky little 5.10 -# tool called `elf-reloc' is used to modify segment offsets from 5.11 -# MONITOR_BASE-relative to LOAD_BASE-relative. 5.12 -# (NB. Linux gets round this by turning its image into raw binary, then 5.13 -# wrapping that with a low-memory bootstrapper.) 5.14 -default: boot/boot.o $(OBJS) 5.15 - $(LD) -r -o arch.o $(OBJS) 5.16 - $(LD) $(LDFLAGS) boot/boot.o $(ALL_OBJS) -o $(TARGET) 5.17 - $(BASEDIR)/tools/elf-reloc $(MONITOR_BASE) $(LOAD_BASE) $(TARGET) 5.18 - 5.19 -clean: 5.20 - rm -f *.o *~ core boot/*.o boot/*~ boot/core
6.1 --- a/xen-2.4.16/arch/i386/Rules.mk Mon Feb 24 16:55:07 2003 +0000 6.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 6.3 @@ -1,14 +0,0 @@ 6.4 -######################################## 6.5 -# x86-specific definitions 6.6 - 6.7 -CC := gcc 6.8 -LD := ld 6.9 -# Linker should relocate monitor to this address 6.10 -MONITOR_BASE := 0xFC500000 6.11 -# Bootloader should load monitor to this real address 6.12 -LOAD_BASE := 0x00100000 6.13 -CFLAGS := -nostdinc -fno-builtin -O3 -Wall -DMONITOR_BASE=$(MONITOR_BASE) 6.14 -CFLAGS += -fomit-frame-pointer -I$(BASEDIR)/include -D__KERNEL__ -DNDEBUG 6.15 -LDFLAGS := -T xeno.lds -N 6.16 - 6.17 -
7.1 --- a/xen-2.4.16/arch/i386/acpitable.c Mon Feb 24 16:55:07 2003 +0000 7.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 7.3 @@ -1,549 +0,0 @@ 7.4 -/* 7.5 - * acpitable.c - IA32-specific ACPI boot-time initialization (Revision: 1) 7.6 - * 7.7 - * Copyright (C) 1999 Andrew Henroid 7.8 - * Copyright (C) 2001 Richard Schaal 7.9 - * Copyright (C) 2001 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> 7.10 - * Copyright (C) 2001 Jun Nakajima <jun.nakajima@intel.com> 7.11 - * Copyright (C) 2001 Arjan van de Ven <arjanv@redhat.com> 7.12 - * 7.13 - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 7.14 - * 7.15 - * This program is free software; you can redistribute it and/or modify 7.16 - * it under the terms of the GNU General Public License as published by 7.17 - * the Free Software Foundation; either version 2 of the License, or 7.18 - * (at your option) any later version. 7.19 - * 7.20 - * This program is distributed in the hope that it will be useful, 7.21 - * but WITHOUT ANY WARRANTY; without even the implied warranty of 7.22 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 7.23 - * GNU General Public License for more details. 7.24 - * 7.25 - * You should have received a copy of the GNU General Public License 7.26 - * along with this program; if not, write to the Free Software 7.27 - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 7.28 - * 7.29 - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 7.30 - * 7.31 - * $Id: acpitable.c,v 1.7 2001/11/04 12:21:18 fenrus Exp $ 7.32 - */ 7.33 -#include <xeno/config.h> 7.34 -#include <xeno/kernel.h> 7.35 -#include <xeno/init.h> 7.36 -#include <xeno/types.h> 7.37 -/*#include <xeno/stddef.h>*/ 7.38 -#include <xeno/slab.h> 7.39 -#include <xeno/pci.h> 7.40 -#include <asm/mpspec.h> 7.41 -#include <asm/io.h> 7.42 -#include <asm/apic.h> 7.43 -#include <asm/apicdef.h> 7.44 -#include <asm/page.h> 7.45 -/*#include <asm/pgtable.h>*/ 7.46 - 7.47 -#include "acpitable.h" 7.48 - 7.49 -static acpi_table_handler acpi_boot_ops[ACPI_TABLE_COUNT]; 7.50 - 7.51 - 7.52 -static unsigned char __init 7.53 -acpi_checksum(void *buffer, int length) 7.54 -{ 7.55 - int i; 7.56 - unsigned char *bytebuffer; 7.57 - unsigned char sum = 0; 7.58 - 7.59 - if (!buffer || length <= 0) 7.60 - return 0; 7.61 - 7.62 - bytebuffer = (unsigned char *) buffer; 7.63 - 7.64 - for (i = 0; i < length; i++) 7.65 - sum += *(bytebuffer++); 7.66 - 7.67 - return sum; 7.68 -} 7.69 - 7.70 -static void __init 7.71 -acpi_print_table_header(acpi_table_header * header) 7.72 -{ 7.73 - if (!header) 7.74 - return; 7.75 - 7.76 - printk(KERN_INFO "ACPI table found: %.4s v%d [%.6s %.8s %d.%d]\n", 7.77 - header->signature, header->revision, header->oem_id, 7.78 - header->oem_table_id, header->oem_revision >> 16, 7.79 - header->oem_revision & 0xffff); 7.80 - 7.81 - return; 7.82 -} 7.83 - 7.84 -/******************************************************************************* 7.85 - * 7.86 - * FUNCTION: acpi_tb_scan_memory_for_rsdp 7.87 - * 7.88 - * PARAMETERS: address - Starting pointer for search 7.89 - * length - Maximum length to search 7.90 - * 7.91 - * RETURN: Pointer to the RSDP if found and valid, otherwise NULL. 7.92 - * 7.93 - * DESCRIPTION: Search a block of memory for the RSDP signature 7.94 - * 7.95 - ******************************************************************************/ 7.96 - 7.97 -static void *__init 7.98 -acpi_tb_scan_memory_for_rsdp(void *address, int length) 7.99 -{ 7.100 - u32 offset; 7.101 - 7.102 - if (length <= 0) 7.103 - return NULL; 7.104 - 7.105 - /* Search from given start addr for the requested length */ 7.106 - 7.107 - offset = 0; 7.108 - 7.109 - while (offset < length) { 7.110 - /* The signature must match and the checksum must be correct */ 7.111 - if (strncmp(address, RSDP_SIG, sizeof(RSDP_SIG) - 1) == 0 && 7.112 - acpi_checksum(address, RSDP_CHECKSUM_LENGTH) == 0) { 7.113 - /* If so, we have found the RSDP */ 7.114 - printk(KERN_INFO "ACPI: RSDP located at physical address %p\n", 7.115 - address); 7.116 - return address; 7.117 - } 7.118 - offset += RSDP_SCAN_STEP; 7.119 - address += RSDP_SCAN_STEP; 7.120 - } 7.121 - 7.122 - /* Searched entire block, no RSDP was found */ 7.123 - printk(KERN_INFO "ACPI: Searched entire block, no RSDP was found.\n"); 7.124 - return NULL; 7.125 -} 7.126 - 7.127 -/******************************************************************************* 7.128 - * 7.129 - * FUNCTION: acpi_find_root_pointer 7.130 - * 7.131 - * PARAMETERS: none 7.132 - * 7.133 - * RETURN: physical address of the RSDP 7.134 - * 7.135 - * DESCRIPTION: Search lower 1_mbyte of memory for the root system descriptor 7.136 - * pointer structure. If it is found, set *RSDP to point to it. 7.137 - * 7.138 - * NOTE: The RSDP must be either in the first 1_k of the Extended 7.139 - * BIOS Data Area or between E0000 and FFFFF (ACPI 1.0 section 7.140 - * 5.2.2; assertion #421). 7.141 - * 7.142 - ******************************************************************************/ 7.143 - 7.144 -static struct acpi_table_rsdp * __init 7.145 -acpi_find_root_pointer(void) 7.146 -{ 7.147 - struct acpi_table_rsdp * rsdp; 7.148 - 7.149 - /* 7.150 - * Physical address is given 7.151 - */ 7.152 - /* 7.153 - * Region 1) Search EBDA (low memory) paragraphs 7.154 - */ 7.155 - rsdp = acpi_tb_scan_memory_for_rsdp(__va(LO_RSDP_WINDOW_BASE), 7.156 - LO_RSDP_WINDOW_SIZE); 7.157 - 7.158 - if (rsdp) 7.159 - return rsdp; 7.160 - 7.161 - /* 7.162 - * Region 2) Search upper memory: 16-byte boundaries in E0000h-F0000h 7.163 - */ 7.164 - rsdp = acpi_tb_scan_memory_for_rsdp(__va(HI_RSDP_WINDOW_BASE), 7.165 - HI_RSDP_WINDOW_SIZE); 7.166 - 7.167 - 7.168 - 7.169 - if (rsdp) 7.170 - return rsdp; 7.171 - 7.172 - printk(KERN_ERR "ACPI: System description tables not found\n"); 7.173 - return NULL; 7.174 -} 7.175 - 7.176 - 7.177 -/* 7.178 - * Temporarily use the virtual area starting from FIX_IO_APIC_BASE_END, 7.179 - * to map the target physical address. The problem is that set_fixmap() 7.180 - * provides a single page, and it is possible that the page is not 7.181 - * sufficient. 7.182 - * By using this area, we can map up to MAX_IO_APICS pages temporarily, 7.183 - * i.e. until the next __va_range() call. 7.184 - * 7.185 - * Important Safety Note: The fixed I/O APIC page numbers are *subtracted* 7.186 - * from the fixed base. That's why we start at FIX_IO_APIC_BASE_END and 7.187 - * count idx down while incrementing the phys address. 7.188 - */ 7.189 -static __init char * 7.190 -__va_range(unsigned long phys, unsigned long size) 7.191 -{ 7.192 - unsigned long base, offset, mapped_size; 7.193 - int idx; 7.194 - 7.195 - offset = phys & (PAGE_SIZE - 1); 7.196 - mapped_size = PAGE_SIZE - offset; 7.197 - set_fixmap(FIX_IO_APIC_BASE_END, phys); 7.198 - base = fix_to_virt(FIX_IO_APIC_BASE_END); 7.199 - dprintk("__va_range(0x%lx, 0x%lx): idx=%d mapped at %lx\n", phys, size, 7.200 - FIX_IO_APIC_BASE_END, base); 7.201 - 7.202 - /* 7.203 - * Most cases can be covered by the below. 7.204 - */ 7.205 - idx = FIX_IO_APIC_BASE_END; 7.206 - while (mapped_size < size) { 7.207 - if (--idx < FIX_IO_APIC_BASE_0) 7.208 - return 0; /* cannot handle this */ 7.209 - phys += PAGE_SIZE; 7.210 - set_fixmap(idx, phys); 7.211 - mapped_size += PAGE_SIZE; 7.212 - } 7.213 - 7.214 - return ((unsigned char *) base + offset); 7.215 -} 7.216 - 7.217 -static int __init acpi_tables_init(void) 7.218 -{ 7.219 - int result = -ENODEV; 7.220 - acpi_table_header *header = NULL; 7.221 - struct acpi_table_rsdp *rsdp = NULL; 7.222 - struct acpi_table_rsdt *rsdt = NULL; 7.223 - struct acpi_table_rsdt saved_rsdt; 7.224 - int tables = 0; 7.225 - int type = 0; 7.226 - int i = 0; 7.227 - 7.228 - 7.229 - rsdp = (struct acpi_table_rsdp *) acpi_find_root_pointer(); 7.230 - 7.231 - if (!rsdp) 7.232 - return -ENODEV; 7.233 - 7.234 - printk(KERN_INFO "%.8s v%d [%.6s]\n", rsdp->signature, rsdp->revision, 7.235 - rsdp->oem_id); 7.236 - 7.237 - if (strncmp(rsdp->signature, RSDP_SIG,strlen(RSDP_SIG))) { 7.238 - printk(KERN_WARNING "RSDP table signature incorrect\n"); 7.239 - return -EINVAL; 7.240 - } 7.241 - 7.242 - rsdt = (struct acpi_table_rsdt *) 7.243 - __va_range(rsdp->rsdt_address, sizeof(struct acpi_table_rsdt)); 7.244 - 7.245 - if (!rsdt) { 7.246 - printk(KERN_WARNING "ACPI: Invalid root system description tables (RSDT)\n"); 7.247 - return -ENODEV; 7.248 - } 7.249 - 7.250 - header = & rsdt->header; 7.251 - acpi_print_table_header(header); 7.252 - 7.253 - if (strncmp(header->signature, RSDT_SIG, strlen(RSDT_SIG))) { 7.254 - printk(KERN_WARNING "ACPI: RSDT signature incorrect\n"); 7.255 - return -ENODEV; 7.256 - } 7.257 - 7.258 - /* 7.259 - * The number of tables is computed by taking the 7.260 - * size of all entries (header size minus total 7.261 - * size of RSDT) divided by the size of each entry 7.262 - * (4-byte table pointers). 7.263 - */ 7.264 - tables = (header->length - sizeof(acpi_table_header)) / 4; 7.265 - 7.266 - memcpy(&saved_rsdt, rsdt, sizeof(saved_rsdt)); 7.267 - 7.268 - if (saved_rsdt.header.length > sizeof(saved_rsdt)) { 7.269 - printk(KERN_WARNING "ACPI: Too big length in RSDT: %d\n", saved_rsdt.header.length); 7.270 - return -ENODEV; 7.271 - } 7.272 - 7.273 - for (i = 0; i < tables; i++) { 7.274 - /* Map in header, then map in full table length. */ 7.275 - header = (acpi_table_header *) 7.276 - __va_range(saved_rsdt.entry[i], 7.277 - sizeof(acpi_table_header)); 7.278 - if (!header) 7.279 - break; 7.280 - header = (acpi_table_header *) 7.281 - __va_range(saved_rsdt.entry[i], header->length); 7.282 - if (!header) 7.283 - break; 7.284 - 7.285 - acpi_print_table_header(header); 7.286 - 7.287 - if (acpi_checksum(header,header->length)) { 7.288 - printk(KERN_WARNING "ACPI %s has invalid checksum\n", 7.289 - acpi_table_signatures[i]); 7.290 - continue; 7.291 - } 7.292 - 7.293 - for (type = 0; type < ACPI_TABLE_COUNT; type++) 7.294 - if (!strncmp((char *) &header->signature, 7.295 - acpi_table_signatures[type],strlen(acpi_table_signatures[type]))) 7.296 - break; 7.297 - 7.298 - if (type >= ACPI_TABLE_COUNT) { 7.299 - printk(KERN_WARNING "ACPI: Unsupported table %.4s\n", 7.300 - header->signature); 7.301 - continue; 7.302 - } 7.303 - 7.304 - 7.305 - if (!acpi_boot_ops[type]) 7.306 - continue; 7.307 - 7.308 - result = acpi_boot_ops[type] (header, 7.309 - (unsigned long) saved_rsdt. 7.310 - entry[i]); 7.311 - } 7.312 - 7.313 - return result; 7.314 -} 7.315 - 7.316 -static int total_cpus __initdata = 0; 7.317 -int have_acpi_tables; 7.318 - 7.319 -extern void __init MP_processor_info(struct mpc_config_processor *); 7.320 - 7.321 -static void __init 7.322 -acpi_parse_lapic(struct acpi_table_lapic *local_apic) 7.323 -{ 7.324 - struct mpc_config_processor proc_entry; 7.325 - int ix = 0; 7.326 - 7.327 - if (!local_apic) 7.328 - return; 7.329 - 7.330 - printk(KERN_INFO "LAPIC (acpi_id[0x%04x] id[0x%x] enabled[%d])\n", 7.331 - local_apic->acpi_id, local_apic->id, local_apic->flags.enabled); 7.332 - 7.333 - printk(KERN_INFO "CPU %d (0x%02x00)", total_cpus, local_apic->id); 7.334 - 7.335 - if (local_apic->flags.enabled) { 7.336 - printk(" enabled"); 7.337 - ix = local_apic->id; 7.338 - if (ix >= MAX_APICS) { 7.339 - printk(KERN_WARNING 7.340 - "Processor #%d INVALID - (Max ID: %d).\n", ix, 7.341 - MAX_APICS); 7.342 - return; 7.343 - } 7.344 - /* 7.345 - * Fill in the info we want to save. Not concerned about 7.346 - * the processor ID. Processor features aren't present in 7.347 - * the table. 7.348 - */ 7.349 - proc_entry.mpc_type = MP_PROCESSOR; 7.350 - proc_entry.mpc_apicid = local_apic->id; 7.351 - proc_entry.mpc_cpuflag = CPU_ENABLED; 7.352 - if (proc_entry.mpc_apicid == boot_cpu_physical_apicid) { 7.353 - printk(" (BSP)"); 7.354 - proc_entry.mpc_cpuflag |= CPU_BOOTPROCESSOR; 7.355 - } 7.356 - proc_entry.mpc_cpufeature = 7.357 - (boot_cpu_data.x86 << 8) | 7.358 - (boot_cpu_data.x86_model << 4) | 7.359 - boot_cpu_data.x86_mask; 7.360 - proc_entry.mpc_featureflag = boot_cpu_data.x86_capability[0]; 7.361 - proc_entry.mpc_reserved[0] = 0; 7.362 - proc_entry.mpc_reserved[1] = 0; 7.363 - proc_entry.mpc_apicver = 0x10; /* integrated APIC */ 7.364 - MP_processor_info(&proc_entry); 7.365 - } else { 7.366 - printk(" disabled"); 7.367 - } 7.368 - printk("\n"); 7.369 - 7.370 - total_cpus++; 7.371 - return; 7.372 -} 7.373 - 7.374 -static void __init 7.375 -acpi_parse_ioapic(struct acpi_table_ioapic *ioapic) 7.376 -{ 7.377 - 7.378 - if (!ioapic) 7.379 - return; 7.380 - 7.381 - printk(KERN_INFO 7.382 - "IOAPIC (id[0x%x] address[0x%x] global_irq_base[0x%x])\n", 7.383 - ioapic->id, ioapic->address, ioapic->global_irq_base); 7.384 - 7.385 - if (nr_ioapics >= MAX_IO_APICS) { 7.386 - printk(KERN_WARNING 7.387 - "Max # of I/O APICs (%d) exceeded (found %d).\n", 7.388 - MAX_IO_APICS, nr_ioapics); 7.389 -/* panic("Recompile kernel with bigger MAX_IO_APICS!\n"); */ 7.390 - } 7.391 -} 7.392 - 7.393 - 7.394 -/* Interrupt source overrides inform the machine about exceptions 7.395 - to the normal "PIC" mode interrupt routing */ 7.396 - 7.397 -static void __init 7.398 -acpi_parse_int_src_ovr(struct acpi_table_int_src_ovr *intsrc) 7.399 -{ 7.400 - if (!intsrc) 7.401 - return; 7.402 - 7.403 - printk(KERN_INFO 7.404 - "INT_SRC_OVR (bus[%d] irq[0x%x] global_irq[0x%x] polarity[0x%x] trigger[0x%x])\n", 7.405 - intsrc->bus, intsrc->bus_irq, intsrc->global_irq, 7.406 - intsrc->flags.polarity, intsrc->flags.trigger); 7.407 -} 7.408 - 7.409 -/* 7.410 - * At this point, we look at the interrupt assignment entries in the MPS 7.411 - * table. 7.412 - */ 7.413 - 7.414 -static void __init acpi_parse_nmi_src(struct acpi_table_nmi_src *nmisrc) 7.415 -{ 7.416 - if (!nmisrc) 7.417 - return; 7.418 - 7.419 - printk(KERN_INFO 7.420 - "NMI_SRC (polarity[0x%x] trigger[0x%x] global_irq[0x%x])\n", 7.421 - nmisrc->flags.polarity, nmisrc->flags.trigger, 7.422 - nmisrc->global_irq); 7.423 - 7.424 -} 7.425 -static void __init 7.426 -acpi_parse_lapic_nmi(struct acpi_table_lapic_nmi *localnmi) 7.427 -{ 7.428 - if (!localnmi) 7.429 - return; 7.430 - 7.431 - printk(KERN_INFO 7.432 - "LAPIC_NMI (acpi_id[0x%04x] polarity[0x%x] trigger[0x%x] lint[0x%x])\n", 7.433 - localnmi->acpi_id, localnmi->flags.polarity, 7.434 - localnmi->flags.trigger, localnmi->lint); 7.435 -} 7.436 -static void __init 7.437 -acpi_parse_lapic_addr_ovr(struct acpi_table_lapic_addr_ovr *lapic_addr_ovr) 7.438 -{ 7.439 - if (!lapic_addr_ovr) 7.440 - return; 7.441 - 7.442 - printk(KERN_INFO "LAPIC_ADDR_OVR (address[0x%lx])\n", 7.443 - (unsigned long) lapic_addr_ovr->address); 7.444 - 7.445 -} 7.446 - 7.447 -static void __init 7.448 -acpi_parse_plat_int_src(struct acpi_table_plat_int_src *plintsrc) 7.449 -{ 7.450 - if (!plintsrc) 7.451 - return; 7.452 - 7.453 - printk(KERN_INFO 7.454 - "PLAT_INT_SRC (polarity[0x%x] trigger[0x%x] type[0x%x] id[0x%04x] eid[0x%x] iosapic_vector[0x%x] global_irq[0x%x]\n", 7.455 - plintsrc->flags.polarity, plintsrc->flags.trigger, 7.456 - plintsrc->type, plintsrc->id, plintsrc->eid, 7.457 - plintsrc->iosapic_vector, plintsrc->global_irq); 7.458 -} 7.459 -static int __init 7.460 -acpi_parse_madt(acpi_table_header * header, unsigned long phys) 7.461 -{ 7.462 - 7.463 - struct acpi_table_madt *madt; 7.464 - acpi_madt_entry_header *entry_header; 7.465 - int table_size; 7.466 - 7.467 - madt = (struct acpi_table_madt *) __va_range(phys, header->length); 7.468 - 7.469 - if (!madt) 7.470 - return -EINVAL; 7.471 - 7.472 - table_size = (int) (header->length - sizeof(*madt)); 7.473 - entry_header = 7.474 - (acpi_madt_entry_header *) ((void *) madt + sizeof(*madt)); 7.475 - 7.476 - while (entry_header && (table_size > 0)) { 7.477 - switch (entry_header->type) { 7.478 - case ACPI_MADT_LAPIC: 7.479 - acpi_parse_lapic((struct acpi_table_lapic *) 7.480 - entry_header); 7.481 - break; 7.482 - case ACPI_MADT_IOAPIC: 7.483 - acpi_parse_ioapic((struct acpi_table_ioapic *) 7.484 - entry_header); 7.485 - break; 7.486 - case ACPI_MADT_INT_SRC_OVR: 7.487 - acpi_parse_int_src_ovr((struct acpi_table_int_src_ovr *) 7.488 - entry_header); 7.489 - break; 7.490 - case ACPI_MADT_NMI_SRC: 7.491 - acpi_parse_nmi_src((struct acpi_table_nmi_src *) 7.492 - entry_header); 7.493 - break; 7.494 - case ACPI_MADT_LAPIC_NMI: 7.495 - acpi_parse_lapic_nmi((struct acpi_table_lapic_nmi *) 7.496 - entry_header); 7.497 - break; 7.498 - case ACPI_MADT_LAPIC_ADDR_OVR: 7.499 - acpi_parse_lapic_addr_ovr((struct 7.500 - acpi_table_lapic_addr_ovr *) 7.501 - entry_header); 7.502 - break; 7.503 - case ACPI_MADT_PLAT_INT_SRC: 7.504 - acpi_parse_plat_int_src((struct acpi_table_plat_int_src 7.505 - *) entry_header); 7.506 - break; 7.507 - default: 7.508 - printk(KERN_WARNING 7.509 - "Unsupported MADT entry type 0x%x\n", 7.510 - entry_header->type); 7.511 - break; 7.512 - } 7.513 - table_size -= entry_header->length; 7.514 - entry_header = 7.515 - (acpi_madt_entry_header *) ((void *) entry_header + 7.516 - entry_header->length); 7.517 - } 7.518 - 7.519 - if (!total_cpus) { 7.520 - printk("ACPI: No Processors found in the APCI table.\n"); 7.521 - return -EINVAL; 7.522 - } 7.523 - 7.524 - printk(KERN_INFO "%d CPUs total\n", total_cpus); 7.525 - 7.526 - if (madt->lapic_address) 7.527 - mp_lapic_addr = madt->lapic_address; 7.528 - else 7.529 - mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 7.530 - 7.531 - printk(KERN_INFO "Local APIC address %x\n", madt->lapic_address); 7.532 - 7.533 - return 0; 7.534 -} 7.535 - 7.536 -extern int opt_noacpi; 7.537 - 7.538 -/* 7.539 - * Configure the processor info using MADT in the ACPI tables. If we fail to 7.540 - * configure that, then we use the MPS tables. 7.541 - */ 7.542 -void __init 7.543 -config_acpi_tables(void) 7.544 -{ 7.545 - memset(&acpi_boot_ops, 0, sizeof(acpi_boot_ops)); 7.546 - acpi_boot_ops[ACPI_APIC] = acpi_parse_madt; 7.547 - 7.548 - if (!opt_noacpi && !acpi_tables_init()) { 7.549 - have_acpi_tables = 1; 7.550 - printk("Enabling the CPU's according to the ACPI table\n"); 7.551 - } 7.552 -}
8.1 --- a/xen-2.4.16/arch/i386/acpitable.h Mon Feb 24 16:55:07 2003 +0000 8.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 8.3 @@ -1,260 +0,0 @@ 8.4 -/* 8.5 - * acpitable.c - IA32-specific ACPI boot-time initialization (Revision: 1) 8.6 - * 8.7 - * Copyright (C) 1999 Andrew Henroid 8.8 - * Copyright (C) 2001 Richard Schaal 8.9 - * Copyright (C) 2001 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com> 8.10 - * Copyright (C) 2001 Jun Nakajima <jun.nakajima@intel.com> 8.11 - * Copyright (C) 2001 Arjan van de Ven <arjanv@redhat.com> 8.12 - * 8.13 - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 8.14 - * 8.15 - * This program is free software; you can redistribute it and/or modify 8.16 - * it under the terms of the GNU General Public License as published by 8.17 - * the Free Software Foundation; either version 2 of the License, or 8.18 - * (at your option) any later version. 8.19 - * 8.20 - * This program is distributed in the hope that it will be useful, 8.21 - * but WITHOUT ANY WARRANTY; without even the implied warranty of 8.22 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 8.23 - * GNU General Public License for more details. 8.24 - * 8.25 - * You should have received a copy of the GNU General Public License 8.26 - * along with this program; if not, write to the Free Software 8.27 - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 8.28 - * 8.29 - * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 8.30 - * 8.31 - * $Id: acpitable.h,v 1.3 2001/11/03 22:41:34 fenrus Exp $ 8.32 - */ 8.33 - 8.34 -/* 8.35 - * The following codes are cut&pasted from drivers/acpi. Part of the code 8.36 - * there can be not updated or delivered yet. 8.37 - * To avoid conflicts when CONFIG_ACPI is defined, the following codes are 8.38 - * modified so that they are self-contained in this file. 8.39 - * -- jun 8.40 - */ 8.41 - 8.42 -#ifndef _HEADER_ACPITABLE_H_ 8.43 -#define _HEADER_ACPITABLE_H_ 8.44 - 8.45 -#define dprintk printk 8.46 -typedef unsigned int ACPI_TBLPTR; 8.47 - 8.48 -typedef struct { /* ACPI common table header */ 8.49 - char signature[4]; /* identifies type of table */ 8.50 - u32 length; /* length of table, 8.51 - in bytes, * including header */ 8.52 - u8 revision; /* specification minor version # */ 8.53 - u8 checksum; /* to make sum of entire table == 0 */ 8.54 - char oem_id[6]; /* OEM identification */ 8.55 - char oem_table_id[8]; /* OEM table identification */ 8.56 - u32 oem_revision; /* OEM revision number */ 8.57 - char asl_compiler_id[4]; /* ASL compiler vendor ID */ 8.58 - u32 asl_compiler_revision; /* ASL compiler revision number */ 8.59 -} acpi_table_header __attribute__ ((packed));; 8.60 - 8.61 -enum { 8.62 - ACPI_APIC = 0, 8.63 - ACPI_BOOT, 8.64 - ACPI_DBGP, 8.65 - ACPI_DSDT, 8.66 - ACPI_ECDT, 8.67 - ACPI_ETDT, 8.68 - ACPI_FACP, 8.69 - ACPI_FACS, 8.70 - ACPI_OEMX, 8.71 - ACPI_PSDT, 8.72 - ACPI_SBST, 8.73 - ACPI_SLIT, 8.74 - ACPI_SPCR, 8.75 - ACPI_SRAT, 8.76 - ACPI_SSDT, 8.77 - ACPI_SPMI, 8.78 - ACPI_XSDT, 8.79 - ACPI_TABLE_COUNT 8.80 -}; 8.81 - 8.82 -static char *acpi_table_signatures[ACPI_TABLE_COUNT] = { 8.83 - "APIC", 8.84 - "BOOT", 8.85 - "DBGP", 8.86 - "DSDT", 8.87 - "ECDT", 8.88 - "ETDT", 8.89 - "FACP", 8.90 - "FACS", 8.91 - "OEM", 8.92 - "PSDT", 8.93 - "SBST", 8.94 - "SLIT", 8.95 - "SPCR", 8.96 - "SRAT", 8.97 - "SSDT", 8.98 - "SPMI", 8.99 - "XSDT" 8.100 -}; 8.101 - 8.102 -struct acpi_table_madt { 8.103 - acpi_table_header header; 8.104 - u32 lapic_address; 8.105 - struct { 8.106 - u32 pcat_compat:1; 8.107 - u32 reserved:31; 8.108 - } flags __attribute__ ((packed)); 8.109 -} __attribute__ ((packed));; 8.110 - 8.111 -enum { 8.112 - ACPI_MADT_LAPIC = 0, 8.113 - ACPI_MADT_IOAPIC, 8.114 - ACPI_MADT_INT_SRC_OVR, 8.115 - ACPI_MADT_NMI_SRC, 8.116 - ACPI_MADT_LAPIC_NMI, 8.117 - ACPI_MADT_LAPIC_ADDR_OVR, 8.118 - ACPI_MADT_IOSAPIC, 8.119 - ACPI_MADT_LSAPIC, 8.120 - ACPI_MADT_PLAT_INT_SRC, 8.121 - ACPI_MADT_ENTRY_COUNT 8.122 -}; 8.123 - 8.124 -#define RSDP_SIG "RSD PTR " 8.125 -#define RSDT_SIG "RSDT" 8.126 - 8.127 -#define ACPI_DEBUG_PRINT(pl) 8.128 - 8.129 -#define ACPI_MEMORY_MODE 0x01 8.130 -#define ACPI_LOGICAL_ADDRESSING 0x00 8.131 -#define ACPI_PHYSICAL_ADDRESSING 0x01 8.132 - 8.133 -#define LO_RSDP_WINDOW_BASE 0 /* Physical Address */ 8.134 -#define HI_RSDP_WINDOW_BASE 0xE0000 /* Physical Address */ 8.135 -#define LO_RSDP_WINDOW_SIZE 0x400 8.136 -#define HI_RSDP_WINDOW_SIZE 0x20000 8.137 -#define RSDP_SCAN_STEP 16 8.138 -#define RSDP_CHECKSUM_LENGTH 20 8.139 - 8.140 -typedef int (*acpi_table_handler) (acpi_table_header * header, unsigned long); 8.141 - 8.142 -struct acpi_table_rsdp { 8.143 - char signature[8]; 8.144 - u8 checksum; 8.145 - char oem_id[6]; 8.146 - u8 revision; 8.147 - u32 rsdt_address; 8.148 -} __attribute__ ((packed)); 8.149 - 8.150 -struct acpi_table_rsdt { 8.151 - acpi_table_header header; 8.152 - u32 entry[ACPI_TABLE_COUNT]; 8.153 -} __attribute__ ((packed)); 8.154 - 8.155 -typedef struct { 8.156 - u8 type; 8.157 - u8 length; 8.158 -} acpi_madt_entry_header __attribute__ ((packed)); 8.159 - 8.160 -typedef struct { 8.161 - u16 polarity:2; 8.162 - u16 trigger:2; 8.163 - u16 reserved:12; 8.164 -} acpi_madt_int_flags __attribute__ ((packed)); 8.165 - 8.166 -struct acpi_table_lapic { 8.167 - acpi_madt_entry_header header; 8.168 - u8 acpi_id; 8.169 - u8 id; 8.170 - struct { 8.171 - u32 enabled:1; 8.172 - u32 reserved:31; 8.173 - } flags __attribute__ ((packed)); 8.174 -} __attribute__ ((packed)); 8.175 - 8.176 -struct acpi_table_ioapic { 8.177 - acpi_madt_entry_header header; 8.178 - u8 id; 8.179 - u8 reserved; 8.180 - u32 address; 8.181 - u32 global_irq_base; 8.182 -} __attribute__ ((packed)); 8.183 - 8.184 -struct acpi_table_int_src_ovr { 8.185 - acpi_madt_entry_header header; 8.186 - u8 bus; 8.187 - u8 bus_irq; 8.188 - u32 global_irq; 8.189 - acpi_madt_int_flags flags; 8.190 -} __attribute__ ((packed)); 8.191 - 8.192 -struct acpi_table_nmi_src { 8.193 - acpi_madt_entry_header header; 8.194 - acpi_madt_int_flags flags; 8.195 - u32 global_irq; 8.196 -} __attribute__ ((packed)); 8.197 - 8.198 -struct acpi_table_lapic_nmi { 8.199 - acpi_madt_entry_header header; 8.200 - u8 acpi_id; 8.201 - acpi_madt_int_flags flags; 8.202 - u8 lint; 8.203 -} __attribute__ ((packed)); 8.204 - 8.205 -struct acpi_table_lapic_addr_ovr { 8.206 - acpi_madt_entry_header header; 8.207 - u8 reserved[2]; 8.208 - u64 address; 8.209 -} __attribute__ ((packed)); 8.210 - 8.211 -struct acpi_table_iosapic { 8.212 - acpi_madt_entry_header header; 8.213 - u8 id; 8.214 - u8 reserved; 8.215 - u32 global_irq_base; 8.216 - u64 address; 8.217 -} __attribute__ ((packed)); 8.218 - 8.219 -struct acpi_table_lsapic { 8.220 - acpi_madt_entry_header header; 8.221 - u8 acpi_id; 8.222 - u8 id; 8.223 - u8 eid; 8.224 - u8 reserved[3]; 8.225 - struct { 8.226 - u32 enabled:1; 8.227 - u32 reserved:31; 8.228 - } flags; 8.229 -} __attribute__ ((packed)); 8.230 - 8.231 -struct acpi_table_plat_int_src { 8.232 - acpi_madt_entry_header header; 8.233 - acpi_madt_int_flags flags; 8.234 - u8 type; 8.235 - u8 id; 8.236 - u8 eid; 8.237 - u8 iosapic_vector; 8.238 - u32 global_irq; 8.239 - u32 reserved; 8.240 -} __attribute__ ((packed)); 8.241 - 8.242 -/* 8.243 - * ACPI Table Descriptor. One per ACPI table 8.244 - */ 8.245 -typedef struct acpi_table_desc { 8.246 - struct acpi_table_desc *prev; 8.247 - struct acpi_table_desc *next; 8.248 - struct acpi_table_desc *installed_desc; 8.249 - acpi_table_header *pointer; 8.250 - void *base_pointer; 8.251 - u8 *aml_pointer; 8.252 - u64 physical_address; 8.253 - u32 aml_length; 8.254 - u32 length; 8.255 - u32 count; 8.256 - u16 table_id; 8.257 - u8 type; 8.258 - u8 allocation; 8.259 - u8 loaded_into_namespace; 8.260 - 8.261 -} acpi_table_desc __attribute__ ((packed));; 8.262 - 8.263 -#endif
9.1 --- a/xen-2.4.16/arch/i386/apic.c Mon Feb 24 16:55:07 2003 +0000 9.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 9.3 @@ -1,845 +0,0 @@ 9.4 -/* -*- Mode:C; c-basic-offset:4; tab-width:4 -*- 9.5 - **************************************************************************** 9.6 - * (C) 2002 - Rolf Neugebauer - Intel Research Cambridge 9.7 - **************************************************************************** 9.8 - * 9.9 - * File: apic.c 9.10 - * Author: 9.11 - * Changes: 9.12 - * 9.13 - * Date: Nov 2002 9.14 - * 9.15 - * Environment: Xen Hypervisor 9.16 - * Description: programmable APIC timer interface for accurate timers 9.17 - * modified version of Linux' apic.c 9.18 - * 9.19 - **************************************************************************** 9.20 - * $Id: c-insert.c,v 1.7 2002/11/08 16:04:34 rn Exp $ 9.21 - **************************************************************************** 9.22 - */ 9.23 - 9.24 -/* 9.25 - * Local APIC handling, local APIC timers 9.26 - * 9.27 - * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com> 9.28 - * 9.29 - * Fixes 9.30 - * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 9.31 - * thanks to Eric Gilmore 9.32 - * and Rolf G. Tews 9.33 - * for testing these extensively. 9.34 - */ 9.35 - 9.36 - 9.37 -#include <xeno/config.h> 9.38 -#include <xeno/init.h> 9.39 -#include <xeno/sched.h> 9.40 -#include <xeno/irq.h> 9.41 -#include <xeno/delay.h> 9.42 -#include <asm/mc146818rtc.h> 9.43 -#include <asm/msr.h> 9.44 -#include <xeno/errno.h> 9.45 -#include <asm/atomic.h> 9.46 -#include <xeno/smp.h> 9.47 -#include <xeno/interrupt.h> 9.48 -#include <asm/mpspec.h> 9.49 -#include <asm/pgalloc.h> 9.50 -#include <asm/hardirq.h> 9.51 - 9.52 -#include <xeno/ac_timer.h> 9.53 - 9.54 -#undef APIC_TIME_TRACE 9.55 -#ifdef APIC_TIME_TRACE 9.56 -#define TRC(_x) _x 9.57 -#else 9.58 -#define TRC(_x) 9.59 -#endif 9.60 - 9.61 - 9.62 -/* Using APIC to generate smp_local_timer_interrupt? */ 9.63 -int using_apic_timer = 0; 9.64 - 9.65 -int get_maxlvt(void) 9.66 -{ 9.67 - unsigned int v, ver, maxlvt; 9.68 - 9.69 - v = apic_read(APIC_LVR); 9.70 - ver = GET_APIC_VERSION(v); 9.71 - /* 82489DXs do not report # of LVT entries. */ 9.72 - maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2; 9.73 - return maxlvt; 9.74 -} 9.75 - 9.76 -static void clear_local_APIC(void) 9.77 -{ 9.78 - int maxlvt; 9.79 - unsigned long v; 9.80 - 9.81 - maxlvt = get_maxlvt(); 9.82 - 9.83 - /* 9.84 - * Careful: we have to set masks only first to deassert 9.85 - * any level-triggered sources. 9.86 - */ 9.87 - v = apic_read(APIC_LVTT); 9.88 - apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED); 9.89 - v = apic_read(APIC_LVT0); 9.90 - apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); 9.91 - v = apic_read(APIC_LVT1); 9.92 - apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED); 9.93 - if (maxlvt >= 3) { 9.94 - v = apic_read(APIC_LVTERR); 9.95 - apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED); 9.96 - } 9.97 - if (maxlvt >= 4) { 9.98 - v = apic_read(APIC_LVTPC); 9.99 - apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED); 9.100 - } 9.101 - 9.102 - /* 9.103 - * Clean APIC state for other OSs: 9.104 - */ 9.105 - apic_write_around(APIC_LVTT, APIC_LVT_MASKED); 9.106 - apic_write_around(APIC_LVT0, APIC_LVT_MASKED); 9.107 - apic_write_around(APIC_LVT1, APIC_LVT_MASKED); 9.108 - if (maxlvt >= 3) 9.109 - apic_write_around(APIC_LVTERR, APIC_LVT_MASKED); 9.110 - if (maxlvt >= 4) 9.111 - apic_write_around(APIC_LVTPC, APIC_LVT_MASKED); 9.112 -} 9.113 - 9.114 -void __init connect_bsp_APIC(void) 9.115 -{ 9.116 - if (pic_mode) { 9.117 - /* 9.118 - * Do not trust the local APIC being empty at bootup. 9.119 - */ 9.120 - clear_local_APIC(); 9.121 - /* 9.122 - * PIC mode, enable APIC mode in the IMCR, i.e. 9.123 - * connect BSP's local APIC to INT and NMI lines. 9.124 - */ 9.125 - printk("leaving PIC mode, enabling APIC mode.\n"); 9.126 - outb(0x70, 0x22); 9.127 - outb(0x01, 0x23); 9.128 - } 9.129 -} 9.130 - 9.131 -void disconnect_bsp_APIC(void) 9.132 -{ 9.133 - if (pic_mode) { 9.134 - /* 9.135 - * Put the board back into PIC mode (has an effect 9.136 - * only on certain older boards). Note that APIC 9.137 - * interrupts, including IPIs, won't work beyond 9.138 - * this point! The only exception are INIT IPIs. 9.139 - */ 9.140 - printk("disabling APIC mode, entering PIC mode.\n"); 9.141 - outb(0x70, 0x22); 9.142 - outb(0x00, 0x23); 9.143 - } 9.144 -} 9.145 - 9.146 -void disable_local_APIC(void) 9.147 -{ 9.148 - unsigned long value; 9.149 - 9.150 - clear_local_APIC(); 9.151 - 9.152 - /* 9.153 - * Disable APIC (implies clearing of registers 9.154 - * for 82489DX!). 9.155 - */ 9.156 - value = apic_read(APIC_SPIV); 9.157 - value &= ~APIC_SPIV_APIC_ENABLED; 9.158 - apic_write_around(APIC_SPIV, value); 9.159 -} 9.160 - 9.161 -/* 9.162 - * This is to verify that we're looking at a real local APIC. 9.163 - * Check these against your board if the CPUs aren't getting 9.164 - * started for no apparent reason. 9.165 - */ 9.166 -int __init verify_local_APIC(void) 9.167 -{ 9.168 - unsigned int reg0, reg1; 9.169 - 9.170 - /* 9.171 - * The version register is read-only in a real APIC. 9.172 - */ 9.173 - reg0 = apic_read(APIC_LVR); 9.174 - Dprintk("Getting VERSION: %x\n", reg0); 9.175 - apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK); 9.176 - reg1 = apic_read(APIC_LVR); 9.177 - Dprintk("Getting VERSION: %x\n", reg1); 9.178 - 9.179 - /* 9.180 - * The two version reads above should print the same 9.181 - * numbers. If the second one is different, then we 9.182 - * poke at a non-APIC. 9.183 - */ 9.184 - if (reg1 != reg0) 9.185 - return 0; 9.186 - 9.187 - /* 9.188 - * Check if the version looks reasonably. 9.189 - */ 9.190 - reg1 = GET_APIC_VERSION(reg0); 9.191 - if (reg1 == 0x00 || reg1 == 0xff) 9.192 - return 0; 9.193 - reg1 = get_maxlvt(); 9.194 - if (reg1 < 0x02 || reg1 == 0xff) 9.195 - return 0; 9.196 - 9.197 - /* 9.198 - * The ID register is read/write in a real APIC. 9.199 - */ 9.200 - reg0 = apic_read(APIC_ID); 9.201 - Dprintk("Getting ID: %x\n", reg0); 9.202 - apic_write(APIC_ID, reg0 ^ APIC_ID_MASK); 9.203 - reg1 = apic_read(APIC_ID); 9.204 - Dprintk("Getting ID: %x\n", reg1); 9.205 - apic_write(APIC_ID, reg0); 9.206 - if (reg1 != (reg0 ^ APIC_ID_MASK)) 9.207 - return 0; 9.208 - 9.209 - /* 9.210 - * The next two are just to see if we have sane values. 9.211 - * They're only really relevant if we're in Virtual Wire 9.212 - * compatibility mode, but most boxes are anymore. 9.213 - */ 9.214 - reg0 = apic_read(APIC_LVT0); 9.215 - Dprintk("Getting LVT0: %x\n", reg0); 9.216 - reg1 = apic_read(APIC_LVT1); 9.217 - Dprintk("Getting LVT1: %x\n", reg1); 9.218 - 9.219 - return 1; 9.220 -} 9.221 - 9.222 -void __init sync_Arb_IDs(void) 9.223 -{ 9.224 - /* Wait for idle. */ 9.225 - apic_wait_icr_idle(); 9.226 - 9.227 - Dprintk("Synchronizing Arb IDs.\n"); 9.228 - apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG 9.229 - | APIC_DM_INIT); 9.230 -} 9.231 - 9.232 -extern void __error_in_apic_c (void); 9.233 - 9.234 -/* 9.235 - * WAS: An initial setup of the virtual wire mode. 9.236 - * NOW: We don't bother doing anything. All we need at this point 9.237 - * is to receive timer ticks, so that 'jiffies' is incremented. 9.238 - * If we're SMP, then we can assume BIOS did setup for us. 9.239 - * If we're UP, then the APIC should be disabled (it is at reset). 9.240 - * If we're UP and APIC is enabled, then BIOS is clever and has 9.241 - * probably done initial interrupt routing for us. 9.242 - */ 9.243 -void __init init_bsp_APIC(void) 9.244 -{ 9.245 -} 9.246 - 9.247 -void __init setup_local_APIC (void) 9.248 -{ 9.249 - unsigned long value, ver, maxlvt; 9.250 - 9.251 - value = apic_read(APIC_LVR); 9.252 - ver = GET_APIC_VERSION(value); 9.253 - 9.254 - if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f) 9.255 - __error_in_apic_c(); 9.256 - 9.257 - /* Double-check wether this APIC is really registered. */ 9.258 - if (!test_bit(GET_APIC_ID(apic_read(APIC_ID)), &phys_cpu_present_map)) 9.259 - BUG(); 9.260 - 9.261 - /* 9.262 - * Intel recommends to set DFR, LDR and TPR before enabling 9.263 - * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel 9.264 - * document number 292116). So here it goes... 9.265 - */ 9.266 - 9.267 - /* 9.268 - * In clustered apic mode, the firmware does this for us 9.269 - * Put the APIC into flat delivery mode. 9.270 - * Must be "all ones" explicitly for 82489DX. 9.271 - */ 9.272 - apic_write_around(APIC_DFR, 0xffffffff); 9.273 - 9.274 - /* 9.275 - * Set up the logical destination ID. 9.276 - */ 9.277 - value = apic_read(APIC_LDR); 9.278 - value &= ~APIC_LDR_MASK; 9.279 - value |= (1<<(smp_processor_id()+24)); 9.280 - apic_write_around(APIC_LDR, value); 9.281 - 9.282 - /* 9.283 - * Set Task Priority to 'accept all'. We never change this 9.284 - * later on. 9.285 - */ 9.286 - value = apic_read(APIC_TASKPRI); 9.287 - value &= ~APIC_TPRI_MASK; 9.288 - apic_write_around(APIC_TASKPRI, value); 9.289 - 9.290 - /* 9.291 - * Now that we are all set up, enable the APIC 9.292 - */ 9.293 - value = apic_read(APIC_SPIV); 9.294 - value &= ~APIC_VECTOR_MASK; 9.295 - /* 9.296 - * Enable APIC 9.297 - */ 9.298 - value |= APIC_SPIV_APIC_ENABLED; 9.299 - 9.300 - /* Enable focus processor (bit==0) */ 9.301 - value &= ~APIC_SPIV_FOCUS_DISABLED; 9.302 - 9.303 - /* Set spurious IRQ vector */ 9.304 - value |= SPURIOUS_APIC_VECTOR; 9.305 - apic_write_around(APIC_SPIV, value); 9.306 - 9.307 - /* 9.308 - * Set up LVT0, LVT1: 9.309 - * 9.310 - * set up through-local-APIC on the BP's LINT0. This is not 9.311 - * strictly necessery in pure symmetric-IO mode, but sometimes 9.312 - * we delegate interrupts to the 8259A. 9.313 - */ 9.314 - /* 9.315 - * TODO: set up through-local-APIC from through-I/O-APIC? --macro 9.316 - */ 9.317 - value = apic_read(APIC_LVT0) & APIC_LVT_MASKED; 9.318 - if (!smp_processor_id()) { 9.319 - value = APIC_DM_EXTINT; 9.320 - printk("enabled ExtINT on CPU#%d\n", smp_processor_id()); 9.321 - } else { 9.322 - value = APIC_DM_EXTINT | APIC_LVT_MASKED; 9.323 - printk("masked ExtINT on CPU#%d\n", smp_processor_id()); 9.324 - } 9.325 - apic_write_around(APIC_LVT0, value); 9.326 - 9.327 - /* 9.328 - * only the BP should see the LINT1 NMI signal, obviously. 9.329 - */ 9.330 - if (!smp_processor_id()) 9.331 - value = APIC_DM_NMI; 9.332 - else 9.333 - value = APIC_DM_NMI | APIC_LVT_MASKED; 9.334 - if (!APIC_INTEGRATED(ver)) /* 82489DX */ 9.335 - value |= APIC_LVT_LEVEL_TRIGGER; 9.336 - apic_write_around(APIC_LVT1, value); 9.337 - 9.338 - if (APIC_INTEGRATED(ver)) { /* !82489DX */ 9.339 - maxlvt = get_maxlvt(); 9.340 - if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 9.341 - apic_write(APIC_ESR, 0); 9.342 - value = apic_read(APIC_ESR); 9.343 - printk("ESR value before enabling vector: %08lx\n", value); 9.344 - 9.345 - value = ERROR_APIC_VECTOR; /* enables sending errors */ 9.346 - apic_write_around(APIC_LVTERR, value); 9.347 - /* spec says clear errors after enabling vector. */ 9.348 - if (maxlvt > 3) 9.349 - apic_write(APIC_ESR, 0); 9.350 - value = apic_read(APIC_ESR); 9.351 - printk("ESR value after enabling vector: %08lx\n", value); 9.352 - } else { 9.353 - printk("No ESR for 82489DX.\n"); 9.354 - } 9.355 -} 9.356 - 9.357 - 9.358 -static inline void apic_pm_init1(void) { } 9.359 -static inline void apic_pm_init2(void) { } 9.360 - 9.361 - 9.362 -/* 9.363 - * Detect and enable local APICs on non-SMP boards. 9.364 - * Original code written by Keir Fraser. 9.365 - */ 9.366 - 9.367 -static int __init detect_init_APIC (void) 9.368 -{ 9.369 - u32 h, l, features; 9.370 - extern void get_cpu_vendor(struct cpuinfo_x86*); 9.371 - 9.372 - /* Workaround for us being called before identify_cpu(). */ 9.373 - get_cpu_vendor(&boot_cpu_data); 9.374 - 9.375 - switch (boot_cpu_data.x86_vendor) { 9.376 - case X86_VENDOR_AMD: 9.377 - if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) 9.378 - break; 9.379 - goto no_apic; 9.380 - case X86_VENDOR_INTEL: 9.381 - if (boot_cpu_data.x86 == 6 || 9.382 - (boot_cpu_data.x86 == 15 && cpu_has_apic) || 9.383 - (boot_cpu_data.x86 == 5 && cpu_has_apic)) 9.384 - break; 9.385 - goto no_apic; 9.386 - default: 9.387 - goto no_apic; 9.388 - } 9.389 - 9.390 - if (!cpu_has_apic) { 9.391 - /* 9.392 - * Some BIOSes disable the local APIC in the 9.393 - * APIC_BASE MSR. This can only be done in 9.394 - * software for Intel P6 and AMD K7 (Model > 1). 9.395 - */ 9.396 - rdmsr(MSR_IA32_APICBASE, l, h); 9.397 - if (!(l & MSR_IA32_APICBASE_ENABLE)) { 9.398 - printk("Local APIC disabled by BIOS -- reenabling.\n"); 9.399 - l &= ~MSR_IA32_APICBASE_BASE; 9.400 - l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE; 9.401 - wrmsr(MSR_IA32_APICBASE, l, h); 9.402 - } 9.403 - } 9.404 - 9.405 - /* The APIC feature bit should now be enabled in `cpuid' */ 9.406 - features = cpuid_edx(1); 9.407 - if (!(features & (1 << X86_FEATURE_APIC))) { 9.408 - printk("Could not enable APIC!\n"); 9.409 - return -1; 9.410 - } 9.411 - 9.412 - set_bit(X86_FEATURE_APIC, &boot_cpu_data.x86_capability); 9.413 - mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 9.414 - boot_cpu_physical_apicid = 0; 9.415 - 9.416 - printk("Found and enabled local APIC!\n"); 9.417 - apic_pm_init1(); 9.418 - return 0; 9.419 - 9.420 - no_apic: 9.421 - printk("No local APIC present or hardware disabled\n"); 9.422 - return -1; 9.423 -} 9.424 - 9.425 -void __init init_apic_mappings(void) 9.426 -{ 9.427 - unsigned long apic_phys = 0; 9.428 - 9.429 - /* 9.430 - * If no local APIC can be found then set up a fake all zeroes page to 9.431 - * simulate the local APIC and another one for the IO-APIC. 9.432 - */ 9.433 - if (!smp_found_config && detect_init_APIC()) { 9.434 - apic_phys = get_free_page(GFP_KERNEL); 9.435 - apic_phys = __pa(apic_phys); 9.436 - } else 9.437 - apic_phys = mp_lapic_addr; 9.438 - 9.439 - set_fixmap_nocache(FIX_APIC_BASE, apic_phys); 9.440 - Dprintk("mapped APIC to %08lx (%08lx)\n", APIC_BASE, apic_phys); 9.441 - 9.442 - /* 9.443 - * Fetch the APIC ID of the BSP in case we have a 9.444 - * default configuration (or the MP table is broken). 9.445 - */ 9.446 - if (boot_cpu_physical_apicid == -1U) 9.447 - boot_cpu_physical_apicid = GET_APIC_ID(apic_read(APIC_ID)); 9.448 - 9.449 -#ifdef CONFIG_X86_IO_APIC 9.450 - { 9.451 - unsigned long ioapic_phys = 0, idx = FIX_IO_APIC_BASE_0; 9.452 - int i; 9.453 - 9.454 - for (i = 0; i < nr_ioapics; i++) { 9.455 - if (smp_found_config) 9.456 - ioapic_phys = mp_ioapics[i].mpc_apicaddr; 9.457 - set_fixmap_nocache(idx, ioapic_phys); 9.458 - Dprintk("mapped IOAPIC to %08lx (%08lx)\n", 9.459 - __fix_to_virt(idx), ioapic_phys); 9.460 - idx++; 9.461 - } 9.462 - } 9.463 -#endif 9.464 -} 9.465 - 9.466 -/***************************************************************************** 9.467 - * APIC calibration 9.468 - * 9.469 - * The APIC is programmed in bus cycles. 9.470 - * Timeout values should specified in real time units. 9.471 - * The "cheapest" time source is the cyclecounter. 9.472 - * 9.473 - * Thus, we need a mappings from: bus cycles <- cycle counter <- system time 9.474 - * 9.475 - * The calibration is currently a bit shoddy since it requires the external 9.476 - * timer chip to generate periodic timer interupts. 9.477 - *****************************************************************************/ 9.478 - 9.479 -/* used for system time scaling */ 9.480 -static unsigned int bus_freq; 9.481 -static u32 bus_cycle; /* length of one bus cycle in pico-seconds */ 9.482 -static u32 bus_scale; /* scaling factor convert ns to bus cycles */ 9.483 -u64 cpu_freq; 9.484 - 9.485 -/* 9.486 - * The timer chip is already set up at HZ interrupts per second here, 9.487 - * but we do not accept timer interrupts yet. We only allow the BP 9.488 - * to calibrate. 9.489 - */ 9.490 -static unsigned int __init get_8254_timer_count(void) 9.491 -{ 9.492 - /*extern spinlock_t i8253_lock;*/ 9.493 - /*unsigned long flags;*/ 9.494 - unsigned int count; 9.495 - /*spin_lock_irqsave(&i8253_lock, flags);*/ 9.496 - outb_p(0x00, 0x43); 9.497 - count = inb_p(0x40); 9.498 - count |= inb_p(0x40) << 8; 9.499 - /*spin_unlock_irqrestore(&i8253_lock, flags);*/ 9.500 - return count; 9.501 -} 9.502 - 9.503 -void __init wait_8254_wraparound(void) 9.504 -{ 9.505 - unsigned int curr_count, prev_count=~0; 9.506 - int delta; 9.507 - curr_count = get_8254_timer_count(); 9.508 - do { 9.509 - prev_count = curr_count; 9.510 - curr_count = get_8254_timer_count(); 9.511 - delta = curr_count-prev_count; 9.512 - /* 9.513 - * This limit for delta seems arbitrary, but it isn't, it's slightly 9.514 - * above the level of error a buggy Mercury/Neptune chipset timer can 9.515 - * cause. 9.516 - */ 9.517 - } while (delta < 300); 9.518 -} 9.519 - 9.520 -/* 9.521 - * This function sets up the local APIC timer, with a timeout of 9.522 - * 'clocks' APIC bus clock. During calibration we actually call 9.523 - * this function with a very large value and read the current time after 9.524 - * a well defined period of time as expired. 9.525 - * 9.526 - * Calibration is only performed once, for CPU0! 9.527 - * 9.528 - * We do reads before writes even if unnecessary, to get around the 9.529 - * P5 APIC double write bug. 9.530 - */ 9.531 -#define APIC_DIVISOR 1 9.532 -static void __setup_APIC_LVTT(unsigned int clocks) 9.533 -{ 9.534 - unsigned int lvtt1_value, tmp_value; 9.535 - lvtt1_value = SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV)|LOCAL_TIMER_VECTOR; 9.536 - apic_write_around(APIC_LVTT, lvtt1_value); 9.537 - tmp_value = apic_read(APIC_TDCR); 9.538 - apic_write_around(APIC_TDCR, (tmp_value | APIC_TDR_DIV_1)); 9.539 - apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR); 9.540 -} 9.541 - 9.542 -/* 9.543 - * this is done for every CPU from setup_APIC_clocks() below. 9.544 - * We setup each local APIC with a zero timeout value for now. 9.545 - * Unlike Linux, we don't have to wait for slices etc. 9.546 - */ 9.547 -void setup_APIC_timer(void * data) 9.548 -{ 9.549 - unsigned long flags; 9.550 - __save_flags(flags); 9.551 - __sti(); 9.552 - printk("cpu: %d: setup timer.", smp_processor_id()); 9.553 - __setup_APIC_LVTT(0); 9.554 - printk("done\n"); 9.555 - __restore_flags(flags); 9.556 -} 9.557 - 9.558 -/* 9.559 - * In this function we calibrate APIC bus clocks to the external timer. 9.560 - * 9.561 - * As a result we have the Bys Speed and CPU speed in Hz. 9.562 - * 9.563 - * We want to do the calibration only once (for CPU0). CPUs connected by the 9.564 - * same APIC bus have the very same bus frequency. 9.565 - * 9.566 - * This bit is a bit shoddy since we use the very same periodic timer interrupt 9.567 - * we try to eliminate to calibrate the APIC. 9.568 - */ 9.569 - 9.570 -int __init calibrate_APIC_clock(void) 9.571 -{ 9.572 - unsigned long long t1 = 0, t2 = 0; 9.573 - long tt1, tt2; 9.574 - long result; 9.575 - int i; 9.576 - const int LOOPS = HZ/10; 9.577 - 9.578 - printk("calibrating APIC timer for CPU%d...\n", smp_processor_id()); 9.579 - 9.580 - /* Put whatever arbitrary (but long enough) timeout 9.581 - * value into the APIC clock, we just want to get the 9.582 - * counter running for calibration. */ 9.583 - __setup_APIC_LVTT(1000000000); 9.584 - 9.585 - /* The timer chip counts down to zero. Let's wait 9.586 - * for a wraparound to start exact measurement: 9.587 - * (the current tick might have been already half done) */ 9.588 - wait_8254_wraparound(); 9.589 - 9.590 - /* We wrapped around just now. Let's start: */ 9.591 - rdtscll(t1); 9.592 - tt1 = apic_read(APIC_TMCCT); 9.593 - 9.594 - /* Let's wait LOOPS wraprounds: */ 9.595 - for (i = 0; i < LOOPS; i++) 9.596 - wait_8254_wraparound(); 9.597 - 9.598 - tt2 = apic_read(APIC_TMCCT); 9.599 - rdtscll(t2); 9.600 - 9.601 - /* The APIC bus clock counter is 32 bits only, it 9.602 - * might have overflown, but note that we use signed 9.603 - * longs, thus no extra care needed. 9.604 - * underflown to be exact, as the timer counts down ;) */ 9.605 - result = (tt1-tt2)*APIC_DIVISOR/LOOPS; 9.606 - 9.607 - printk("..... CPU speed is %ld.%04ld MHz.\n", 9.608 - ((long)(t2-t1)/LOOPS)/(1000000/HZ), 9.609 - ((long)(t2-t1)/LOOPS)%(1000000/HZ)); 9.610 - 9.611 - printk("..... Bus speed is %ld.%04ld MHz.\n", 9.612 - result/(1000000/HZ), 9.613 - result%(1000000/HZ)); 9.614 - 9.615 - cpu_freq = (u64)(((t2-t1)/LOOPS)*HZ); 9.616 - 9.617 - /* set up multipliers for accurate timer code */ 9.618 - bus_freq = result*HZ; 9.619 - bus_cycle = (u32) (1000000000000LL/bus_freq); /* in pico seconds */ 9.620 - bus_scale = (1000*262144)/bus_cycle; 9.621 - 9.622 - /* print results */ 9.623 - printk("..... bus_freq = %u Hz\n", bus_freq); 9.624 - printk("..... bus_cycle = %u ps\n", bus_cycle); 9.625 - printk("..... bus_scale = %u \n", bus_scale); 9.626 - /* reset APIC to zero timeout value */ 9.627 - __setup_APIC_LVTT(0); 9.628 - return result; 9.629 -} 9.630 - 9.631 -/* 9.632 - * initialise the APIC timers for all CPUs 9.633 - * we start with the first and find out processor frequency and bus speed 9.634 - */ 9.635 -void __init setup_APIC_clocks (void) 9.636 -{ 9.637 - printk("Using local APIC timer interrupts.\n"); 9.638 - using_apic_timer = 1; 9.639 - __cli(); 9.640 - /* calibrate CPU0 for CPU speed and BUS speed */ 9.641 - bus_freq = calibrate_APIC_clock(); 9.642 - /* Now set up the timer for real. */ 9.643 - setup_APIC_timer((void *)bus_freq); 9.644 - __sti(); 9.645 - /* and update all other cpus */ 9.646 - smp_call_function(setup_APIC_timer, (void *)bus_freq, 1, 1); 9.647 -} 9.648 - 9.649 -#undef APIC_DIVISOR 9.650 - 9.651 -/* 9.652 - * reprogram the APIC timer. Timeoutvalue is in ns from start of boot 9.653 - * returns 1 on success 9.654 - * returns 0 if the timeout value is too small or in the past. 9.655 - */ 9.656 -int reprogram_ac_timer(s_time_t timeout) 9.657 -{ 9.658 - int cpu = smp_processor_id(); 9.659 - s_time_t now; 9.660 - s_time_t expire; 9.661 - u64 apic_tmict; 9.662 - 9.663 - now = NOW(); 9.664 - expire = timeout - now; /* value from now */ 9.665 - 9.666 - if (expire <= 0) { 9.667 - printk("APICT[%02d] Timeout in the past 0x%08X%08X > 0x%08X%08X\n", 9.668 - cpu, (u32)(now>>32), (u32)now, (u32)(timeout>>32),(u32)timeout); 9.669 - return 0; /* timeout value in the past */ 9.670 - } 9.671 - 9.672 - /* conversion to bus units */ 9.673 - apic_tmict = (((u64)bus_scale) * expire)>>18; 9.674 - 9.675 - if (apic_tmict >= 0xffffffff) { 9.676 - printk("APICT[%02d] Timeout value too large\n", cpu); 9.677 - apic_tmict = 0xffffffff; 9.678 - } 9.679 - if (apic_tmict == 0) { 9.680 - printk("APICT[%02d] timeout value too small\n", cpu); 9.681 - return 0; 9.682 - } 9.683 - 9.684 - /* programm timer */ 9.685 - apic_write(APIC_TMICT, (unsigned long)apic_tmict); 9.686 - 9.687 - TRC(printk("APICT[%02d] reprog(): expire=%lld %u\n", 9.688 - cpu, expire, apic_tmict)); 9.689 - return 1; 9.690 -} 9.691 - 9.692 -/* 9.693 - * Local timer interrupt handler. 9.694 - * here the programmable, accurate timers are executed. 9.695 - * If we are on CPU0 and we should have updated jiffies, we do this 9.696 - * as well and and deal with traditional linux timers. Note, that of 9.697 - * the timer APIC on CPU does not go off every 10ms or so the linux 9.698 - * timers loose accuracy, but that shouldn't be a problem. 9.699 - */ 9.700 -static s_time_t last_cpu0_tirq = 0; 9.701 -inline void smp_local_timer_interrupt(struct pt_regs * regs) 9.702 -{ 9.703 - int cpu = smp_processor_id(); 9.704 - s_time_t diff, now; 9.705 - 9.706 - /* if CPU 0 do old timer stuff */ 9.707 - if (cpu == 0) 9.708 - { 9.709 - now = NOW(); 9.710 - diff = now - last_cpu0_tirq; 9.711 - 9.712 - if (diff <= 0) { 9.713 - printk ("System Time went backwards: %lld\n", diff); 9.714 - return; 9.715 - } 9.716 - 9.717 - while (diff >= MILLISECS(10)) { 9.718 - do_timer(regs); 9.719 - diff -= MILLISECS(10); 9.720 - last_cpu0_tirq += MILLISECS(10); 9.721 - } 9.722 - } 9.723 - /* call accurate timer function */ 9.724 - do_ac_timer(); 9.725 -} 9.726 - 9.727 -/* 9.728 - * Local APIC timer interrupt. This is the most natural way for doing 9.729 - * local interrupts, but local timer interrupts can be emulated by 9.730 - * broadcast interrupts too. [in case the hw doesnt support APIC timers] 9.731 - * 9.732 - * [ if a single-CPU system runs an SMP kernel then we call the local 9.733 - * interrupt as well. Thus we cannot inline the local irq ... ] 9.734 - */ 9.735 -unsigned int apic_timer_irqs [NR_CPUS]; 9.736 - 9.737 -void smp_apic_timer_interrupt(struct pt_regs * regs) 9.738 -{ 9.739 - int cpu = smp_processor_id(); 9.740 - 9.741 - /* 9.742 - * the NMI deadlock-detector uses this. 9.743 - */ 9.744 - apic_timer_irqs[cpu]++; 9.745 - 9.746 - /* 9.747 - * NOTE! We'd better ACK the irq immediately, because timer handling can 9.748 - * be slow. XXX is this save? 9.749 - */ 9.750 - ack_APIC_irq(); 9.751 - 9.752 - /* call the local handler */ 9.753 - irq_enter(cpu, 0); 9.754 - smp_local_timer_interrupt(regs); 9.755 - irq_exit(cpu, 0); 9.756 - 9.757 - if (softirq_pending(cpu)) 9.758 - do_softirq(); 9.759 -} 9.760 - 9.761 -/* 9.762 - * This interrupt should _never_ happen with our APIC/SMP architecture 9.763 - */ 9.764 -asmlinkage void smp_spurious_interrupt(void) 9.765 -{ 9.766 - unsigned long v; 9.767 - 9.768 - /* 9.769 - * Check if this really is a spurious interrupt and ACK it 9.770 - * if it is a vectored one. Just in case... 9.771 - * Spurious interrupts should not be ACKed. 9.772 - */ 9.773 - v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1)); 9.774 - if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f))) 9.775 - ack_APIC_irq(); 9.776 - 9.777 - /* see sw-dev-man vol 3, chapter 7.4.13.5 */ 9.778 - printk("spurious APIC interrupt on CPU#%d, should never happen.\n", 9.779 - smp_processor_id()); 9.780 -} 9.781 - 9.782 -/* 9.783 - * This interrupt should never happen with our APIC/SMP architecture 9.784 - */ 9.785 - 9.786 -asmlinkage void smp_error_interrupt(void) 9.787 -{ 9.788 - unsigned long v, v1; 9.789 - 9.790 - /* First tickle the hardware, only then report what went on. -- REW */ 9.791 - v = apic_read(APIC_ESR); 9.792 - apic_write(APIC_ESR, 0); 9.793 - v1 = apic_read(APIC_ESR); 9.794 - ack_APIC_irq(); 9.795 - atomic_inc(&irq_err_count); 9.796 - 9.797 - /* Here is what the APIC error bits mean: 9.798 - 0: Send CS error 9.799 - 1: Receive CS error 9.800 - 2: Send accept error 9.801 - 3: Receive accept error 9.802 - 4: Reserved 9.803 - 5: Send illegal vector 9.804 - 6: Received illegal vector 9.805 - 7: Illegal register address 9.806 - */ 9.807 - printk ("APIC error on CPU%d: %02lx(%02lx)\n", 9.808 - smp_processor_id(), v , v1); 9.809 -} 9.810 - 9.811 -/* 9.812 - * This initializes the IO-APIC and APIC hardware if this is 9.813 - * a UP kernel. 9.814 - */ 9.815 -int __init APIC_init_uniprocessor (void) 9.816 -{ 9.817 - if (!smp_found_config && !cpu_has_apic) 9.818 - return -1; 9.819 - 9.820 - /* 9.821 - * Complain if the BIOS pretends there is one. 9.822 - */ 9.823 - if (!cpu_has_apic&&APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) 9.824 - { 9.825 - printk("BIOS bug, local APIC #%d not detected!...\n", 9.826 - boot_cpu_physical_apicid); 9.827 - return -1; 9.828 - } 9.829 - 9.830 - verify_local_APIC(); 9.831 - 9.832 - connect_bsp_APIC(); 9.833 - 9.834 - phys_cpu_present_map = 1; 9.835 - apic_write_around(APIC_ID, boot_cpu_physical_apicid); 9.836 - 9.837 - apic_pm_init2(); 9.838 - 9.839 - setup_local_APIC(); 9.840 - 9.841 -#ifdef CONFIG_X86_IO_APIC 9.842 - if (smp_found_config && nr_ioapics) 9.843 - setup_IO_APIC(); 9.844 -#endif 9.845 - setup_APIC_clocks(); 9.846 - 9.847 - return 0; 9.848 -}
10.1 --- a/xen-2.4.16/arch/i386/boot/boot.S Mon Feb 24 16:55:07 2003 +0000 10.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 10.3 @@ -1,239 +0,0 @@ 10.4 -#include <xeno/config.h> 10.5 -#include <asm/page.h> 10.6 - 10.7 -#define SECONDARY_CPU_FLAG 0xA5A5A5A5 10.8 - 10.9 - .text 10.10 - 10.11 -ENTRY(start) 10.12 - jmp hal_entry 10.13 - 10.14 - .align 4 10.15 - 10.16 -/*** MULTIBOOT HEADER ****/ 10.17 - /* Magic number indicating a Multiboot header. */ 10.18 - .long 0x1BADB002 10.19 - /* Flags to bootloader (see Multiboot spec). */ 10.20 - .long 0x00000006 10.21 - /* Checksum: must be the negated sum of the first two fields. */ 10.22 - .long -0x1BADB008 10.23 - /* Unused loader addresses (ELF header has all this already).*/ 10.24 - .long 0,0,0,0,0 10.25 - /* EGA text mode. */ 10.26 - .long 1,0,0,0 10.27 - 10.28 -hal_entry: 10.29 - /* Set up a few descriptors: on entry only CS is guaranteed good. */ 10.30 - lgdt %cs:nopaging_gdt_descr-__PAGE_OFFSET 10.31 - mov $(__HYPERVISOR_DS),%ecx 10.32 - mov %ecx,%ds 10.33 - mov %ecx,%es 10.34 - ljmp $(__HYPERVISOR_CS),$(1f)-__PAGE_OFFSET 10.35 -1: lss stack_start-__PAGE_OFFSET,%esp 10.36 - 10.37 - /* Reset EFLAGS (subsumes CLI and CLD). */ 10.38 - pushl $0 10.39 - popf 10.40 - 10.41 - /* CPU type checks. We need P6+. */ 10.42 - mov $0x200000,%edx 10.43 - pushfl 10.44 - pop %ecx 10.45 - and %edx,%ecx 10.46 - jne bad_cpu # ID bit should be clear 10.47 - pushl %edx 10.48 - popfl 10.49 - pushfl 10.50 - pop %ecx 10.51 - and %edx,%ecx 10.52 - je bad_cpu # ID bit should be set 10.53 - 10.54 - /* Set up CR0. */ 10.55 - mov %cr0,%ecx 10.56 - and $0x00000011,%ecx # save ET and PE 10.57 - or $0x00050022,%ecx # set AM, WP, NE and MP 10.58 - mov %ecx,%cr0 10.59 - 10.60 - /* Set up FPU. */ 10.61 - fninit 10.62 - 10.63 - /* Set up CR4, except global flag which Intel requires should be */ 10.64 - /* left until after paging is enabled (IA32 Manual Vol. 3, Sec. 2.5) */ 10.65 - mov %cr4,%ecx 10.66 - or mmu_cr4_features-__PAGE_OFFSET,%ecx 10.67 - mov %ecx,mmu_cr4_features-__PAGE_OFFSET 10.68 - and $0x7f,%ecx /* disable GLOBAL bit */ 10.69 - mov %ecx,%cr4 10.70 - 10.71 - /* Is this a non-boot processor? */ 10.72 - cmp $(SECONDARY_CPU_FLAG),%ebx 10.73 - jne continue_boot_cpu 10.74 - 10.75 - call start_paging 10.76 - lidt idt_descr 10.77 - jmp initialize_secondary 10.78 - 10.79 -continue_boot_cpu: 10.80 - add $__PAGE_OFFSET,%ebx 10.81 - push %ebx /* Multiboot info struct */ 10.82 - push %eax /* Multiboot magic value */ 10.83 - 10.84 - /* Initialize BSS (no nasty surprises!) */ 10.85 - mov $__bss_start-__PAGE_OFFSET,%edi 10.86 - mov $_end-__PAGE_OFFSET,%ecx 10.87 - sub %edi,%ecx 10.88 - xor %eax,%eax 10.89 - rep stosb 10.90 - 10.91 - /* Initialize low and high mappings of all memory with 4MB pages */ 10.92 - mov $idle0_pg_table-__PAGE_OFFSET,%edi 10.93 - mov $0x1e3,%eax /* PRESENT+RW+A+D+4MB+GLOBAL */ 10.94 -1: mov %eax,__PAGE_OFFSET>>20(%edi) /* high mapping */ 10.95 - stosl /* low mapping */ 10.96 - add $(1<<L2_PAGETABLE_SHIFT),%eax 10.97 - cmp $MAX_DIRECTMAP_ADDRESS+0x1e3,%eax 10.98 - jne 1b 10.99 - 10.100 - call start_paging 10.101 - call setup_idt 10.102 - lidt idt_descr 10.103 - 10.104 - /* Call into main C routine. This should never return.*/ 10.105 - call cmain 10.106 - ud2 /* Force a panic (invalid opcode). */ 10.107 - 10.108 -start_paging: 10.109 - mov $idle0_pg_table-__PAGE_OFFSET,%eax 10.110 - mov %eax,%cr3 10.111 - mov %cr0,%eax 10.112 - or $0x80010000,%eax /* set PG and WP bits */ 10.113 - mov %eax,%cr0 10.114 - jmp 1f 10.115 -1: /* Install relocated selectors (FS/GS unused). */ 10.116 - lgdt gdt_descr 10.117 - mov $(__HYPERVISOR_DS),%ecx 10.118 - mov %ecx,%ds 10.119 - mov %ecx,%es 10.120 - mov %ecx,%ss 10.121 - ljmp $(__HYPERVISOR_CS),$1f 10.122 -1: /* Paging enabled, so we can now enable GLOBAL mappings in CR4. */ 10.123 - movl mmu_cr4_features,%ecx 10.124 - movl %ecx,%cr4 10.125 - /* Relocate ESP */ 10.126 - add $__PAGE_OFFSET,%esp 10.127 - /* Relocate EIP via return jump */ 10.128 - pop %ecx 10.129 - add $__PAGE_OFFSET,%ecx 10.130 - jmp *%ecx 10.131 - 10.132 - 10.133 -/*** INTERRUPT INITIALISATION ***/ 10.134 - 10.135 -setup_idt: 10.136 - lea ignore_int,%edx 10.137 - mov $(__HYPERVISOR_CS << 16),%eax 10.138 - mov %dx,%ax /* selector = 0x0010 = cs */ 10.139 - mov $0x8E00,%dx /* interrupt gate - dpl=0, present */ 10.140 - 10.141 - lea SYMBOL_NAME(idt_table),%edi 10.142 - mov $256,%ecx 10.143 -1: mov %eax,(%edi) 10.144 - mov %edx,4(%edi) 10.145 - add $8,%edi 10.146 - loop 1b 10.147 - ret 10.148 - 10.149 -/* This is the default interrupt handler. */ 10.150 -int_msg: 10.151 - .asciz "Unknown interrupt\n" 10.152 - ALIGN 10.153 -ignore_int: 10.154 - cld 10.155 - push %eax 10.156 - push %ecx 10.157 - push %edx 10.158 - pushl %es 10.159 - pushl %ds 10.160 - mov $(__HYPERVISOR_DS),%eax 10.161 - mov %eax,%ds 10.162 - mov %eax,%es 10.163 - pushl $int_msg 10.164 - call SYMBOL_NAME(printf) 10.165 -1: jmp 1b 10.166 - pop %eax 10.167 - popl %ds 10.168 - popl %es 10.169 - pop %edx 10.170 - pop %ecx 10.171 - pop %eax 10.172 - iret 10.173 - 10.174 - 10.175 -bad_cpu_msg: 10.176 - .asciz "Bad CPU type. Need P6+." 10.177 - ALIGN 10.178 -bad_cpu: 10.179 - call init_serial 10.180 - mov $bad_cpu_msg,%esi 10.181 -1: lodsb 10.182 - test %al,%al 10.183 - je 1f 10.184 - push %eax 10.185 - call putchar_serial 10.186 - add $4,%esp 10.187 - jmp 1b 10.188 -1: jmp 1b 10.189 - 10.190 - 10.191 -/*** STACK LOCATION ***/ 10.192 - 10.193 -ENTRY(stack_start) 10.194 - .long SYMBOL_NAME(idle0_task_union)+8192-__PAGE_OFFSET 10.195 - .long __HYPERVISOR_DS 10.196 - 10.197 -/*** DESCRIPTOR TABLES ***/ 10.198 - 10.199 -.globl SYMBOL_NAME(idt) 10.200 -.globl SYMBOL_NAME(gdt) 10.201 - 10.202 - ALIGN 10.203 - 10.204 - .word 0 10.205 -idt_descr: 10.206 - .word 256*8-1 10.207 -SYMBOL_NAME(idt): 10.208 - .long SYMBOL_NAME(idt_table) 10.209 - 10.210 - .word 0 10.211 -gdt_descr: 10.212 - .word 256*8-1 10.213 -SYMBOL_NAME(gdt): 10.214 - .long SYMBOL_NAME(gdt_table) /* gdt base */ 10.215 - 10.216 - .word 0 10.217 -nopaging_gdt_descr: 10.218 - .word 256*8-1 10.219 - .long SYMBOL_NAME(gdt_table)-__PAGE_OFFSET 10.220 - 10.221 - ALIGN 10.222 -/* NB. Rings != 0 get access up to 0xFC400000. This allows access to the */ 10.223 -/* machine->physical mapping table. Ring 0 can access all memory. */ 10.224 -ENTRY(gdt_table) 10.225 - .quad 0x0000000000000000 /* NULL descriptor */ 10.226 - .quad 0x0000000000000000 /* not used */ 10.227 - .quad 0x00cfba000000c3ff /* 0x11 ring 1 3.95GB code at 0x0 */ 10.228 - .quad 0x00cfb2000000c3ff /* 0x19 ring 1 3.95GB data at 0x0 */ 10.229 - .quad 0x00cffa000000c3ff /* 0x23 ring 3 3.95GB code at 0x0 */ 10.230 - .quad 0x00cff2000000c3ff /* 0x2b ring 3 3.95GB data at 0x0 */ 10.231 - .quad 0x00cf9a000000ffff /* 0x30 ring 0 4.00GB code at 0x0 */ 10.232 - .quad 0x00cf92000000ffff /* 0x38 ring 0 4.00GB data at 0x0 */ 10.233 - .fill NR_CPUS,8,0 /* space for TSS's */ 10.234 - 10.235 -# The following adds 12kB to the kernel file size. 10.236 - .org 0x1000 10.237 -ENTRY(idle0_pg_table) 10.238 - .org 0x2000 10.239 -ENTRY(idle0_task_union) 10.240 - .org 0x4000 10.241 -ENTRY(stext) 10.242 -ENTRY(_stext)
11.1 --- a/xen-2.4.16/arch/i386/delay.c Mon Feb 24 16:55:07 2003 +0000 11.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 11.3 @@ -1,29 +0,0 @@ 11.4 -/* 11.5 - * Precise Delay Loops for i386 11.6 - * 11.7 - * Copyright (C) 1993 Linus Torvalds 11.8 - * Copyright (C) 1997 Martin Mares <mj@atrey.karlin.mff.cuni.cz> 11.9 - * 11.10 - * The __delay function must _NOT_ be inlined as its execution time 11.11 - * depends wildly on alignment on many x86 processors. The additional 11.12 - * jump magic is needed to get the timing stable on all the CPU's 11.13 - * we have to worry about. 11.14 - */ 11.15 - 11.16 -#include <xeno/config.h> 11.17 -#include <xeno/delay.h> 11.18 -#include <asm/msr.h> 11.19 -#include <asm/processor.h> 11.20 - 11.21 -void __udelay(unsigned long usecs) 11.22 -{ 11.23 - unsigned long ticks = usecs * ticks_per_usec; 11.24 - unsigned long s, e; 11.25 - 11.26 - rdtscl(s); 11.27 - do 11.28 - { 11.29 - rep_nop(); 11.30 - rdtscl(e); 11.31 - } while ((e-s) < ticks); 11.32 -}
12.1 --- a/xen-2.4.16/arch/i386/entry.S Mon Feb 24 16:55:07 2003 +0000 12.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 12.3 @@ -1,534 +0,0 @@ 12.4 -/* 12.5 - * linux/arch/i386/entry.S 12.6 - * 12.7 - * Copyright (C) 1991, 1992 Linus Torvalds 12.8 - */ 12.9 - 12.10 -/* 12.11 - * entry.S contains the system-call and fault low-level handling routines. 12.12 - * This also contains the timer-interrupt handler, as well as all interrupts 12.13 - * and faults that can result in a task-switch. 12.14 - * 12.15 - * Stack layout in 'ret_from_system_call': 12.16 - * 0(%esp) - %ebx 12.17 - * 4(%esp) - %ecx 12.18 - * 8(%esp) - %edx 12.19 - * C(%esp) - %esi 12.20 - * 10(%esp) - %edi 12.21 - * 14(%esp) - %ebp 12.22 - * 18(%esp) - %eax 12.23 - * 1C(%esp) - %ds 12.24 - * 20(%esp) - %es 12.25 - * 24(%esp) - orig_eax 12.26 - * 28(%esp) - %eip 12.27 - * 2C(%esp) - %cs 12.28 - * 30(%esp) - %eflags 12.29 - * 34(%esp) - %oldesp 12.30 - * 38(%esp) - %oldss 12.31 - * 12.32 - * "current" is in register %ebx during any slow entries. 12.33 - */ 12.34 -/* The idea for callbacks from monitor -> guest OS. 12.35 - * 12.36 - * First, we require that all callbacks (either via a supplied 12.37 - * interrupt-descriptor-table, or via the special event or failsafe callbacks 12.38 - * in the shared-info-structure) are to ring 1. This just makes life easier, 12.39 - * in that it means we don't have to do messy GDT/LDT lookups to find 12.40 - * out which the privilege-level of the return code-selector. That code 12.41 - * would just be a hassle to write, and would need to account for running 12.42 - * off the end of the GDT/LDT, for example. The event callback has quite 12.43 - * a constrained callback method: the guest OS provides a linear address 12.44 - * which we call back to using the hard-coded __GUEST_CS descriptor (which 12.45 - * is a ring 1 descriptor). For IDT callbacks, we check that the provided 12.46 - * return CS is not == __HYPERVISOR_{CS,DS}. Apart from that we're safe as 12.47 - * don't allow a guest OS to install ring-0 privileges into the GDT/LDT. 12.48 - * It's up to the guest OS to ensure all returns via the IDT are to ring 1. 12.49 - * If not, we load incorrect SS/ESP values from the TSS (for ring 1 rather 12.50 - * than the correct ring) and bad things are bound to ensue -- IRET is 12.51 - * likely to fault, and we may end up killing the domain (no harm can 12.52 - * come to the hypervisor itself, though). 12.53 - * 12.54 - * When doing a callback, we check if the return CS is in ring 0. If so, 12.55 - * callback is delayed until next return to ring != 0. 12.56 - * If return CS is in ring 1, then we create a callback frame 12.57 - * starting at return SS/ESP. The base of the frame does an intra-privilege 12.58 - * interrupt-return. 12.59 - * If return CS is in ring > 1, we create a callback frame starting 12.60 - * at SS/ESP taken from appropriate section of the current TSS. The base 12.61 - * of the frame does an inter-privilege interrupt-return. 12.62 - * 12.63 - * Note that the "failsafe callback" uses a special stackframe: 12.64 - * { return_DS, return_ES, return_EIP, return_CS, return_EFLAGS, ... } 12.65 - * That is, original values for DS/ES are placed on stack rather than 12.66 - * in DS/ES themselves. Why? It saves us loading them, only to have them 12.67 - * saved/restored in guest OS. Furthermore, if we load them we may cause 12.68 - * a fault if they are invalid, which is a hassle to deal with. We avoid 12.69 - * that problem if we don't load them :-) This property allows us to use 12.70 - * the failsafe callback as a fallback: if we ever fault on loading DS/ES 12.71 - * on return to ring != 0, we can simply package it up as a return via 12.72 - * the failsafe callback, and let the guest OS sort it out (perhaps by 12.73 - * killing an application process). Note that we also do this for any 12.74 - * faulting IRET -- just let the guest OS handle it via the event 12.75 - * callback. 12.76 - * 12.77 - * We terminate a domain in the following cases: 12.78 - * - creating a callback stack frame (due to bad ring-1 stack). 12.79 - * - faulting IRET on entry to failsafe callback handler. 12.80 - * So, each domain must keep its ring-1 %ss/%esp and failsafe callback 12.81 - * handler in good order (absolutely no faults allowed!). 12.82 - */ 12.83 - 12.84 -#include <xeno/config.h> 12.85 -#include <asm/smp.h> 12.86 - 12.87 -EBX = 0x00 12.88 -ECX = 0x04 12.89 -EDX = 0x08 12.90 -ESI = 0x0C 12.91 -EDI = 0x10 12.92 -EBP = 0x14 12.93 -EAX = 0x18 12.94 -DS = 0x1C 12.95 -ES = 0x20 12.96 -ORIG_EAX = 0x24 12.97 -EIP = 0x28 12.98 -CS = 0x2C 12.99 -EFLAGS = 0x30 12.100 -OLDESP = 0x34 12.101 -OLDSS = 0x38 12.102 - 12.103 -/* Offsets in task_struct */ 12.104 -PROCESSOR = 0 12.105 -STATE = 4 12.106 -HYP_EVENTS = 8 12.107 -DOMAIN = 12 12.108 -SHARED_INFO = 16 12.109 - 12.110 -/* Offsets in shared_info_t */ 12.111 -EVENTS = 0 12.112 -EVENTS_ENABLE = 4 12.113 -EVENT_ADDR = 8 12.114 -FAILSAFE_ADDR = 12 12.115 - 12.116 -/* Offsets in guest_trap_bounce */ 12.117 -GTB_ERROR_CODE = 0 12.118 -GTB_CR2 = 4 12.119 -GTB_FLAGS = 8 12.120 -GTB_CS = 10 12.121 -GTB_EIP = 12 12.122 -GTBF_TRAP = 1 12.123 -GTBF_TRAP_NOCODE = 2 12.124 -GTBF_TRAP_CR2 = 4 12.125 - 12.126 -CF_MASK = 0x00000001 12.127 -IF_MASK = 0x00000200 12.128 -NT_MASK = 0x00004000 12.129 - 12.130 -#define SAVE_ALL \ 12.131 - cld; \ 12.132 - pushl %es; \ 12.133 - pushl %ds; \ 12.134 - pushl %eax; \ 12.135 - pushl %ebp; \ 12.136 - pushl %edi; \ 12.137 - pushl %esi; \ 12.138 - pushl %edx; \ 12.139 - pushl %ecx; \ 12.140 - pushl %ebx; \ 12.141 - movl $(__HYPERVISOR_DS),%edx; \ 12.142 - movl %edx,%ds; \ 12.143 - movl %edx,%es; 12.144 - 12.145 -#define RESTORE_ALL \ 12.146 - popl %ebx; \ 12.147 - popl %ecx; \ 12.148 - popl %edx; \ 12.149 - popl %esi; \ 12.150 - popl %edi; \ 12.151 - popl %ebp; \ 12.152 - popl %eax; \ 12.153 -1: popl %ds; \ 12.154 -2: popl %es; \ 12.155 - addl $4,%esp; \ 12.156 -3: iret; \ 12.157 -.section .fixup,"ax"; \ 12.158 -6: subl $4,%esp; \ 12.159 - pushl %es; \ 12.160 -5: pushl %ds; \ 12.161 -4: pushl %eax; \ 12.162 - pushl %ebp; \ 12.163 - pushl %edi; \ 12.164 - pushl %esi; \ 12.165 - pushl %edx; \ 12.166 - pushl %ecx; \ 12.167 - pushl %ebx; \ 12.168 - pushl %ss; \ 12.169 - popl %ds; \ 12.170 - pushl %ss; \ 12.171 - popl %es; \ 12.172 - jmp failsafe_callback; \ 12.173 -.previous; \ 12.174 -.section __ex_table,"a"; \ 12.175 - .align 4; \ 12.176 - .long 1b,4b; \ 12.177 - .long 2b,5b; \ 12.178 - .long 3b,6b; \ 12.179 -.previous 12.180 - 12.181 -#define GET_CURRENT(reg) \ 12.182 - movl $-8192, reg; \ 12.183 - andl %esp, reg 12.184 - 12.185 -ENTRY(ret_from_newdomain) 12.186 - GET_CURRENT(%ebx) 12.187 - jmp test_all_events 12.188 - 12.189 - ALIGN 12.190 -restore_all: 12.191 - RESTORE_ALL 12.192 - 12.193 - ALIGN 12.194 -ENTRY(hypervisor_call) 12.195 - pushl %eax # save orig_eax 12.196 - SAVE_ALL 12.197 - GET_CURRENT(%ebx) 12.198 - andl $255,%eax 12.199 - call *SYMBOL_NAME(hypervisor_call_table)(,%eax,4) 12.200 - movl %eax,EAX(%esp) # save the return value 12.201 - 12.202 -test_all_events: 12.203 - mov PROCESSOR(%ebx),%eax 12.204 - shl $4,%eax # sizeof(irq_cpustat) == 16 12.205 - lea guest_trap_bounce(%eax),%edx 12.206 - cli # tests must not race interrupts 12.207 - xorl %ecx,%ecx 12.208 - notl %ecx 12.209 -test_softirqs: 12.210 - mov PROCESSOR(%ebx),%eax 12.211 - shl $4,%eax # sizeof(irq_cpustat) == 16 12.212 - test %ecx,SYMBOL_NAME(irq_stat)(%eax,1) 12.213 - jnz process_softirqs 12.214 -test_hyp_events: 12.215 - test %ecx, HYP_EVENTS(%ebx) 12.216 - jnz process_hyp_events 12.217 -test_guest_events: 12.218 - movl SHARED_INFO(%ebx),%eax 12.219 - test %ecx,EVENTS(%eax) 12.220 - jz restore_all 12.221 - test %ecx,EVENTS_ENABLE(%eax) 12.222 - jz restore_all 12.223 - /* Prevent unnecessary reentry of event callback (stack overflow!) */ 12.224 - xorl %ecx,%ecx 12.225 - movl %ecx,EVENTS_ENABLE(%eax) 12.226 -/* %eax == shared_info, %ebx == task_struct, %edx == guest_trap_bounce */ 12.227 -process_guest_events: 12.228 - movl EVENT_ADDR(%eax),%eax 12.229 - movl %eax,GTB_EIP(%edx) 12.230 - movw $__GUEST_CS,GTB_CS(%edx) 12.231 - call create_bounce_frame 12.232 - jmp restore_all 12.233 - 12.234 - ALIGN 12.235 -process_softirqs: 12.236 - push %edx 12.237 - call SYMBOL_NAME(do_softirq) 12.238 - pop %edx 12.239 - jmp test_hyp_events 12.240 - 12.241 - ALIGN 12.242 -process_hyp_events: 12.243 - sti 12.244 - call SYMBOL_NAME(do_hyp_events) 12.245 - jmp test_all_events 12.246 - 12.247 -/* No special register assumptions */ 12.248 -failsafe_callback: 12.249 - GET_CURRENT(%ebx) 12.250 - mov PROCESSOR(%ebx),%eax 12.251 - shl $4,%eax 12.252 - lea guest_trap_bounce(%eax),%edx 12.253 - movl SHARED_INFO(%ebx),%eax 12.254 - movl FAILSAFE_ADDR(%eax),%eax 12.255 - movl %eax,GTB_EIP(%edx) 12.256 - movw $__GUEST_CS,GTB_CS(%edx) 12.257 - call create_bounce_frame 12.258 - subl $8,%esi # add DS/ES to failsafe stack frame 12.259 - movl DS(%esp),%eax 12.260 -FAULT1: movl %eax,(%esi) 12.261 - movl ES(%esp),%eax 12.262 -FAULT2: movl %eax,4(%esi) 12.263 - movl %esi,OLDESP(%esp) 12.264 - popl %ebx 12.265 - popl %ecx 12.266 - popl %edx 12.267 - popl %esi 12.268 - popl %edi 12.269 - popl %ebp 12.270 - popl %eax 12.271 - addl $12,%esp 12.272 -FAULT3: iret 12.273 - 12.274 - 12.275 -/* CREATE A BASIC EXCEPTION FRAME ON GUEST OS (RING-1) STACK: */ 12.276 -/* {EIP, CS, EFLAGS, [ESP, SS]} */ 12.277 -/* %edx == guest_trap_bounce, %ebx == task_struct */ 12.278 -/* %eax,%ecx are clobbered. %ds:%esi contain new OLDSS/OLDESP. */ 12.279 -create_bounce_frame: 12.280 - mov CS+4(%esp),%cl 12.281 - test $2,%cl 12.282 - jz 1f /* jump if returning to an existing ring-1 activation */ 12.283 - /* obtain ss/esp from TSS -- no current ring-1 activations */ 12.284 - movl PROCESSOR(%ebx),%eax 12.285 - shll $8,%eax /* multiply by 256 */ 12.286 - addl $init_tss + 12,%eax 12.287 - movl (%eax),%esi /* tss->esp1 */ 12.288 -FAULT4: movl 4(%eax),%ds /* tss->ss1 */ 12.289 - /* base of stack frame must contain ss/esp (inter-priv iret) */ 12.290 - subl $8,%esi 12.291 - movl OLDESP+4(%esp),%eax 12.292 -FAULT5: movl %eax,(%esi) 12.293 - movl OLDSS+4(%esp),%eax 12.294 -FAULT6: movl %eax,4(%esi) 12.295 - jmp 2f 12.296 -1: /* obtain ss/esp from oldss/oldesp -- a ring-1 activation exists */ 12.297 - movl OLDESP+4(%esp),%esi 12.298 -FAULT7: movl OLDSS+4(%esp),%ds 12.299 -2: /* Construct a stack frame: EFLAGS, CS/EIP */ 12.300 - subl $12,%esi 12.301 - movl EIP+4(%esp),%eax 12.302 -FAULT8: movl %eax,(%esi) 12.303 - movl CS+4(%esp),%eax 12.304 -FAULT9: movl %eax,4(%esi) 12.305 - movl EFLAGS+4(%esp),%eax 12.306 -FAULT10:movl %eax,8(%esi) 12.307 - /* Rewrite our stack frame and return to ring 1. */ 12.308 - /* IA32 Ref. Vol. 3: TF, VM, RF and NT flags are cleared on trap. */ 12.309 - andl $0xfffcbeff,%eax 12.310 - movl %eax,EFLAGS+4(%esp) 12.311 - movl %ds,OLDSS+4(%esp) 12.312 - movl %esi,OLDESP+4(%esp) 12.313 - movzwl %es:GTB_CS(%edx),%eax 12.314 - movl %eax,CS+4(%esp) 12.315 - movl %es:GTB_EIP(%edx),%eax 12.316 - movl %eax,EIP+4(%esp) 12.317 - ret 12.318 - 12.319 - 12.320 -.section __ex_table,"a" 12.321 - .align 4 12.322 - .long FAULT1, kill_domain_fixup3 # Fault writing to ring-1 stack 12.323 - .long FAULT2, kill_domain_fixup3 # Fault writing to ring-1 stack 12.324 - .long FAULT3, kill_domain_fixup1 # Fault executing failsafe iret 12.325 - .long FAULT4, kill_domain_fixup2 # Fault loading ring-1 stack selector 12.326 - .long FAULT5, kill_domain_fixup2 # Fault writing to ring-1 stack 12.327 - .long FAULT6, kill_domain_fixup2 # Fault writing to ring-1 stack 12.328 - .long FAULT7, kill_domain_fixup2 # Fault loading ring-1 stack selector 12.329 - .long FAULT8, kill_domain_fixup2 # Fault writing to ring-1 stack 12.330 - .long FAULT9, kill_domain_fixup2 # Fault writing to ring-1 stack 12.331 - .long FAULT10,kill_domain_fixup2 # Fault writing to ring-1 stack 12.332 - .long FAULT11,kill_domain_fixup3 # Fault writing to ring-1 stack 12.333 - .long FAULT12,kill_domain_fixup3 # Fault writing to ring-1 stack 12.334 -.previous 12.335 - 12.336 -# This handler kills domains which experience unrecoverable faults. 12.337 -.section .fixup,"ax" 12.338 -kill_domain_fixup1: 12.339 - subl $4,%esp 12.340 - SAVE_ALL 12.341 - jmp kill_domain 12.342 -kill_domain_fixup2: 12.343 - addl $4,%esp 12.344 -kill_domain_fixup3: 12.345 - pushl %ss 12.346 - popl %ds 12.347 - jmp kill_domain 12.348 -.previous 12.349 - 12.350 - ALIGN 12.351 -process_guest_exception_and_events: 12.352 - mov PROCESSOR(%ebx),%eax 12.353 - shl $4,%eax # sizeof(irq_cpustat) == 16 12.354 - lea guest_trap_bounce(%eax),%edx 12.355 - testb $~0,GTB_FLAGS(%edx) 12.356 - jz test_all_events 12.357 - call create_bounce_frame # just the basic frame 12.358 - mov %es:GTB_FLAGS(%edx),%cl 12.359 - test $GTBF_TRAP_NOCODE,%cl 12.360 - jnz 2f 12.361 - subl $4,%esi # push error_code onto guest frame 12.362 - movl %es:GTB_ERROR_CODE(%edx),%eax 12.363 -FAULT11:movl %eax,(%esi) 12.364 - test $GTBF_TRAP_CR2,%cl 12.365 - jz 1f 12.366 - subl $4,%esi # push %cr2 onto guest frame 12.367 - movl %es:GTB_CR2(%edx),%eax 12.368 -FAULT12:movl %eax,(%esi) 12.369 -1: movl %esi,OLDESP(%esp) 12.370 -2: push %es # unclobber %ds 12.371 - pop %ds 12.372 - movb $0,GTB_FLAGS(%edx) 12.373 - jmp test_all_events 12.374 - 12.375 - ALIGN 12.376 -ENTRY(ret_from_intr) 12.377 - GET_CURRENT(%ebx) 12.378 - movb CS(%esp),%al 12.379 - testb $3,%al # return to non-supervisor? 12.380 - jne test_all_events 12.381 - jmp restore_all 12.382 - 12.383 - ALIGN 12.384 -ret_from_exception: 12.385 - movb CS(%esp),%al 12.386 - testb $3,%al # return to non-supervisor? 12.387 - jne process_guest_exception_and_events 12.388 - jmp restore_all 12.389 - 12.390 - ALIGN 12.391 - 12.392 -ENTRY(divide_error) 12.393 - pushl $0 # no error code 12.394 - pushl $ SYMBOL_NAME(do_divide_error) 12.395 - ALIGN 12.396 -error_code: 12.397 - pushl %ds 12.398 - pushl %eax 12.399 - xorl %eax,%eax 12.400 - pushl %ebp 12.401 - pushl %edi 12.402 - pushl %esi 12.403 - pushl %edx 12.404 - decl %eax # eax = -1 12.405 - pushl %ecx 12.406 - pushl %ebx 12.407 - cld 12.408 - movl %es,%ecx 12.409 - movl ORIG_EAX(%esp), %esi # get the error code 12.410 - movl ES(%esp), %edi # get the function address 12.411 - movl %eax, ORIG_EAX(%esp) 12.412 - movl %ecx, ES(%esp) 12.413 - movl %esp,%edx 12.414 - pushl %esi # push the error code 12.415 - pushl %edx # push the pt_regs pointer 12.416 - movl $(__HYPERVISOR_DS),%edx 12.417 - movl %edx,%ds 12.418 - movl %edx,%es 12.419 - GET_CURRENT(%ebx) 12.420 - call *%edi 12.421 - addl $8,%esp 12.422 - jmp ret_from_exception 12.423 - 12.424 -ENTRY(coprocessor_error) 12.425 - pushl $0 12.426 - pushl $ SYMBOL_NAME(do_coprocessor_error) 12.427 - jmp error_code 12.428 - 12.429 -ENTRY(simd_coprocessor_error) 12.430 - pushl $0 12.431 - pushl $ SYMBOL_NAME(do_simd_coprocessor_error) 12.432 - jmp error_code 12.433 - 12.434 -ENTRY(device_not_available) 12.435 - pushl $0 12.436 - pushl $SYMBOL_NAME(math_state_restore) 12.437 - jmp error_code 12.438 - 12.439 -ENTRY(debug) 12.440 - pushl $0 12.441 - pushl $ SYMBOL_NAME(do_debug) 12.442 - jmp error_code 12.443 - 12.444 -ENTRY(nmi) 12.445 - pushl %eax 12.446 - SAVE_ALL 12.447 - movl %esp,%edx 12.448 - pushl $0 12.449 - pushl %edx 12.450 - call SYMBOL_NAME(do_nmi) 12.451 - addl $8,%esp 12.452 - RESTORE_ALL 12.453 - 12.454 -ENTRY(int3) 12.455 - pushl $0 12.456 - pushl $ SYMBOL_NAME(do_int3) 12.457 - jmp error_code 12.458 - 12.459 -ENTRY(overflow) 12.460 - pushl $0 12.461 - pushl $ SYMBOL_NAME(do_overflow) 12.462 - jmp error_code 12.463 - 12.464 -ENTRY(bounds) 12.465 - pushl $0 12.466 - pushl $ SYMBOL_NAME(do_bounds) 12.467 - jmp error_code 12.468 - 12.469 -ENTRY(invalid_op) 12.470 - pushl $0 12.471 - pushl $ SYMBOL_NAME(do_invalid_op) 12.472 - jmp error_code 12.473 - 12.474 -ENTRY(coprocessor_segment_overrun) 12.475 - pushl $0 12.476 - pushl $ SYMBOL_NAME(do_coprocessor_segment_overrun) 12.477 - jmp error_code 12.478 - 12.479 -ENTRY(double_fault) 12.480 - pushl $ SYMBOL_NAME(do_double_fault) 12.481 - jmp error_code 12.482 - 12.483 -ENTRY(invalid_TSS) 12.484 - pushl $ SYMBOL_NAME(do_invalid_TSS) 12.485 - jmp error_code 12.486 - 12.487 -ENTRY(segment_not_present) 12.488 - pushl $ SYMBOL_NAME(do_segment_not_present) 12.489 - jmp error_code 12.490 - 12.491 -ENTRY(stack_segment) 12.492 - pushl $ SYMBOL_NAME(do_stack_segment) 12.493 - jmp error_code 12.494 - 12.495 -ENTRY(general_protection) 12.496 - pushl $ SYMBOL_NAME(do_general_protection) 12.497 - jmp error_code 12.498 - 12.499 -ENTRY(alignment_check) 12.500 - pushl $ SYMBOL_NAME(do_alignment_check) 12.501 - jmp error_code 12.502 - 12.503 -ENTRY(page_fault) 12.504 - pushl $ SYMBOL_NAME(do_page_fault) 12.505 - jmp error_code 12.506 - 12.507 -ENTRY(machine_check) 12.508 - pushl $0 12.509 - pushl $ SYMBOL_NAME(do_machine_check) 12.510 - jmp error_code 12.511 - 12.512 -ENTRY(spurious_interrupt_bug) 12.513 - pushl $0 12.514 - pushl $ SYMBOL_NAME(do_spurious_interrupt_bug) 12.515 - jmp error_code 12.516 - 12.517 -.data 12.518 -ENTRY(hypervisor_call_table) 12.519 - .long SYMBOL_NAME(do_set_trap_table) 12.520 - .long SYMBOL_NAME(do_process_page_updates) 12.521 - .long SYMBOL_NAME(do_console_write) 12.522 - .long SYMBOL_NAME(do_set_gdt) 12.523 - .long SYMBOL_NAME(do_stack_and_ldt_switch) 12.524 - .long SYMBOL_NAME(do_net_update) 12.525 - .long SYMBOL_NAME(do_fpu_taskswitch) 12.526 - .long SYMBOL_NAME(do_sched_op) 12.527 - .long SYMBOL_NAME(kill_domain) 12.528 - .long SYMBOL_NAME(do_dom0_op) 12.529 - .long SYMBOL_NAME(do_network_op) 12.530 - .long SYMBOL_NAME(do_block_io_op) 12.531 - .long SYMBOL_NAME(do_set_debugreg) 12.532 - .long SYMBOL_NAME(do_get_debugreg) 12.533 - .long SYMBOL_NAME(do_update_descriptor) 12.534 - .long SYMBOL_NAME(do_set_fast_trap) 12.535 - .rept NR_syscalls-(.-hypervisor_call_table)/4 12.536 - .long SYMBOL_NAME(sys_ni_syscall) 12.537 - .endr
13.1 --- a/xen-2.4.16/arch/i386/extable.c Mon Feb 24 16:55:07 2003 +0000 13.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 13.3 @@ -1,62 +0,0 @@ 13.4 -/* 13.5 - * linux/arch/i386/mm/extable.c 13.6 - */ 13.7 - 13.8 -#include <linux/config.h> 13.9 -#include <linux/module.h> 13.10 -#include <linux/spinlock.h> 13.11 -#include <asm/uaccess.h> 13.12 - 13.13 -extern const struct exception_table_entry __start___ex_table[]; 13.14 -extern const struct exception_table_entry __stop___ex_table[]; 13.15 - 13.16 -static inline unsigned long 13.17 -search_one_table(const struct exception_table_entry *first, 13.18 - const struct exception_table_entry *last, 13.19 - unsigned long value) 13.20 -{ 13.21 - while (first <= last) { 13.22 - const struct exception_table_entry *mid; 13.23 - long diff; 13.24 - 13.25 - mid = (last - first) / 2 + first; 13.26 - diff = mid->insn - value; 13.27 - if (diff == 0) 13.28 - return mid->fixup; 13.29 - else if (diff < 0) 13.30 - first = mid+1; 13.31 - else 13.32 - last = mid-1; 13.33 - } 13.34 - return 0; 13.35 -} 13.36 - 13.37 -extern spinlock_t modlist_lock; 13.38 - 13.39 -unsigned long 13.40 -search_exception_table(unsigned long addr) 13.41 -{ 13.42 - unsigned long ret = 0; 13.43 - 13.44 -#ifndef CONFIG_MODULES 13.45 - /* There is only the kernel to search. */ 13.46 - ret = search_one_table(__start___ex_table, __stop___ex_table-1, addr); 13.47 - return ret; 13.48 -#else 13.49 - unsigned long flags; 13.50 - /* The kernel is the last "module" -- no need to treat it special. */ 13.51 - struct module *mp; 13.52 - 13.53 - spin_lock_irqsave(&modlist_lock, flags); 13.54 - for (mp = module_list; mp != NULL; mp = mp->next) { 13.55 - if (mp->ex_table_start == NULL || !(mp->flags&(MOD_RUNNING|MOD_INITIALIZING))) 13.56 - continue; 13.57 - ret = search_one_table(mp->ex_table_start, 13.58 - mp->ex_table_end - 1, addr); 13.59 - if (ret) 13.60 - break; 13.61 - } 13.62 - spin_unlock_irqrestore(&modlist_lock, flags); 13.63 - return ret; 13.64 -#endif 13.65 -}
14.1 --- a/xen-2.4.16/arch/i386/i387.c Mon Feb 24 16:55:07 2003 +0000 14.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 14.3 @@ -1,56 +0,0 @@ 14.4 -/* 14.5 - * linux/arch/i386/kernel/i387.c 14.6 - * 14.7 - * Copyright (C) 1994 Linus Torvalds 14.8 - * 14.9 - * Pentium III FXSR, SSE support 14.10 - * General FPU state handling cleanups 14.11 - * Gareth Hughes <gareth@valinux.com>, May 2000 14.12 - */ 14.13 - 14.14 -#include <xeno/config.h> 14.15 -#include <xeno/sched.h> 14.16 -#include <asm/processor.h> 14.17 -#include <asm/i387.h> 14.18 - 14.19 -void init_fpu(void) 14.20 -{ 14.21 - __asm__("fninit"); 14.22 - if ( cpu_has_xmm ) load_mxcsr(0x1f80); 14.23 - current->flags |= PF_DONEFPUINIT; 14.24 -} 14.25 - 14.26 -static inline void __save_init_fpu( struct task_struct *tsk ) 14.27 -{ 14.28 - if ( cpu_has_fxsr ) { 14.29 - asm volatile( "fxsave %0 ; fnclex" 14.30 - : "=m" (tsk->thread.i387.fxsave) ); 14.31 - } else { 14.32 - asm volatile( "fnsave %0 ; fwait" 14.33 - : "=m" (tsk->thread.i387.fsave) ); 14.34 - } 14.35 - tsk->flags &= ~PF_USEDFPU; 14.36 -} 14.37 - 14.38 -void save_init_fpu( struct task_struct *tsk ) 14.39 -{ 14.40 - /* 14.41 - * The guest OS may have set the 'virtual STTS' flag. 14.42 - * This causes us to set the real flag, so we'll need 14.43 - * to temporarily clear it while saving f-p state. 14.44 - */ 14.45 - if ( tsk->flags & PF_GUEST_STTS ) clts(); 14.46 - __save_init_fpu(tsk); 14.47 - stts(); 14.48 -} 14.49 - 14.50 -void restore_fpu( struct task_struct *tsk ) 14.51 -{ 14.52 - if ( cpu_has_fxsr ) { 14.53 - asm volatile( "fxrstor %0" 14.54 - : : "m" (tsk->thread.i387.fxsave) ); 14.55 - } else { 14.56 - asm volatile( "frstor %0" 14.57 - : : "m" (tsk->thread.i387.fsave) ); 14.58 - } 14.59 -}
15.1 --- a/xen-2.4.16/arch/i386/i8259.c Mon Feb 24 16:55:07 2003 +0000 15.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 15.3 @@ -1,481 +0,0 @@ 15.4 -/****************************************************************************** 15.5 - * i8259.c 15.6 - * 15.7 - * Well, this is required for SMP systems as well, as it build interrupt 15.8 - * tables for IO APICS as well as uniprocessor 8259-alikes. 15.9 - */ 15.10 - 15.11 -#include <xeno/config.h> 15.12 -#include <xeno/init.h> 15.13 -#include <asm/ptrace.h> 15.14 -#include <xeno/errno.h> 15.15 -#include <xeno/sched.h> 15.16 -#include <xeno/interrupt.h> 15.17 -#include <xeno/irq.h> 15.18 - 15.19 -#include <asm/atomic.h> 15.20 -#include <asm/system.h> 15.21 -#include <asm/io.h> 15.22 -#include <asm/desc.h> 15.23 -#include <asm/bitops.h> 15.24 -#include <xeno/delay.h> 15.25 -#include <asm/apic.h> 15.26 - 15.27 - 15.28 -/* 15.29 - * Common place to define all x86 IRQ vectors 15.30 - * 15.31 - * This builds up the IRQ handler stubs using some ugly macros in irq.h 15.32 - * 15.33 - * These macros create the low-level assembly IRQ routines that save 15.34 - * register context and call do_IRQ(). do_IRQ() then does all the 15.35 - * operations that are needed to keep the AT (or SMP IOAPIC) 15.36 - * interrupt-controller happy. 15.37 - */ 15.38 - 15.39 -BUILD_COMMON_IRQ() 15.40 - 15.41 -#define BI(x,y) \ 15.42 - BUILD_IRQ(x##y) 15.43 - 15.44 -#define BUILD_16_IRQS(x) \ 15.45 - BI(x,0) BI(x,1) BI(x,2) BI(x,3) \ 15.46 - BI(x,4) BI(x,5) BI(x,6) BI(x,7) \ 15.47 - BI(x,8) BI(x,9) BI(x,a) BI(x,b) \ 15.48 - BI(x,c) BI(x,d) BI(x,e) BI(x,f) 15.49 - 15.50 -/* 15.51 - * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts: 15.52 - * (these are usually mapped to vectors 0x30-0x3f) 15.53 - */ 15.54 - BUILD_16_IRQS(0x0) 15.55 - 15.56 -#ifdef CONFIG_X86_IO_APIC 15.57 -/* 15.58 - * The IO-APIC gives us many more interrupt sources. Most of these 15.59 - * are unused but an SMP system is supposed to have enough memory ... 15.60 - * sometimes (mostly wrt. hw bugs) we get corrupted vectors all 15.61 - * across the spectrum, so we really want to be prepared to get all 15.62 - * of these. Plus, more powerful systems might have more than 64 15.63 - * IO-APIC registers. 15.64 - * 15.65 - * (these are usually mapped into the 0x30-0xff vector range) 15.66 - */ 15.67 - BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3) 15.68 - BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7) 15.69 - BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb) 15.70 - BUILD_16_IRQS(0xc) 15.71 -#endif 15.72 - 15.73 -#undef BUILD_16_IRQS 15.74 -#undef BI 15.75 - 15.76 - 15.77 -/* 15.78 - * The following vectors are part of the Linux architecture, there 15.79 - * is no hardware IRQ pin equivalent for them, they are triggered 15.80 - * through the ICC by us (IPIs) 15.81 - */ 15.82 -#ifdef CONFIG_SMP 15.83 - BUILD_SMP_INTERRUPT(event_check_interrupt,EVENT_CHECK_VECTOR) 15.84 - BUILD_SMP_INTERRUPT(invalidate_interrupt,INVALIDATE_TLB_VECTOR) 15.85 - BUILD_SMP_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR) 15.86 -#endif 15.87 - 15.88 -/* 15.89 - * every pentium local APIC has two 'local interrupts', with a 15.90 - * soft-definable vector attached to both interrupts, one of 15.91 - * which is a timer interrupt, the other one is error counter 15.92 - * overflow. Linux uses the local APIC timer interrupt to get 15.93 - * a much simpler SMP time architecture: 15.94 - */ 15.95 -#ifdef CONFIG_X86_LOCAL_APIC 15.96 - BUILD_SMP_TIMER_INTERRUPT(apic_timer_interrupt,LOCAL_TIMER_VECTOR) 15.97 - BUILD_SMP_INTERRUPT(error_interrupt,ERROR_APIC_VECTOR) 15.98 - BUILD_SMP_INTERRUPT(spurious_interrupt,SPURIOUS_APIC_VECTOR) 15.99 -#endif 15.100 - 15.101 -#define IRQ(x,y) \ 15.102 - IRQ##x##y##_interrupt 15.103 - 15.104 -#define IRQLIST_16(x) \ 15.105 - IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \ 15.106 - IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \ 15.107 - IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \ 15.108 - IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f) 15.109 - 15.110 - void (*interrupt[NR_IRQS])(void) = { 15.111 - IRQLIST_16(0x0), 15.112 - 15.113 -#ifdef CONFIG_X86_IO_APIC 15.114 - IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3), 15.115 - IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7), 15.116 - IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb), 15.117 - IRQLIST_16(0xc) 15.118 -#endif 15.119 - }; 15.120 - 15.121 -#undef IRQ 15.122 -#undef IRQLIST_16 15.123 - 15.124 -/* 15.125 - * This is the 'legacy' 8259A Programmable Interrupt Controller, 15.126 - * present in the majority of PC/AT boxes. 15.127 - * plus some generic x86 specific things if generic specifics makes 15.128 - * any sense at all. 15.129 - * this file should become arch/i386/kernel/irq.c when the old irq.c 15.130 - * moves to arch independent land 15.131 - */ 15.132 - 15.133 -spinlock_t i8259A_lock = SPIN_LOCK_UNLOCKED; 15.134 - 15.135 -static void end_8259A_irq (unsigned int irq) 15.136 -{ 15.137 - if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 15.138 - enable_8259A_irq(irq); 15.139 -} 15.140 - 15.141 -#define shutdown_8259A_irq disable_8259A_irq 15.142 - 15.143 -void mask_and_ack_8259A(unsigned int); 15.144 - 15.145 -static unsigned int startup_8259A_irq(unsigned int irq) 15.146 -{ 15.147 - enable_8259A_irq(irq); 15.148 - return 0; /* never anything pending */ 15.149 -} 15.150 - 15.151 -static struct hw_interrupt_type i8259A_irq_type = { 15.152 - "XT-PIC", 15.153 - startup_8259A_irq, 15.154 - shutdown_8259A_irq, 15.155 - enable_8259A_irq, 15.156 - disable_8259A_irq, 15.157 - mask_and_ack_8259A, 15.158 - end_8259A_irq, 15.159 - NULL 15.160 -}; 15.161 - 15.162 -/* 15.163 - * 8259A PIC functions to handle ISA devices: 15.164 - */ 15.165 - 15.166 -/* 15.167 - * This contains the irq mask for both 8259A irq controllers, 15.168 - */ 15.169 -static unsigned int cached_irq_mask = 0xffff; 15.170 - 15.171 -#define __byte(x,y) (((unsigned char *)&(y))[x]) 15.172 -#define cached_21 (__byte(0,cached_irq_mask)) 15.173 -#define cached_A1 (__byte(1,cached_irq_mask)) 15.174 - 15.175 -/* 15.176 - * Not all IRQs can be routed through the IO-APIC, eg. on certain (older) 15.177 - * boards the timer interrupt is not really connected to any IO-APIC pin, 15.178 - * it's fed to the master 8259A's IR0 line only. 15.179 - * 15.180 - * Any '1' bit in this mask means the IRQ is routed through the IO-APIC. 15.181 - * this 'mixed mode' IRQ handling costs nothing because it's only used 15.182 - * at IRQ setup time. 15.183 - */ 15.184 -unsigned long io_apic_irqs; 15.185 - 15.186 -void disable_8259A_irq(unsigned int irq) 15.187 -{ 15.188 - unsigned int mask = 1 << irq; 15.189 - unsigned long flags; 15.190 - 15.191 - spin_lock_irqsave(&i8259A_lock, flags); 15.192 - cached_irq_mask |= mask; 15.193 - if (irq & 8) 15.194 - outb(cached_A1,0xA1); 15.195 - else 15.196 - outb(cached_21,0x21); 15.197 - spin_unlock_irqrestore(&i8259A_lock, flags); 15.198 -} 15.199 - 15.200 -void enable_8259A_irq(unsigned int irq) 15.201 -{ 15.202 - unsigned int mask = ~(1 << irq); 15.203 - unsigned long flags; 15.204 - 15.205 - spin_lock_irqsave(&i8259A_lock, flags); 15.206 - cached_irq_mask &= mask; 15.207 - if (irq & 8) 15.208 - outb(cached_A1,0xA1); 15.209 - else 15.210 - outb(cached_21,0x21); 15.211 - spin_unlock_irqrestore(&i8259A_lock, flags); 15.212 -} 15.213 - 15.214 -int i8259A_irq_pending(unsigned int irq) 15.215 -{ 15.216 - unsigned int mask = 1<<irq; 15.217 - unsigned long flags; 15.218 - int ret; 15.219 - 15.220 - spin_lock_irqsave(&i8259A_lock, flags); 15.221 - if (irq < 8) 15.222 - ret = inb(0x20) & mask; 15.223 - else 15.224 - ret = inb(0xA0) & (mask >> 8); 15.225 - spin_unlock_irqrestore(&i8259A_lock, flags); 15.226 - 15.227 - return ret; 15.228 -} 15.229 - 15.230 -void make_8259A_irq(unsigned int irq) 15.231 -{ 15.232 - disable_irq_nosync(irq); 15.233 - io_apic_irqs &= ~(1<<irq); 15.234 - irq_desc[irq].handler = &i8259A_irq_type; 15.235 - enable_irq(irq); 15.236 -} 15.237 - 15.238 -/* 15.239 - * This function assumes to be called rarely. Switching between 15.240 - * 8259A registers is slow. 15.241 - * This has to be protected by the irq controller spinlock 15.242 - * before being called. 15.243 - */ 15.244 -static inline int i8259A_irq_real(unsigned int irq) 15.245 -{ 15.246 - int value; 15.247 - int irqmask = 1<<irq; 15.248 - 15.249 - if (irq < 8) { 15.250 - outb(0x0B,0x20); /* ISR register */ 15.251 - value = inb(0x20) & irqmask; 15.252 - outb(0x0A,0x20); /* back to the IRR register */ 15.253 - return value; 15.254 - } 15.255 - outb(0x0B,0xA0); /* ISR register */ 15.256 - value = inb(0xA0) & (irqmask >> 8); 15.257 - outb(0x0A,0xA0); /* back to the IRR register */ 15.258 - return value; 15.259 -} 15.260 - 15.261 -/* 15.262 - * Careful! The 8259A is a fragile beast, it pretty 15.263 - * much _has_ to be done exactly like this (mask it 15.264 - * first, _then_ send the EOI, and the order of EOI 15.265 - * to the two 8259s is important! 15.266 - */ 15.267 -void mask_and_ack_8259A(unsigned int irq) 15.268 -{ 15.269 - unsigned int irqmask = 1 << irq; 15.270 - unsigned long flags; 15.271 - 15.272 - spin_lock_irqsave(&i8259A_lock, flags); 15.273 - /* 15.274 - * Lightweight spurious IRQ detection. We do not want 15.275 - * to overdo spurious IRQ handling - it's usually a sign 15.276 - * of hardware problems, so we only do the checks we can 15.277 - * do without slowing down good hardware unnecesserily. 15.278 - * 15.279 - * Note that IRQ7 and IRQ15 (the two spurious IRQs 15.280 - * usually resulting from the 8259A-1|2 PICs) occur 15.281 - * even if the IRQ is masked in the 8259A. Thus we 15.282 - * can check spurious 8259A IRQs without doing the 15.283 - * quite slow i8259A_irq_real() call for every IRQ. 15.284 - * This does not cover 100% of spurious interrupts, 15.285 - * but should be enough to warn the user that there 15.286 - * is something bad going on ... 15.287 - */ 15.288 - if (cached_irq_mask & irqmask) 15.289 - goto spurious_8259A_irq; 15.290 - cached_irq_mask |= irqmask; 15.291 - 15.292 - handle_real_irq: 15.293 - if (irq & 8) { 15.294 - inb(0xA1); /* DUMMY - (do we need this?) */ 15.295 - outb(cached_A1,0xA1); 15.296 - outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */ 15.297 - outb(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */ 15.298 - } else { 15.299 - inb(0x21); /* DUMMY - (do we need this?) */ 15.300 - outb(cached_21,0x21); 15.301 - outb(0x60+irq,0x20); /* 'Specific EOI' to master */ 15.302 - } 15.303 - spin_unlock_irqrestore(&i8259A_lock, flags); 15.304 - return; 15.305 - 15.306 - spurious_8259A_irq: 15.307 - /* 15.308 - * this is the slow path - should happen rarely. 15.309 - */ 15.310 - if (i8259A_irq_real(irq)) 15.311 - /* 15.312 - * oops, the IRQ _is_ in service according to the 15.313 - * 8259A - not spurious, go handle it. 15.314 - */ 15.315 - goto handle_real_irq; 15.316 - 15.317 - { 15.318 - static int spurious_irq_mask; 15.319 - /* 15.320 - * At this point we can be sure the IRQ is spurious, 15.321 - * lets ACK and report it. [once per IRQ] 15.322 - */ 15.323 - if (!(spurious_irq_mask & irqmask)) { 15.324 - printk("spurious 8259A interrupt: IRQ%d.\n", irq); 15.325 - spurious_irq_mask |= irqmask; 15.326 - } 15.327 - atomic_inc(&irq_err_count); 15.328 - /* 15.329 - * Theoretically we do not have to handle this IRQ, 15.330 - * but in Linux this does not cause problems and is 15.331 - * simpler for us. 15.332 - */ 15.333 - goto handle_real_irq; 15.334 - } 15.335 -} 15.336 - 15.337 -void __init init_8259A(int auto_eoi) 15.338 -{ 15.339 - unsigned long flags; 15.340 - 15.341 - spin_lock_irqsave(&i8259A_lock, flags); 15.342 - 15.343 - outb(0xff, 0x21); /* mask all of 8259A-1 */ 15.344 - outb(0xff, 0xA1); /* mask all of 8259A-2 */ 15.345 - 15.346 - /* 15.347 - * outb_p - this has to work on a wide range of PC hardware. 15.348 - */ 15.349 - outb_p(0x11, 0x20); /* ICW1: select 8259A-1 init */ 15.350 - outb_p(0x30 + 0, 0x21); /* ICW2: 8259A-1 IR0-7 mapped to 0x30-0x37 */ 15.351 - outb_p(0x04, 0x21); /* 8259A-1 (the master) has a slave on IR2 */ 15.352 - if (auto_eoi) 15.353 - outb_p(0x03, 0x21); /* master does Auto EOI */ 15.354 - else 15.355 - outb_p(0x01, 0x21); /* master expects normal EOI */ 15.356 - 15.357 - outb_p(0x11, 0xA0); /* ICW1: select 8259A-2 init */ 15.358 - outb_p(0x30 + 8, 0xA1); /* ICW2: 8259A-2 IR0-7 mapped to 0x38-0x3f */ 15.359 - outb_p(0x02, 0xA1); /* 8259A-2 is a slave on master's IR2 */ 15.360 - outb_p(0x01, 0xA1); /* (slave's support for AEOI in flat mode 15.361 - is to be investigated) */ 15.362 - 15.363 - if (auto_eoi) 15.364 - /* 15.365 - * in AEOI mode we just have to mask the interrupt 15.366 - * when acking. 15.367 - */ 15.368 - i8259A_irq_type.ack = disable_8259A_irq; 15.369 - else 15.370 - i8259A_irq_type.ack = mask_and_ack_8259A; 15.371 - 15.372 - udelay(100); /* wait for 8259A to initialize */ 15.373 - 15.374 - outb(cached_21, 0x21); /* restore master IRQ mask */ 15.375 - outb(cached_A1, 0xA1); /* restore slave IRQ mask */ 15.376 - 15.377 - spin_unlock_irqrestore(&i8259A_lock, flags); 15.378 -} 15.379 - 15.380 - 15.381 -/* 15.382 - * IRQ2 is cascade interrupt to second interrupt controller 15.383 - */ 15.384 - 15.385 -static struct irqaction irq2 = { no_action, 0, 0, "cascade", NULL, NULL}; 15.386 - 15.387 -void __init init_ISA_irqs (void) 15.388 -{ 15.389 - int i; 15.390 - 15.391 -#ifdef CONFIG_X86_LOCAL_APIC 15.392 - init_bsp_APIC(); 15.393 -#endif 15.394 - init_8259A(0); 15.395 - 15.396 - for (i = 0; i < NR_IRQS; i++) { 15.397 - irq_desc[i].status = IRQ_DISABLED; 15.398 - irq_desc[i].action = 0; 15.399 - irq_desc[i].depth = 1; 15.400 - 15.401 - if (i < 16) { 15.402 - /* 15.403 - * 16 old-style INTA-cycle interrupts: 15.404 - */ 15.405 - irq_desc[i].handler = &i8259A_irq_type; 15.406 - } else { 15.407 - /* 15.408 - * 'high' PCI IRQs filled in on demand 15.409 - */ 15.410 - irq_desc[i].handler = &no_irq_type; 15.411 - } 15.412 - } 15.413 -} 15.414 - 15.415 -void __init init_IRQ(void) 15.416 -{ 15.417 - int i; 15.418 - 15.419 - init_ISA_irqs(); 15.420 - 15.421 - /* 15.422 - * Cover the whole vector space, no vector can escape 15.423 - * us. (some of these will be overridden and become 15.424 - * 'special' SMP interrupts) 15.425 - */ 15.426 - for (i = 0; i < NR_IRQS; i++) { 15.427 - int vector = FIRST_EXTERNAL_VECTOR + i; 15.428 - if (vector != HYPERVISOR_CALL_VECTOR) 15.429 - set_intr_gate(vector, interrupt[i]); 15.430 - } 15.431 - 15.432 -#ifdef CONFIG_SMP 15.433 - /* 15.434 - * IRQ0 must be given a fixed assignment and initialized, 15.435 - * because it's used before the IO-APIC is set up. 15.436 - */ 15.437 - set_intr_gate(FIRST_DEVICE_VECTOR, interrupt[0]); 15.438 - 15.439 - /* 15.440 - * The reschedule interrupt is a CPU-to-CPU reschedule-helper 15.441 - * IPI, driven by wakeup. 15.442 - */ 15.443 - set_intr_gate(EVENT_CHECK_VECTOR, event_check_interrupt); 15.444 - 15.445 - /* IPI for invalidation */ 15.446 - set_intr_gate(INVALIDATE_TLB_VECTOR, invalidate_interrupt); 15.447 - 15.448 - /* IPI for generic function call */ 15.449 - set_intr_gate(CALL_FUNCTION_VECTOR, call_function_interrupt); 15.450 -#endif 15.451 - 15.452 -#ifdef CONFIG_X86_LOCAL_APIC 15.453 - /* self generated IPI for local APIC timer */ 15.454 - set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt); 15.455 - 15.456 - /* IPI vectors for APIC spurious and error interrupts */ 15.457 - set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt); 15.458 - set_intr_gate(ERROR_APIC_VECTOR, error_interrupt); 15.459 -#endif 15.460 - 15.461 - /* 15.462 - * Set the clock to HZ Hz, we already have a valid 15.463 - * vector now: 15.464 - */ 15.465 -#define CLOCK_TICK_RATE 1193180 /* crystal freq (Hz) */ 15.466 -#define LATCH (((CLOCK_TICK_RATE)+(HZ/2))/HZ) 15.467 - outb_p(0x34,0x43); /* binary, mode 2, LSB/MSB, ch 0 */ 15.468 - outb_p(LATCH & 0xff , 0x40); /* LSB */ 15.469 - outb(LATCH >> 8 , 0x40); /* MSB */ 15.470 - 15.471 - setup_irq(2, &irq2); 15.472 -} 15.473 - 15.474 -/* 15.475 - * we only need the timer interrupt for callibrating the tsc<->time<->bus cycle 15.476 - * mappings. After this all timeing related functions should be run of the 15.477 - * APIC timers. This function allows us to disable the 15.478 - */ 15.479 -void __init disable_pit(void) 15.480 -{ 15.481 - printk("Disable PIT. Not needed anymore\n"); 15.482 - /* This is not the most elegant way, but hey. */ 15.483 - disable_irq(0); 15.484 -}
16.1 --- a/xen-2.4.16/arch/i386/idle0_task.c Mon Feb 24 16:55:07 2003 +0000 16.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 16.3 @@ -1,20 +0,0 @@ 16.4 -#include <xeno/config.h> 16.5 -#include <xeno/sched.h> 16.6 -#include <asm/desc.h> 16.7 - 16.8 -/* 16.9 - * Initial task structure. XXX KAF: To get this 8192-byte aligned without 16.10 - * linker tricks I copy it into aligned BSS area at boot time. 16.11 - * Actual name idle0_task_union now declared in boot.S. 16.12 - */ 16.13 -struct task_struct first_task_struct = IDLE0_TASK(idle0_task_union.task); 16.14 - 16.15 -/* 16.16 - * per-CPU TSS segments. Threads are completely 'soft' on Linux, 16.17 - * no more per-task TSS's. The TSS size is kept cacheline-aligned 16.18 - * so they are allowed to end up in the .data.cacheline_aligned 16.19 - * section. Since TSS's are completely CPU-local, we want them 16.20 - * on exact cacheline boundaries, to eliminate cacheline ping-pong. 16.21 - */ 16.22 -struct tss_struct init_tss[NR_CPUS] __cacheline_aligned = { [0 ... NR_CPUS-1] = INIT_TSS }; 16.23 -
17.1 --- a/xen-2.4.16/arch/i386/io_apic.c Mon Feb 24 16:55:07 2003 +0000 17.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 17.3 @@ -1,1683 +0,0 @@ 17.4 -/* 17.5 - * Intel IO-APIC support for multi-Pentium hosts. 17.6 - * 17.7 - * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo 17.8 - * 17.9 - * Many thanks to Stig Venaas for trying out countless experimental 17.10 - * patches and reporting/debugging problems patiently! 17.11 - * 17.12 - * (c) 1999, Multiple IO-APIC support, developed by 17.13 - * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and 17.14 - * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>, 17.15 - * further tested and cleaned up by Zach Brown <zab@redhat.com> 17.16 - * and Ingo Molnar <mingo@redhat.com> 17.17 - * 17.18 - * Fixes 17.19 - * Maciej W. Rozycki : Bits for genuine 82489DX APICs; 17.20 - * thanks to Eric Gilmore 17.21 - * and Rolf G. Tews 17.22 - * for testing these extensively 17.23 - */ 17.24 - 17.25 -#include <xeno/config.h> 17.26 -#include <xeno/init.h> 17.27 -#include <xeno/interrupt.h> 17.28 -#include <xeno/irq.h> 17.29 -#include <xeno/delay.h> 17.30 -#include <xeno/sched.h> 17.31 -#include <xeno/config.h> 17.32 -#include <asm/mc146818rtc.h> 17.33 -#include <asm/io.h> 17.34 -#include <asm/smp.h> 17.35 -#include <asm/desc.h> 17.36 -#include <asm/smpboot.h> 17.37 - 17.38 - 17.39 -static unsigned int nmi_watchdog; /* XXXX XEN */ 17.40 - 17.41 -#undef APIC_LOCKUP_DEBUG 17.42 - 17.43 -#define APIC_LOCKUP_DEBUG 17.44 - 17.45 -static spinlock_t ioapic_lock = SPIN_LOCK_UNLOCKED; 17.46 - 17.47 -unsigned int int_dest_addr_mode = APIC_DEST_LOGICAL; 17.48 -unsigned char int_delivery_mode = dest_LowestPrio; 17.49 - 17.50 - 17.51 -/* 17.52 - * # of IRQ routing registers 17.53 - */ 17.54 -int nr_ioapic_registers[MAX_IO_APICS]; 17.55 - 17.56 -/* 17.57 - * Rough estimation of how many shared IRQs there are, can 17.58 - * be changed anytime. 17.59 - */ 17.60 -#define MAX_PLUS_SHARED_IRQS NR_IRQS 17.61 -#define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS) 17.62 - 17.63 -/* 17.64 - * This is performance-critical, we want to do it O(1) 17.65 - * 17.66 - * the indexing order of this array favors 1:1 mappings 17.67 - * between pins and IRQs. 17.68 - */ 17.69 - 17.70 -static struct irq_pin_list { 17.71 - int apic, pin, next; 17.72 -} irq_2_pin[PIN_MAP_SIZE]; 17.73 - 17.74 -/* 17.75 - * The common case is 1:1 IRQ<->pin mappings. Sometimes there are 17.76 - * shared ISA-space IRQs, so we have to support them. We are super 17.77 - * fast in the common case, and fast for shared ISA-space IRQs. 17.78 - */ 17.79 -static void __init add_pin_to_irq(unsigned int irq, int apic, int pin) 17.80 -{ 17.81 - static int first_free_entry = NR_IRQS; 17.82 - struct irq_pin_list *entry = irq_2_pin + irq; 17.83 - 17.84 - while (entry->next) 17.85 - entry = irq_2_pin + entry->next; 17.86 - 17.87 - if (entry->pin != -1) { 17.88 - entry->next = first_free_entry; 17.89 - entry = irq_2_pin + entry->next; 17.90 - if (++first_free_entry >= PIN_MAP_SIZE) 17.91 - panic("io_apic.c: whoops"); 17.92 - } 17.93 - entry->apic = apic; 17.94 - entry->pin = pin; 17.95 -} 17.96 - 17.97 -/* 17.98 - * Reroute an IRQ to a different pin. 17.99 - */ 17.100 -static void __init replace_pin_at_irq(unsigned int irq, 17.101 - int oldapic, int oldpin, 17.102 - int newapic, int newpin) 17.103 -{ 17.104 - struct irq_pin_list *entry = irq_2_pin + irq; 17.105 - 17.106 - while (1) { 17.107 - if (entry->apic == oldapic && entry->pin == oldpin) { 17.108 - entry->apic = newapic; 17.109 - entry->pin = newpin; 17.110 - } 17.111 - if (!entry->next) 17.112 - break; 17.113 - entry = irq_2_pin + entry->next; 17.114 - } 17.115 -} 17.116 - 17.117 -#define __DO_ACTION(R, ACTION, FINAL) \ 17.118 - \ 17.119 -{ \ 17.120 - int pin; \ 17.121 - struct irq_pin_list *entry = irq_2_pin + irq; \ 17.122 - \ 17.123 - for (;;) { \ 17.124 - unsigned int reg; \ 17.125 - pin = entry->pin; \ 17.126 - if (pin == -1) \ 17.127 - break; \ 17.128 - reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \ 17.129 - reg ACTION; \ 17.130 - io_apic_modify(entry->apic, reg); \ 17.131 - if (!entry->next) \ 17.132 - break; \ 17.133 - entry = irq_2_pin + entry->next; \ 17.134 - } \ 17.135 - FINAL; \ 17.136 -} 17.137 - 17.138 -#define DO_ACTION(name,R,ACTION, FINAL) \ 17.139 - \ 17.140 - static void name##_IO_APIC_irq (unsigned int irq) \ 17.141 - __DO_ACTION(R, ACTION, FINAL) 17.142 - 17.143 -DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) ) 17.144 - /* mask = 1 */ 17.145 -DO_ACTION( __unmask, 0, &= 0xfffeffff, ) 17.146 - /* mask = 0 */ 17.147 -DO_ACTION( __mask_and_edge, 0, = (reg & 0xffff7fff) | 0x00010000, ) 17.148 - /* mask = 1, trigger = 0 */ 17.149 -DO_ACTION( __unmask_and_level, 0, = (reg & 0xfffeffff) | 0x00008000, ) 17.150 - /* mask = 0, trigger = 1 */ 17.151 - 17.152 -static void mask_IO_APIC_irq (unsigned int irq) 17.153 -{ 17.154 - unsigned long flags; 17.155 - 17.156 - spin_lock_irqsave(&ioapic_lock, flags); 17.157 - __mask_IO_APIC_irq(irq); 17.158 - spin_unlock_irqrestore(&ioapic_lock, flags); 17.159 -} 17.160 - 17.161 -static void unmask_IO_APIC_irq (unsigned int irq) 17.162 -{ 17.163 - unsigned long flags; 17.164 - 17.165 - spin_lock_irqsave(&ioapic_lock, flags); 17.166 - __unmask_IO_APIC_irq(irq); 17.167 - spin_unlock_irqrestore(&ioapic_lock, flags); 17.168 -} 17.169 - 17.170 -void clear_IO_APIC_pin(unsigned int apic, unsigned int pin) 17.171 -{ 17.172 - struct IO_APIC_route_entry entry; 17.173 - unsigned long flags; 17.174 - 17.175 - /* 17.176 - * Disable it in the IO-APIC irq-routing table: 17.177 - */ 17.178 - memset(&entry, 0, sizeof(entry)); 17.179 - entry.mask = 1; 17.180 - spin_lock_irqsave(&ioapic_lock, flags); 17.181 - io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0)); 17.182 - io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1)); 17.183 - spin_unlock_irqrestore(&ioapic_lock, flags); 17.184 -} 17.185 - 17.186 -static void clear_IO_APIC (void) 17.187 -{ 17.188 - int apic, pin; 17.189 - 17.190 - for (apic = 0; apic < nr_ioapics; apic++) 17.191 - for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) 17.192 - clear_IO_APIC_pin(apic, pin); 17.193 -} 17.194 - 17.195 -/* 17.196 - * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to 17.197 - * specific CPU-side IRQs. 17.198 - */ 17.199 - 17.200 -#define MAX_PIRQS 8 17.201 -int pirq_entries [MAX_PIRQS]; 17.202 -int pirqs_enabled; 17.203 - 17.204 -int skip_ioapic_setup; 17.205 -#if 0 17.206 - 17.207 -static int __init noioapic_setup(char *str) 17.208 -{ 17.209 - skip_ioapic_setup = 1; 17.210 - return 1; 17.211 -} 17.212 - 17.213 -__setup("noapic", noioapic_setup); 17.214 - 17.215 -static int __init ioapic_setup(char *str) 17.216 -{ 17.217 - skip_ioapic_setup = 0; 17.218 - return 1; 17.219 -} 17.220 - 17.221 -__setup("apic", ioapic_setup); 17.222 - 17.223 - 17.224 - 17.225 -static int __init ioapic_pirq_setup(char *str) 17.226 -{ 17.227 - int i, max; 17.228 - int ints[MAX_PIRQS+1]; 17.229 - 17.230 - get_options(str, ARRAY_SIZE(ints), ints); 17.231 - 17.232 - for (i = 0; i < MAX_PIRQS; i++) 17.233 - pirq_entries[i] = -1; 17.234 - 17.235 - pirqs_enabled = 1; 17.236 - printk(KERN_INFO "PIRQ redirection, working around broken MP-BIOS.\n"); 17.237 - max = MAX_PIRQS; 17.238 - if (ints[0] < MAX_PIRQS) 17.239 - max = ints[0]; 17.240 - 17.241 - for (i = 0; i < max; i++) { 17.242 - printk(KERN_DEBUG "... PIRQ%d -> IRQ %d\n", i, ints[i+1]); 17.243 - /* 17.244 - * PIRQs are mapped upside down, usually. 17.245 - */ 17.246 - pirq_entries[MAX_PIRQS-i-1] = ints[i+1]; 17.247 - } 17.248 - return 1; 17.249 -} 17.250 - 17.251 -__setup("pirq=", ioapic_pirq_setup); 17.252 - 17.253 -#endif 17.254 - 17.255 -/* 17.256 - * Find the IRQ entry number of a certain pin. 17.257 - */ 17.258 -static int __init find_irq_entry(int apic, int pin, int type) 17.259 -{ 17.260 - int i; 17.261 - 17.262 - for (i = 0; i < mp_irq_entries; i++) 17.263 - if (mp_irqs[i].mpc_irqtype == type && 17.264 - (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid || 17.265 - mp_irqs[i].mpc_dstapic == MP_APIC_ALL) && 17.266 - mp_irqs[i].mpc_dstirq == pin) 17.267 - return i; 17.268 - 17.269 - return -1; 17.270 -} 17.271 - 17.272 -/* 17.273 - * Find the pin to which IRQ[irq] (ISA) is connected 17.274 - */ 17.275 -static int __init find_isa_irq_pin(int irq, int type) 17.276 -{ 17.277 - int i; 17.278 - 17.279 - for (i = 0; i < mp_irq_entries; i++) { 17.280 - int lbus = mp_irqs[i].mpc_srcbus; 17.281 - 17.282 - if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA || 17.283 - mp_bus_id_to_type[lbus] == MP_BUS_EISA || 17.284 - mp_bus_id_to_type[lbus] == MP_BUS_MCA) && 17.285 - (mp_irqs[i].mpc_irqtype == type) && 17.286 - (mp_irqs[i].mpc_srcbusirq == irq)) 17.287 - 17.288 - return mp_irqs[i].mpc_dstirq; 17.289 - } 17.290 - return -1; 17.291 -} 17.292 - 17.293 -/* 17.294 - * Find a specific PCI IRQ entry. 17.295 - * Not an __init, possibly needed by modules 17.296 - */ 17.297 -static int pin_2_irq(int idx, int apic, int pin); 17.298 - 17.299 -int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin) 17.300 -{ 17.301 - int apic, i, best_guess = -1; 17.302 - 17.303 - Dprintk("querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n", 17.304 - bus, slot, pin); 17.305 - if ((mp_bus_id_to_pci_bus==NULL) || (mp_bus_id_to_pci_bus[bus] == -1)) { 17.306 - printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus); 17.307 - return -1; 17.308 - } 17.309 - for (i = 0; i < mp_irq_entries; i++) { 17.310 - int lbus = mp_irqs[i].mpc_srcbus; 17.311 - 17.312 - for (apic = 0; apic < nr_ioapics; apic++) 17.313 - if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic || 17.314 - mp_irqs[i].mpc_dstapic == MP_APIC_ALL) 17.315 - break; 17.316 - 17.317 - if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) && 17.318 - !mp_irqs[i].mpc_irqtype && 17.319 - (bus == lbus) && 17.320 - (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) { 17.321 - int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq); 17.322 - 17.323 - if (!(apic || IO_APIC_IRQ(irq))) 17.324 - continue; 17.325 - 17.326 - if (pin == (mp_irqs[i].mpc_srcbusirq & 3)) 17.327 - return irq; 17.328 - /* 17.329 - * Use the first all-but-pin matching entry as a 17.330 - * best-guess fuzzy result for broken mptables. 17.331 - */ 17.332 - if (best_guess < 0) 17.333 - best_guess = irq; 17.334 - } 17.335 - } 17.336 - return best_guess; 17.337 -} 17.338 - 17.339 -/* 17.340 - * EISA Edge/Level control register, ELCR 17.341 - */ 17.342 -static int __init EISA_ELCR(unsigned int irq) 17.343 -{ 17.344 - if (irq < 16) { 17.345 - unsigned int port = 0x4d0 + (irq >> 3); 17.346 - return (inb(port) >> (irq & 7)) & 1; 17.347 - } 17.348 - printk(KERN_INFO "Broken MPtable reports ISA irq %d\n", irq); 17.349 - return 0; 17.350 -} 17.351 - 17.352 -/* EISA interrupts are always polarity zero and can be edge or level 17.353 - * trigger depending on the ELCR value. If an interrupt is listed as 17.354 - * EISA conforming in the MP table, that means its trigger type must 17.355 - * be read in from the ELCR */ 17.356 - 17.357 -#define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq)) 17.358 -#define default_EISA_polarity(idx) (0) 17.359 - 17.360 -/* ISA interrupts are always polarity zero edge triggered, 17.361 - * when listed as conforming in the MP table. */ 17.362 - 17.363 -#define default_ISA_trigger(idx) (0) 17.364 -#define default_ISA_polarity(idx) (0) 17.365 - 17.366 -/* PCI interrupts are always polarity one level triggered, 17.367 - * when listed as conforming in the MP table. */ 17.368 - 17.369 -#define default_PCI_trigger(idx) (1) 17.370 -#define default_PCI_polarity(idx) (1) 17.371 - 17.372 -/* MCA interrupts are always polarity zero level triggered, 17.373 - * when listed as conforming in the MP table. */ 17.374 - 17.375 -#define default_MCA_trigger(idx) (1) 17.376 -#define default_MCA_polarity(idx) (0) 17.377 - 17.378 -static int __init MPBIOS_polarity(int idx) 17.379 -{ 17.380 - int bus = mp_irqs[idx].mpc_srcbus; 17.381 - int polarity; 17.382 - 17.383 - /* 17.384 - * Determine IRQ line polarity (high active or low active): 17.385 - */ 17.386 - switch (mp_irqs[idx].mpc_irqflag & 3) 17.387 - { 17.388 - case 0: /* conforms, ie. bus-type dependent polarity */ 17.389 - { 17.390 - switch (mp_bus_id_to_type[bus]) 17.391 - { 17.392 - case MP_BUS_ISA: /* ISA pin */ 17.393 - { 17.394 - polarity = default_ISA_polarity(idx); 17.395 - break; 17.396 - } 17.397 - case MP_BUS_EISA: /* EISA pin */ 17.398 - { 17.399 - polarity = default_EISA_polarity(idx); 17.400 - break; 17.401 - } 17.402 - case MP_BUS_PCI: /* PCI pin */ 17.403 - { 17.404 - polarity = default_PCI_polarity(idx); 17.405 - break; 17.406 - } 17.407 - case MP_BUS_MCA: /* MCA pin */ 17.408 - { 17.409 - polarity = default_MCA_polarity(idx); 17.410 - break; 17.411 - } 17.412 - default: 17.413 - { 17.414 - printk(KERN_WARNING "broken BIOS!!\n"); 17.415 - polarity = 1; 17.416 - break; 17.417 - } 17.418 - } 17.419 - break; 17.420 - } 17.421 - case 1: /* high active */ 17.422 - { 17.423 - polarity = 0; 17.424 - break; 17.425 - } 17.426 - case 2: /* reserved */ 17.427 - { 17.428 - printk(KERN_WARNING "broken BIOS!!\n"); 17.429 - polarity = 1; 17.430 - break; 17.431 - } 17.432 - case 3: /* low active */ 17.433 - { 17.434 - polarity = 1; 17.435 - break; 17.436 - } 17.437 - default: /* invalid */ 17.438 - { 17.439 - printk(KERN_WARNING "broken BIOS!!\n"); 17.440 - polarity = 1; 17.441 - break; 17.442 - } 17.443 - } 17.444 - return polarity; 17.445 -} 17.446 - 17.447 -static int __init MPBIOS_trigger(int idx) 17.448 -{ 17.449 - int bus = mp_irqs[idx].mpc_srcbus; 17.450 - int trigger; 17.451 - 17.452 - /* 17.453 - * Determine IRQ trigger mode (edge or level sensitive): 17.454 - */ 17.455 - switch ((mp_irqs[idx].mpc_irqflag>>2) & 3) 17.456 - { 17.457 - case 0: /* conforms, ie. bus-type dependent */ 17.458 - { 17.459 - switch (mp_bus_id_to_type[bus]) 17.460 - { 17.461 - case MP_BUS_ISA: /* ISA pin */ 17.462 - { 17.463 - trigger = default_ISA_trigger(idx); 17.464 - break; 17.465 - } 17.466 - case MP_BUS_EISA: /* EISA pin */ 17.467 - { 17.468 - trigger = default_EISA_trigger(idx); 17.469 - break; 17.470 - } 17.471 - case MP_BUS_PCI: /* PCI pin */ 17.472 - { 17.473 - trigger = default_PCI_trigger(idx); 17.474 - break; 17.475 - } 17.476 - case MP_BUS_MCA: /* MCA pin */ 17.477 - { 17.478 - trigger = default_MCA_trigger(idx); 17.479 - break; 17.480 - } 17.481 - default: 17.482 - { 17.483 - printk(KERN_WARNING "broken BIOS!!\n"); 17.484 - trigger = 1; 17.485 - break; 17.486 - } 17.487 - } 17.488 - break; 17.489 - } 17.490 - case 1: /* edge */ 17.491 - { 17.492 - trigger = 0; 17.493 - break; 17.494 - } 17.495 - case 2: /* reserved */ 17.496 - { 17.497 - printk(KERN_WARNING "broken BIOS!!\n"); 17.498 - trigger = 1; 17.499 - break; 17.500 - } 17.501 - case 3: /* level */ 17.502 - { 17.503 - trigger = 1; 17.504 - break; 17.505 - } 17.506 - default: /* invalid */ 17.507 - { 17.508 - printk(KERN_WARNING "broken BIOS!!\n"); 17.509 - trigger = 0; 17.510 - break; 17.511 - } 17.512 - } 17.513 - return trigger; 17.514 -} 17.515 - 17.516 -static inline int irq_polarity(int idx) 17.517 -{ 17.518 - return MPBIOS_polarity(idx); 17.519 -} 17.520 - 17.521 -static inline int irq_trigger(int idx) 17.522 -{ 17.523 - return MPBIOS_trigger(idx); 17.524 -} 17.525 - 17.526 -static int pin_2_irq(int idx, int apic, int pin) 17.527 -{ 17.528 - int irq, i; 17.529 - int bus = mp_irqs[idx].mpc_srcbus; 17.530 - 17.531 - /* 17.532 - * Debugging check, we are in big trouble if this message pops up! 17.533 - */ 17.534 - if (mp_irqs[idx].mpc_dstirq != pin) 17.535 - printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n"); 17.536 - 17.537 - switch (mp_bus_id_to_type[bus]) 17.538 - { 17.539 - case MP_BUS_ISA: /* ISA pin */ 17.540 - case MP_BUS_EISA: 17.541 - case MP_BUS_MCA: 17.542 - { 17.543 - irq = mp_irqs[idx].mpc_srcbusirq; 17.544 - break; 17.545 - } 17.546 - case MP_BUS_PCI: /* PCI pin */ 17.547 - { 17.548 - /* 17.549 - * PCI IRQs are mapped in order 17.550 - */ 17.551 - i = irq = 0; 17.552 - while (i < apic) 17.553 - irq += nr_ioapic_registers[i++]; 17.554 - irq += pin; 17.555 - break; 17.556 - } 17.557 - default: 17.558 - { 17.559 - printk(KERN_ERR "unknown bus type %d.\n",bus); 17.560 - irq = 0; 17.561 - break; 17.562 - } 17.563 - } 17.564 - 17.565 - /* 17.566 - * PCI IRQ command line redirection. Yes, limits are hardcoded. 17.567 - */ 17.568 - if ((pin >= 16) && (pin <= 23)) { 17.569 - if (pirq_entries[pin-16] != -1) { 17.570 - if (!pirq_entries[pin-16]) { 17.571 - printk(KERN_DEBUG "disabling PIRQ%d\n", pin-16); 17.572 - } else { 17.573 - irq = pirq_entries[pin-16]; 17.574 - printk(KERN_DEBUG "using PIRQ%d -> IRQ %d\n", 17.575 - pin-16, irq); 17.576 - } 17.577 - } 17.578 - } 17.579 - return irq; 17.580 -} 17.581 - 17.582 -static inline int IO_APIC_irq_trigger(int irq) 17.583 -{ 17.584 - int apic, idx, pin; 17.585 - 17.586 - for (apic = 0; apic < nr_ioapics; apic++) { 17.587 - for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { 17.588 - idx = find_irq_entry(apic,pin,mp_INT); 17.589 - if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin))) 17.590 - return irq_trigger(idx); 17.591 - } 17.592 - } 17.593 - /* 17.594 - * nonexistent IRQs are edge default 17.595 - */ 17.596 - return 0; 17.597 -} 17.598 - 17.599 -int irq_vector[NR_IRQS] = { FIRST_DEVICE_VECTOR , 0 }; 17.600 - 17.601 -static int __init assign_irq_vector(int irq) 17.602 -{ 17.603 - static int current_vector = FIRST_DEVICE_VECTOR, offset = 0; 17.604 - if (IO_APIC_VECTOR(irq) > 0) 17.605 - return IO_APIC_VECTOR(irq); 17.606 -next: 17.607 - current_vector += 8; 17.608 - 17.609 - /* XXX Skip the guestOS -> Xen syscall vector! XXX */ 17.610 - if (current_vector == HYPERVISOR_CALL_VECTOR) goto next; 17.611 - /* XXX Skip the Linux/BSD fast-trap vector! XXX */ 17.612 - if (current_vector == 0x80) goto next; 17.613 - 17.614 -#if 0 17.615 - if (current_vector == SYSCALL_VECTOR) 17.616 - goto next; 17.617 -#endif 17.618 - 17.619 - if (current_vector > FIRST_SYSTEM_VECTOR) { 17.620 - offset++; 17.621 - current_vector = FIRST_DEVICE_VECTOR + offset; 17.622 - } 17.623 - 17.624 - if (current_vector == FIRST_SYSTEM_VECTOR) 17.625 - panic("ran out of interrupt sources!"); 17.626 - 17.627 - IO_APIC_VECTOR(irq) = current_vector; 17.628 - return current_vector; 17.629 -} 17.630 - 17.631 -extern void (*interrupt[NR_IRQS])(void); 17.632 -static struct hw_interrupt_type ioapic_level_irq_type; 17.633 -static struct hw_interrupt_type ioapic_edge_irq_type; 17.634 - 17.635 -void __init setup_IO_APIC_irqs(void) 17.636 -{ 17.637 - struct IO_APIC_route_entry entry; 17.638 - int apic, pin, idx, irq, first_notcon = 1, vector; 17.639 - unsigned long flags; 17.640 - 17.641 - printk(KERN_DEBUG "init IO_APIC IRQs\n"); 17.642 - 17.643 - for (apic = 0; apic < nr_ioapics; apic++) { 17.644 - for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) { 17.645 - 17.646 - /* 17.647 - * add it to the IO-APIC irq-routing table: 17.648 - */ 17.649 - memset(&entry,0,sizeof(entry)); 17.650 - 17.651 - entry.delivery_mode = INT_DELIVERY_MODE; 17.652 - entry.dest_mode = (INT_DEST_ADDR_MODE != 0); 17.653 - entry.mask = 0; /* enable IRQ */ 17.654 - entry.dest.logical.logical_dest = target_cpus(); 17.655 - 17.656 - idx = find_irq_entry(apic,pin,mp_INT); 17.657 - if (idx == -1) { 17.658 - if (first_notcon) { 17.659 - printk(KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin); 17.660 - first_notcon = 0; 17.661 - } else 17.662 - printk(", %d-%d", mp_ioapics[apic].mpc_apicid, pin); 17.663 - continue; 17.664 - } 17.665 - 17.666 - entry.trigger = irq_trigger(idx); 17.667 - entry.polarity = irq_polarity(idx); 17.668 - 17.669 - if (irq_trigger(idx)) { 17.670 - entry.trigger = 1; 17.671 - entry.mask = 1; 17.672 - } 17.673 - 17.674 - irq = pin_2_irq(idx, apic, pin); 17.675 - /* 17.676 - * skip adding the timer int on secondary nodes, which causes 17.677 - * a small but painful rift in the time-space continuum 17.678 - */ 17.679 - if ((clustered_apic_mode == CLUSTERED_APIC_NUMAQ) 17.680 - && (apic != 0) && (irq == 0)) 17.681 - continue; 17.682 - else 17.683 - add_pin_to_irq(irq, apic, pin); 17.684 - 17.685 - if (!apic && !IO_APIC_IRQ(irq)) 17.686 - continue; 17.687 - 17.688 - if (IO_APIC_IRQ(irq)) { 17.689 - vector = assign_irq_vector(irq); 17.690 - entry.vector = vector; 17.691 - 17.692 - if (IO_APIC_irq_trigger(irq)) 17.693 - irq_desc[irq].handler = &ioapic_level_irq_type; 17.694 - else 17.695 - irq_desc[irq].handler = &ioapic_edge_irq_type; 17.696 - 17.697 - set_intr_gate(vector, interrupt[irq]); 17.698 - 17.699 - if (!apic && (irq < 16)) 17.700 - disable_8259A_irq(irq); 17.701 - } 17.702 - spin_lock_irqsave(&ioapic_lock, flags); 17.703 - io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1)); 17.704 - io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0)); 17.705 - spin_unlock_irqrestore(&ioapic_lock, flags); 17.706 - } 17.707 - } 17.708 - 17.709 - if (!first_notcon) 17.710 - printk(" not connected.\n"); 17.711 -} 17.712 - 17.713 -/* 17.714 - * Set up the 8259A-master output pin as broadcast to all 17.715 - * CPUs. 17.716 - */ 17.717 -void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector) 17.718 -{ 17.719 - struct IO_APIC_route_entry entry; 17.720 - unsigned long flags; 17.721 - 17.722 - memset(&entry,0,sizeof(entry)); 17.723 - 17.724 - disable_8259A_irq(0); 17.725 - 17.726 - /* mask LVT0 */ 17.727 - apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); 17.728 - 17.729 - /* 17.730 - * We use logical delivery to get the timer IRQ 17.731 - * to the first CPU. 17.732 - */ 17.733 - entry.dest_mode = (INT_DEST_ADDR_MODE != 0); 17.734 - entry.mask = 0; /* unmask IRQ now */ 17.735 - entry.dest.logical.logical_dest = target_cpus(); 17.736 - entry.delivery_mode = INT_DELIVERY_MODE; 17.737 - entry.polarity = 0; 17.738 - entry.trigger = 0; 17.739 - entry.vector = vector; 17.740 - 17.741 - /* 17.742 - * The timer IRQ doesn't have to know that behind the 17.743 - * scene we have a 8259A-master in AEOI mode ... 17.744 - */ 17.745 - irq_desc[0].handler = &ioapic_edge_irq_type; 17.746 - 17.747 - /* 17.748 - * Add it to the IO-APIC irq-routing table: 17.749 - */ 17.750 - spin_lock_irqsave(&ioapic_lock, flags); 17.751 - io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1)); 17.752 - io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0)); 17.753 - spin_unlock_irqrestore(&ioapic_lock, flags); 17.754 - 17.755 - enable_8259A_irq(0); 17.756 -} 17.757 - 17.758 -void __init UNEXPECTED_IO_APIC(void) 17.759 -{ 17.760 - printk(KERN_WARNING 17.761 - "An unexpected IO-APIC was found. If this kernel release is less than\n" 17.762 - "three months old please report this to linux-smp@vger.kernel.org\n"); 17.763 -} 17.764 - 17.765 -void __init print_IO_APIC(void) 17.766 -{ 17.767 - int apic, i; 17.768 - struct IO_APIC_reg_00 reg_00; 17.769 - struct IO_APIC_reg_01 reg_01; 17.770 - struct IO_APIC_reg_02 reg_02; 17.771 - unsigned long flags; 17.772 - 17.773 - printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries); 17.774 - for (i = 0; i < nr_ioapics; i++) 17.775 - printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n", 17.776 - mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]); 17.777 - 17.778 - /* 17.779 - * We are a bit conservative about what we expect. We have to 17.780 - * know about every hardware change ASAP. 17.781 - */ 17.782 - printk(KERN_INFO "testing the IO APIC.......................\n"); 17.783 - 17.784 - for (apic = 0; apic < nr_ioapics; apic++) { 17.785 - 17.786 - spin_lock_irqsave(&ioapic_lock, flags); 17.787 - *(int *)®_00 = io_apic_read(apic, 0); 17.788 - *(int *)®_01 = io_apic_read(apic, 1); 17.789 - if (reg_01.version >= 0x10) 17.790 - *(int *)®_02 = io_apic_read(apic, 2); 17.791 - spin_unlock_irqrestore(&ioapic_lock, flags); 17.792 - 17.793 - printk("\n"); 17.794 - printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid); 17.795 - printk(KERN_DEBUG ".... register #00: %08X\n", *(int *)®_00); 17.796 - printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.ID); 17.797 - if (reg_00.__reserved_1 || reg_00.__reserved_2) 17.798 - UNEXPECTED_IO_APIC(); 17.799 - 17.800 - printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01); 17.801 - printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.entries); 17.802 - if ( (reg_01.entries != 0x0f) && /* older (Neptune) boards */ 17.803 - (reg_01.entries != 0x17) && /* typical ISA+PCI boards */ 17.804 - (reg_01.entries != 0x1b) && /* Compaq Proliant boards */ 17.805 - (reg_01.entries != 0x1f) && /* dual Xeon boards */ 17.806 - (reg_01.entries != 0x22) && /* bigger Xeon boards */ 17.807 - (reg_01.entries != 0x2E) && 17.808 - (reg_01.entries != 0x3F) 17.809 - ) 17.810 - UNEXPECTED_IO_APIC(); 17.811 - 17.812 - printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.PRQ); 17.813 - printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.version); 17.814 - if ( (reg_01.version != 0x01) && /* 82489DX IO-APICs */ 17.815 - (reg_01.version != 0x02) && /* VIA */ 17.816 - (reg_01.version != 0x10) && /* oldest IO-APICs */ 17.817 - (reg_01.version != 0x11) && /* Pentium/Pro IO-APICs */ 17.818 - (reg_01.version != 0x13) && /* Xeon IO-APICs */ 17.819 - (reg_01.version != 0x20) /* Intel P64H (82806 AA) */ 17.820 - ) 17.821 - UNEXPECTED_IO_APIC(); 17.822 - if (reg_01.__reserved_1 || reg_01.__reserved_2) 17.823 - UNEXPECTED_IO_APIC(); 17.824 - 17.825 - if (reg_01.version >= 0x10) { 17.826 - printk(KERN_DEBUG ".... register #02: %08X\n", *(int *)®_02); 17.827 - printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.arbitration); 17.828 - if (reg_02.__reserved_1 || reg_02.__reserved_2) 17.829 - UNEXPECTED_IO_APIC(); 17.830 - } 17.831 - 17.832 -#if 0 17.833 - printk(KERN_DEBUG ".... IRQ redirection table:\n"); 17.834 - 17.835 - printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol" 17.836 - " Stat Dest Deli Vect: \n"); 17.837 - 17.838 - for (i = 0; i <= reg_01.entries; i++) { 17.839 - struct IO_APIC_route_entry entry; 17.840 - 17.841 - spin_lock_irqsave(&ioapic_lock, flags); 17.842 - *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2); 17.843 - *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2); 17.844 - spin_unlock_irqrestore(&ioapic_lock, flags); 17.845 - 17.846 - printk(KERN_DEBUG " %02x %03X %02X ", 17.847 - i, 17.848 - entry.dest.logical.logical_dest, 17.849 - entry.dest.physical.physical_dest 17.850 - ); 17.851 - 17.852 - printk("%1d %1d %1d %1d %1d %1d %1d %02X\n", 17.853 - entry.mask, 17.854 - entry.trigger, 17.855 - entry.irr, 17.856 - entry.polarity, 17.857 - entry.delivery_status, 17.858 - entry.dest_mode, 17.859 - entry.delivery_mode, 17.860 - entry.vector 17.861 - ); 17.862 - } 17.863 - } 17.864 - printk(KERN_DEBUG "IRQ to pin mappings:\n"); 17.865 - for (i = 0; i < NR_IRQS; i++) { 17.866 - struct irq_pin_list *entry = irq_2_pin + i; 17.867 - if (entry->pin < 0) 17.868 - continue; 17.869 - printk(KERN_DEBUG "IRQ%d ", i); 17.870 - for (;;) { 17.871 - printk("-> %d:%d", entry->apic, entry->pin); 17.872 - if (!entry->next) 17.873 - break; 17.874 - entry = irq_2_pin + entry->next; 17.875 - } 17.876 - printk("\n"); 17.877 -#endif 17.878 - } 17.879 - 17.880 - printk(KERN_INFO ".................................... done.\n"); 17.881 - 17.882 - return; 17.883 -} 17.884 - 17.885 -static void print_APIC_bitfield (int base) 17.886 -{ 17.887 - unsigned int v; 17.888 - int i, j; 17.889 - 17.890 - printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG); 17.891 - for (i = 0; i < 8; i++) { 17.892 - v = apic_read(base + i*0x10); 17.893 - for (j = 0; j < 32; j++) { 17.894 - if (v & (1<<j)) 17.895 - printk("1"); 17.896 - else 17.897 - printk("0"); 17.898 - } 17.899 - printk("\n"); 17.900 - } 17.901 -} 17.902 - 17.903 -void /*__init*/ print_local_APIC(void * dummy) 17.904 -{ 17.905 - unsigned int v, ver, maxlvt; 17.906 - 17.907 - printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n", 17.908 - smp_processor_id(), hard_smp_processor_id()); 17.909 - v = apic_read(APIC_ID); 17.910 - printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v)); 17.911 - v = apic_read(APIC_LVR); 17.912 - printk(KERN_INFO "... APIC VERSION: %08x\n", v); 17.913 - ver = GET_APIC_VERSION(v); 17.914 - maxlvt = get_maxlvt(); 17.915 - 17.916 - v = apic_read(APIC_TASKPRI); 17.917 - printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK); 17.918 - 17.919 - if (APIC_INTEGRATED(ver)) { /* !82489DX */ 17.920 - v = apic_read(APIC_ARBPRI); 17.921 - printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v, 17.922 - v & APIC_ARBPRI_MASK); 17.923 - v = apic_read(APIC_PROCPRI); 17.924 - printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v); 17.925 - } 17.926 - 17.927 - v = apic_read(APIC_EOI); 17.928 - printk(KERN_DEBUG "... APIC EOI: %08x\n", v); 17.929 - v = apic_read(APIC_RRR); 17.930 - printk(KERN_DEBUG "... APIC RRR: %08x\n", v); 17.931 - v = apic_read(APIC_LDR); 17.932 - printk(KERN_DEBUG "... APIC LDR: %08x\n", v); 17.933 - v = apic_read(APIC_DFR); 17.934 - printk(KERN_DEBUG "... APIC DFR: %08x\n", v); 17.935 - v = apic_read(APIC_SPIV); 17.936 - printk(KERN_DEBUG "... APIC SPIV: %08x\n", v); 17.937 - 17.938 - printk(KERN_DEBUG "... APIC ISR field:\n"); 17.939 - print_APIC_bitfield(APIC_ISR); 17.940 - printk(KERN_DEBUG "... APIC TMR field:\n"); 17.941 - print_APIC_bitfield(APIC_TMR); 17.942 - printk(KERN_DEBUG "... APIC IRR field:\n"); 17.943 - print_APIC_bitfield(APIC_IRR); 17.944 - 17.945 - if (APIC_INTEGRATED(ver)) { /* !82489DX */ 17.946 - if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 17.947 - apic_write(APIC_ESR, 0); 17.948 - v = apic_read(APIC_ESR); 17.949 - printk(KERN_DEBUG "... APIC ESR: %08x\n", v); 17.950 - } 17.951 - 17.952 - v = apic_read(APIC_ICR); 17.953 - printk(KERN_DEBUG "... APIC ICR: %08x\n", v); 17.954 - v = apic_read(APIC_ICR2); 17.955 - printk(KERN_DEBUG "... APIC ICR2: %08x\n", v); 17.956 - 17.957 - v = apic_read(APIC_LVTT); 17.958 - printk(KERN_DEBUG "... APIC LVTT: %08x\n", v); 17.959 - 17.960 - if (maxlvt > 3) { /* PC is LVT#4. */ 17.961 - v = apic_read(APIC_LVTPC); 17.962 - printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v); 17.963 - } 17.964 - v = apic_read(APIC_LVT0); 17.965 - printk(KERN_DEBUG "... APIC LVT0: %08x\n", v); 17.966 - v = apic_read(APIC_LVT1); 17.967 - printk(KERN_DEBUG "... APIC LVT1: %08x\n", v); 17.968 - 17.969 - if (maxlvt > 2) { /* ERR is LVT#3. */ 17.970 - v = apic_read(APIC_LVTERR); 17.971 - printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v); 17.972 - } 17.973 - 17.974 - v = apic_read(APIC_TMICT); 17.975 - printk(KERN_DEBUG "... APIC TMICT: %08x\n", v); 17.976 - v = apic_read(APIC_TMCCT); 17.977 - printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v); 17.978 - v = apic_read(APIC_TDCR); 17.979 - printk(KERN_DEBUG "... APIC TDCR: %08x\n", v); 17.980 - printk("\n"); 17.981 -} 17.982 - 17.983 -void print_all_local_APICs (void) 17.984 -{ 17.985 - smp_call_function(print_local_APIC, NULL, 1, 1); 17.986 - print_local_APIC(NULL); 17.987 -} 17.988 - 17.989 -void /*__init*/ print_PIC(void) 17.990 -{ 17.991 - extern spinlock_t i8259A_lock; 17.992 - unsigned int v, flags; 17.993 - 17.994 - printk(KERN_DEBUG "\nprinting PIC contents\n"); 17.995 - 17.996 - spin_lock_irqsave(&i8259A_lock, flags); 17.997 - 17.998 - v = inb(0xa1) << 8 | inb(0x21); 17.999 - printk(KERN_DEBUG "... PIC IMR: %04x\n", v); 17.1000 - 17.1001 - v = inb(0xa0) << 8 | inb(0x20); 17.1002 - printk(KERN_DEBUG "... PIC IRR: %04x\n", v); 17.1003 - 17.1004 - outb(0x0b,0xa0); 17.1005 - outb(0x0b,0x20); 17.1006 - v = inb(0xa0) << 8 | inb(0x20); 17.1007 - outb(0x0a,0xa0); 17.1008 - outb(0x0a,0x20); 17.1009 - 17.1010 - spin_unlock_irqrestore(&i8259A_lock, flags); 17.1011 - 17.1012 - printk(KERN_DEBUG "... PIC ISR: %04x\n", v); 17.1013 - 17.1014 - v = inb(0x4d1) << 8 | inb(0x4d0); 17.1015 - printk(KERN_DEBUG "... PIC ELCR: %04x\n", v); 17.1016 -} 17.1017 - 17.1018 -static void __init enable_IO_APIC(void) 17.1019 -{ 17.1020 - struct IO_APIC_reg_01 reg_01; 17.1021 - int i; 17.1022 - unsigned long flags; 17.1023 - 17.1024 - for (i = 0; i < PIN_MAP_SIZE; i++) { 17.1025 - irq_2_pin[i].pin = -1; 17.1026 - irq_2_pin[i].next = 0; 17.1027 - } 17.1028 - if (!pirqs_enabled) 17.1029 - for (i = 0; i < MAX_PIRQS; i++) 17.1030 - pirq_entries[i] = -1; 17.1031 - 17.1032 - /* 17.1033 - * The number of IO-APIC IRQ registers (== #pins): 17.1034 - */ 17.1035 - for (i = 0; i < nr_ioapics; i++) { 17.1036 - spin_lock_irqsave(&ioapic_lock, flags); 17.1037 - *(int *)®_01 = io_apic_read(i, 1); 17.1038 - spin_unlock_irqrestore(&ioapic_lock, flags); 17.1039 - nr_ioapic_registers[i] = reg_01.entries+1; 17.1040 - } 17.1041 - 17.1042 - /* 17.1043 - * Do not trust the IO-APIC being empty at bootup 17.1044 - */ 17.1045 - clear_IO_APIC(); 17.1046 -} 17.1047 - 17.1048 -/* 17.1049 - * Not an __init, needed by the reboot code 17.1050 - */ 17.1051 -void disable_IO_APIC(void) 17.1052 -{ 17.1053 - /* 17.1054 - * Clear the IO-APIC before rebooting: 17.1055 - */ 17.1056 - clear_IO_APIC(); 17.1057 - 17.1058 - disconnect_bsp_APIC(); 17.1059 -} 17.1060 - 17.1061 -/* 17.1062 - * function to set the IO-APIC physical IDs based on the 17.1063 - * values stored in the MPC table. 17.1064 - * 17.1065 - * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999 17.1066 - */ 17.1067 - 17.1068 -static void __init setup_ioapic_ids_from_mpc (void) 17.1069 -{ 17.1070 - struct IO_APIC_reg_00 reg_00; 17.1071 - unsigned long phys_id_present_map = phys_cpu_present_map; 17.1072 - int apic; 17.1073 - int i; 17.1074 - unsigned char old_id; 17.1075 - unsigned long flags; 17.1076 - 17.1077 - if (clustered_apic_mode) 17.1078 - /* We don't have a good way to do this yet - hack */ 17.1079 - phys_id_present_map = (u_long) 0xf; 17.1080 - /* 17.1081 - * Set the IOAPIC ID to the value stored in the MPC table. 17.1082 - */ 17.1083 - for (apic = 0; apic < nr_ioapics; apic++) { 17.1084 - 17.1085 - /* Read the register 0 value */ 17.1086 - spin_lock_irqsave(&ioapic_lock, flags); 17.1087 - *(int *)®_00 = io_apic_read(apic, 0); 17.1088 - spin_unlock_irqrestore(&ioapic_lock, flags); 17.1089 - 17.1090 - old_id = mp_ioapics[apic].mpc_apicid; 17.1091 - 17.1092 - if (mp_ioapics[apic].mpc_apicid >= apic_broadcast_id) { 17.1093 - printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n", 17.1094 - apic, mp_ioapics[apic].mpc_apicid); 17.1095 - printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", 17.1096 - reg_00.ID); 17.1097 - mp_ioapics[apic].mpc_apicid = reg_00.ID; 17.1098 - } 17.1099 - 17.1100 - /* 17.1101 - * Sanity check, is the ID really free? Every APIC in a 17.1102 - * system must have a unique ID or we get lots of nice 17.1103 - * 'stuck on smp_invalidate_needed IPI wait' messages. 17.1104 - * I/O APIC IDs no longer have any meaning for xAPICs and SAPICs. 17.1105 - */ 17.1106 - if ((clustered_apic_mode != CLUSTERED_APIC_XAPIC) && 17.1107 - (phys_id_present_map & (1 << mp_ioapics[apic].mpc_apicid))) { 17.1108 - printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n", 17.1109 - apic, mp_ioapics[apic].mpc_apicid); 17.1110 - for (i = 0; i < 0xf; i++) 17.1111 - if (!(phys_id_present_map & (1 << i))) 17.1112 - break; 17.1113 - if (i >= apic_broadcast_id) 17.1114 - panic("Max APIC ID exceeded!\n"); 17.1115 - printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n", 17.1116 - i); 17.1117 - phys_id_present_map |= 1 << i; 17.1118 - mp_ioapics[apic].mpc_apicid = i; 17.1119 - } else { 17.1120 - printk("Setting %d in the phys_id_present_map\n", mp_ioapics[apic].mpc_apicid); 17.1121 - phys_id_present_map |= 1 << mp_ioapics[apic].mpc_apicid; 17.1122 - } 17.1123 - 17.1124 - 17.1125 - /* 17.1126 - * We need to adjust the IRQ routing table 17.1127 - * if the ID changed. 17.1128 - */ 17.1129 - if (old_id != mp_ioapics[apic].mpc_apicid) 17.1130 - for (i = 0; i < mp_irq_entries; i++) 17.1131 - if (mp_irqs[i].mpc_dstapic == old_id) 17.1132 - mp_irqs[i].mpc_dstapic 17.1133 - = mp_ioapics[apic].mpc_apicid; 17.1134 - 17.1135 - /* 17.1136 - * Read the right value from the MPC table and 17.1137 - * write it into the ID register. 17.1138 - */ 17.1139 - printk(KERN_INFO "...changing IO-APIC physical APIC ID to %d ...", 17.1140 - mp_ioapics[apic].mpc_apicid); 17.1141 - 17.1142 - reg_00.ID = mp_ioapics[apic].mpc_apicid; 17.1143 - spin_lock_irqsave(&ioapic_lock, flags); 17.1144 - io_apic_write(apic, 0, *(int *)®_00); 17.1145 - spin_unlock_irqrestore(&ioapic_lock, flags); 17.1146 - 17.1147 - /* 17.1148 - * Sanity check 17.1149 - */ 17.1150 - spin_lock_irqsave(&ioapic_lock, flags); 17.1151 - *(int *)®_00 = io_apic_read(apic, 0); 17.1152 - spin_unlock_irqrestore(&ioapic_lock, flags); 17.1153 - if (reg_00.ID != mp_ioapics[apic].mpc_apicid) 17.1154 - panic("could not set ID!\n"); 17.1155 - else 17.1156 - printk(" ok.\n"); 17.1157 - } 17.1158 -} 17.1159 - 17.1160 -/* 17.1161 - * There is a nasty bug in some older SMP boards, their mptable lies 17.1162 - * about the timer IRQ. We do the following to work around the situation: 17.1163 - * 17.1164 - * - timer IRQ defaults to IO-APIC IRQ 17.1165 - * - if this function detects that timer IRQs are defunct, then we fall 17.1166 - * back to ISA timer IRQs 17.1167 - */ 17.1168 -static int __init timer_irq_works(void) 17.1169 -{ 17.1170 - unsigned int t1 = jiffies; 17.1171 - 17.1172 - sti(); 17.1173 - /* Let ten ticks pass... */ 17.1174 - mdelay((10 * 1000) / HZ); 17.1175 - 17.1176 - /* 17.1177 - * Expect a few ticks at least, to be sure some possible 17.1178 - * glue logic does not lock up after one or two first 17.1179 - * ticks in a non-ExtINT mode. Also the local APIC 17.1180 - * might have cached one ExtINT interrupt. Finally, at 17.1181 - * least one tick may be lost due to delays. 17.1182 - */ 17.1183 - if (jiffies - t1 > 4) 17.1184 - return 1; 17.1185 - 17.1186 - return 0; 17.1187 -} 17.1188 - 17.1189 -/* 17.1190 - * In the SMP+IOAPIC case it might happen that there are an unspecified 17.1191 - * number of pending IRQ events unhandled. These cases are very rare, 17.1192 - * so we 'resend' these IRQs via IPIs, to the same CPU. It's much 17.1193 - * better to do it this way as thus we do not have to be aware of 17.1194 - * 'pending' interrupts in the IRQ path, except at this point. 17.1195 - */ 17.1196 -/* 17.1197 - * Edge triggered needs to resend any interrupt 17.1198 - * that was delayed but this is now handled in the device 17.1199 - * independent code. 17.1200 - */ 17.1201 -#define enable_edge_ioapic_irq unmask_IO_APIC_irq 17.1202 - 17.1203 -static void disable_edge_ioapic_irq (unsigned int irq) { /* nothing */ } 17.1204 - 17.1205 -/* 17.1206 - * Starting up a edge-triggered IO-APIC interrupt is 17.1207 - * nasty - we need to make sure that we get the edge. 17.1208 - * If it is already asserted for some reason, we need 17.1209 - * return 1 to indicate that is was pending. 17.1210 - * 17.1211 - * This is not complete - we should be able to fake 17.1212 - * an edge even if it isn't on the 8259A... 17.1213 - */ 17.1214 - 17.1215 -static unsigned int startup_edge_ioapic_irq(unsigned int irq) 17.1216 -{ 17.1217 - int was_pending = 0; 17.1218 - unsigned long flags; 17.1219 - 17.1220 - spin_lock_irqsave(&ioapic_lock, flags); 17.1221 - if (irq < 16) { 17.1222 - disable_8259A_irq(irq); 17.1223 - if (i8259A_irq_pending(irq)) 17.1224 - was_pending = 1; 17.1225 - } 17.1226 - __unmask_IO_APIC_irq(irq); 17.1227 - spin_unlock_irqrestore(&ioapic_lock, flags); 17.1228 - 17.1229 - return was_pending; 17.1230 -} 17.1231 - 17.1232 -#define shutdown_edge_ioapic_irq disable_edge_ioapic_irq 17.1233 - 17.1234 -/* 17.1235 - * Once we have recorded IRQ_PENDING already, we can mask the 17.1236 - * interrupt for real. This prevents IRQ storms from unhandled 17.1237 - * devices. 17.1238 - */ 17.1239 -static void ack_edge_ioapic_irq(unsigned int irq) 17.1240 -{ 17.1241 - if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED)) 17.1242 - == (IRQ_PENDING | IRQ_DISABLED)) 17.1243 - mask_IO_APIC_irq(irq); 17.1244 - ack_APIC_irq(); 17.1245 -} 17.1246 - 17.1247 -static void end_edge_ioapic_irq (unsigned int i) { /* nothing */ } 17.1248 - 17.1249 - 17.1250 -/* 17.1251 - * Level triggered interrupts can just be masked, 17.1252 - * and shutting down and starting up the interrupt 17.1253 - * is the same as enabling and disabling them -- except 17.1254 - * with a startup need to return a "was pending" value. 17.1255 - * 17.1256 - * Level triggered interrupts are special because we 17.1257 - * do not touch any IO-APIC register while handling 17.1258 - * them. We ack the APIC in the end-IRQ handler, not 17.1259 - * in the start-IRQ-handler. Protection against reentrance 17.1260 - * from the same interrupt is still provided, both by the 17.1261 - * generic IRQ layer and by the fact that an unacked local 17.1262 - * APIC does not accept IRQs. 17.1263 - */ 17.1264 -static unsigned int startup_level_ioapic_irq (unsigned int irq) 17.1265 -{ 17.1266 - unmask_IO_APIC_irq(irq); 17.1267 - 17.1268 - return 0; /* don't check for pending */ 17.1269 -} 17.1270 - 17.1271 -#define shutdown_level_ioapic_irq mask_IO_APIC_irq 17.1272 -#define enable_level_ioapic_irq unmask_IO_APIC_irq 17.1273 -#define disable_level_ioapic_irq mask_IO_APIC_irq 17.1274 - 17.1275 -static void end_level_ioapic_irq (unsigned int irq) 17.1276 -{ 17.1277 - unsigned long v; 17.1278 - int i; 17.1279 - 17.1280 -/* 17.1281 - * It appears there is an erratum which affects at least version 0x11 17.1282 - * of I/O APIC (that's the 82093AA and cores integrated into various 17.1283 - * chipsets). Under certain conditions a level-triggered interrupt is 17.1284 - * erroneously delivered as edge-triggered one but the respective IRR 17.1285 - * bit gets set nevertheless. As a result the I/O unit expects an EOI 17.1286 - * message but it will never arrive and further interrupts are blocked 17.1287 - * from the source. The exact reason is so far unknown, but the 17.1288 - * phenomenon was observed when two consecutive interrupt requests 17.1289 - * from a given source get delivered to the same CPU and the source is 17.1290 - * temporarily disabled in between. 17.1291 - * 17.1292 - * A workaround is to simulate an EOI message manually. We achieve it 17.1293 - * by setting the trigger mode to edge and then to level when the edge 17.1294 - * trigger mode gets detected in the TMR of a local APIC for a 17.1295 - * level-triggered interrupt. We mask the source for the time of the 17.1296 - * operation to prevent an edge-triggered interrupt escaping meanwhile. 17.1297 - * The idea is from Manfred Spraul. --macro 17.1298 - */ 17.1299 - i = IO_APIC_VECTOR(irq); 17.1300 - v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1)); 17.1301 - 17.1302 - ack_APIC_irq(); 17.1303 - 17.1304 - if (!(v & (1 << (i & 0x1f)))) { 17.1305 -#ifdef APIC_LOCKUP_DEBUG 17.1306 - struct irq_pin_list *entry; 17.1307 -#endif 17.1308 - 17.1309 -#ifdef APIC_MISMATCH_DEBUG 17.1310 - atomic_inc(&irq_mis_count); 17.1311 -#endif 17.1312 - spin_lock(&ioapic_lock); 17.1313 - __mask_and_edge_IO_APIC_irq(irq); 17.1314 -#ifdef APIC_LOCKUP_DEBUG 17.1315 - for (entry = irq_2_pin + irq;;) { 17.1316 - unsigned int reg; 17.1317 - 17.1318 - if (entry->pin == -1) 17.1319 - break; 17.1320 - reg = io_apic_read(entry->apic, 0x10 + entry->pin * 2); 17.1321 - if (reg & 0x00004000) 17.1322 - printk(KERN_CRIT "Aieee!!! Remote IRR" 17.1323 - " still set after unlock!\n"); 17.1324 - if (!entry->next) 17.1325 - break; 17.1326 - entry = irq_2_pin + entry->next; 17.1327 - } 17.1328 -#endif 17.1329 - __unmask_and_level_IO_APIC_irq(irq); 17.1330 - spin_unlock(&ioapic_lock); 17.1331 - } 17.1332 -} 17.1333 - 17.1334 -static void mask_and_ack_level_ioapic_irq (unsigned int irq) { /* nothing */ } 17.1335 - 17.1336 -static void set_ioapic_affinity (unsigned int irq, unsigned long mask) 17.1337 -{ 17.1338 - unsigned long flags; 17.1339 - /* 17.1340 - * Only the first 8 bits are valid. 17.1341 - */ 17.1342 - mask = mask << 24; 17.1343 - 17.1344 - spin_lock_irqsave(&ioapic_lock, flags); 17.1345 - __DO_ACTION(1, = mask, ) 17.1346 - spin_unlock_irqrestore(&ioapic_lock, flags); 17.1347 -} 17.1348 - 17.1349 -/* 17.1350 - * Level and edge triggered IO-APIC interrupts need different handling, 17.1351 - * so we use two separate IRQ descriptors. Edge triggered IRQs can be 17.1352 - * handled with the level-triggered descriptor, but that one has slightly 17.1353 - * more overhead. Level-triggered interrupts cannot be handled with the 17.1354 - * edge-triggered handler, without risking IRQ storms and other ugly 17.1355 - * races. 17.1356 - */ 17.1357 - 17.1358 -static struct hw_interrupt_type ioapic_edge_irq_type = { 17.1359 - "IO-APIC-edge", 17.1360 - startup_edge_ioapic_irq, 17.1361 - shutdown_edge_ioapic_irq, 17.1362 - enable_edge_ioapic_irq, 17.1363 - disable_edge_ioapic_irq, 17.1364 - ack_edge_ioapic_irq, 17.1365 - end_edge_ioapic_irq, 17.1366 - set_ioapic_affinity, 17.1367 -}; 17.1368 - 17.1369 -static struct hw_interrupt_type ioapic_level_irq_type = { 17.1370 - "IO-APIC-level", 17.1371 - startup_level_ioapic_irq, 17.1372 - shutdown_level_ioapic_irq, 17.1373 - enable_level_ioapic_irq, 17.1374 - disable_level_ioapic_irq, 17.1375 - mask_and_ack_level_ioapic_irq, 17.1376 - end_level_ioapic_irq, 17.1377 - set_ioapic_affinity, 17.1378 -}; 17.1379 - 17.1380 -static inline void init_IO_APIC_traps(void) 17.1381 -{ 17.1382 - int irq; 17.1383 - 17.1384 - /* 17.1385 - * NOTE! The local APIC isn't very good at handling 17.1386 - * multiple interrupts at the same interrupt level. 17.1387 - * As the interrupt level is determined by taking the 17.1388 - * vector number and shifting that right by 4, we 17.1389 - * want to spread these out a bit so that they don't 17.1390 - * all fall in the same interrupt level. 17.1391 - * 17.1392 - * Also, we've got to be careful not to trash gate 17.1393 - * 0x80, because int 0x80 is hm, kind of importantish. ;) 17.1394 - */ 17.1395 - for (irq = 0; irq < NR_IRQS ; irq++) { 17.1396 - if (IO_APIC_IRQ(irq) && !IO_APIC_VECTOR(irq)) { 17.1397 - /* 17.1398 - * Hmm.. We don't have an entry for this, 17.1399 - * so default to an old-fashioned 8259 17.1400 - * interrupt if we can.. 17.1401 - */ 17.1402 - if (irq < 16) 17.1403 - make_8259A_irq(irq); 17.1404 - else 17.1405 - /* Strange. Oh, well.. */ 17.1406 - irq_desc[irq].handler = &no_irq_type; 17.1407 - } 17.1408 - } 17.1409 -} 17.1410 - 17.1411 -static void enable_lapic_irq (unsigned int irq) 17.1412 -{ 17.1413 - unsigned long v; 17.1414 - 17.1415 - v = apic_read(APIC_LVT0); 17.1416 - apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED); 17.1417 -} 17.1418 - 17.1419 -static void disable_lapic_irq (unsigned int irq) 17.1420 -{ 17.1421 - unsigned long v; 17.1422 - 17.1423 - v = apic_read(APIC_LVT0); 17.1424 - apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED); 17.1425 -} 17.1426 - 17.1427 -static void ack_lapic_irq (unsigned int irq) 17.1428 -{ 17.1429 - ack_APIC_irq(); 17.1430 -} 17.1431 - 17.1432 -static void end_lapic_irq (unsigned int i) { /* nothing */ } 17.1433 - 17.1434 -static struct hw_interrupt_type lapic_irq_type = { 17.1435 - "local-APIC-edge", 17.1436 - NULL, /* startup_irq() not used for IRQ0 */ 17.1437 - NULL, /* shutdown_irq() not used for IRQ0 */ 17.1438 - enable_lapic_irq, 17.1439 - disable_lapic_irq, 17.1440 - ack_lapic_irq, 17.1441 - end_lapic_irq 17.1442 -}; 17.1443 - 17.1444 -static void enable_NMI_through_LVT0 (void * dummy) 17.1445 -{ 17.1446 - unsigned int v, ver; 17.1447 - 17.1448 - ver = apic_read(APIC_LVR); 17.1449 - ver = GET_APIC_VERSION(ver); 17.1450 - v = APIC_DM_NMI; /* unmask and set to NMI */ 17.1451 - if (!APIC_INTEGRATED(ver)) /* 82489DX */ 17.1452 - v |= APIC_LVT_LEVEL_TRIGGER; 17.1453 - apic_write_around(APIC_LVT0, v); 17.1454 -} 17.1455 - 17.1456 -static void setup_nmi (void) 17.1457 -{ 17.1458 - /* 17.1459 - * Dirty trick to enable the NMI watchdog ... 17.1460 - * We put the 8259A master into AEOI mode and 17.1461 - * unmask on all local APICs LVT0 as NMI. 17.1462 - * 17.1463 - * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire') 17.1464 - * is from Maciej W. Rozycki - so we do not have to EOI from 17.1465 - * the NMI handler or the timer interrupt. 17.1466 - */ 17.1467 - printk(KERN_INFO "activating NMI Watchdog ..."); 17.1468 - 17.1469 - smp_call_function(enable_NMI_through_LVT0, NULL, 1, 1); 17.1470 - enable_NMI_through_LVT0(NULL); 17.1471 - 17.1472 - printk(" done.\n"); 17.1473 -} 17.1474 - 17.1475 -/* 17.1476 - * This looks a bit hackish but it's about the only one way of sending 17.1477 - * a few INTA cycles to 8259As and any associated glue logic. ICR does 17.1478 - * not support the ExtINT mode, unfortunately. We need to send these 17.1479 - * cycles as some i82489DX-based boards have glue logic that keeps the 17.1480 - * 8259A interrupt line asserted until INTA. --macro 17.1481 - */ 17.1482 -static inline void unlock_ExtINT_logic(void) 17.1483 -{ 17.1484 - int pin, i; 17.1485 - struct IO_APIC_route_entry entry0, entry1; 17.1486 - unsigned char save_control, save_freq_select; 17.1487 - unsigned long flags; 17.1488 - 17.1489 - pin = find_isa_irq_pin(8, mp_INT); 17.1490 - if (pin == -1) 17.1491 - return; 17.1492 - 17.1493 - spin_lock_irqsave(&ioapic_lock, flags); 17.1494 - *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin); 17.1495 - *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin); 17.1496 - spin_unlock_irqrestore(&ioapic_lock, flags); 17.1497 - clear_IO_APIC_pin(0, pin); 17.1498 - 17.1499 - memset(&entry1, 0, sizeof(entry1)); 17.1500 - 17.1501 - entry1.dest_mode = 0; /* physical delivery */ 17.1502 - entry1.mask = 0; /* unmask IRQ now */ 17.1503 - entry1.dest.physical.physical_dest = hard_smp_processor_id(); 17.1504 - entry1.delivery_mode = dest_ExtINT; 17.1505 - entry1.polarity = entry0.polarity; 17.1506 - entry1.trigger = 0; 17.1507 - entry1.vector = 0; 17.1508 - 17.1509 - spin_lock_irqsave(&ioapic_lock, flags); 17.1510 - io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1)); 17.1511 - io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0)); 17.1512 - spin_unlock_irqrestore(&ioapic_lock, flags); 17.1513 - 17.1514 - save_control = CMOS_READ(RTC_CONTROL); 17.1515 - save_freq_select = CMOS_READ(RTC_FREQ_SELECT); 17.1516 - CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6, 17.1517 - RTC_FREQ_SELECT); 17.1518 - CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL); 17.1519 - 17.1520 - i = 100; 17.1521 - while (i-- > 0) { 17.1522 - mdelay(10); 17.1523 - if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF) 17.1524 - i -= 10; 17.1525 - } 17.1526 - 17.1527 - CMOS_WRITE(save_control, RTC_CONTROL); 17.1528 - CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT); 17.1529 - clear_IO_APIC_pin(0, pin); 17.1530 - 17.1531 - spin_lock_irqsave(&ioapic_lock, flags); 17.1532 - io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1)); 17.1533 - io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0)); 17.1534 - spin_unlock_irqrestore(&ioapic_lock, flags); 17.1535 -} 17.1536 - 17.1537 -/* 17.1538 - * This code may look a bit paranoid, but it's supposed to cooperate with 17.1539 - * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ 17.1540 - * is so screwy. Thanks to Brian Perkins for testing/hacking this beast 17.1541 - * fanatically on his truly buggy board. 17.1542 - */ 17.1543 -static inline void check_timer(void) 17.1544 -{ 17.1545 - extern int timer_ack; 17.1546 - int pin1, pin2; 17.1547 - int vector; 17.1548 - 17.1549 - /* 17.1550 - * get/set the timer IRQ vector: 17.1551 - */ 17.1552 - disable_8259A_irq(0); 17.1553 - vector = assign_irq_vector(0); 17.1554 - set_intr_gate(vector, interrupt[0]); 17.1555 - 17.1556 - /* 17.1557 - * Subtle, code in do_timer_interrupt() expects an AEOI 17.1558 - * mode for the 8259A whenever interrupts are routed 17.1559 - * through I/O APICs. Also IRQ0 has to be enabled in 17.1560 - * the 8259A which implies the virtual wire has to be 17.1561 - * disabled in the local APIC. 17.1562 - */ 17.1563 - apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); 17.1564 - init_8259A(1); 17.1565 - timer_ack = 1; 17.1566 - enable_8259A_irq(0); 17.1567 - 17.1568 - pin1 = find_isa_irq_pin(0, mp_INT); 17.1569 - pin2 = find_isa_irq_pin(0, mp_ExtINT); 17.1570 - 17.1571 - printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2); 17.1572 - 17.1573 - if (pin1 != -1) { 17.1574 - /* 17.1575 - * Ok, does IRQ0 through the IOAPIC work? 17.1576 - */ 17.1577 - unmask_IO_APIC_irq(0); 17.1578 - if (timer_irq_works()) { 17.1579 - if (nmi_watchdog == NMI_IO_APIC) { 17.1580 - disable_8259A_irq(0); 17.1581 - setup_nmi(); 17.1582 - enable_8259A_irq(0); 17.1583 - // XXX Xen check_nmi_watchdog(); 17.1584 - } 17.1585 - return; 17.1586 - } 17.1587 - clear_IO_APIC_pin(0, pin1); 17.1588 - printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n"); 17.1589 - } 17.1590 - 17.1591 - printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... "); 17.1592 - if (pin2 != -1) { 17.1593 - printk("\n..... (found pin %d) ...", pin2); 17.1594 - /* 17.1595 - * legacy devices should be connected to IO APIC #0 17.1596 - */ 17.1597 - setup_ExtINT_IRQ0_pin(pin2, vector); 17.1598 - if (timer_irq_works()) { 17.1599 - printk("works.\n"); 17.1600 - if (pin1 != -1) 17.1601 - replace_pin_at_irq(0, 0, pin1, 0, pin2); 17.1602 - else 17.1603 - add_pin_to_irq(0, 0, pin2); 17.1604 - if (nmi_watchdog == NMI_IO_APIC) { 17.1605 - setup_nmi(); 17.1606 - // XXX Xen check_nmi_watchdog(); 17.1607 - } 17.1608 - return; 17.1609 - } 17.1610 - /* 17.1611 - * Cleanup, just in case ... 17.1612 - */ 17.1613 - clear_IO_APIC_pin(0, pin2); 17.1614 - } 17.1615 - printk(" failed.\n"); 17.1616 - 17.1617 - if (nmi_watchdog) { 17.1618 - printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n"); 17.1619 - nmi_watchdog = 0; 17.1620 - } 17.1621 - 17.1622 - printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ..."); 17.1623 - 17.1624 - disable_8259A_irq(0); 17.1625 - irq_desc[0].handler = &lapic_irq_type; 17.1626 - apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */ 17.1627 - enable_8259A_irq(0); 17.1628 - 17.1629 - if (timer_irq_works()) { 17.1630 - printk(" works.\n"); 17.1631 - return; 17.1632 - } 17.1633 - apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector); 17.1634 - printk(" failed.\n"); 17.1635 - 17.1636 - printk(KERN_INFO "...trying to set up timer as ExtINT IRQ..."); 17.1637 - 17.1638 - init_8259A(0); 17.1639 - make_8259A_irq(0); 17.1640 - apic_write_around(APIC_LVT0, APIC_DM_EXTINT); 17.1641 - 17.1642 - unlock_ExtINT_logic(); 17.1643 - 17.1644 - if (timer_irq_works()) { 17.1645 - printk(" works.\n"); 17.1646 - return; 17.1647 - } 17.1648 - printk(" failed :(.\n"); 17.1649 - panic("IO-APIC + timer doesn't work! pester mingo@redhat.com"); 17.1650 -} 17.1651 - 17.1652 -/* 17.1653 - * 17.1654 - * IRQ's that are handled by the old PIC in all cases: 17.1655 - * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ. 17.1656 - * Linux doesn't really care, as it's not actually used 17.1657 - * for any interrupt handling anyway. 17.1658 - * - There used to be IRQ13 here as well, but all 17.1659 - * MPS-compliant must not use it for FPU coupling and we 17.1660 - * want to use exception 16 anyway. And there are 17.1661 - * systems who connect it to an I/O APIC for other uses. 17.1662 - * Thus we don't mark it special any longer. 17.1663 - * 17.1664 - * Additionally, something is definitely wrong with irq9 17.1665 - * on PIIX4 boards. 17.1666 - */ 17.1667 -#define PIC_IRQS (1<<2) 17.1668 - 17.1669 -void __init setup_IO_APIC(void) 17.1670 -{ 17.1671 - enable_IO_APIC(); 17.1672 - 17.1673 - io_apic_irqs = ~PIC_IRQS; 17.1674 - printk("ENABLING IO-APIC IRQs\n"); 17.1675 - 17.1676 - /* 17.1677 - * Set up the IO-APIC IRQ routing table by parsing the MP-BIOS 17.1678 - * mptable: 17.1679 - */ 17.1680 - setup_ioapic_ids_from_mpc(); 17.1681 - sync_Arb_IDs(); 17.1682 - setup_IO_APIC_irqs(); 17.1683 - init_IO_APIC_traps(); 17.1684 - check_timer(); 17.1685 - print_IO_APIC(); 17.1686 -}
18.1 --- a/xen-2.4.16/arch/i386/ioremap.c Mon Feb 24 16:55:07 2003 +0000 18.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 18.3 @@ -1,106 +0,0 @@ 18.4 -/* 18.5 - * arch/i386/mm/ioremap.c 18.6 - * 18.7 - * Re-map IO memory to kernel address space so that we can access it. 18.8 - * This is needed for high PCI addresses that aren't mapped in the 18.9 - * 640k-1MB IO memory area on PC's 18.10 - * 18.11 - * (C) Copyright 1995 1996 Linus Torvalds 18.12 - */ 18.13 - 18.14 -//#include <linux/vmalloc.h> 18.15 -#include <asm/io.h> 18.16 -#include <asm/pgalloc.h> 18.17 -#include <asm/page.h> 18.18 - 18.19 -static unsigned long remap_base = 0; 18.20 - 18.21 -#define L1_PROT (_PAGE_PRESENT|_PAGE_RW|_PAGE_ACCESSED) 18.22 -#define L2_PROT (_PAGE_PRESENT|_PAGE_RW|_PAGE_ACCESSED|_PAGE_DIRTY) 18.23 - 18.24 -#define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK) 18.25 - 18.26 -static void new_l2e(l2_pgentry_t *pl2e) 18.27 -{ 18.28 - l1_pgentry_t *pl1e = (l1_pgentry_t *)get_free_page(GFP_KERNEL); 18.29 - if ( !pl1e ) BUG(); 18.30 - clear_page(pl1e); 18.31 - *pl2e = mk_l2_pgentry(__pa(pl1e)|L2_PROT); 18.32 -} 18.33 - 18.34 - 18.35 -void * __ioremap(unsigned long phys_addr, unsigned long size, unsigned long flags) 18.36 -{ 18.37 - unsigned long vaddr; 18.38 - unsigned long offset, cur=0, last_addr; 18.39 - l2_pgentry_t *pl2e; 18.40 - l1_pgentry_t *pl1e; 18.41 - 18.42 - /* First time through, start allocating from far end of virtual memory. */ 18.43 - if ( !remap_base ) remap_base = IOREMAP_VIRT_START; 18.44 - 18.45 - /* Don't allow wraparound or zero size */ 18.46 - last_addr = phys_addr + size - 1; 18.47 - if (!size || last_addr < phys_addr) 18.48 - return NULL; 18.49 - 18.50 - /* 18.51 - * Don't remap the low PCI/ISA area, it's always mapped.. 18.52 - */ 18.53 - if (phys_addr >= 0xA0000 && last_addr < 0x100000) 18.54 - return phys_to_virt(phys_addr); 18.55 - 18.56 -#if 0 18.57 - /* 18.58 - * Don't allow anybody to remap normal RAM that we're using.. 18.59 - */ 18.60 - if (phys_addr < virt_to_phys(high_memory)) { 18.61 - char *t_addr, *t_end; 18.62 - struct pfn_info *page; 18.63 - 18.64 - t_addr = __va(phys_addr); 18.65 - t_end = t_addr + (size - 1); 18.66 - 18.67 - for(page = virt_to_page(t_addr); page <= virt_to_page(t_end); page++) 18.68 - if(!PageReserved(page)) 18.69 - return NULL; 18.70 - } 18.71 -#endif 18.72 - 18.73 - /* 18.74 - * Mappings have to be page-aligned 18.75 - */ 18.76 - offset = phys_addr & ~PAGE_MASK; 18.77 - phys_addr &= PAGE_MASK; 18.78 - size = PAGE_ALIGN(last_addr) - phys_addr; 18.79 - 18.80 - /* 18.81 - * Ok, go for it.. 18.82 - */ 18.83 - vaddr = remap_base; 18.84 - remap_base += size; 18.85 - pl2e = idle0_pg_table + l2_table_offset(vaddr); 18.86 - if ( l2_pgentry_empty(*pl2e) ) new_l2e(pl2e); 18.87 - pl1e = l2_pgentry_to_l1(*pl2e++) + l1_table_offset(vaddr); 18.88 - for ( ; ; ) 18.89 - { 18.90 - if ( !l1_pgentry_empty(*pl1e) ) BUG(); 18.91 - *pl1e++ = mk_l1_pgentry((phys_addr+cur)|L1_PROT|flags); 18.92 - cur += PAGE_SIZE; 18.93 - if ( cur == size ) break; 18.94 - if ( !((unsigned long)pl1e & (PAGE_SIZE-1)) ) 18.95 - { 18.96 - if ( l2_pgentry_empty(*pl2e) ) new_l2e(pl2e); 18.97 - pl1e = l2_pgentry_to_l1(*pl2e++); 18.98 - } 18.99 - } 18.100 - 18.101 - flush_tlb_all(); 18.102 - 18.103 - return (void *) (offset + (char *)vaddr); 18.104 -} 18.105 - 18.106 -void iounmap(void *addr) 18.107 -{ 18.108 - /* NOP for now. */ 18.109 -}
19.1 --- a/xen-2.4.16/arch/i386/irq.c Mon Feb 24 16:55:07 2003 +0000 19.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 19.3 @@ -1,895 +0,0 @@ 19.4 -/* 19.5 - * linux/arch/i386/kernel/irq.c 19.6 - * 19.7 - * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar 19.8 - * 19.9 - * This file contains the code used by various IRQ handling routines: 19.10 - * asking for different IRQ's should be done through these routines 19.11 - * instead of just grabbing them. Thus setup_irqs with different IRQ numbers 19.12 - * shouldn't result in any weird surprises, and installing new handlers 19.13 - * should be easier. 19.14 - */ 19.15 - 19.16 -/* 19.17 - * (mostly architecture independent, will move to kernel/irq.c in 2.5.) 19.18 - * 19.19 - * IRQs are in fact implemented a bit like signal handlers for the kernel. 19.20 - * Naturally it's not a 1:1 relation, but there are similarities. 19.21 - */ 19.22 - 19.23 -#include <xeno/config.h> 19.24 -#include <xeno/init.h> 19.25 -#include <xeno/errno.h> 19.26 -#include <xeno/sched.h> 19.27 -#include <xeno/interrupt.h> 19.28 -#include <xeno/irq.h> 19.29 -#include <xeno/slab.h> 19.30 - 19.31 -#include <asm/msr.h> 19.32 -#include <asm/hardirq.h> 19.33 -#include <asm/ptrace.h> 19.34 -#include <asm/atomic.h> 19.35 -#include <asm/io.h> 19.36 -#include <asm/smp.h> 19.37 -#include <asm/system.h> 19.38 -#include <asm/bitops.h> 19.39 -#include <asm/pgalloc.h> 19.40 -#include <xeno/delay.h> 19.41 - 19.42 - 19.43 -/* 19.44 - * Linux has a controller-independent x86 interrupt architecture. 19.45 - * every controller has a 'controller-template', that is used 19.46 - * by the main code to do the right thing. Each driver-visible 19.47 - * interrupt source is transparently wired to the apropriate 19.48 - * controller. Thus drivers need not be aware of the 19.49 - * interrupt-controller. 19.50 - * 19.51 - * Various interrupt controllers we handle: 8259 PIC, SMP IO-APIC, 19.52 - * PIIX4's internal 8259 PIC and SGI's Visual Workstation Cobalt (IO-)APIC. 19.53 - * (IO-APICs assumed to be messaging to Pentium local-APICs) 19.54 - * 19.55 - * the code is designed to be easily extended with new/different 19.56 - * interrupt controllers, without having to do assembly magic. 19.57 - */ 19.58 - 19.59 -/* 19.60 - * Controller mappings for all interrupt sources: 19.61 - */ 19.62 -irq_desc_t irq_desc[NR_IRQS] __cacheline_aligned = 19.63 -{ [0 ... NR_IRQS-1] = { 0, &no_irq_type, NULL, 0, SPIN_LOCK_UNLOCKED}}; 19.64 - 19.65 -/* 19.66 - * Special irq handlers. 19.67 - */ 19.68 - 19.69 -void no_action(int cpl, void *dev_id, struct pt_regs *regs) { } 19.70 - 19.71 -/* 19.72 - * Generic no controller code 19.73 - */ 19.74 - 19.75 -static void enable_none(unsigned int irq) { } 19.76 -static unsigned int startup_none(unsigned int irq) { return 0; } 19.77 -static void disable_none(unsigned int irq) { } 19.78 -static void ack_none(unsigned int irq) 19.79 -{ 19.80 -/* 19.81 - * 'what should we do if we get a hw irq event on an illegal vector'. 19.82 - * each architecture has to answer this themselves, it doesnt deserve 19.83 - * a generic callback i think. 19.84 - */ 19.85 -#if CONFIG_X86 19.86 - printk("unexpected IRQ trap at vector %02x\n", irq); 19.87 -#ifdef CONFIG_X86_LOCAL_APIC 19.88 - /* 19.89 - * Currently unexpected vectors happen only on SMP and APIC. 19.90 - * We _must_ ack these because every local APIC has only N 19.91 - * irq slots per priority level, and a 'hanging, unacked' IRQ 19.92 - * holds up an irq slot - in excessive cases (when multiple 19.93 - * unexpected vectors occur) that might lock up the APIC 19.94 - * completely. 19.95 - */ 19.96 - ack_APIC_irq(); 19.97 -#endif 19.98 -#endif 19.99 -} 19.100 - 19.101 -/* startup is the same as "enable", shutdown is same as "disable" */ 19.102 -#define shutdown_none disable_none 19.103 -#define end_none enable_none 19.104 - 19.105 -struct hw_interrupt_type no_irq_type = { 19.106 - "none", 19.107 - startup_none, 19.108 - shutdown_none, 19.109 - enable_none, 19.110 - disable_none, 19.111 - ack_none, 19.112 - end_none 19.113 -}; 19.114 - 19.115 -atomic_t irq_err_count; 19.116 -#ifdef CONFIG_X86_IO_APIC 19.117 -#ifdef APIC_MISMATCH_DEBUG 19.118 -atomic_t irq_mis_count; 19.119 -#endif 19.120 -#endif 19.121 - 19.122 -/* 19.123 - * Generic, controller-independent functions: 19.124 - */ 19.125 - 19.126 -/* 19.127 - * Global interrupt locks for SMP. Allow interrupts to come in on any 19.128 - * CPU, yet make cli/sti act globally to protect critical regions.. 19.129 - */ 19.130 - 19.131 -#ifdef CONFIG_SMP 19.132 -unsigned char global_irq_holder = 0xff; 19.133 -unsigned volatile long global_irq_lock; /* pendantic: long for set_bit --RR */ 19.134 - 19.135 -#define MAXCOUNT 100000000 19.136 - 19.137 -/* 19.138 - * I had a lockup scenario where a tight loop doing 19.139 - * spin_unlock()/spin_lock() on CPU#1 was racing with 19.140 - * spin_lock() on CPU#0. CPU#0 should have noticed spin_unlock(), but 19.141 - * apparently the spin_unlock() information did not make it 19.142 - * through to CPU#0 ... nasty, is this by design, do we have to limit 19.143 - * 'memory update oscillation frequency' artificially like here? 19.144 - * 19.145 - * Such 'high frequency update' races can be avoided by careful design, but 19.146 - * some of our major constructs like spinlocks use similar techniques, 19.147 - * it would be nice to clarify this issue. Set this define to 0 if you 19.148 - * want to check whether your system freezes. I suspect the delay done 19.149 - * by SYNC_OTHER_CORES() is in correlation with 'snooping latency', but 19.150 - * i thought that such things are guaranteed by design, since we use 19.151 - * the 'LOCK' prefix. 19.152 - */ 19.153 -#define SUSPECTED_CPU_OR_CHIPSET_BUG_WORKAROUND 0 19.154 - 19.155 -#if SUSPECTED_CPU_OR_CHIPSET_BUG_WORKAROUND 19.156 -# define SYNC_OTHER_CORES(x) udelay(x+1) 19.157 -#else 19.158 -/* 19.159 - * We have to allow irqs to arrive between __sti and __cli 19.160 - */ 19.161 -# define SYNC_OTHER_CORES(x) __asm__ __volatile__ ("nop") 19.162 -#endif 19.163 - 19.164 -static inline void wait_on_irq(int cpu) 19.165 -{ 19.166 - for (;;) { 19.167 - 19.168 - /* 19.169 - * Wait until all interrupts are gone. Wait 19.170 - * for bottom half handlers unless we're 19.171 - * already executing in one.. 19.172 - */ 19.173 - if (!irqs_running()) 19.174 - if (local_bh_count(cpu) || !spin_is_locked(&global_bh_lock)) 19.175 - break; 19.176 - 19.177 - /* Duh, we have to loop. Release the lock to avoid deadlocks */ 19.178 - clear_bit(0,&global_irq_lock); 19.179 - 19.180 - for (;;) { 19.181 - __sti(); 19.182 - SYNC_OTHER_CORES(cpu); 19.183 - __cli(); 19.184 - if (irqs_running()) 19.185 - continue; 19.186 - if (global_irq_lock) 19.187 - continue; 19.188 - if (!local_bh_count(cpu) && spin_is_locked(&global_bh_lock)) 19.189 - continue; 19.190 - if (!test_and_set_bit(0,&global_irq_lock)) 19.191 - break; 19.192 - } 19.193 - } 19.194 -} 19.195 - 19.196 -/* 19.197 - * This is called when we want to synchronize with 19.198 - * interrupts. We may for example tell a device to 19.199 - * stop sending interrupts: but to make sure there 19.200 - * are no interrupts that are executing on another 19.201 - * CPU we need to call this function. 19.202 - */ 19.203 -void synchronize_irq(void) 19.204 -{ 19.205 - if (irqs_running()) { 19.206 - /* Stupid approach */ 19.207 - cli(); 19.208 - sti(); 19.209 - } 19.210 -} 19.211 - 19.212 -static inline void get_irqlock(int cpu) 19.213 -{ 19.214 - if (test_and_set_bit(0,&global_irq_lock)) { 19.215 - /* do we already hold the lock? */ 19.216 - if ((unsigned char) cpu == global_irq_holder) 19.217 - return; 19.218 - /* Uhhuh.. Somebody else got it. Wait.. */ 19.219 - do { 19.220 - do { 19.221 - rep_nop(); 19.222 - } while (test_bit(0,&global_irq_lock)); 19.223 - } while (test_and_set_bit(0,&global_irq_lock)); 19.224 - } 19.225 - /* 19.226 - * We also to make sure that nobody else is running 19.227 - * in an interrupt context. 19.228 - */ 19.229 - wait_on_irq(cpu); 19.230 - 19.231 - /* 19.232 - * Ok, finally.. 19.233 - */ 19.234 - global_irq_holder = cpu; 19.235 -} 19.236 - 19.237 -#define EFLAGS_IF_SHIFT 9 19.238 - 19.239 -/* 19.240 - * A global "cli()" while in an interrupt context 19.241 - * turns into just a local cli(). Interrupts 19.242 - * should use spinlocks for the (very unlikely) 19.243 - * case that they ever want to protect against 19.244 - * each other. 19.245 - * 19.246 - * If we already have local interrupts disabled, 19.247 - * this will not turn a local disable into a 19.248 - * global one (problems with spinlocks: this makes 19.249 - * save_flags+cli+sti usable inside a spinlock). 19.250 - */ 19.251 -void __global_cli(void) 19.252 -{ 19.253 - unsigned int flags; 19.254 - 19.255 - __save_flags(flags); 19.256 - if (flags & (1 << EFLAGS_IF_SHIFT)) { 19.257 - int cpu = smp_processor_id(); 19.258 - __cli(); 19.259 - if (!local_irq_count(cpu)) 19.260 - get_irqlock(cpu); 19.261 - } 19.262 -} 19.263 - 19.264 -void __global_sti(void) 19.265 -{ 19.266 - int cpu = smp_processor_id(); 19.267 - 19.268 - if (!local_irq_count(cpu)) 19.269 - release_irqlock(cpu); 19.270 - __sti(); 19.271 -} 19.272 - 19.273 -/* 19.274 - * SMP flags value to restore to: 19.275 - * 0 - global cli 19.276 - * 1 - global sti 19.277 - * 2 - local cli 19.278 - * 3 - local sti 19.279 - */ 19.280 -unsigned long __global_save_flags(void) 19.281 -{ 19.282 - int retval; 19.283 - int local_enabled; 19.284 - unsigned long flags; 19.285 - int cpu = smp_processor_id(); 19.286 - 19.287 - __save_flags(flags); 19.288 - local_enabled = (flags >> EFLAGS_IF_SHIFT) & 1; 19.289 - /* default to local */ 19.290 - retval = 2 + local_enabled; 19.291 - 19.292 - /* check for global flags if we're not in an interrupt */ 19.293 - if (!local_irq_count(cpu)) { 19.294 - if (local_enabled) 19.295 - retval = 1; 19.296 - if (global_irq_holder == cpu) 19.297 - retval = 0; 19.298 - } 19.299 - return retval; 19.300 -} 19.301 - 19.302 -void __global_restore_flags(unsigned long flags) 19.303 -{ 19.304 - switch (flags) { 19.305 - case 0: 19.306 - __global_cli(); 19.307 - break; 19.308 - case 1: 19.309 - __global_sti(); 19.310 - break; 19.311 - case 2: 19.312 - __cli(); 19.313 - break; 19.314 - case 3: 19.315 - __sti(); 19.316 - break; 19.317 - default: 19.318 - printk("global_restore_flags: %08lx (%08lx)\n", 19.319 - flags, (&flags)[-1]); 19.320 - } 19.321 -} 19.322 - 19.323 -#endif 19.324 - 19.325 -/* 19.326 - * This should really return information about whether 19.327 - * we should do bottom half handling etc. Right now we 19.328 - * end up _always_ checking the bottom half, which is a 19.329 - * waste of time and is not what some drivers would 19.330 - * prefer. 19.331 - */ 19.332 -int handle_IRQ_event(unsigned int irq, struct pt_regs * regs, struct irqaction * action) 19.333 -{ 19.334 - int status; 19.335 - int cpu = smp_processor_id(); 19.336 - 19.337 - irq_enter(cpu, irq); 19.338 - 19.339 - status = 1; /* Force the "do bottom halves" bit */ 19.340 - 19.341 - if (!(action->flags & SA_INTERRUPT)) 19.342 - __sti(); 19.343 - 19.344 - do { 19.345 - status |= action->flags; 19.346 - action->handler(irq, action->dev_id, regs); 19.347 - action = action->next; 19.348 - } while (action); 19.349 - 19.350 - __cli(); 19.351 - 19.352 - irq_exit(cpu, irq); 19.353 - 19.354 - return status; 19.355 -} 19.356 - 19.357 -/* 19.358 - * Generic enable/disable code: this just calls 19.359 - * down into the PIC-specific version for the actual 19.360 - * hardware disable after having gotten the irq 19.361 - * controller lock. 19.362 - */ 19.363 - 19.364 -/** 19.365 - * disable_irq_nosync - disable an irq without waiting 19.366 - * @irq: Interrupt to disable 19.367 - * 19.368 - * Disable the selected interrupt line. Disables and Enables are 19.369 - * nested. 19.370 - * Unlike disable_irq(), this function does not ensure existing 19.371 - * instances of the IRQ handler have completed before returning. 19.372 - * 19.373 - * This function may be called from IRQ context. 19.374 - */ 19.375 - 19.376 -inline void disable_irq_nosync(unsigned int irq) 19.377 -{ 19.378 - irq_desc_t *desc = irq_desc + irq; 19.379 - unsigned long flags; 19.380 - 19.381 - spin_lock_irqsave(&desc->lock, flags); 19.382 - if (!desc->depth++) { 19.383 - desc->status |= IRQ_DISABLED; 19.384 - desc->handler->disable(irq); 19.385 - } 19.386 - spin_unlock_irqrestore(&desc->lock, flags); 19.387 -} 19.388 - 19.389 -/** 19.390 - * disable_irq - disable an irq and wait for completion 19.391 - * @irq: Interrupt to disable 19.392 - * 19.393 - * Disable the selected interrupt line. Enables and Disables are 19.394 - * nested. 19.395 - * This function waits for any pending IRQ handlers for this interrupt 19.396 - * to complete before returning. If you use this function while 19.397 - * holding a resource the IRQ handler may need you will deadlock. 19.398 - * 19.399 - * This function may be called - with care - from IRQ context. 19.400 - */ 19.401 - 19.402 -void disable_irq(unsigned int irq) 19.403 -{ 19.404 - disable_irq_nosync(irq); 19.405 - 19.406 - if (!local_irq_count(smp_processor_id())) { 19.407 - do { 19.408 - barrier(); 19.409 - cpu_relax(); 19.410 - } while (irq_desc[irq].status & IRQ_INPROGRESS); 19.411 - } 19.412 -} 19.413 - 19.414 -/** 19.415 - * enable_irq - enable handling of an irq 19.416 - * @irq: Interrupt to enable 19.417 - * 19.418 - * Undoes the effect of one call to disable_irq(). If this 19.419 - * matches the last disable, processing of interrupts on this 19.420 - * IRQ line is re-enabled. 19.421 - * 19.422 - * This function may be called from IRQ context. 19.423 - */ 19.424 - 19.425 -void enable_irq(unsigned int irq) 19.426 -{ 19.427 - irq_desc_t *desc = irq_desc + irq; 19.428 - unsigned long flags; 19.429 - 19.430 - spin_lock_irqsave(&desc->lock, flags); 19.431 - switch (desc->depth) { 19.432 - case 1: { 19.433 - unsigned int status = desc->status & ~IRQ_DISABLED; 19.434 - desc->status = status; 19.435 - if ((status & (IRQ_PENDING | IRQ_REPLAY)) == IRQ_PENDING) { 19.436 - desc->status = status | IRQ_REPLAY; 19.437 - hw_resend_irq(desc->handler,irq); 19.438 - } 19.439 - desc->handler->enable(irq); 19.440 - /* fall-through */ 19.441 - } 19.442 - default: 19.443 - desc->depth--; 19.444 - break; 19.445 - case 0: 19.446 - printk("enable_irq(%u) unbalanced from %p\n", irq, 19.447 - __builtin_return_address(0)); 19.448 - } 19.449 - spin_unlock_irqrestore(&desc->lock, flags); 19.450 -} 19.451 - 19.452 -/* 19.453 - * do_IRQ handles all normal device IRQ's (the special 19.454 - * SMP cross-CPU interrupts have their own specific 19.455 - * handlers). 19.456 - */ 19.457 -asmlinkage unsigned int do_IRQ(struct pt_regs regs) 19.458 -{ 19.459 - /* 19.460 - * We ack quickly, we don't want the irq controller 19.461 - * thinking we're snobs just because some other CPU has 19.462 - * disabled global interrupts (we have already done the 19.463 - * INT_ACK cycles, it's too late to try to pretend to the 19.464 - * controller that we aren't taking the interrupt). 19.465 - * 19.466 - * 0 return value means that this irq is already being 19.467 - * handled by some other CPU. (or is disabled) 19.468 - */ 19.469 - int irq = regs.orig_eax & 0xff; /* high bits used in ret_from_ code */ 19.470 - int cpu = smp_processor_id(); 19.471 - irq_desc_t *desc = irq_desc + irq; 19.472 - struct irqaction * action; 19.473 - unsigned int status; 19.474 - 19.475 - spin_lock(&desc->lock); 19.476 - desc->handler->ack(irq); 19.477 - /* 19.478 - REPLAY is when Linux resends an IRQ that was dropped earlier 19.479 - WAITING is used by probe to mark irqs that are being tested 19.480 - */ 19.481 - status = desc->status & ~(IRQ_REPLAY | IRQ_WAITING); 19.482 - status |= IRQ_PENDING; /* we _want_ to handle it */ 19.483 - 19.484 - /* 19.485 - * If the IRQ is disabled for whatever reason, we cannot 19.486 - * use the action we have. 19.487 - */ 19.488 - action = NULL; 19.489 - if (!(status & (IRQ_DISABLED | IRQ_INPROGRESS))) { 19.490 - action = desc->action; 19.491 - status &= ~IRQ_PENDING; /* we commit to handling */ 19.492 - status |= IRQ_INPROGRESS; /* we are handling it */ 19.493 - } 19.494 - desc->status = status; 19.495 - 19.496 - /* 19.497 - * If there is no IRQ handler or it was disabled, exit early. 19.498 - Since we set PENDING, if another processor is handling 19.499 - a different instance of this same irq, the other processor 19.500 - will take care of it. 19.501 - */ 19.502 - if (!action) 19.503 - goto out; 19.504 - 19.505 - /* 19.506 - * Edge triggered interrupts need to remember 19.507 - * pending events. 19.508 - * This applies to any hw interrupts that allow a second 19.509 - * instance of the same irq to arrive while we are in do_IRQ 19.510 - * or in the handler. But the code here only handles the _second_ 19.511 - * instance of the irq, not the third or fourth. So it is mostly 19.512 - * useful for irq hardware that does not mask cleanly in an 19.513 - * SMP environment. 19.514 - */ 19.515 - for (;;) { 19.516 - spin_unlock(&desc->lock); 19.517 - handle_IRQ_event(irq, ®s, action); 19.518 - spin_lock(&desc->lock); 19.519 - 19.520 - if (!(desc->status & IRQ_PENDING)) 19.521 - break; 19.522 - desc->status &= ~IRQ_PENDING; 19.523 - } 19.524 - desc->status &= ~IRQ_INPROGRESS; 19.525 - out: 19.526 - /* 19.527 - * The ->end() handler has to deal with interrupts which got 19.528 - * disabled while the handler was running. 19.529 - */ 19.530 - desc->handler->end(irq); 19.531 - spin_unlock(&desc->lock); 19.532 - 19.533 - if (softirq_pending(cpu)) 19.534 - do_softirq(); 19.535 - 19.536 - return 1; 19.537 -} 19.538 - 19.539 -/** 19.540 - * request_irq - allocate an interrupt line 19.541 - * @irq: Interrupt line to allocate 19.542 - * @handler: Function to be called when the IRQ occurs 19.543 - * @irqflags: Interrupt type flags 19.544 - * @devname: An ascii name for the claiming device 19.545 - * @dev_id: A cookie passed back to the handler function 19.546 - * 19.547 - * This call allocates interrupt resources and enables the 19.548 - * interrupt line and IRQ handling. From the point this 19.549 - * call is made your handler function may be invoked. Since 19.550 - * your handler function must clear any interrupt the board 19.551 - * raises, you must take care both to initialise your hardware 19.552 - * and to set up the interrupt handler in the right order. 19.553 - * 19.554 - * Dev_id must be globally unique. Normally the address of the 19.555 - * device data structure is used as the cookie. Since the handler 19.556 - * receives this value it makes sense to use it. 19.557 - * 19.558 - * If your interrupt is shared you must pass a non NULL dev_id 19.559 - * as this is required when freeing the interrupt. 19.560 - * 19.561 - * Flags: 19.562 - * 19.563 - * SA_SHIRQ Interrupt is shared 19.564 - * 19.565 - * SA_INTERRUPT Disable local interrupts while processing 19.566 - */ 19.567 - 19.568 -int request_irq(unsigned int irq, 19.569 - void (*handler)(int, void *, struct pt_regs *), 19.570 - unsigned long irqflags, 19.571 - const char * devname, 19.572 - void *dev_id) 19.573 -{ 19.574 - int retval; 19.575 - struct irqaction * action; 19.576 - 19.577 - if (irq >= NR_IRQS) 19.578 - return -EINVAL; 19.579 - if (!handler) 19.580 - return -EINVAL; 19.581 - 19.582 - action = (struct irqaction *) 19.583 - kmalloc(sizeof(struct irqaction), GFP_KERNEL); 19.584 - if (!action) 19.585 - return -ENOMEM; 19.586 - 19.587 - action->handler = handler; 19.588 - action->flags = irqflags; 19.589 - action->mask = 0; 19.590 - action->name = devname; 19.591 - action->next = NULL; 19.592 - action->dev_id = dev_id; 19.593 - 19.594 - retval = setup_irq(irq, action); 19.595 - if (retval) 19.596 - kfree(action); 19.597 - 19.598 - return retval; 19.599 -} 19.600 - 19.601 -/** 19.602 - * free_irq - free an interrupt 19.603 - * @irq: Interrupt line to free 19.604 - * @dev_id: Device identity to free 19.605 - * 19.606 - * Remove an interrupt handler. The handler is removed and if the 19.607 - * interrupt line is no longer in use by any driver it is disabled. 19.608 - * On a shared IRQ the caller must ensure the interrupt is disabled 19.609 - * on the card it drives before calling this function. The function 19.610 - * does not return until any executing interrupts for this IRQ 19.611 - * have completed. 19.612 - * 19.613 - * This function may be called from interrupt context. 19.614 - * 19.615 - * Bugs: Attempting to free an irq in a handler for the same irq hangs 19.616 - * the machine. 19.617 - */ 19.618 - 19.619 -void free_irq(unsigned int irq, void *dev_id) 19.620 -{ 19.621 - irq_desc_t *desc; 19.622 - struct irqaction **p; 19.623 - unsigned long flags; 19.624 - 19.625 - if (irq >= NR_IRQS) 19.626 - return; 19.627 - 19.628 - desc = irq_desc + irq; 19.629 - spin_lock_irqsave(&desc->lock,flags); 19.630 - p = &desc->action; 19.631 - for (;;) { 19.632 - struct irqaction * action = *p; 19.633 - if (action) { 19.634 - struct irqaction **pp = p; 19.635 - p = &action->next; 19.636 - if (action->dev_id != dev_id) 19.637 - continue; 19.638 - 19.639 - /* Found it - now remove it from the list of entries */ 19.640 - *pp = action->next; 19.641 - if (!desc->action) { 19.642 - desc->status |= IRQ_DISABLED; 19.643 - desc->handler->shutdown(irq); 19.644 - } 19.645 - spin_unlock_irqrestore(&desc->lock,flags); 19.646 - 19.647 -#ifdef CONFIG_SMP 19.648 - /* Wait to make sure it's not being used on another CPU */ 19.649 - while (desc->status & IRQ_INPROGRESS) { 19.650 - barrier(); 19.651 - cpu_relax(); 19.652 - } 19.653 -#endif 19.654 - kfree(action); 19.655 - return; 19.656 - } 19.657 - printk("Trying to free free IRQ%d\n",irq); 19.658 - spin_unlock_irqrestore(&desc->lock,flags); 19.659 - return; 19.660 - } 19.661 -} 19.662 - 19.663 -/* 19.664 - * IRQ autodetection code.. 19.665 - * 19.666 - * This depends on the fact that any interrupt that 19.667 - * comes in on to an unassigned handler will get stuck 19.668 - * with "IRQ_WAITING" cleared and the interrupt 19.669 - * disabled. 19.670 - */ 19.671 - 19.672 -static spinlock_t probe_sem = SPIN_LOCK_UNLOCKED; 19.673 - 19.674 -/** 19.675 - * probe_irq_on - begin an interrupt autodetect 19.676 - * 19.677 - * Commence probing for an interrupt. The interrupts are scanned 19.678 - * and a mask of potential interrupt lines is returned. 19.679 - * 19.680 - */ 19.681 - 19.682 -unsigned long probe_irq_on(void) 19.683 -{ 19.684 - unsigned int i; 19.685 - irq_desc_t *desc; 19.686 - unsigned long val; 19.687 - unsigned long s=0, e=0; 19.688 - 19.689 - spin_lock(&probe_sem); 19.690 - /* 19.691 - * something may have generated an irq long ago and we want to 19.692 - * flush such a longstanding irq before considering it as spurious. 19.693 - */ 19.694 - for (i = NR_IRQS-1; i > 0; i--) { 19.695 - desc = irq_desc + i; 19.696 - 19.697 - spin_lock_irq(&desc->lock); 19.698 - if (!irq_desc[i].action) 19.699 - irq_desc[i].handler->startup(i); 19.700 - spin_unlock_irq(&desc->lock); 19.701 - } 19.702 - 19.703 - /* Wait for longstanding interrupts to trigger (20ms delay). */ 19.704 - rdtscl(s); 19.705 - do { 19.706 - synchronize_irq(); 19.707 - rdtscl(e); 19.708 - } while ( ((e-s)/ticks_per_usec) < 20000 ); 19.709 - 19.710 - /* 19.711 - * enable any unassigned irqs 19.712 - * (we must startup again here because if a longstanding irq 19.713 - * happened in the previous stage, it may have masked itself) 19.714 - */ 19.715 - for (i = NR_IRQS-1; i > 0; i--) { 19.716 - desc = irq_desc + i; 19.717 - 19.718 - spin_lock_irq(&desc->lock); 19.719 - if (!desc->action) { 19.720 - desc->status |= IRQ_AUTODETECT | IRQ_WAITING; 19.721 - if (desc->handler->startup(i)) 19.722 - desc->status |= IRQ_PENDING; 19.723 - } 19.724 - spin_unlock_irq(&desc->lock); 19.725 - } 19.726 - 19.727 - /* 19.728 - * Wait for spurious interrupts to trigger (100ms delay). 19.729 - */ 19.730 - rdtscl(s); 19.731 - do { 19.732 - synchronize_irq(); 19.733 - rdtscl(e); 19.734 - } while ( ((e-s)/ticks_per_usec) < 100000 ); 19.735 - 19.736 - /* 19.737 - * Now filter out any obviously spurious interrupts 19.738 - */ 19.739 - val = 0; 19.740 - for (i = 0; i < NR_IRQS; i++) { 19.741 - irq_desc_t *desc = irq_desc + i; 19.742 - unsigned int status; 19.743 - 19.744 - spin_lock_irq(&desc->lock); 19.745 - status = desc->status; 19.746 - 19.747 - if (status & IRQ_AUTODETECT) { 19.748 - /* It triggered already - consider it spurious. */ 19.749 - if (!(status & IRQ_WAITING)) { 19.750 - desc->status = status & ~IRQ_AUTODETECT; 19.751 - desc->handler->shutdown(i); 19.752 - } else 19.753 - if (i < 32) 19.754 - val |= 1 << i; 19.755 - } 19.756 - spin_unlock_irq(&desc->lock); 19.757 - } 19.758 - 19.759 - return val; 19.760 -} 19.761 - 19.762 -/* 19.763 - * Return a mask of triggered interrupts (this 19.764 - * can handle only legacy ISA interrupts). 19.765 - */ 19.766 - 19.767 -/** 19.768 - * probe_irq_mask - scan a bitmap of interrupt lines 19.769 - * @val: mask of interrupts to consider 19.770 - * 19.771 - * Scan the ISA bus interrupt lines and return a bitmap of 19.772 - * active interrupts. The interrupt probe logic state is then 19.773 - * returned to its previous value. 19.774 - * 19.775 - * Note: we need to scan all the irq's even though we will 19.776 - * only return ISA irq numbers - just so that we reset them 19.777 - * all to a known state. 19.778 - */ 19.779 -unsigned int probe_irq_mask(unsigned long val) 19.780 -{ 19.781 - int i; 19.782 - unsigned int mask; 19.783 - 19.784 - mask = 0; 19.785 - for (i = 0; i < NR_IRQS; i++) { 19.786 - irq_desc_t *desc = irq_desc + i; 19.787 - unsigned int status; 19.788 - 19.789 - spin_lock_irq(&desc->lock); 19.790 - status = desc->status; 19.791 - 19.792 - if (status & IRQ_AUTODETECT) { 19.793 - if (i < 16 && !(status & IRQ_WAITING)) 19.794 - mask |= 1 << i; 19.795 - 19.796 - desc->status = status & ~IRQ_AUTODETECT; 19.797 - desc->handler->shutdown(i); 19.798 - } 19.799 - spin_unlock_irq(&desc->lock); 19.800 - } 19.801 - spin_unlock(&probe_sem); 19.802 - 19.803 - return mask & val; 19.804 -} 19.805 - 19.806 -/* 19.807 - * Return the one interrupt that triggered (this can 19.808 - * handle any interrupt source). 19.809 - */ 19.810 - 19.811 -/** 19.812 - * probe_irq_off - end an interrupt autodetect 19.813 - * @val: mask of potential interrupts (unused) 19.814 - * 19.815 - * Scans the unused interrupt lines and returns the line which 19.816 - * appears to have triggered the interrupt. If no interrupt was 19.817 - * found then zero is returned. If more than one interrupt is 19.818 - * found then minus the first candidate is returned to indicate 19.819 - * their is doubt. 19.820 - * 19.821 - * The interrupt probe logic state is returned to its previous 19.822 - * value. 19.823 - * 19.824 - * BUGS: When used in a module (which arguably shouldnt happen) 19.825 - * nothing prevents two IRQ probe callers from overlapping. The 19.826 - * results of this are non-optimal. 19.827 - */ 19.828 - 19.829 -int probe_irq_off(unsigned long val) 19.830 -{ 19.831 - int i, irq_found, nr_irqs; 19.832 - 19.833 - nr_irqs = 0; 19.834 - irq_found = 0; 19.835 - for (i = 0; i < NR_IRQS; i++) { 19.836 - irq_desc_t *desc = irq_desc + i; 19.837 - unsigned int status; 19.838 - 19.839 - spin_lock_irq(&desc->lock); 19.840 - status = desc->status; 19.841 - 19.842 - if (status & IRQ_AUTODETECT) { 19.843 - if (!(status & IRQ_WAITING)) { 19.844 - if (!nr_irqs) 19.845 - irq_found = i; 19.846 - nr_irqs++; 19.847 - } 19.848 - desc->status = status & ~IRQ_AUTODETECT; 19.849 - desc->handler->shutdown(i); 19.850 - } 19.851 - spin_unlock_irq(&desc->lock); 19.852 - } 19.853 - spin_unlock(&probe_sem); 19.854 - 19.855 - if (nr_irqs > 1) 19.856 - irq_found = -irq_found; 19.857 - return irq_found; 19.858 -} 19.859 - 19.860 -/* this was setup_x86_irq but it seems pretty generic */ 19.861 -int setup_irq(unsigned int irq, struct irqaction * new) 19.862 -{ 19.863 - int shared = 0; 19.864 - unsigned long flags; 19.865 - struct irqaction *old, **p; 19.866 - irq_desc_t *desc = irq_desc + irq; 19.867 - 19.868 - /* 19.869 - * The following block of code has to be executed atomically 19.870 - */ 19.871 - spin_lock_irqsave(&desc->lock,flags); 19.872 - p = &desc->action; 19.873 - if ((old = *p) != NULL) { 19.874 - /* Can't share interrupts unless both agree to */ 19.875 - if (!(old->flags & new->flags & SA_SHIRQ)) { 19.876 - spin_unlock_irqrestore(&desc->lock,flags); 19.877 - return -EBUSY; 19.878 - } 19.879 - 19.880 - /* add new interrupt at end of irq queue */ 19.881 - do { 19.882 - p = &old->next; 19.883 - old = *p; 19.884 - } while (old); 19.885 - shared = 1; 19.886 - } 19.887 - 19.888 - *p = new; 19.889 - 19.890 - if (!shared) { 19.891 - desc->depth = 0; 19.892 - desc->status &= ~(IRQ_DISABLED | IRQ_AUTODETECT | IRQ_WAITING); 19.893 - desc->handler->startup(irq); 19.894 - } 19.895 - spin_unlock_irqrestore(&desc->lock,flags); 19.896 - 19.897 - return 0; 19.898 -}
20.1 --- a/xen-2.4.16/arch/i386/mm.c Mon Feb 24 16:55:07 2003 +0000 20.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 20.3 @@ -1,141 +0,0 @@ 20.4 -#include <xeno/config.h> 20.5 -#include <xeno/lib.h> 20.6 -#include <xeno/init.h> 20.7 -#include <xeno/mm.h> 20.8 -#include <asm/page.h> 20.9 -#include <asm/pgalloc.h> 20.10 -#include <asm/fixmap.h> 20.11 - 20.12 -static inline void set_pte_phys (unsigned long vaddr, 20.13 - l1_pgentry_t entry) 20.14 -{ 20.15 - l2_pgentry_t *l2ent; 20.16 - l1_pgentry_t *l1ent; 20.17 - 20.18 - l2ent = idle0_pg_table + l2_table_offset(vaddr); 20.19 - l1ent = l2_pgentry_to_l1(*l2ent) + l1_table_offset(vaddr); 20.20 - *l1ent = entry; 20.21 - 20.22 - /* It's enough to flush this one mapping. */ 20.23 - __flush_tlb_one(vaddr); 20.24 -} 20.25 - 20.26 -void __set_fixmap (enum fixed_addresses idx, 20.27 - l1_pgentry_t entry) 20.28 -{ 20.29 - unsigned long address = __fix_to_virt(idx); 20.30 - 20.31 - if (idx >= __end_of_fixed_addresses) { 20.32 - printk("Invalid __set_fixmap\n"); 20.33 - return; 20.34 - } 20.35 - set_pte_phys(address, entry); 20.36 -} 20.37 - 20.38 -static void __init fixrange_init (unsigned long start, 20.39 - unsigned long end, l2_pgentry_t *pg_base) 20.40 -{ 20.41 - l2_pgentry_t *l2e; 20.42 - int i; 20.43 - unsigned long vaddr, page; 20.44 - 20.45 - vaddr = start; 20.46 - i = l2_table_offset(vaddr); 20.47 - l2e = pg_base + i; 20.48 - 20.49 - for ( ; (i < ENTRIES_PER_L2_PAGETABLE) && (vaddr != end); l2e++, i++ ) 20.50 - { 20.51 - if ( !l2_pgentry_empty(*l2e) ) continue; 20.52 - page = (unsigned long)get_free_page(GFP_KERNEL); 20.53 - clear_page(page); 20.54 - *l2e = mk_l2_pgentry(__pa(page) | PAGE_HYPERVISOR); 20.55 - vaddr += 1 << L2_PAGETABLE_SHIFT; 20.56 - } 20.57 -} 20.58 - 20.59 -void __init paging_init(void) 20.60 -{ 20.61 - unsigned long addr; 20.62 - void *ioremap_pt; 20.63 - 20.64 - /* XXX initialised in boot.S */ 20.65 - /*if ( cpu_has_pge ) set_in_cr4(X86_CR4_PGE);*/ 20.66 - /*if ( cpu_has_pse ) set_in_cr4(X86_CR4_PSE);*/ 20.67 - /*if ( cpu_has_pae ) set_in_cr4(X86_CR4_PAE);*/ 20.68 - 20.69 - /* 20.70 - * Fixed mappings, only the page table structure has to be 20.71 - * created - mappings will be set by set_fixmap(): 20.72 - */ 20.73 - addr = FIXADDR_START & ~((1<<L2_PAGETABLE_SHIFT)-1); 20.74 - fixrange_init(addr, 0, idle0_pg_table); 20.75 - 20.76 - /* Create page table for ioremap(). */ 20.77 - ioremap_pt = (void *)get_free_page(GFP_KERNEL); 20.78 - clear_page(ioremap_pt); 20.79 - idle0_pg_table[IOREMAP_VIRT_START >> L2_PAGETABLE_SHIFT] = 20.80 - mk_l2_pgentry(__pa(ioremap_pt) | PAGE_HYPERVISOR); 20.81 - 20.82 - /* Create read-only mapping of MPT for guest-OS use. */ 20.83 - idle0_pg_table[READONLY_MPT_VIRT_START >> L2_PAGETABLE_SHIFT] = 20.84 - idle0_pg_table[RDWR_MPT_VIRT_START >> L2_PAGETABLE_SHIFT]; 20.85 - mk_l2_readonly(idle0_pg_table + 20.86 - (READONLY_MPT_VIRT_START >> L2_PAGETABLE_SHIFT)); 20.87 -} 20.88 - 20.89 -void __init zap_low_mappings (void) 20.90 -{ 20.91 - int i, j; 20.92 - for ( i = 0; i < smp_num_cpus; i++ ) 20.93 - { 20.94 - for ( j = 0; j < DOMAIN_ENTRIES_PER_L2_PAGETABLE; j++ ) 20.95 - { 20.96 - idle_pg_table[i][j] = mk_l2_pgentry(0); 20.97 - } 20.98 - } 20.99 - flush_tlb_all(); 20.100 -} 20.101 - 20.102 - 20.103 -long do_stack_and_ldt_switch( 20.104 - unsigned long ss, unsigned long esp, unsigned long ldts) 20.105 -{ 20.106 - int nr = smp_processor_id(); 20.107 - struct tss_struct *t = &init_tss[nr]; 20.108 - 20.109 - if ( (ss == __HYPERVISOR_CS) || (ss == __HYPERVISOR_DS) ) 20.110 - return -1; 20.111 - 20.112 - if ( ldts != current->mm.ldt_sel ) 20.113 - { 20.114 - unsigned long *ptabent; 20.115 - ptabent = (unsigned long *)GET_GDT_ADDRESS(current); 20.116 - /* Out of range for GDT table? */ 20.117 - if ( (ldts * 8) > GET_GDT_ENTRIES(current) ) return -1; 20.118 - ptabent += ldts * 2; /* 8 bytes per desc == 2 * unsigned long */ 20.119 - /* Not an LDT entry? (S=0b, type =0010b) */ 20.120 - if ( (*ptabent & 0x00001f00) != 0x00000200 ) return -1; 20.121 - current->mm.ldt_sel = ldts; 20.122 - __load_LDT(ldts); 20.123 - } 20.124 - 20.125 - current->thread.ss1 = ss; 20.126 - current->thread.esp1 = esp; 20.127 - t->ss1 = ss; 20.128 - t->esp1 = esp; 20.129 - 20.130 - return 0; 20.131 -} 20.132 - 20.133 - 20.134 -long do_set_gdt(unsigned long *frame_list, int entries) 20.135 -{ 20.136 - return -ENOSYS; 20.137 -} 20.138 - 20.139 - 20.140 -long do_update_descriptor( 20.141 - unsigned long pa, unsigned long word1, unsigned long word2) 20.142 -{ 20.143 - return -ENOSYS; 20.144 -}
21.1 --- a/xen-2.4.16/arch/i386/mpparse.c Mon Feb 24 16:55:07 2003 +0000 21.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 21.3 @@ -1,944 +0,0 @@ 21.4 -/* 21.5 - * Intel Multiprocessor Specificiation 1.1 and 1.4 21.6 - * compliant MP-table parsing routines. 21.7 - * 21.8 - * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> 21.9 - * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> 21.10 - * 21.11 - * Fixes 21.12 - * Erich Boleyn : MP v1.4 and additional changes. 21.13 - * Alan Cox : Added EBDA scanning 21.14 - * Ingo Molnar : various cleanups and rewrites 21.15 - * Maciej W. Rozycki : Bits for default MP configurations 21.16 - */ 21.17 - 21.18 -#include <xeno/config.h> 21.19 -#include <xeno/init.h> 21.20 -#include <xeno/lib.h> 21.21 -#include <asm/io.h> 21.22 -#include <xeno/irq.h> 21.23 -#include <xeno/smp.h> 21.24 -#include <asm/mpspec.h> 21.25 -#include <asm/pgalloc.h> 21.26 -#include <asm/smpboot.h> 21.27 -#include <xeno/kernel.h> 21.28 - 21.29 -int numnodes = 1; /* XXX Xen */ 21.30 - 21.31 -/* Have we found an MP table */ 21.32 -int smp_found_config; 21.33 - 21.34 -/* 21.35 - * Various Linux-internal data structures created from the 21.36 - * MP-table. 21.37 - */ 21.38 -int apic_version [MAX_APICS]; 21.39 -int quad_local_to_mp_bus_id [NR_CPUS/4][4]; 21.40 -int mp_current_pci_id; 21.41 -int *mp_bus_id_to_type; 21.42 -int *mp_bus_id_to_node; 21.43 -int *mp_bus_id_to_local; 21.44 -int *mp_bus_id_to_pci_bus; 21.45 -int max_mp_busses; 21.46 -int max_irq_sources; 21.47 - 21.48 -/* I/O APIC entries */ 21.49 -struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS]; 21.50 - 21.51 -/* # of MP IRQ source entries */ 21.52 -struct mpc_config_intsrc *mp_irqs; 21.53 - 21.54 -/* MP IRQ source entries */ 21.55 -int mp_irq_entries; 21.56 - 21.57 -int nr_ioapics; 21.58 - 21.59 -int pic_mode; 21.60 -unsigned long mp_lapic_addr; 21.61 - 21.62 -/* Processor that is doing the boot up */ 21.63 -unsigned int boot_cpu_physical_apicid = -1U; 21.64 -unsigned int boot_cpu_logical_apicid = -1U; 21.65 -/* Internal processor count */ 21.66 -static unsigned int num_processors; 21.67 - 21.68 -/* Bitmask of physically existing CPUs */ 21.69 -unsigned long phys_cpu_present_map; 21.70 -unsigned long logical_cpu_present_map; 21.71 - 21.72 -#ifdef CONFIG_X86_CLUSTERED_APIC 21.73 -unsigned char esr_disable = 0; 21.74 -unsigned char clustered_apic_mode = CLUSTERED_APIC_NONE; 21.75 -unsigned int apic_broadcast_id = APIC_BROADCAST_ID_APIC; 21.76 -#endif 21.77 -unsigned char raw_phys_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID }; 21.78 - 21.79 -/* 21.80 - * Intel MP BIOS table parsing routines: 21.81 - */ 21.82 - 21.83 -#ifndef CONFIG_X86_VISWS_APIC 21.84 -/* 21.85 - * Checksum an MP configuration block. 21.86 - */ 21.87 - 21.88 -static int __init mpf_checksum(unsigned char *mp, int len) 21.89 -{ 21.90 - int sum = 0; 21.91 - 21.92 - while (len--) 21.93 - sum += *mp++; 21.94 - 21.95 - return sum & 0xFF; 21.96 -} 21.97 - 21.98 -/* 21.99 - * Processor encoding in an MP configuration block 21.100 - */ 21.101 - 21.102 -static char __init *mpc_family(int family,int model) 21.103 -{ 21.104 - static char n[32]; 21.105 - static char *model_defs[]= 21.106 - { 21.107 - "80486DX","80486DX", 21.108 - "80486SX","80486DX/2 or 80487", 21.109 - "80486SL","80486SX/2", 21.110 - "Unknown","80486DX/2-WB", 21.111 - "80486DX/4","80486DX/4-WB" 21.112 - }; 21.113 - 21.114 - switch (family) { 21.115 - case 0x04: 21.116 - if (model < 10) 21.117 - return model_defs[model]; 21.118 - break; 21.119 - 21.120 - case 0x05: 21.121 - return("Pentium(tm)"); 21.122 - 21.123 - case 0x06: 21.124 - return("Pentium(tm) Pro"); 21.125 - 21.126 - case 0x0F: 21.127 - if (model == 0x00) 21.128 - return("Pentium 4(tm)"); 21.129 - if (model == 0x02) 21.130 - return("Pentium 4(tm) XEON(tm)"); 21.131 - if (model == 0x0F) 21.132 - return("Special controller"); 21.133 - } 21.134 - sprintf(n,"Unknown CPU [%d:%d]",family, model); 21.135 - return n; 21.136 -} 21.137 - 21.138 -#ifdef CONFIG_X86_IO_APIC 21.139 -// XXX Xen extern int have_acpi_tables; /* set by acpitable.c */ 21.140 -#define have_acpi_tables (0) 21.141 -#else 21.142 -#define have_acpi_tables (0) 21.143 -#endif 21.144 - 21.145 -/* 21.146 - * Have to match translation table entries to main table entries by counter 21.147 - * hence the mpc_record variable .... can't see a less disgusting way of 21.148 - * doing this .... 21.149 - */ 21.150 - 21.151 -static int mpc_record; 21.152 -static struct mpc_config_translation *translation_table[MAX_MPC_ENTRY] __initdata; 21.153 - 21.154 -void __init MP_processor_info (struct mpc_config_processor *m) 21.155 -{ 21.156 - int ver, quad, logical_apicid; 21.157 - 21.158 - if (!(m->mpc_cpuflag & CPU_ENABLED)) 21.159 - return; 21.160 - 21.161 - logical_apicid = m->mpc_apicid; 21.162 - if (clustered_apic_mode == CLUSTERED_APIC_NUMAQ) { 21.163 - quad = translation_table[mpc_record]->trans_quad; 21.164 - logical_apicid = (quad << 4) + 21.165 - (m->mpc_apicid ? m->mpc_apicid << 1 : 1); 21.166 - printk("Processor #%d %s APIC version %d (quad %d, apic %d)\n", 21.167 - m->mpc_apicid, 21.168 - mpc_family((m->mpc_cpufeature & CPU_FAMILY_MASK)>>8 , 21.169 - (m->mpc_cpufeature & CPU_MODEL_MASK)>>4), 21.170 - m->mpc_apicver, quad, logical_apicid); 21.171 - } else { 21.172 - printk("Processor #%d %s APIC version %d\n", 21.173 - m->mpc_apicid, 21.174 - mpc_family((m->mpc_cpufeature & CPU_FAMILY_MASK)>>8 , 21.175 - (m->mpc_cpufeature & CPU_MODEL_MASK)>>4), 21.176 - m->mpc_apicver); 21.177 - } 21.178 - 21.179 - if (m->mpc_featureflag&(1<<0)) 21.180 - Dprintk(" Floating point unit present.\n"); 21.181 - if (m->mpc_featureflag&(1<<7)) 21.182 - Dprintk(" Machine Exception supported.\n"); 21.183 - if (m->mpc_featureflag&(1<<8)) 21.184 - Dprintk(" 64 bit compare & exchange supported.\n"); 21.185 - if (m->mpc_featureflag&(1<<9)) 21.186 - Dprintk(" Internal APIC present.\n"); 21.187 - if (m->mpc_featureflag&(1<<11)) 21.188 - Dprintk(" SEP present.\n"); 21.189 - if (m->mpc_featureflag&(1<<12)) 21.190 - Dprintk(" MTRR present.\n"); 21.191 - if (m->mpc_featureflag&(1<<13)) 21.192 - Dprintk(" PGE present.\n"); 21.193 - if (m->mpc_featureflag&(1<<14)) 21.194 - Dprintk(" MCA present.\n"); 21.195 - if (m->mpc_featureflag&(1<<15)) 21.196 - Dprintk(" CMOV present.\n"); 21.197 - if (m->mpc_featureflag&(1<<16)) 21.198 - Dprintk(" PAT present.\n"); 21.199 - if (m->mpc_featureflag&(1<<17)) 21.200 - Dprintk(" PSE present.\n"); 21.201 - if (m->mpc_featureflag&(1<<18)) 21.202 - Dprintk(" PSN present.\n"); 21.203 - if (m->mpc_featureflag&(1<<19)) 21.204 - Dprintk(" Cache Line Flush Instruction present.\n"); 21.205 - /* 20 Reserved */ 21.206 - if (m->mpc_featureflag&(1<<21)) 21.207 - Dprintk(" Debug Trace and EMON Store present.\n"); 21.208 - if (m->mpc_featureflag&(1<<22)) 21.209 - Dprintk(" ACPI Thermal Throttle Registers present.\n"); 21.210 - if (m->mpc_featureflag&(1<<23)) 21.211 - Dprintk(" MMX present.\n"); 21.212 - if (m->mpc_featureflag&(1<<24)) 21.213 - Dprintk(" FXSR present.\n"); 21.214 - if (m->mpc_featureflag&(1<<25)) 21.215 - Dprintk(" XMM present.\n"); 21.216 - if (m->mpc_featureflag&(1<<26)) 21.217 - Dprintk(" Willamette New Instructions present.\n"); 21.218 - if (m->mpc_featureflag&(1<<27)) 21.219 - Dprintk(" Self Snoop present.\n"); 21.220 - if (m->mpc_featureflag&(1<<28)) 21.221 - Dprintk(" HT present.\n"); 21.222 - if (m->mpc_featureflag&(1<<29)) 21.223 - Dprintk(" Thermal Monitor present.\n"); 21.224 - /* 30, 31 Reserved */ 21.225 - 21.226 - 21.227 - if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) { 21.228 - Dprintk(" Bootup CPU\n"); 21.229 - boot_cpu_physical_apicid = m->mpc_apicid; 21.230 - boot_cpu_logical_apicid = logical_apicid; 21.231 - } 21.232 - 21.233 - num_processors++; 21.234 - 21.235 - if (m->mpc_apicid > MAX_APICS) { 21.236 - printk("Processor #%d INVALID. (Max ID: %d).\n", 21.237 - m->mpc_apicid, MAX_APICS); 21.238 - --num_processors; 21.239 - return; 21.240 - } 21.241 - ver = m->mpc_apicver; 21.242 - 21.243 - logical_cpu_present_map |= 1 << (num_processors-1); 21.244 - phys_cpu_present_map |= apicid_to_phys_cpu_present(m->mpc_apicid); 21.245 - 21.246 - /* 21.247 - * Validate version 21.248 - */ 21.249 - if (ver == 0x0) { 21.250 - printk("BIOS bug, APIC version is 0 for CPU#%d! fixing up to 0x10. (tell your hw vendor)\n", m->mpc_apicid); 21.251 - ver = 0x10; 21.252 - } 21.253 - apic_version[m->mpc_apicid] = ver; 21.254 - raw_phys_apicid[num_processors - 1] = m->mpc_apicid; 21.255 -} 21.256 - 21.257 -static void __init MP_bus_info (struct mpc_config_bus *m) 21.258 -{ 21.259 - char str[7]; 21.260 - int quad; 21.261 - 21.262 - memcpy(str, m->mpc_bustype, 6); 21.263 - str[6] = 0; 21.264 - 21.265 - if (clustered_apic_mode == CLUSTERED_APIC_NUMAQ) { 21.266 - quad = translation_table[mpc_record]->trans_quad; 21.267 - mp_bus_id_to_node[m->mpc_busid] = quad; 21.268 - mp_bus_id_to_local[m->mpc_busid] = translation_table[mpc_record]->trans_local; 21.269 - quad_local_to_mp_bus_id[quad][translation_table[mpc_record]->trans_local] = m->mpc_busid; 21.270 - printk("Bus #%d is %s (node %d)\n", m->mpc_busid, str, quad); 21.271 - } else { 21.272 - Dprintk("Bus #%d is %s\n", m->mpc_busid, str); 21.273 - } 21.274 - 21.275 - if (strncmp(str, BUSTYPE_ISA, sizeof(BUSTYPE_ISA)-1) == 0) { 21.276 - mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA; 21.277 - } else if (strncmp(str, BUSTYPE_EISA, sizeof(BUSTYPE_EISA)-1) == 0) { 21.278 - mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA; 21.279 - } else if (strncmp(str, BUSTYPE_PCI, sizeof(BUSTYPE_PCI)-1) == 0) { 21.280 - mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI; 21.281 - mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id; 21.282 - mp_current_pci_id++; 21.283 - } else if (strncmp(str, BUSTYPE_MCA, sizeof(BUSTYPE_MCA)-1) == 0) { 21.284 - mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA; 21.285 - } else { 21.286 - printk("Unknown bustype %s - ignoring\n", str); 21.287 - } 21.288 -} 21.289 - 21.290 -static void __init MP_ioapic_info (struct mpc_config_ioapic *m) 21.291 -{ 21.292 - if (!(m->mpc_flags & MPC_APIC_USABLE)) 21.293 - return; 21.294 - 21.295 - printk("I/O APIC #%d Version %d at 0x%lX.\n", 21.296 - m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr); 21.297 - if (nr_ioapics >= MAX_IO_APICS) { 21.298 - printk("Max # of I/O APICs (%d) exceeded (found %d).\n", 21.299 - MAX_IO_APICS, nr_ioapics); 21.300 - panic("Recompile kernel with bigger MAX_IO_APICS!.\n"); 21.301 - } 21.302 - if (!m->mpc_apicaddr) { 21.303 - printk(KERN_ERR "WARNING: bogus zero I/O APIC address" 21.304 - " found in MP table, skipping!\n"); 21.305 - return; 21.306 - } 21.307 - mp_ioapics[nr_ioapics] = *m; 21.308 - nr_ioapics++; 21.309 -} 21.310 - 21.311 -static void __init MP_intsrc_info (struct mpc_config_intsrc *m) 21.312 -{ 21.313 - mp_irqs [mp_irq_entries] = *m; 21.314 - Dprintk("Int: type %d, pol %d, trig %d, bus %d," 21.315 - " IRQ %02x, APIC ID %x, APIC INT %02x\n", 21.316 - m->mpc_irqtype, m->mpc_irqflag & 3, 21.317 - (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus, 21.318 - m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq); 21.319 - if (++mp_irq_entries == max_irq_sources) 21.320 - panic("Max # of irq sources exceeded!!\n"); 21.321 -} 21.322 - 21.323 -static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m) 21.324 -{ 21.325 - Dprintk("Lint: type %d, pol %d, trig %d, bus %d," 21.326 - " IRQ %02x, APIC ID %x, APIC LINT %02x\n", 21.327 - m->mpc_irqtype, m->mpc_irqflag & 3, 21.328 - (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid, 21.329 - m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint); 21.330 - /* 21.331 - * Well it seems all SMP boards in existence 21.332 - * use ExtINT/LVT1 == LINT0 and 21.333 - * NMI/LVT2 == LINT1 - the following check 21.334 - * will show us if this assumptions is false. 21.335 - * Until then we do not have to add baggage. 21.336 - */ 21.337 - if ((m->mpc_irqtype == mp_ExtINT) && 21.338 - (m->mpc_destapiclint != 0)) 21.339 - BUG(); 21.340 - if ((m->mpc_irqtype == mp_NMI) && 21.341 - (m->mpc_destapiclint != 1)) 21.342 - BUG(); 21.343 -} 21.344 - 21.345 -static void __init MP_translation_info (struct mpc_config_translation *m) 21.346 -{ 21.347 - printk("Translation: record %d, type %d, quad %d, global %d, local %d\n", mpc_record, m->trans_type, m->trans_quad, m->trans_global, m->trans_local); 21.348 - 21.349 - if (mpc_record >= MAX_MPC_ENTRY) 21.350 - printk("MAX_MPC_ENTRY exceeded!\n"); 21.351 - else 21.352 - translation_table[mpc_record] = m; /* stash this for later */ 21.353 - if (m->trans_quad+1 > numnodes) 21.354 - numnodes = m->trans_quad+1; 21.355 -} 21.356 - 21.357 -/* 21.358 - * Read/parse the MPC oem tables 21.359 - */ 21.360 - 21.361 -static void __init smp_read_mpc_oem(struct mp_config_oemtable *oemtable, \ 21.362 - unsigned short oemsize) 21.363 -{ 21.364 - int count = sizeof (*oemtable); /* the header size */ 21.365 - unsigned char *oemptr = ((unsigned char *)oemtable)+count; 21.366 - 21.367 - printk("Found an OEM MPC table at %8p - parsing it ... \n", oemtable); 21.368 - if (memcmp(oemtable->oem_signature,MPC_OEM_SIGNATURE,4)) 21.369 - { 21.370 - printk("SMP mpc oemtable: bad signature [%c%c%c%c]!\n", 21.371 - oemtable->oem_signature[0], 21.372 - oemtable->oem_signature[1], 21.373 - oemtable->oem_signature[2], 21.374 - oemtable->oem_signature[3]); 21.375 - return; 21.376 - } 21.377 - if (mpf_checksum((unsigned char *)oemtable,oemtable->oem_length)) 21.378 - { 21.379 - printk("SMP oem mptable: checksum error!\n"); 21.380 - return; 21.381 - } 21.382 - while (count < oemtable->oem_length) { 21.383 - switch (*oemptr) { 21.384 - case MP_TRANSLATION: 21.385 - { 21.386 - struct mpc_config_translation *m= 21.387 - (struct mpc_config_translation *)oemptr; 21.388 - MP_translation_info(m); 21.389 - oemptr += sizeof(*m); 21.390 - count += sizeof(*m); 21.391 - ++mpc_record; 21.392 - break; 21.393 - } 21.394 - default: 21.395 - { 21.396 - printk("Unrecognised OEM table entry type! - %d\n", (int) *oemptr); 21.397 - return; 21.398 - } 21.399 - } 21.400 - } 21.401 -} 21.402 - 21.403 -/* 21.404 - * Read/parse the MPC 21.405 - */ 21.406 - 21.407 -static int __init smp_read_mpc(struct mp_config_table *mpc) 21.408 -{ 21.409 - char oem[16], prod[14]; 21.410 - int count=sizeof(*mpc); 21.411 - unsigned char *mpt=((unsigned char *)mpc)+count; 21.412 - int num_bus = 0; 21.413 - int num_irq = 0; 21.414 - unsigned char *bus_data; 21.415 - 21.416 - if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) { 21.417 - panic("SMP mptable: bad signature [%c%c%c%c]!\n", 21.418 - mpc->mpc_signature[0], 21.419 - mpc->mpc_signature[1], 21.420 - mpc->mpc_signature[2], 21.421 - mpc->mpc_signature[3]); 21.422 - return 0; 21.423 - } 21.424 - if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) { 21.425 - panic("SMP mptable: checksum error!\n"); 21.426 - return 0; 21.427 - } 21.428 - if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) { 21.429 - printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n", 21.430 - mpc->mpc_spec); 21.431 - return 0; 21.432 - } 21.433 - if (!mpc->mpc_lapic) { 21.434 - printk(KERN_ERR "SMP mptable: null local APIC address!\n"); 21.435 - return 0; 21.436 - } 21.437 - memcpy(oem,mpc->mpc_oem,8); 21.438 - oem[8]=0; 21.439 - printk("OEM ID: %s ",oem); 21.440 - 21.441 - memcpy(prod,mpc->mpc_productid,12); 21.442 - prod[12]=0; 21.443 - printk("Product ID: %s ",prod); 21.444 - 21.445 - detect_clustered_apic(oem, prod); 21.446 - 21.447 - printk("APIC at: 0x%lX\n",mpc->mpc_lapic); 21.448 - 21.449 - /* save the local APIC address, it might be non-default, 21.450 - * but only if we're not using the ACPI tables 21.451 - */ 21.452 - if (!have_acpi_tables) 21.453 - mp_lapic_addr = mpc->mpc_lapic; 21.454 - 21.455 - if ((clustered_apic_mode == CLUSTERED_APIC_NUMAQ) && mpc->mpc_oemptr) { 21.456 - /* We need to process the oem mpc tables to tell us which quad things are in ... */ 21.457 - mpc_record = 0; 21.458 - smp_read_mpc_oem((struct mp_config_oemtable *) mpc->mpc_oemptr, mpc->mpc_oemsize); 21.459 - mpc_record = 0; 21.460 - } 21.461 - 21.462 - /* Pre-scan to determine the number of bus and 21.463 - * interrupts records we have 21.464 - */ 21.465 - while (count < mpc->mpc_length) { 21.466 - switch (*mpt) { 21.467 - case MP_PROCESSOR: 21.468 - mpt += sizeof(struct mpc_config_processor); 21.469 - count += sizeof(struct mpc_config_processor); 21.470 - break; 21.471 - case MP_BUS: 21.472 - ++num_bus; 21.473 - mpt += sizeof(struct mpc_config_bus); 21.474 - count += sizeof(struct mpc_config_bus); 21.475 - break; 21.476 - case MP_INTSRC: 21.477 - ++num_irq; 21.478 - mpt += sizeof(struct mpc_config_intsrc); 21.479 - count += sizeof(struct mpc_config_intsrc); 21.480 - break; 21.481 - case MP_IOAPIC: 21.482 - mpt += sizeof(struct mpc_config_ioapic); 21.483 - count += sizeof(struct mpc_config_ioapic); 21.484 - break; 21.485 - case MP_LINTSRC: 21.486 - mpt += sizeof(struct mpc_config_lintsrc); 21.487 - count += sizeof(struct mpc_config_lintsrc); 21.488 - break; 21.489 - default: 21.490 - count = mpc->mpc_length; 21.491 - break; 21.492 - } 21.493 - } 21.494 - /* 21.495 - * Paranoia: Allocate one extra of both the number of busses and number 21.496 - * of irqs, and make sure that we have at least 4 interrupts per PCI 21.497 - * slot. But some machines do not report very many busses, so we need 21.498 - * to fall back on the older defaults. 21.499 - */ 21.500 - ++num_bus; 21.501 - max_mp_busses = max(num_bus, MAX_MP_BUSSES); 21.502 - if (num_irq < (4 * max_mp_busses)) 21.503 - num_irq = 4 * num_bus; /* 4 intr/PCI slot */ 21.504 - ++num_irq; 21.505 - max_irq_sources = max(num_irq, MAX_IRQ_SOURCES); 21.506 - 21.507 - count = (max_mp_busses * sizeof(int)) * 4; 21.508 - count += (max_irq_sources * sizeof(struct mpc_config_intsrc)); 21.509 - 21.510 - { 21.511 - //bus_data = alloc_bootmem(count); XXX Xen 21.512 - static char arr[4096]; 21.513 - if(count > 4096) BUG(); 21.514 - bus_data = (void*)arr; 21.515 - 21.516 - } 21.517 - if (!bus_data) { 21.518 - printk(KERN_ERR "SMP mptable: out of memory!\n"); 21.519 - return 0; 21.520 - } 21.521 - mp_bus_id_to_type = (int *)&bus_data[0]; 21.522 - mp_bus_id_to_node = (int *)&bus_data[(max_mp_busses * sizeof(int))]; 21.523 - mp_bus_id_to_local = (int *)&bus_data[(max_mp_busses * sizeof(int)) * 2]; 21.524 - mp_bus_id_to_pci_bus = (int *)&bus_data[(max_mp_busses * sizeof(int)) * 3]; 21.525 - mp_irqs = (struct mpc_config_intsrc *)&bus_data[(max_mp_busses * sizeof(int)) * 4]; 21.526 - memset(mp_bus_id_to_pci_bus, -1, max_mp_busses); 21.527 - 21.528 - /* 21.529 - * Now process the configuration blocks. 21.530 - */ 21.531 - count = sizeof(*mpc); 21.532 - mpt = ((unsigned char *)mpc)+count; 21.533 - while (count < mpc->mpc_length) { 21.534 - switch(*mpt) { 21.535 - case MP_PROCESSOR: 21.536 - { 21.537 - struct mpc_config_processor *m= 21.538 - (struct mpc_config_processor *)mpt; 21.539 - 21.540 - /* ACPI may already have provided this one for us */ 21.541 - if (!have_acpi_tables) 21.542 - MP_processor_info(m); 21.543 - mpt += sizeof(*m); 21.544 - count += sizeof(*m); 21.545 - break; 21.546 - } 21.547 - case MP_BUS: 21.548 - { 21.549 - struct mpc_config_bus *m= 21.550 - (struct mpc_config_bus *)mpt; 21.551 - MP_bus_info(m); 21.552 - mpt += sizeof(*m); 21.553 - count += sizeof(*m); 21.554 - break; 21.555 - } 21.556 - case MP_IOAPIC: 21.557 - { 21.558 - struct mpc_config_ioapic *m= 21.559 - (struct mpc_config_ioapic *)mpt; 21.560 - MP_ioapic_info(m); 21.561 - mpt+=sizeof(*m); 21.562 - count+=sizeof(*m); 21.563 - break; 21.564 - } 21.565 - case MP_INTSRC: 21.566 - { 21.567 - struct mpc_config_intsrc *m= 21.568 - (struct mpc_config_intsrc *)mpt; 21.569 - 21.570 - MP_intsrc_info(m); 21.571 - mpt+=sizeof(*m); 21.572 - count+=sizeof(*m); 21.573 - break; 21.574 - } 21.575 - case MP_LINTSRC: 21.576 - { 21.577 - struct mpc_config_lintsrc *m= 21.578 - (struct mpc_config_lintsrc *)mpt; 21.579 - MP_lintsrc_info(m); 21.580 - mpt+=sizeof(*m); 21.581 - count+=sizeof(*m); 21.582 - break; 21.583 - } 21.584 - default: 21.585 - { 21.586 - count = mpc->mpc_length; 21.587 - break; 21.588 - } 21.589 - } 21.590 - ++mpc_record; 21.591 - } 21.592 - 21.593 - if (clustered_apic_mode){ 21.594 - phys_cpu_present_map = logical_cpu_present_map; 21.595 - } 21.596 - 21.597 - 21.598 - printk("Enabling APIC mode: "); 21.599 - if(clustered_apic_mode == CLUSTERED_APIC_NUMAQ) 21.600 - printk("Clustered Logical. "); 21.601 - else if(clustered_apic_mode == CLUSTERED_APIC_XAPIC) 21.602 - printk("Physical. "); 21.603 - else 21.604 - printk("Flat. "); 21.605 - printk("Using %d I/O APICs\n",nr_ioapics); 21.606 - 21.607 - if (!num_processors) 21.608 - printk(KERN_ERR "SMP mptable: no processors registered!\n"); 21.609 - return num_processors; 21.610 -} 21.611 - 21.612 -static int __init ELCR_trigger(unsigned int irq) 21.613 -{ 21.614 - unsigned int port; 21.615 - 21.616 - port = 0x4d0 + (irq >> 3); 21.617 - return (inb(port) >> (irq & 7)) & 1; 21.618 -} 21.619 - 21.620 -static void __init construct_default_ioirq_mptable(int mpc_default_type) 21.621 -{ 21.622 - struct mpc_config_intsrc intsrc; 21.623 - int i; 21.624 - int ELCR_fallback = 0; 21.625 - 21.626 - intsrc.mpc_type = MP_INTSRC; 21.627 - intsrc.mpc_irqflag = 0; /* conforming */ 21.628 - intsrc.mpc_srcbus = 0; 21.629 - intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid; 21.630 - 21.631 - intsrc.mpc_irqtype = mp_INT; 21.632 - 21.633 - /* 21.634 - * If true, we have an ISA/PCI system with no IRQ entries 21.635 - * in the MP table. To prevent the PCI interrupts from being set up 21.636 - * incorrectly, we try to use the ELCR. The sanity check to see if 21.637 - * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can 21.638 - * never be level sensitive, so we simply see if the ELCR agrees. 21.639 - * If it does, we assume it's valid. 21.640 - */ 21.641 - if (mpc_default_type == 5) { 21.642 - printk("ISA/PCI bus type with no IRQ information... falling back to ELCR\n"); 21.643 - 21.644 - if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13)) 21.645 - printk("ELCR contains invalid data... not using ELCR\n"); 21.646 - else { 21.647 - printk("Using ELCR to identify PCI interrupts\n"); 21.648 - ELCR_fallback = 1; 21.649 - } 21.650 - } 21.651 - 21.652 - for (i = 0; i < 16; i++) { 21.653 - switch (mpc_default_type) { 21.654 - case 2: 21.655 - if (i == 0 || i == 13) 21.656 - continue; /* IRQ0 & IRQ13 not connected */ 21.657 - /* fall through */ 21.658 - default: 21.659 - if (i == 2) 21.660 - continue; /* IRQ2 is never connected */ 21.661 - } 21.662 - 21.663 - if (ELCR_fallback) { 21.664 - /* 21.665 - * If the ELCR indicates a level-sensitive interrupt, we 21.666 - * copy that information over to the MP table in the 21.667 - * irqflag field (level sensitive, active high polarity). 21.668 - */ 21.669 - if (ELCR_trigger(i)) 21.670 - intsrc.mpc_irqflag = 13; 21.671 - else 21.672 - intsrc.mpc_irqflag = 0; 21.673 - } 21.674 - 21.675 - intsrc.mpc_srcbusirq = i; 21.676 - intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */ 21.677 - MP_intsrc_info(&intsrc); 21.678 - } 21.679 - 21.680 - intsrc.mpc_irqtype = mp_ExtINT; 21.681 - intsrc.mpc_srcbusirq = 0; 21.682 - intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */ 21.683 - MP_intsrc_info(&intsrc); 21.684 -} 21.685 - 21.686 -static inline void __init construct_default_ISA_mptable(int mpc_default_type) 21.687 -{ 21.688 - struct mpc_config_processor processor; 21.689 - struct mpc_config_bus bus; 21.690 - struct mpc_config_ioapic ioapic; 21.691 - struct mpc_config_lintsrc lintsrc; 21.692 - int linttypes[2] = { mp_ExtINT, mp_NMI }; 21.693 - int i; 21.694 - 21.695 - /* 21.696 - * local APIC has default address 21.697 - */ 21.698 - mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 21.699 - 21.700 - /* 21.701 - * 2 CPUs, numbered 0 & 1. 21.702 - */ 21.703 - processor.mpc_type = MP_PROCESSOR; 21.704 - /* Either an integrated APIC or a discrete 82489DX. */ 21.705 - processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01; 21.706 - processor.mpc_cpuflag = CPU_ENABLED; 21.707 - processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) | 21.708 - (boot_cpu_data.x86_model << 4) | 21.709 - boot_cpu_data.x86_mask; 21.710 - processor.mpc_featureflag = boot_cpu_data.x86_capability[0]; 21.711 - processor.mpc_reserved[0] = 0; 21.712 - processor.mpc_reserved[1] = 0; 21.713 - for (i = 0; i < 2; i++) { 21.714 - processor.mpc_apicid = i; 21.715 - MP_processor_info(&processor); 21.716 - } 21.717 - 21.718 - bus.mpc_type = MP_BUS; 21.719 - bus.mpc_busid = 0; 21.720 - switch (mpc_default_type) { 21.721 - default: 21.722 - printk("???\nUnknown standard configuration %d\n", 21.723 - mpc_default_type); 21.724 - /* fall through */ 21.725 - case 1: 21.726 - case 5: 21.727 - memcpy(bus.mpc_bustype, "ISA ", 6); 21.728 - break; 21.729 - case 2: 21.730 - case 6: 21.731 - case 3: 21.732 - memcpy(bus.mpc_bustype, "EISA ", 6); 21.733 - break; 21.734 - case 4: 21.735 - case 7: 21.736 - memcpy(bus.mpc_bustype, "MCA ", 6); 21.737 - } 21.738 - MP_bus_info(&bus); 21.739 - if (mpc_default_type > 4) { 21.740 - bus.mpc_busid = 1; 21.741 - memcpy(bus.mpc_bustype, "PCI ", 6); 21.742 - MP_bus_info(&bus); 21.743 - } 21.744 - 21.745 - ioapic.mpc_type = MP_IOAPIC; 21.746 - ioapic.mpc_apicid = 2; 21.747 - ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01; 21.748 - ioapic.mpc_flags = MPC_APIC_USABLE; 21.749 - ioapic.mpc_apicaddr = 0xFEC00000; 21.750 - MP_ioapic_info(&ioapic); 21.751 - 21.752 - /* 21.753 - * We set up most of the low 16 IO-APIC pins according to MPS rules. 21.754 - */ 21.755 - construct_default_ioirq_mptable(mpc_default_type); 21.756 - 21.757 - lintsrc.mpc_type = MP_LINTSRC; 21.758 - lintsrc.mpc_irqflag = 0; /* conforming */ 21.759 - lintsrc.mpc_srcbusid = 0; 21.760 - lintsrc.mpc_srcbusirq = 0; 21.761 - lintsrc.mpc_destapic = MP_APIC_ALL; 21.762 - for (i = 0; i < 2; i++) { 21.763 - lintsrc.mpc_irqtype = linttypes[i]; 21.764 - lintsrc.mpc_destapiclint = i; 21.765 - MP_lintsrc_info(&lintsrc); 21.766 - } 21.767 -} 21.768 - 21.769 -static struct intel_mp_floating *mpf_found; 21.770 -extern void config_acpi_tables(void); 21.771 - 21.772 -/* 21.773 - * Scan the memory blocks for an SMP configuration block. 21.774 - */ 21.775 -void __init get_smp_config (void) 21.776 -{ 21.777 - struct intel_mp_floating *mpf = mpf_found; 21.778 - 21.779 -#ifdef CONFIG_X86_IO_APIC 21.780 - /* 21.781 - * Check if the ACPI tables are provided. Use them only to get 21.782 - * the processor information, mainly because it provides 21.783 - * the info on the logical processor(s), rather than the physical 21.784 - * processor(s) that are provided by the MPS. We attempt to 21.785 - * check only if the user provided a commandline override 21.786 - */ 21.787 - config_acpi_tables(); 21.788 -#endif 21.789 - 21.790 - printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification); 21.791 - if (mpf->mpf_feature2 & (1<<7)) { 21.792 - printk(" IMCR and PIC compatibility mode.\n"); 21.793 - pic_mode = 1; 21.794 - } else { 21.795 - printk(" Virtual Wire compatibility mode.\n"); 21.796 - pic_mode = 0; 21.797 - } 21.798 - 21.799 - /* 21.800 - * Now see if we need to read further. 21.801 - */ 21.802 - if (mpf->mpf_feature1 != 0) { 21.803 - 21.804 - printk("Default MP configuration #%d\n", mpf->mpf_feature1); 21.805 - construct_default_ISA_mptable(mpf->mpf_feature1); 21.806 - 21.807 - } else if (mpf->mpf_physptr) { 21.808 - 21.809 - /* 21.810 - * Read the physical hardware table. Anything here will 21.811 - * override the defaults. 21.812 - */ 21.813 - if (!smp_read_mpc((void *)mpf->mpf_physptr)) { 21.814 - smp_found_config = 0; 21.815 - printk(KERN_ERR "BIOS bug, MP table errors detected!...\n"); 21.816 - printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n"); 21.817 - return; 21.818 - } 21.819 - /* 21.820 - * If there are no explicit MP IRQ entries, then we are 21.821 - * broken. We set up most of the low 16 IO-APIC pins to 21.822 - * ISA defaults and hope it will work. 21.823 - */ 21.824 - if (!mp_irq_entries) { 21.825 - struct mpc_config_bus bus; 21.826 - 21.827 - printk("BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n"); 21.828 - 21.829 - bus.mpc_type = MP_BUS; 21.830 - bus.mpc_busid = 0; 21.831 - memcpy(bus.mpc_bustype, "ISA ", 6); 21.832 - MP_bus_info(&bus); 21.833 - 21.834 - construct_default_ioirq_mptable(0); 21.835 - } 21.836 - 21.837 - } else 21.838 - BUG(); 21.839 - 21.840 - printk("Processors: %d\n", num_processors); 21.841 - /* 21.842 - * Only use the first configuration found. 21.843 - */ 21.844 -} 21.845 - 21.846 -static int __init smp_scan_config (unsigned long base, unsigned long length) 21.847 -{ 21.848 - unsigned long *bp = phys_to_virt(base); 21.849 - struct intel_mp_floating *mpf; 21.850 - 21.851 - Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length); 21.852 - if (sizeof(*mpf) != 16) 21.853 - printk("Error: MPF size\n"); 21.854 - 21.855 - while (length > 0) { 21.856 - mpf = (struct intel_mp_floating *)bp; 21.857 - if ((*bp == SMP_MAGIC_IDENT) && 21.858 - (mpf->mpf_length == 1) && 21.859 - !mpf_checksum((unsigned char *)bp, 16) && 21.860 - ((mpf->mpf_specification == 1) 21.861 - || (mpf->mpf_specification == 4)) ) { 21.862 - 21.863 - smp_found_config = 1; 21.864 - printk("found SMP MP-table at %08lx\n", 21.865 - virt_to_phys(mpf)); 21.866 - reserve_bootmem(virt_to_phys(mpf), PAGE_SIZE); 21.867 - if (mpf->mpf_physptr) 21.868 - reserve_bootmem(mpf->mpf_physptr, PAGE_SIZE); 21.869 - mpf_found = mpf; 21.870 - return 1; 21.871 - } 21.872 - bp += 4; 21.873 - length -= 16; 21.874 - } 21.875 - return 0; 21.876 -} 21.877 - 21.878 -void __init find_intel_smp (void) 21.879 -{ 21.880 - unsigned int address; 21.881 - 21.882 - /* 21.883 - * FIXME: Linux assumes you have 640K of base ram.. 21.884 - * this continues the error... 21.885 - * 21.886 - * 1) Scan the bottom 1K for a signature 21.887 - * 2) Scan the top 1K of base RAM 21.888 - * 3) Scan the 64K of bios 21.889 - */ 21.890 - if (smp_scan_config(0x0,0x400) || 21.891 - smp_scan_config(639*0x400,0x400) || 21.892 - smp_scan_config(0xF0000,0x10000)) 21.893 - return; 21.894 - /* 21.895 - * If it is an SMP machine we should know now, unless the 21.896 - * configuration is in an EISA/MCA bus machine with an 21.897 - * extended bios data area. 21.898 - * 21.899 - * there is a real-mode segmented pointer pointing to the 21.900 - * 4K EBDA area at 0x40E, calculate and scan it here. 21.901 - * 21.902 - * NOTE! There were Linux loaders that will corrupt the EBDA 21.903 - * area, and as such this kind of SMP config may be less 21.904 - * trustworthy, simply because the SMP table may have been 21.905 - * stomped on during early boot. Thankfully the bootloaders 21.906 - * now honour the EBDA. 21.907 - */ 21.908 - 21.909 - address = *(unsigned short *)phys_to_virt(0x40E); 21.910 - address <<= 4; 21.911 - smp_scan_config(address, 0x1000); 21.912 -} 21.913 - 21.914 -#else 21.915 - 21.916 -/* 21.917 - * The Visual Workstation is Intel MP compliant in the hardware 21.918 - * sense, but it doesn't have a BIOS(-configuration table). 21.919 - * No problem for Linux. 21.920 - */ 21.921 -void __init find_visws_smp(void) 21.922 -{ 21.923 - smp_found_config = 1; 21.924 - 21.925 - phys_cpu_present_map |= 2; /* or in id 1 */ 21.926 - apic_version[1] |= 0x10; /* integrated APIC */ 21.927 - apic_version[0] |= 0x10; 21.928 - 21.929 - mp_lapic_addr = APIC_DEFAULT_PHYS_BASE; 21.930 -} 21.931 - 21.932 -#endif 21.933 - 21.934 -/* 21.935 - * - Intel MP Configuration Table 21.936 - * - or SGI Visual Workstation configuration 21.937 - */ 21.938 -void __init find_smp_config (void) 21.939 -{ 21.940 -#ifdef CONFIG_X86_LOCAL_APIC 21.941 - find_intel_smp(); 21.942 -#endif 21.943 -#ifdef CONFIG_VISWS 21.944 - find_visws_smp(); 21.945 -#endif 21.946 -} 21.947 -
22.1 --- a/xen-2.4.16/arch/i386/pci-dma.c Mon Feb 24 16:55:07 2003 +0000 22.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 22.3 @@ -1,37 +0,0 @@ 22.4 -/* 22.5 - * Dynamic DMA mapping support. 22.6 - * 22.7 - * On i386 there is no hardware dynamic DMA address translation, 22.8 - * so consistent alloc/free are merely page allocation/freeing. 22.9 - * The rest of the dynamic DMA mapping interface is implemented 22.10 - * in asm/pci.h. 22.11 - */ 22.12 - 22.13 -#include <linux/types.h> 22.14 -#include <linux/mm.h> 22.15 -#include <linux/lib.h> 22.16 -#include <linux/pci.h> 22.17 -#include <asm/io.h> 22.18 - 22.19 -void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size, 22.20 - dma_addr_t *dma_handle) 22.21 -{ 22.22 - void *ret; 22.23 - int gfp = GFP_ATOMIC; 22.24 - 22.25 - if (hwdev == NULL || ((u32)hwdev->dma_mask < 0xffffffff)) 22.26 - gfp |= GFP_DMA; 22.27 - ret = (void *)__get_free_pages(gfp, get_order(size)); 22.28 - 22.29 - if (ret != NULL) { 22.30 - memset(ret, 0, size); 22.31 - *dma_handle = virt_to_bus(ret); 22.32 - } 22.33 - return ret; 22.34 -} 22.35 - 22.36 -void pci_free_consistent(struct pci_dev *hwdev, size_t size, 22.37 - void *vaddr, dma_addr_t dma_handle) 22.38 -{ 22.39 - free_pages((unsigned long)vaddr, get_order(size)); 22.40 -}
23.1 --- a/xen-2.4.16/arch/i386/pci-i386.c Mon Feb 24 16:55:07 2003 +0000 23.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 23.3 @@ -1,391 +0,0 @@ 23.4 -/* 23.5 - * Low-Level PCI Access for i386 machines 23.6 - * 23.7 - * Copyright 1993, 1994 Drew Eckhardt 23.8 - * Visionary Computing 23.9 - * (Unix and Linux consulting and custom programming) 23.10 - * Drew@Colorado.EDU 23.11 - * +1 (303) 786-7975 23.12 - * 23.13 - * Drew's work was sponsored by: 23.14 - * iX Multiuser Multitasking Magazine 23.15 - * Hannover, Germany 23.16 - * hm@ix.de 23.17 - * 23.18 - * Copyright 1997--2000 Martin Mares <mj@ucw.cz> 23.19 - * 23.20 - * For more information, please consult the following manuals (look at 23.21 - * http://www.pcisig.com/ for how to get them): 23.22 - * 23.23 - * PCI BIOS Specification 23.24 - * PCI Local Bus Specification 23.25 - * PCI to PCI Bridge Specification 23.26 - * PCI System Design Guide 23.27 - * 23.28 - * 23.29 - * CHANGELOG : 23.30 - * Jun 17, 1994 : Modified to accommodate the broken pre-PCI BIOS SPECIFICATION 23.31 - * Revision 2.0 present on <thys@dennis.ee.up.ac.za>'s ASUS mainboard. 23.32 - * 23.33 - * Jan 5, 1995 : Modified to probe PCI hardware at boot time by Frederic 23.34 - * Potter, potter@cao-vlsi.ibp.fr 23.35 - * 23.36 - * Jan 10, 1995 : Modified to store the information about configured pci 23.37 - * devices into a list, which can be accessed via /proc/pci by 23.38 - * Curtis Varner, cvarner@cs.ucr.edu 23.39 - * 23.40 - * Jan 12, 1995 : CPU-PCI bridge optimization support by Frederic Potter. 23.41 - * Alpha version. Intel & UMC chipset support only. 23.42 - * 23.43 - * Apr 16, 1995 : Source merge with the DEC Alpha PCI support. Most of the code 23.44 - * moved to drivers/pci/pci.c. 23.45 - * 23.46 - * Dec 7, 1996 : Added support for direct configuration access of boards 23.47 - * with Intel compatible access schemes (tsbogend@alpha.franken.de) 23.48 - * 23.49 - * Feb 3, 1997 : Set internal functions to static, save/restore flags 23.50 - * avoid dead locks reading broken PCI BIOS, werner@suse.de 23.51 - * 23.52 - * Apr 26, 1997 : Fixed case when there is BIOS32, but not PCI BIOS 23.53 - * (mj@atrey.karlin.mff.cuni.cz) 23.54 - * 23.55 - * May 7, 1997 : Added some missing cli()'s. [mj] 23.56 - * 23.57 - * Jun 20, 1997 : Corrected problems in "conf1" type accesses. 23.58 - * (paubert@iram.es) 23.59 - * 23.60 - * Aug 2, 1997 : Split to PCI BIOS handling and direct PCI access parts 23.61 - * and cleaned it up... Martin Mares <mj@atrey.karlin.mff.cuni.cz> 23.62 - * 23.63 - * Feb 6, 1998 : No longer using BIOS to find devices and device classes. [mj] 23.64 - * 23.65 - * May 1, 1998 : Support for peer host bridges. [mj] 23.66 - * 23.67 - * Jun 19, 1998 : Changed to use spinlocks, so that PCI configuration space 23.68 - * can be accessed from interrupts even on SMP systems. [mj] 23.69 - * 23.70 - * August 1998 : Better support for peer host bridges and more paranoid 23.71 - * checks for direct hardware access. Ugh, this file starts to look as 23.72 - * a large gallery of common hardware bug workarounds (watch the comments) 23.73 - * -- the PCI specs themselves are sane, but most implementors should be 23.74 - * hit hard with \hammer scaled \magstep5. [mj] 23.75 - * 23.76 - * Jan 23, 1999 : More improvements to peer host bridge logic. i450NX fixup. [mj] 23.77 - * 23.78 - * Feb 8, 1999 : Added UM8886BF I/O address fixup. [mj] 23.79 - * 23.80 - * August 1999 : New resource management and configuration access stuff. [mj] 23.81 - * 23.82 - * Sep 19, 1999 : Use PCI IRQ routing tables for detection of peer host bridges. 23.83 - * Based on ideas by Chris Frantz and David Hinds. [mj] 23.84 - * 23.85 - * Sep 28, 1999 : Handle unreported/unassigned IRQs. Thanks to Shuu Yamaguchi 23.86 - * for a lot of patience during testing. [mj] 23.87 - * 23.88 - * Oct 8, 1999 : Split to pci-i386.c, pci-pc.c and pci-visws.c. [mj] 23.89 - */ 23.90 - 23.91 -#include <linux/types.h> 23.92 -/*#include <linux/kernel.h>*/ 23.93 -#include <linux/pci.h> 23.94 -#include <linux/init.h> 23.95 -#include <linux/ioport.h> 23.96 -#include <linux/errno.h> 23.97 - 23.98 -#include "pci-i386.h" 23.99 - 23.100 -void 23.101 -pcibios_update_resource(struct pci_dev *dev, struct resource *root, 23.102 - struct resource *res, int resource) 23.103 -{ 23.104 - u32 new, check; 23.105 - int reg; 23.106 - 23.107 - new = res->start | (res->flags & PCI_REGION_FLAG_MASK); 23.108 - if (resource < 6) { 23.109 - reg = PCI_BASE_ADDRESS_0 + 4*resource; 23.110 - } else if (resource == PCI_ROM_RESOURCE) { 23.111 - res->flags |= PCI_ROM_ADDRESS_ENABLE; 23.112 - new |= PCI_ROM_ADDRESS_ENABLE; 23.113 - reg = dev->rom_base_reg; 23.114 - } else { 23.115 - /* Somebody might have asked allocation of a non-standard resource */ 23.116 - return; 23.117 - } 23.118 - 23.119 - pci_write_config_dword(dev, reg, new); 23.120 - pci_read_config_dword(dev, reg, &check); 23.121 - if ((new ^ check) & ((new & PCI_BASE_ADDRESS_SPACE_IO) ? PCI_BASE_ADDRESS_IO_MASK : PCI_BASE_ADDRESS_MEM_MASK)) { 23.122 - printk(KERN_ERR "PCI: Error while updating region " 23.123 - "%s/%d (%08x != %08x)\n", dev->slot_name, resource, 23.124 - new, check); 23.125 - } 23.126 -} 23.127 - 23.128 -/* 23.129 - * We need to avoid collisions with `mirrored' VGA ports 23.130 - * and other strange ISA hardware, so we always want the 23.131 - * addresses to be allocated in the 0x000-0x0ff region 23.132 - * modulo 0x400. 23.133 - * 23.134 - * Why? Because some silly external IO cards only decode 23.135 - * the low 10 bits of the IO address. The 0x00-0xff region 23.136 - * is reserved for motherboard devices that decode all 16 23.137 - * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 23.138 - * but we want to try to avoid allocating at 0x2900-0x2bff 23.139 - * which might have be mirrored at 0x0100-0x03ff.. 23.140 - */ 23.141 -void 23.142 -pcibios_align_resource(void *data, struct resource *res, 23.143 - unsigned long size, unsigned long align) 23.144 -{ 23.145 - if (res->flags & IORESOURCE_IO) { 23.146 - unsigned long start = res->start; 23.147 - 23.148 - if (start & 0x300) { 23.149 - start = (start + 0x3ff) & ~0x3ff; 23.150 - res->start = start; 23.151 - } 23.152 - } 23.153 -} 23.154 - 23.155 - 23.156 -/* 23.157 - * Handle resources of PCI devices. If the world were perfect, we could 23.158 - * just allocate all the resource regions and do nothing more. It isn't. 23.159 - * On the other hand, we cannot just re-allocate all devices, as it would 23.160 - * require us to know lots of host bridge internals. So we attempt to 23.161 - * keep as much of the original configuration as possible, but tweak it 23.162 - * when it's found to be wrong. 23.163 - * 23.164 - * Known BIOS problems we have to work around: 23.165 - * - I/O or memory regions not configured 23.166 - * - regions configured, but not enabled in the command register 23.167 - * - bogus I/O addresses above 64K used 23.168 - * - expansion ROMs left enabled (this may sound harmless, but given 23.169 - * the fact the PCI specs explicitly allow address decoders to be 23.170 - * shared between expansion ROMs and other resource regions, it's 23.171 - * at least dangerous) 23.172 - * 23.173 - * Our solution: 23.174 - * (1) Allocate resources for all buses behind PCI-to-PCI bridges. 23.175 - * This gives us fixed barriers on where we can allocate. 23.176 - * (2) Allocate resources for all enabled devices. If there is 23.177 - * a collision, just mark the resource as unallocated. Also 23.178 - * disable expansion ROMs during this step. 23.179 - * (3) Try to allocate resources for disabled devices. If the 23.180 - * resources were assigned correctly, everything goes well, 23.181 - * if they weren't, they won't disturb allocation of other 23.182 - * resources. 23.183 - * (4) Assign new addresses to resources which were either 23.184 - * not configured at all or misconfigured. If explicitly 23.185 - * requested by the user, configure expansion ROM address 23.186 - * as well. 23.187 - */ 23.188 - 23.189 -static void __init pcibios_allocate_bus_resources(struct list_head *bus_list) 23.190 -{ 23.191 - struct list_head *ln; 23.192 - struct pci_bus *bus; 23.193 - struct pci_dev *dev; 23.194 - int idx; 23.195 - struct resource *r, *pr; 23.196 - 23.197 - /* Depth-First Search on bus tree */ 23.198 - for (ln=bus_list->next; ln != bus_list; ln=ln->next) { 23.199 - bus = pci_bus_b(ln); 23.200 - if ((dev = bus->self)) { 23.201 - for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) { 23.202 - r = &dev->resource[idx]; 23.203 - if (!r->start) 23.204 - continue; 23.205 - pr = pci_find_parent_resource(dev, r); 23.206 - if (!pr || request_resource(pr, r) < 0) 23.207 - printk(KERN_ERR "PCI: Cannot allocate resource region %d of bridge %s\n", idx, dev->slot_name); 23.208 - } 23.209 - } 23.210 - pcibios_allocate_bus_resources(&bus->children); 23.211 - } 23.212 -} 23.213 - 23.214 -static void __init pcibios_allocate_resources(int pass) 23.215 -{ 23.216 - struct pci_dev *dev; 23.217 - int idx, disabled; 23.218 - u16 command; 23.219 - struct resource *r, *pr; 23.220 - 23.221 - pci_for_each_dev(dev) { 23.222 - pci_read_config_word(dev, PCI_COMMAND, &command); 23.223 - for(idx = 0; idx < 6; idx++) { 23.224 - r = &dev->resource[idx]; 23.225 - if (r->parent) /* Already allocated */ 23.226 - continue; 23.227 - if (!r->start) /* Address not assigned at all */ 23.228 - continue; 23.229 - if (r->flags & IORESOURCE_IO) 23.230 - disabled = !(command & PCI_COMMAND_IO); 23.231 - else 23.232 - disabled = !(command & PCI_COMMAND_MEMORY); 23.233 - if (pass == disabled) { 23.234 - DBG("PCI: Resource %08lx-%08lx (f=%lx, d=%d, p=%d)\n", 23.235 - r->start, r->end, r->flags, disabled, pass); 23.236 - pr = pci_find_parent_resource(dev, r); 23.237 - if (!pr || request_resource(pr, r) < 0) { 23.238 - printk(KERN_ERR "PCI: Cannot allocate resource region %d of device %s\n", idx, dev->slot_name); 23.239 - /* We'll assign a new address later */ 23.240 - r->end -= r->start; 23.241 - r->start = 0; 23.242 - } 23.243 - } 23.244 - } 23.245 - if (!pass) { 23.246 - r = &dev->resource[PCI_ROM_RESOURCE]; 23.247 - if (r->flags & PCI_ROM_ADDRESS_ENABLE) { 23.248 - /* Turn the ROM off, leave the resource region, but keep it unregistered. */ 23.249 - u32 reg; 23.250 - DBG("PCI: Switching off ROM of %s\n", dev->slot_name); 23.251 - r->flags &= ~PCI_ROM_ADDRESS_ENABLE; 23.252 - pci_read_config_dword(dev, dev->rom_base_reg, ®); 23.253 - pci_write_config_dword(dev, dev->rom_base_reg, reg & ~PCI_ROM_ADDRESS_ENABLE); 23.254 - } 23.255 - } 23.256 - } 23.257 -} 23.258 - 23.259 -static void __init pcibios_assign_resources(void) 23.260 -{ 23.261 - struct pci_dev *dev; 23.262 - int idx; 23.263 - struct resource *r; 23.264 - 23.265 - pci_for_each_dev(dev) { 23.266 - int class = dev->class >> 8; 23.267 - 23.268 - /* Don't touch classless devices and host bridges */ 23.269 - if (!class || class == PCI_CLASS_BRIDGE_HOST) 23.270 - continue; 23.271 - 23.272 - for(idx=0; idx<6; idx++) { 23.273 - r = &dev->resource[idx]; 23.274 - 23.275 - /* 23.276 - * Don't touch IDE controllers and I/O ports of video cards! 23.277 - */ 23.278 - if ((class == PCI_CLASS_STORAGE_IDE && idx < 4) || 23.279 - (class == PCI_CLASS_DISPLAY_VGA && (r->flags & IORESOURCE_IO))) 23.280 - continue; 23.281 - 23.282 - /* 23.283 - * We shall assign a new address to this resource, either because 23.284 - * the BIOS forgot to do so or because we have decided the old 23.285 - * address was unusable for some reason. 23.286 - */ 23.287 - if (!r->start && r->end) 23.288 - pci_assign_resource(dev, idx); 23.289 - } 23.290 - 23.291 - if (pci_probe & PCI_ASSIGN_ROMS) { 23.292 - r = &dev->resource[PCI_ROM_RESOURCE]; 23.293 - r->end -= r->start; 23.294 - r->start = 0; 23.295 - if (r->end) 23.296 - pci_assign_resource(dev, PCI_ROM_RESOURCE); 23.297 - } 23.298 - } 23.299 -} 23.300 - 23.301 -void __init pcibios_resource_survey(void) 23.302 -{ 23.303 - DBG("PCI: Allocating resources\n"); 23.304 - pcibios_allocate_bus_resources(&pci_root_buses); 23.305 - pcibios_allocate_resources(0); 23.306 - pcibios_allocate_resources(1); 23.307 - pcibios_assign_resources(); 23.308 -} 23.309 - 23.310 -int pcibios_enable_resources(struct pci_dev *dev, int mask) 23.311 -{ 23.312 - u16 cmd, old_cmd; 23.313 - int idx; 23.314 - struct resource *r; 23.315 - 23.316 - pci_read_config_word(dev, PCI_COMMAND, &cmd); 23.317 - old_cmd = cmd; 23.318 - for(idx=0; idx<6; idx++) { 23.319 - /* Only set up the requested stuff */ 23.320 - if (!(mask & (1<<idx))) 23.321 - continue; 23.322 - 23.323 - r = &dev->resource[idx]; 23.324 - if (!r->start && r->end) { 23.325 - printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", dev->slot_name); 23.326 - return -EINVAL; 23.327 - } 23.328 - if (r->flags & IORESOURCE_IO) 23.329 - cmd |= PCI_COMMAND_IO; 23.330 - if (r->flags & IORESOURCE_MEM) 23.331 - cmd |= PCI_COMMAND_MEMORY; 23.332 - } 23.333 - if (dev->resource[PCI_ROM_RESOURCE].start) 23.334 - cmd |= PCI_COMMAND_MEMORY; 23.335 - if (cmd != old_cmd) { 23.336 - printk("PCI: Enabling device %s (%04x -> %04x)\n", dev->slot_name, old_cmd, cmd); 23.337 - pci_write_config_word(dev, PCI_COMMAND, cmd); 23.338 - } 23.339 - return 0; 23.340 -} 23.341 - 23.342 -/* 23.343 - * If we set up a device for bus mastering, we need to check the latency 23.344 - * timer as certain crappy BIOSes forget to set it properly. 23.345 - */ 23.346 -unsigned int pcibios_max_latency = 255; 23.347 - 23.348 -void pcibios_set_master(struct pci_dev *dev) 23.349 -{ 23.350 - u8 lat; 23.351 - pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat); 23.352 - if (lat < 16) 23.353 - lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency; 23.354 - else if (lat > pcibios_max_latency) 23.355 - lat = pcibios_max_latency; 23.356 - else 23.357 - return; 23.358 - printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", dev->slot_name, lat); 23.359 - pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); 23.360 -} 23.361 - 23.362 -#if 0 23.363 -int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma, 23.364 - enum pci_mmap_state mmap_state, int write_combine) 23.365 -{ 23.366 - unsigned long prot; 23.367 - 23.368 - /* I/O space cannot be accessed via normal processor loads and 23.369 - * stores on this platform. 23.370 - */ 23.371 - if (mmap_state == pci_mmap_io) 23.372 - return -EINVAL; 23.373 - 23.374 - /* Leave vm_pgoff as-is, the PCI space address is the physical 23.375 - * address on this platform. 23.376 - */ 23.377 - vma->vm_flags |= (VM_SHM | VM_LOCKED | VM_IO); 23.378 - 23.379 - prot = pgprot_val(vma->vm_page_prot); 23.380 - if (boot_cpu_data.x86 > 3) 23.381 - prot |= _PAGE_PCD | _PAGE_PWT; 23.382 - vma->vm_page_prot = __pgprot(prot); 23.383 - 23.384 - /* Write-combine setting is ignored, it is changed via the mtrr 23.385 - * interfaces on this platform. 23.386 - */ 23.387 - if (remap_page_range(vma->vm_start, vma->vm_pgoff << PAGE_SHIFT, 23.388 - vma->vm_end - vma->vm_start, 23.389 - vma->vm_page_prot)) 23.390 - return -EAGAIN; 23.391 - 23.392 - return 0; 23.393 -} 23.394 -#endif
24.1 --- a/xen-2.4.16/arch/i386/pci-i386.h Mon Feb 24 16:55:07 2003 +0000 24.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 24.3 @@ -1,69 +0,0 @@ 24.4 -/* 24.5 - * Low-Level PCI Access for i386 machines. 24.6 - * 24.7 - * (c) 1999 Martin Mares <mj@ucw.cz> 24.8 - */ 24.9 - 24.10 -#undef DEBUG 24.11 - 24.12 -#ifdef DEBUG 24.13 -#define DBG(x...) printk(x) 24.14 -#else 24.15 -#define DBG(x...) 24.16 -#endif 24.17 - 24.18 -#define PCI_PROBE_BIOS 0x0001 24.19 -#define PCI_PROBE_CONF1 0x0002 24.20 -#define PCI_PROBE_CONF2 0x0004 24.21 -#define PCI_NO_SORT 0x0100 24.22 -#define PCI_BIOS_SORT 0x0200 24.23 -#define PCI_NO_CHECKS 0x0400 24.24 -#define PCI_ASSIGN_ROMS 0x1000 24.25 -#define PCI_BIOS_IRQ_SCAN 0x2000 24.26 -#define PCI_ASSIGN_ALL_BUSSES 0x4000 24.27 - 24.28 -extern unsigned int pci_probe; 24.29 - 24.30 -/* pci-i386.c */ 24.31 - 24.32 -extern unsigned int pcibios_max_latency; 24.33 - 24.34 -void pcibios_resource_survey(void); 24.35 -int pcibios_enable_resources(struct pci_dev *, int); 24.36 - 24.37 -/* pci-pc.c */ 24.38 - 24.39 -extern int pcibios_last_bus; 24.40 -extern struct pci_bus *pci_root_bus; 24.41 -extern struct pci_ops *pci_root_ops; 24.42 - 24.43 -/* pci-irq.c */ 24.44 - 24.45 -struct irq_info { 24.46 - u8 bus, devfn; /* Bus, device and function */ 24.47 - struct { 24.48 - u8 link; /* IRQ line ID, chipset dependent, 0=not routed */ 24.49 - u16 bitmap; /* Available IRQs */ 24.50 - } __attribute__((packed)) irq[4]; 24.51 - u8 slot; /* Slot number, 0=onboard */ 24.52 - u8 rfu; 24.53 -} __attribute__((packed)); 24.54 - 24.55 -struct irq_routing_table { 24.56 - u32 signature; /* PIRQ_SIGNATURE should be here */ 24.57 - u16 version; /* PIRQ_VERSION */ 24.58 - u16 size; /* Table size in bytes */ 24.59 - u8 rtr_bus, rtr_devfn; /* Where the interrupt router lies */ 24.60 - u16 exclusive_irqs; /* IRQs devoted exclusively to PCI usage */ 24.61 - u16 rtr_vendor, rtr_device; /* Vendor and device ID of interrupt router */ 24.62 - u32 miniport_data; /* Crap */ 24.63 - u8 rfu[11]; 24.64 - u8 checksum; /* Modulo 256 checksum must give zero */ 24.65 - struct irq_info slots[0]; 24.66 -} __attribute__((packed)); 24.67 - 24.68 -extern unsigned int pcibios_irq_mask; 24.69 - 24.70 -void pcibios_irq_init(void); 24.71 -void pcibios_fixup_irqs(void); 24.72 -void pcibios_enable_irq(struct pci_dev *dev);
25.1 --- a/xen-2.4.16/arch/i386/pci-irq.c Mon Feb 24 16:55:07 2003 +0000 25.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 25.3 @@ -1,795 +0,0 @@ 25.4 -/* 25.5 - * Low-Level PCI Support for PC -- Routing of Interrupts 25.6 - * 25.7 - * (c) 1999--2000 Martin Mares <mj@ucw.cz> 25.8 - */ 25.9 - 25.10 -#include <linux/config.h> 25.11 -#include <linux/types.h> 25.12 -/*#include <linux/kernel.h>*/ 25.13 -#include <linux/pci.h> 25.14 -#include <linux/init.h> 25.15 -#include <linux/slab.h> 25.16 -#include <linux/interrupt.h> 25.17 -#include <linux/irq.h> 25.18 -#include <linux/sched.h> 25.19 - 25.20 -#include <asm/io.h> 25.21 -#include <asm/smp.h> 25.22 -#include <asm/io_apic.h> 25.23 - 25.24 -#include "pci-i386.h" 25.25 - 25.26 -#define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24)) 25.27 -#define PIRQ_VERSION 0x0100 25.28 - 25.29 -int broken_hp_bios_irq9; 25.30 - 25.31 -static struct irq_routing_table *pirq_table; 25.32 - 25.33 -/* 25.34 - * Never use: 0, 1, 2 (timer, keyboard, and cascade) 25.35 - * Avoid using: 13, 14 and 15 (FP error and IDE). 25.36 - * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse) 25.37 - */ 25.38 -unsigned int pcibios_irq_mask = 0xfff8; 25.39 - 25.40 -static int pirq_penalty[16] = { 25.41 - 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000, 25.42 - 0, 0, 0, 0, 1000, 100000, 100000, 100000 25.43 -}; 25.44 - 25.45 -struct irq_router { 25.46 - char *name; 25.47 - u16 vendor, device; 25.48 - int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq); 25.49 - int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, int new); 25.50 -}; 25.51 - 25.52 -/* 25.53 - * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table. 25.54 - */ 25.55 - 25.56 -static struct irq_routing_table * __init pirq_find_routing_table(void) 25.57 -{ 25.58 - u8 *addr; 25.59 - struct irq_routing_table *rt; 25.60 - int i; 25.61 - u8 sum; 25.62 - 25.63 - for(addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) { 25.64 - rt = (struct irq_routing_table *) addr; 25.65 - if (rt->signature != PIRQ_SIGNATURE || 25.66 - rt->version != PIRQ_VERSION || 25.67 - rt->size % 16 || 25.68 - rt->size < sizeof(struct irq_routing_table)) 25.69 - continue; 25.70 - sum = 0; 25.71 - for(i=0; i<rt->size; i++) 25.72 - sum += addr[i]; 25.73 - if (!sum) { 25.74 - DBG("PCI: Interrupt Routing Table found at 0x%p\n", rt); 25.75 - return rt; 25.76 - } 25.77 - } 25.78 - return NULL; 25.79 -} 25.80 - 25.81 -/* 25.82 - * If we have a IRQ routing table, use it to search for peer host 25.83 - * bridges. It's a gross hack, but since there are no other known 25.84 - * ways how to get a list of buses, we have to go this way. 25.85 - */ 25.86 - 25.87 -static void __init pirq_peer_trick(void) 25.88 -{ 25.89 - struct irq_routing_table *rt = pirq_table; 25.90 - u8 busmap[256]; 25.91 - int i; 25.92 - struct irq_info *e; 25.93 - 25.94 - memset(busmap, 0, sizeof(busmap)); 25.95 - for(i=0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) { 25.96 - e = &rt->slots[i]; 25.97 -#ifdef DEBUG 25.98 - { 25.99 - int j; 25.100 - DBG("%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot); 25.101 - for(j=0; j<4; j++) 25.102 - DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap); 25.103 - DBG("\n"); 25.104 - } 25.105 -#endif 25.106 - busmap[e->bus] = 1; 25.107 - } 25.108 - for(i=1; i<256; i++) 25.109 - /* 25.110 - * It might be a secondary bus, but in this case its parent is already 25.111 - * known (ascending bus order) and therefore pci_scan_bus returns immediately. 25.112 - */ 25.113 - if (busmap[i] && pci_scan_bus(i, pci_root_bus->ops, NULL)) 25.114 - printk(KERN_INFO "PCI: Discovered primary peer bus %02x [IRQ]\n", i); 25.115 - pcibios_last_bus = -1; 25.116 -} 25.117 - 25.118 -/* 25.119 - * Code for querying and setting of IRQ routes on various interrupt routers. 25.120 - */ 25.121 - 25.122 -static void eisa_set_level_irq(unsigned int irq) 25.123 -{ 25.124 - unsigned char mask = 1 << (irq & 7); 25.125 - unsigned int port = 0x4d0 + (irq >> 3); 25.126 - unsigned char val = inb(port); 25.127 - 25.128 - if (!(val & mask)) { 25.129 - DBG(" -> edge"); 25.130 - outb(val | mask, port); 25.131 - } 25.132 -} 25.133 - 25.134 -/* 25.135 - * Common IRQ routing practice: nybbles in config space, 25.136 - * offset by some magic constant. 25.137 - */ 25.138 -static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr) 25.139 -{ 25.140 - u8 x; 25.141 - unsigned reg = offset + (nr >> 1); 25.142 - 25.143 - pci_read_config_byte(router, reg, &x); 25.144 - return (nr & 1) ? (x >> 4) : (x & 0xf); 25.145 -} 25.146 - 25.147 -static void write_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr, unsigned int val) 25.148 -{ 25.149 - u8 x; 25.150 - unsigned reg = offset + (nr >> 1); 25.151 - 25.152 - pci_read_config_byte(router, reg, &x); 25.153 - x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val); 25.154 - pci_write_config_byte(router, reg, x); 25.155 -} 25.156 - 25.157 -/* 25.158 - * ALI pirq entries are damn ugly, and completely undocumented. 25.159 - * This has been figured out from pirq tables, and it's not a pretty 25.160 - * picture. 25.161 - */ 25.162 -static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 25.163 -{ 25.164 - static unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 }; 25.165 - 25.166 - return irqmap[read_config_nybble(router, 0x48, pirq-1)]; 25.167 -} 25.168 - 25.169 -static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 25.170 -{ 25.171 - static unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 }; 25.172 - unsigned int val = irqmap[irq]; 25.173 - 25.174 - if (val) { 25.175 - write_config_nybble(router, 0x48, pirq-1, val); 25.176 - return 1; 25.177 - } 25.178 - return 0; 25.179 -} 25.180 - 25.181 -/* 25.182 - * The Intel PIIX4 pirq rules are fairly simple: "pirq" is 25.183 - * just a pointer to the config space. 25.184 - */ 25.185 -static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 25.186 -{ 25.187 - u8 x; 25.188 - 25.189 - pci_read_config_byte(router, pirq, &x); 25.190 - return (x < 16) ? x : 0; 25.191 -} 25.192 - 25.193 -static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 25.194 -{ 25.195 - pci_write_config_byte(router, pirq, irq); 25.196 - return 1; 25.197 -} 25.198 - 25.199 -/* 25.200 - * The VIA pirq rules are nibble-based, like ALI, 25.201 - * but without the ugly irq number munging. 25.202 - */ 25.203 -static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 25.204 -{ 25.205 - return read_config_nybble(router, 0x55, pirq); 25.206 -} 25.207 - 25.208 -static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 25.209 -{ 25.210 - write_config_nybble(router, 0x55, pirq, irq); 25.211 - return 1; 25.212 -} 25.213 - 25.214 -/* 25.215 - * ITE 8330G pirq rules are nibble-based 25.216 - * FIXME: pirqmap may be { 1, 0, 3, 2 }, 25.217 - * 2+3 are both mapped to irq 9 on my system 25.218 - */ 25.219 -static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 25.220 -{ 25.221 - static unsigned char pirqmap[4] = { 1, 0, 2, 3 }; 25.222 - return read_config_nybble(router,0x43, pirqmap[pirq-1]); 25.223 -} 25.224 - 25.225 -static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 25.226 -{ 25.227 - static unsigned char pirqmap[4] = { 1, 0, 2, 3 }; 25.228 - write_config_nybble(router, 0x43, pirqmap[pirq-1], irq); 25.229 - return 1; 25.230 -} 25.231 - 25.232 -/* 25.233 - * OPTI: high four bits are nibble pointer.. 25.234 - * I wonder what the low bits do? 25.235 - */ 25.236 -static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 25.237 -{ 25.238 - return read_config_nybble(router, 0xb8, pirq >> 4); 25.239 -} 25.240 - 25.241 -static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 25.242 -{ 25.243 - write_config_nybble(router, 0xb8, pirq >> 4, irq); 25.244 - return 1; 25.245 -} 25.246 - 25.247 -/* 25.248 - * Cyrix: nibble offset 0x5C 25.249 - */ 25.250 -static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 25.251 -{ 25.252 - return read_config_nybble(router, 0x5C, (pirq-1)^1); 25.253 -} 25.254 - 25.255 -static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 25.256 -{ 25.257 - write_config_nybble(router, 0x5C, (pirq-1)^1, irq); 25.258 - return 1; 25.259 -} 25.260 - 25.261 -/* 25.262 - * PIRQ routing for SiS 85C503 router used in several SiS chipsets 25.263 - * According to the SiS 5595 datasheet (preliminary V1.0, 12/24/1997) 25.264 - * the related registers work as follows: 25.265 - * 25.266 - * general: one byte per re-routable IRQ, 25.267 - * bit 7 IRQ mapping enabled (0) or disabled (1) 25.268 - * bits [6:4] reserved 25.269 - * bits [3:0] IRQ to map to 25.270 - * allowed: 3-7, 9-12, 14-15 25.271 - * reserved: 0, 1, 2, 8, 13 25.272 - * 25.273 - * individual registers in device config space: 25.274 - * 25.275 - * 0x41/0x42/0x43/0x44: PCI INT A/B/C/D - bits as in general case 25.276 - * 25.277 - * 0x61: IDEIRQ: bits as in general case - but: 25.278 - * bits [6:5] must be written 01 25.279 - * bit 4 channel-select primary (0), secondary (1) 25.280 - * 25.281 - * 0x62: USBIRQ: bits as in general case - but: 25.282 - * bit 4 OHCI function disabled (0), enabled (1) 25.283 - * 25.284 - * 0x6a: ACPI/SCI IRQ - bits as in general case 25.285 - * 25.286 - * 0x7e: Data Acq. Module IRQ - bits as in general case 25.287 - * 25.288 - * Apparently there are systems implementing PCI routing table using both 25.289 - * link values 0x01-0x04 and 0x41-0x44 for PCI INTA..D, but register offsets 25.290 - * like 0x62 as link values for USBIRQ e.g. So there is no simple 25.291 - * "register = offset + pirq" relation. 25.292 - * Currently we support PCI INTA..D and USBIRQ and try our best to handle 25.293 - * both link mappings. 25.294 - * IDE/ACPI/DAQ mapping is currently unsupported (left untouched as set by BIOS). 25.295 - */ 25.296 - 25.297 -static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 25.298 -{ 25.299 - u8 x; 25.300 - int reg = pirq; 25.301 - 25.302 - switch(pirq) { 25.303 - case 0x01: 25.304 - case 0x02: 25.305 - case 0x03: 25.306 - case 0x04: 25.307 - reg += 0x40; 25.308 - case 0x41: 25.309 - case 0x42: 25.310 - case 0x43: 25.311 - case 0x44: 25.312 - case 0x62: 25.313 - pci_read_config_byte(router, reg, &x); 25.314 - if (reg != 0x62) 25.315 - break; 25.316 - if (!(x & 0x40)) 25.317 - return 0; 25.318 - break; 25.319 - case 0x61: 25.320 - case 0x6a: 25.321 - case 0x7e: 25.322 - printk(KERN_INFO "SiS pirq: advanced IDE/ACPI/DAQ mapping not yet implemented\n"); 25.323 - return 0; 25.324 - default: 25.325 - printk(KERN_INFO "SiS router pirq escape (%d)\n", pirq); 25.326 - return 0; 25.327 - } 25.328 - return (x & 0x80) ? 0 : (x & 0x0f); 25.329 -} 25.330 - 25.331 -static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 25.332 -{ 25.333 - u8 x; 25.334 - int reg = pirq; 25.335 - 25.336 - switch(pirq) { 25.337 - case 0x01: 25.338 - case 0x02: 25.339 - case 0x03: 25.340 - case 0x04: 25.341 - reg += 0x40; 25.342 - case 0x41: 25.343 - case 0x42: 25.344 - case 0x43: 25.345 - case 0x44: 25.346 - case 0x62: 25.347 - x = (irq&0x0f) ? (irq&0x0f) : 0x80; 25.348 - if (reg != 0x62) 25.349 - break; 25.350 - /* always mark OHCI enabled, as nothing else knows about this */ 25.351 - x |= 0x40; 25.352 - break; 25.353 - case 0x61: 25.354 - case 0x6a: 25.355 - case 0x7e: 25.356 - printk(KERN_INFO "advanced SiS pirq mapping not yet implemented\n"); 25.357 - return 0; 25.358 - default: 25.359 - printk(KERN_INFO "SiS router pirq escape (%d)\n", pirq); 25.360 - return 0; 25.361 - } 25.362 - pci_write_config_byte(router, reg, x); 25.363 - 25.364 - return 1; 25.365 -} 25.366 - 25.367 -/* 25.368 - * VLSI: nibble offset 0x74 - educated guess due to routing table and 25.369 - * config space of VLSI 82C534 PCI-bridge/router (1004:0102) 25.370 - * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard 25.371 - * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6 25.372 - * for the busbridge to the docking station. 25.373 - */ 25.374 - 25.375 -static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 25.376 -{ 25.377 - if (pirq > 8) { 25.378 - printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq); 25.379 - return 0; 25.380 - } 25.381 - return read_config_nybble(router, 0x74, pirq-1); 25.382 -} 25.383 - 25.384 -static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 25.385 -{ 25.386 - if (pirq > 8) { 25.387 - printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq); 25.388 - return 0; 25.389 - } 25.390 - write_config_nybble(router, 0x74, pirq-1, irq); 25.391 - return 1; 25.392 -} 25.393 - 25.394 -/* 25.395 - * ServerWorks: PCI interrupts mapped to system IRQ lines through Index 25.396 - * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register 25.397 - * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect 25.398 - * register is a straight binary coding of desired PIC IRQ (low nibble). 25.399 - * 25.400 - * The 'link' value in the PIRQ table is already in the correct format 25.401 - * for the Index register. There are some special index values: 25.402 - * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1, 25.403 - * and 0x03 for SMBus. 25.404 - */ 25.405 -static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 25.406 -{ 25.407 - outb_p(pirq, 0xc00); 25.408 - return inb(0xc01) & 0xf; 25.409 -} 25.410 - 25.411 -static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 25.412 -{ 25.413 - outb_p(pirq, 0xc00); 25.414 - outb_p(irq, 0xc01); 25.415 - return 1; 25.416 -} 25.417 - 25.418 -/* Support for AMD756 PCI IRQ Routing 25.419 - * Jhon H. Caicedo <jhcaiced@osso.org.co> 25.420 - * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced) 25.421 - * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced) 25.422 - * The AMD756 pirq rules are nibble-based 25.423 - * offset 0x56 0-3 PIRQA 4-7 PIRQB 25.424 - * offset 0x57 0-3 PIRQC 4-7 PIRQD 25.425 - */ 25.426 -static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 25.427 -{ 25.428 - u8 irq; 25.429 - irq = 0; 25.430 - if (pirq <= 4) 25.431 - { 25.432 - irq = read_config_nybble(router, 0x56, pirq - 1); 25.433 - } 25.434 - printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d get irq : %2d\n", 25.435 - dev->vendor, dev->device, pirq, irq); 25.436 - return irq; 25.437 -} 25.438 - 25.439 -static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 25.440 -{ 25.441 - printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d SET irq : %2d\n", 25.442 - dev->vendor, dev->device, pirq, irq); 25.443 - if (pirq <= 4) 25.444 - { 25.445 - write_config_nybble(router, 0x56, pirq - 1, irq); 25.446 - } 25.447 - return 1; 25.448 -} 25.449 - 25.450 -#ifdef CONFIG_PCI_BIOS 25.451 - 25.452 -static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 25.453 -{ 25.454 - struct pci_dev *bridge; 25.455 - int pin = pci_get_interrupt_pin(dev, &bridge); 25.456 - return pcibios_set_irq_routing(bridge, pin, irq); 25.457 -} 25.458 - 25.459 -static struct irq_router pirq_bios_router = 25.460 - { "BIOS", 0, 0, NULL, pirq_bios_set }; 25.461 - 25.462 -#endif 25.463 - 25.464 -static struct irq_router pirq_routers[] = { 25.465 - { "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371FB_0, pirq_piix_get, pirq_piix_set }, 25.466 - { "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, pirq_piix_get, pirq_piix_set }, 25.467 - { "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, pirq_piix_get, pirq_piix_set }, 25.468 - { "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371MX, pirq_piix_get, pirq_piix_set }, 25.469 - { "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_0, pirq_piix_get, pirq_piix_set }, 25.470 - { "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, pirq_piix_get, pirq_piix_set }, 25.471 - { "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, pirq_piix_get, pirq_piix_set }, 25.472 - { "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, pirq_piix_get, pirq_piix_set }, 25.473 - { "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, pirq_piix_get, pirq_piix_set }, 25.474 - { "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, pirq_piix_get, pirq_piix_set }, 25.475 - { "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, pirq_piix_get, pirq_piix_set }, 25.476 - { "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, pirq_piix_get, pirq_piix_set }, 25.477 - { "PIIX", PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801E_0, pirq_piix_get, pirq_piix_set }, 25.478 - 25.479 - { "ALI", PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, pirq_ali_get, pirq_ali_set }, 25.480 - 25.481 - { "ITE", PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_IT8330G_0, pirq_ite_get, pirq_ite_set }, 25.482 - 25.483 - { "VIA", PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, pirq_via_get, pirq_via_set }, 25.484 - { "VIA", PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, pirq_via_get, pirq_via_set }, 25.485 - { "VIA", PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, pirq_via_get, pirq_via_set }, 25.486 - 25.487 - { "OPTI", PCI_VENDOR_ID_OPTI, PCI_DEVICE_ID_OPTI_82C700, pirq_opti_get, pirq_opti_set }, 25.488 - 25.489 - { "NatSemi", PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_5520, pirq_cyrix_get, pirq_cyrix_set }, 25.490 - { "SIS", PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, pirq_sis_get, pirq_sis_set }, 25.491 - { "VLSI 82C534", PCI_VENDOR_ID_VLSI, PCI_DEVICE_ID_VLSI_82C534, pirq_vlsi_get, pirq_vlsi_set }, 25.492 - { "ServerWorks", PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4, 25.493 - pirq_serverworks_get, pirq_serverworks_set }, 25.494 - { "ServerWorks", PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5, 25.495 - pirq_serverworks_get, pirq_serverworks_set }, 25.496 - { "AMD756 VIPER", PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_740B, 25.497 - pirq_amd756_get, pirq_amd756_set }, 25.498 - { "AMD766", PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7413, 25.499 - pirq_amd756_get, pirq_amd756_set }, 25.500 - { "AMD768", PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7443, 25.501 - pirq_amd756_get, pirq_amd756_set }, 25.502 - 25.503 - { "default", 0, 0, NULL, NULL } 25.504 -}; 25.505 - 25.506 -static struct irq_router *pirq_router; 25.507 -static struct pci_dev *pirq_router_dev; 25.508 - 25.509 -static void __init pirq_find_router(void) 25.510 -{ 25.511 - struct irq_routing_table *rt = pirq_table; 25.512 - struct irq_router *r; 25.513 - 25.514 -#ifdef CONFIG_PCI_BIOS 25.515 - if (!rt->signature) { 25.516 - printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n"); 25.517 - pirq_router = &pirq_bios_router; 25.518 - return; 25.519 - } 25.520 -#endif 25.521 - 25.522 - DBG("PCI: Attempting to find IRQ router for %04x:%04x\n", 25.523 - rt->rtr_vendor, rt->rtr_device); 25.524 - 25.525 - /* fall back to default router if nothing else found */ 25.526 - pirq_router = &pirq_routers[ARRAY_SIZE(pirq_routers) - 1]; 25.527 - 25.528 - pirq_router_dev = pci_find_slot(rt->rtr_bus, rt->rtr_devfn); 25.529 - if (!pirq_router_dev) { 25.530 - DBG("PCI: Interrupt router not found at %02x:%02x\n", rt->rtr_bus, rt->rtr_devfn); 25.531 - return; 25.532 - } 25.533 - 25.534 - for(r=pirq_routers; r->vendor; r++) { 25.535 - /* Exact match against router table entry? Use it! */ 25.536 - if (r->vendor == rt->rtr_vendor && r->device == rt->rtr_device) { 25.537 - pirq_router = r; 25.538 - break; 25.539 - } 25.540 - /* Match against router device entry? Use it as a fallback */ 25.541 - if (r->vendor == pirq_router_dev->vendor && r->device == pirq_router_dev->device) { 25.542 - pirq_router = r; 25.543 - } 25.544 - } 25.545 - printk(KERN_INFO "PCI: Using IRQ router %s [%04x/%04x] at %s\n", 25.546 - pirq_router->name, 25.547 - pirq_router_dev->vendor, 25.548 - pirq_router_dev->device, 25.549 - pirq_router_dev->slot_name); 25.550 -} 25.551 - 25.552 -static struct irq_info *pirq_get_info(struct pci_dev *dev) 25.553 -{ 25.554 - struct irq_routing_table *rt = pirq_table; 25.555 - int entries = (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); 25.556 - struct irq_info *info; 25.557 - 25.558 - for (info = rt->slots; entries--; info++) 25.559 - if (info->bus == dev->bus->number && PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn)) 25.560 - return info; 25.561 - return NULL; 25.562 -} 25.563 - 25.564 -static void pcibios_test_irq_handler(int irq, void *dev_id, struct pt_regs *regs) 25.565 -{ 25.566 -} 25.567 - 25.568 -static int pcibios_lookup_irq(struct pci_dev *dev, int assign) 25.569 -{ 25.570 - u8 pin; 25.571 - struct irq_info *info; 25.572 - int i, pirq, newirq; 25.573 - int irq = 0; 25.574 - u32 mask; 25.575 - struct irq_router *r = pirq_router; 25.576 - struct pci_dev *dev2; 25.577 - char *msg = NULL; 25.578 - 25.579 - if (!pirq_table) 25.580 - return 0; 25.581 - 25.582 - /* Find IRQ routing entry */ 25.583 - pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 25.584 - if (!pin) { 25.585 - DBG(" -> no interrupt pin\n"); 25.586 - return 0; 25.587 - } 25.588 - pin = pin - 1; 25.589 - 25.590 - DBG("IRQ for %s:%d", dev->slot_name, pin); 25.591 - info = pirq_get_info(dev); 25.592 - if (!info) { 25.593 - DBG(" -> not found in routing table\n"); 25.594 - return 0; 25.595 - } 25.596 - pirq = info->irq[pin].link; 25.597 - mask = info->irq[pin].bitmap; 25.598 - if (!pirq) { 25.599 - DBG(" -> not routed\n"); 25.600 - return 0; 25.601 - } 25.602 - DBG(" -> PIRQ %02x, mask %04x, excl %04x", pirq, mask, pirq_table->exclusive_irqs); 25.603 - mask &= pcibios_irq_mask; 25.604 - 25.605 - /* Work around broken HP Pavilion Notebooks which assign USB to 25.606 - IRQ 9 even though it is actually wired to IRQ 11 */ 25.607 - 25.608 - if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) { 25.609 - dev->irq = 11; 25.610 - pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11); 25.611 - r->set(pirq_router_dev, dev, pirq, 11); 25.612 - } 25.613 - 25.614 - /* 25.615 - * Find the best IRQ to assign: use the one 25.616 - * reported by the device if possible. 25.617 - */ 25.618 - newirq = dev->irq; 25.619 - if (!newirq && assign) { 25.620 - for (i = 0; i < 16; i++) { 25.621 - if (!(mask & (1 << i))) 25.622 - continue; 25.623 - if (pirq_penalty[i] < pirq_penalty[newirq] && 25.624 - !request_irq(i, pcibios_test_irq_handler, SA_SHIRQ, "pci-test", dev)) { 25.625 - free_irq(i, dev); 25.626 - newirq = i; 25.627 - } 25.628 - } 25.629 - } 25.630 - DBG(" -> newirq=%d", newirq); 25.631 - 25.632 - /* Check if it is hardcoded */ 25.633 - if ((pirq & 0xf0) == 0xf0) { 25.634 - irq = pirq & 0xf; 25.635 - DBG(" -> hardcoded IRQ %d\n", irq); 25.636 - msg = "Hardcoded"; 25.637 - } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq))) { 25.638 - DBG(" -> got IRQ %d\n", irq); 25.639 - msg = "Found"; 25.640 - } else if (newirq && r->set && (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) { 25.641 - DBG(" -> assigning IRQ %d", newirq); 25.642 - if (r->set(pirq_router_dev, dev, pirq, newirq)) { 25.643 - eisa_set_level_irq(newirq); 25.644 - DBG(" ... OK\n"); 25.645 - msg = "Assigned"; 25.646 - irq = newirq; 25.647 - } 25.648 - } 25.649 - 25.650 - if (!irq) { 25.651 - DBG(" ... failed\n"); 25.652 - if (newirq && mask == (1 << newirq)) { 25.653 - msg = "Guessed"; 25.654 - irq = newirq; 25.655 - } else 25.656 - return 0; 25.657 - } 25.658 - printk(KERN_INFO "PCI: %s IRQ %d for device %s\n", msg, irq, dev->slot_name); 25.659 - 25.660 - /* Update IRQ for all devices with the same pirq value */ 25.661 - pci_for_each_dev(dev2) { 25.662 - pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin); 25.663 - if (!pin) 25.664 - continue; 25.665 - pin--; 25.666 - info = pirq_get_info(dev2); 25.667 - if (!info) 25.668 - continue; 25.669 - if (info->irq[pin].link == pirq) { 25.670 - /* We refuse to override the dev->irq information. Give a warning! */ 25.671 - if (dev2->irq && dev2->irq != irq) { 25.672 - printk(KERN_INFO "IRQ routing conflict for %s, have irq %d, want irq %d\n", 25.673 - dev2->slot_name, dev2->irq, irq); 25.674 - continue; 25.675 - } 25.676 - dev2->irq = irq; 25.677 - pirq_penalty[irq]++; 25.678 - if (dev != dev2) 25.679 - printk(KERN_INFO "PCI: Sharing IRQ %d with %s\n", irq, dev2->slot_name); 25.680 - } 25.681 - } 25.682 - return 1; 25.683 -} 25.684 - 25.685 -void __init pcibios_irq_init(void) 25.686 -{ 25.687 - DBG("PCI: IRQ init\n"); 25.688 - pirq_table = pirq_find_routing_table(); 25.689 -#ifdef CONFIG_PCI_BIOS 25.690 - if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN)) 25.691 - pirq_table = pcibios_get_irq_routing_table(); 25.692 -#endif 25.693 - if (pirq_table) { 25.694 - pirq_peer_trick(); 25.695 - pirq_find_router(); 25.696 - if (pirq_table->exclusive_irqs) { 25.697 - int i; 25.698 - for (i=0; i<16; i++) 25.699 - if (!(pirq_table->exclusive_irqs & (1 << i))) 25.700 - pirq_penalty[i] += 100; 25.701 - } 25.702 - /* If we're using the I/O APIC, avoid using the PCI IRQ routing table */ 25.703 - if (io_apic_assign_pci_irqs) 25.704 - pirq_table = NULL; 25.705 - } 25.706 -} 25.707 - 25.708 -void __init pcibios_fixup_irqs(void) 25.709 -{ 25.710 - struct pci_dev *dev; 25.711 - u8 pin; 25.712 - 25.713 - DBG("PCI: IRQ fixup\n"); 25.714 - pci_for_each_dev(dev) { 25.715 - /* 25.716 - * If the BIOS has set an out of range IRQ number, just ignore it. 25.717 - * Also keep track of which IRQ's are already in use. 25.718 - */ 25.719 - if (dev->irq >= 16) { 25.720 - DBG("%s: ignoring bogus IRQ %d\n", dev->slot_name, dev->irq); 25.721 - dev->irq = 0; 25.722 - } 25.723 - /* If the IRQ is already assigned to a PCI device, ignore its ISA use penalty */ 25.724 - if (pirq_penalty[dev->irq] >= 100 && pirq_penalty[dev->irq] < 100000) 25.725 - pirq_penalty[dev->irq] = 0; 25.726 - pirq_penalty[dev->irq]++; 25.727 - } 25.728 - 25.729 - pci_for_each_dev(dev) { 25.730 - pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 25.731 -#ifdef CONFIG_X86_IO_APIC 25.732 - /* 25.733 - * Recalculate IRQ numbers if we use the I/O APIC. 25.734 - */ 25.735 - if (io_apic_assign_pci_irqs) 25.736 - { 25.737 - int irq; 25.738 - 25.739 - if (pin) { 25.740 - pin--; /* interrupt pins are numbered starting from 1 */ 25.741 - irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin); 25.742 - /* 25.743 - * Busses behind bridges are typically not listed in the MP-table. 25.744 - * In this case we have to look up the IRQ based on the parent bus, 25.745 - * parent slot, and pin number. The SMP code detects such bridged 25.746 - * busses itself so we should get into this branch reliably. 25.747 - */ 25.748 - if (irq < 0 && dev->bus->parent) { /* go back to the bridge */ 25.749 - struct pci_dev * bridge = dev->bus->self; 25.750 - 25.751 - pin = (pin + PCI_SLOT(dev->devfn)) % 4; 25.752 - irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number, 25.753 - PCI_SLOT(bridge->devfn), pin); 25.754 - if (irq >= 0) 25.755 - printk(KERN_WARNING "PCI: using PPB(B%d,I%d,P%d) to get irq %d\n", 25.756 - bridge->bus->number, PCI_SLOT(bridge->devfn), pin, irq); 25.757 - } 25.758 - if (irq >= 0) { 25.759 - printk(KERN_INFO "PCI->APIC IRQ transform: (B%d,I%d,P%d) -> %d\n", 25.760 - dev->bus->number, PCI_SLOT(dev->devfn), pin, irq); 25.761 - dev->irq = irq; 25.762 - } 25.763 - } 25.764 - } 25.765 -#endif 25.766 - /* 25.767 - * Still no IRQ? Try to lookup one... 25.768 - */ 25.769 - if (pin && !dev->irq) 25.770 - pcibios_lookup_irq(dev, 0); 25.771 - } 25.772 -} 25.773 - 25.774 -void pcibios_penalize_isa_irq(int irq) 25.775 -{ 25.776 - /* 25.777 - * If any ISAPnP device reports an IRQ in its list of possible 25.778 - * IRQ's, we try to avoid assigning it to PCI devices. 25.779 - */ 25.780 - pirq_penalty[irq] += 100; 25.781 -} 25.782 - 25.783 -void pcibios_enable_irq(struct pci_dev *dev) 25.784 -{ 25.785 - u8 pin; 25.786 - pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 25.787 - if (pin && !pcibios_lookup_irq(dev, 1) && !dev->irq) { 25.788 - char *msg; 25.789 - if (io_apic_assign_pci_irqs) 25.790 - msg = " Probably buggy MP table."; 25.791 - else if (pci_probe & PCI_BIOS_IRQ_SCAN) 25.792 - msg = ""; 25.793 - else 25.794 - msg = " Please try using pci=biosirq."; 25.795 - printk(KERN_WARNING "PCI: No IRQ known for interrupt pin %c of device %s.%s\n", 25.796 - 'A' + pin - 1, dev->slot_name, msg); 25.797 - } 25.798 -}
26.1 --- a/xen-2.4.16/arch/i386/pci-pc.c Mon Feb 24 16:55:07 2003 +0000 26.2 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 26.3 @@ -1,1494 +0,0 @@ 26.4 -/* 26.5 - * Low-Level PCI Support for PC 26.6 - * 26.7 - * (c) 1999--2000 Martin Mares <mj@ucw.cz> 26.8 - */ 26.9 - 26.10 -#include <linux/config.h> 26.11 -#include <linux/types.h> 26.12 -/*#include <linux/kernel.h>*/ 26.13 -#include <linux/sched.h> 26.14 -#include <linux/pci.h> 26.15 -#include <linux/init.h> 26.16 -#include <linux/ioport.h> 26.17 - 26.18 -/*#include <asm/segment.h>*/ 26.19 -#include <asm/io.h> 26.20 -#include <asm/smp.h> 26.21 -#include <asm/smpboot.h> 26.22 - 26.23 -#include "pci-i386.h" 26.24 - 26.25 -extern int numnodes; 26.26 -#define __KERNEL_CS __HYPERVISOR_CS 26.27 -#define __KERNEL_DS __HYPERVISOR_DS 26.28 - 26.29 -unsigned int pci_probe = PCI_PROBE_BIOS | PCI_PROBE_CONF1 | PCI_PROBE_CONF2; 26.30 - 26.31 -int pcibios_last_bus = -1; 26.32 -struct pci_bus *pci_root_bus = NULL; 26.33 -struct pci_ops *pci_root_ops = NULL; 26.34 - 26.35 -int (*pci_config_read)(int seg, int bus, int dev, int fn, int reg, int len, u32 *value) = NULL; 26.36 -int (*pci_config_write)(int seg, int bus, int dev, int fn, int reg, int len, u32 value) = NULL; 26.37 - 26.38 -#ifdef CONFIG_MULTIQUAD 26.39 -#define BUS2QUAD(global) (mp_bus_id_to_node[global]) 26.40 -#define BUS2LOCAL(global) (mp_bus_id_to_local[global]) 26.41 -#define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local]) 26.42 -#else 26.43 -#define BUS2QUAD(global) (0) 26.44 -#define BUS2LOCAL(global) (global) 26.45 -#define QUADLOCAL2BUS(quad,local) (local) 26.46 -#endif 26.47 - 26.48 -/* 26.49 - * This interrupt-safe spinlock protects all accesses to PCI 26.50 - * configuration space. 26.51 - */ 26.52 -static spinlock_t pci_config_lock = SPIN_LOCK_UNLOCKED; 26.53 - 26.54 - 26.55 -/* 26.56 - * Functions for accessing PCI configuration space with type 1 accesses 26.57 - */ 26.58 - 26.59 -#ifdef CONFIG_PCI_DIRECT 26.60 - 26.61 -#ifdef CONFIG_MULTIQUAD 26.62 -#define PCI_CONF1_ADDRESS(bus, dev, fn, reg) \ 26.63 - (0x80000000 | (BUS2LOCAL(bus) << 16) | (dev << 11) | (fn << 8) | (reg & ~3)) 26.64 - 26.65 -static int pci_conf1_mq_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value) /* CONFIG_MULTIQUAD */ 26.66 -{ 26.67 - unsigned long flags; 26.68 - 26.69 - if (bus > 255 || dev > 31 || fn > 7 || reg > 255) 26.70 - return -EINVAL; 26.71 - 26.72 - spin_lock_irqsave(&pci_config_lock, flags); 26.73 - 26.74 - outl_quad(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8, BUS2QUAD(bus)); 26.75 - 26.76 - switch (len) { 26.77 - case 1: 26.78 - *value = inb_quad(0xCFC + (reg & 3), BUS2QUAD(bus)); 26.79 - break; 26.80 - case 2: 26.81 - *value = inw_quad(0xCFC + (reg & 2), BUS2QUAD(bus)); 26.82 - break; 26.83 - case 4: 26.84 - *value = inl_quad(0xCFC, BUS2QUAD(bus)); 26.85 - break; 26.86 - } 26.87 - 26.88 - spin_unlock_irqrestore(&pci_config_lock, flags); 26.89 - 26.90 - return 0; 26.91 -} 26.92 - 26.93 -static int pci_conf1_mq_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value) /* CONFIG_MULTIQUAD */ 26.94 -{ 26.95 - unsigned long flags; 26.96 - 26.97 - if (bus > 255 || dev > 31 || fn > 7 || reg > 255) 26.98 - return -EINVAL; 26.99 - 26.100 - spin_lock_irqsave(&pci_config_lock, flags); 26.101 - 26.102 - outl_quad(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8, BUS2QUAD(bus)); 26.103 - 26.104 - switch (len) { 26.105 - case 1: 26.106 - outb_quad((u8)value, 0xCFC + (reg & 3), BUS2QUAD(bus)); 26.107 - break; 26.108 - case 2: 26.109 - outw_quad((u16)value, 0xCFC + (reg & 2), BUS2QUAD(bus)); 26.110 - break; 26.111 - case 4: 26.112 - outl_quad((u32)value, 0xCFC, BUS2QUAD(bus)); 26.113 - break; 26.114 - } 26.115 - 26.116 - spin_unlock_irqrestore(&pci_config_lock, flags); 26.117 - 26.118 - return 0; 26.119 -} 26.120 - 26.121 -static int pci_conf1_read_mq_config_byte(struct pci_dev *dev, int where, u8 *value) 26.122 -{ 26.123 - int result; 26.124 - u32 data; 26.125 - 26.126 - result = pci_conf1_mq_read(0, dev->bus->number, PCI_SLOT(dev->devfn), 26.127 - PCI_FUNC(dev->devfn), where, 1, &data); 26.128 - 26.129 - *value = (u8)data; 26.130 - 26.131 - return result; 26.132 -} 26.133 - 26.134 -static int pci_conf1_read_mq_config_word(struct pci_dev *dev, int where, u16 *value) 26.135 -{ 26.136 - int result; 26.137 - u32 data; 26.138 - 26.139 - result = pci_conf1_mq_read(0, dev->bus->number, PCI_SLOT(dev->devfn), 26.140 - PCI_FUNC(dev->devfn), where, 2, &data); 26.141 - 26.142 - *value = (u16)data; 26.143 - 26.144 - return result; 26.145 -} 26.146 - 26.147 -static int pci_conf1_read_mq_config_dword(struct pci_dev *dev, int where, u32 *value) 26.148 -{ 26.149 - if (!value) 26.150 - return -EINVAL; 26.151 - 26.152 - return pci_conf1_mq_read(0, dev->bus->number, PCI_SLOT(dev->devfn), 26.153 - PCI_FUNC(dev->devfn), where, 4, value); 26.154 -} 26.155 - 26.156 -static int pci_conf1_write_mq_config_byte(struct pci_dev *dev, int where, u8 value) 26.157 -{ 26.158 - return pci_conf1_mq_write(0, dev->bus->number, PCI_SLOT(dev->devfn), 26.159 - PCI_FUNC(dev->devfn), where, 1, value); 26.160 -} 26.161 - 26.162 -static int pci_conf1_write_mq_config_word(struct pci_dev *dev, int where, u16 value) 26.163 -{ 26.164 - return pci_conf1_mq_write(0, dev->bus->number, PCI_SLOT(dev->devfn), 26.165 - PCI_FUNC(dev->devfn), where, 2, value); 26.166 -} 26.167 - 26.168 -static int pci_conf1_write_mq_config_dword(struct pci_dev *dev, int where, u32 value) 26.169 -{ 26.170 - return pci_conf1_mq_write(0, dev->bus->number, PCI_SLOT(dev->devfn), 26.171 - PCI_FUNC(dev->devfn), where, 4, value); 26.172 -} 26.173 - 26.174 -static struct pci_ops pci_direct_mq_conf1 = { 26.175 - pci_conf1_read_mq_config_byte, 26.176 - pci_conf1_read_mq_config_word, 26.177 - pci_conf1_read_mq_config_dword, 26.178 - pci_conf1_write_mq_config_byte, 26.179 - pci_conf1_write_mq_config_word, 26.180 - pci_conf1_write_mq_config_dword 26.181 -}; 26.182 - 26.183 -#endif /* !CONFIG_MULTIQUAD */ 26.184 -#define PCI_CONF1_ADDRESS(bus, dev, fn, reg) \ 26.185 - (0x80000000 | (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3)) 26.186 - 26.187 -static int pci_conf1_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value) /* !CONFIG_MULTIQUAD */ 26.188 -{ 26.189 - unsigned long flags; 26.190 - 26.191 - if (bus > 255 || dev > 31 || fn > 7 || reg > 255) 26.192 - return -EINVAL; 26.193 - 26.194 - spin_lock_irqsave(&pci_config_lock, flags); 26.195 - 26.196 - outl(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8); 26.197 - 26.198 - switch (len) { 26.199 - case 1: 26.200 - *value = inb(0xCFC + (reg & 3)); 26.201 - break; 26.202 - case 2: 26.203 - *value = inw(0xCFC + (reg & 2)); 26.204 - break; 26.205 - case 4: 26.206 - *value = inl(0xCFC); 26.207 - break; 26.208 - } 26.209 - 26.210 - spin_unlock_irqrestore(&pci_config_lock, flags); 26.211 - 26.212 - return 0; 26.213 -} 26.214 - 26.215 -static int pci_conf1_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value) /* !CONFIG_MULTIQUAD */ 26.216 -{ 26.217 - unsigned long flags; 26.218 - 26.219 - if ((bus > 255 || dev > 31 || fn > 7 || reg > 255)) 26.220 - return -EINVAL; 26.221 - 26.222 - spin_lock_irqsave(&pci_config_lock, flags); 26.223 - 26.224 - outl(PCI_CONF1_ADDRESS(bus, dev, fn, reg), 0xCF8); 26.225 - 26.226 - switch (len) { 26.227 - case 1: 26.228 - outb((u8)value, 0xCFC + (reg & 3)); 26.229 - break; 26.230 - case 2: 26.231 - outw((u16)value, 0xCFC + (reg & 2)); 26.232 - break; 26.233 - case 4: 26.234 - outl((u32)value, 0xCFC); 26.235 - break; 26.236 - } 26.237 - 26.238 - spin_unlock_irqrestore(&pci_config_lock, flags); 26.239 - 26.240 - return 0; 26.241 -} 26.242 - 26.243 -#undef PCI_CONF1_ADDRESS 26.244 - 26.245 -static int pci_conf1_read_config_byte(struct pci_dev *dev, int where, u8 *value) 26.246 -{ 26.247 - int result; 26.248 - u32 data; 26.249 - 26.250 - result = pci_conf1_read(0, dev->bus->number, PCI_SLOT(dev->devfn), 26.251 - PCI_FUNC(dev->devfn), where, 1, &data); 26.252 - 26.253 - *value = (u8)data; 26.254 - 26.255 - return result; 26.256 -} 26.257 - 26.258 -static int pci_conf1_read_config_word(struct pci_dev *dev, int where, u16 *value) 26.259 -{ 26.260 - int result; 26.261 - u32 data; 26.262 - 26.263 - result = pci_conf1_read(0, dev->bus->number, PCI_SLOT(dev->devfn), 26.264 - PCI_FUNC(dev->devfn), where, 2, &data); 26.265 - 26.266 - *value = (u16)data; 26.267 - 26.268 - return result; 26.269 -} 26.270 - 26.271 -static int pci_conf1_read_config_dword(struct pci_dev *dev, int where, u32 *value) 26.272 -{ 26.273 - return pci_conf1_read(0, dev->bus->number, PCI_SLOT(dev->devfn), 26.274 - PCI_FUNC(dev->devfn), where, 4, value); 26.275 -} 26.276 - 26.277 -static int pci_conf1_write_config_byte(struct pci_dev *dev, int where, u8 value) 26.278 -{ 26.279 - return pci_conf1_write(0, dev->bus->number, PCI_SLOT(dev->devfn), 26.280 - PCI_FUNC(dev->devfn), where, 1, value); 26.281 -} 26.282 - 26.283 -static int pci_conf1_write_config_word(struct pci_dev *dev, int where, u16 value) 26.284 -{ 26.285 - return pci_conf1_write(0, dev->bus->number, PCI_SLOT(dev->devfn), 26.286 - PCI_FUNC(dev->devfn), where, 2, value); 26.287 -} 26.288 - 26.289 -static int pci_conf1_write_config_dword(struct pci_dev *dev, int where, u32 value) 26.290 -{ 26.291 - return pci_conf1_write(0, dev->bus->number, PCI_SLOT(dev->devfn), 26.292 - PCI_FUNC(dev->devfn), where, 4, value); 26.293 -} 26.294 - 26.295 -static struct pci_ops pci_direct_conf1 = { 26.296 - pci_conf1_read_config_byte, 26.297 - pci_conf1_read_config_word, 26.298 - pci_conf1_read_config_dword, 26.299 - pci_conf1_write_config_byte, 26.300 - pci_conf1_write_config_word, 26.301 - pci_conf1_write_config_dword 26.302 -}; 26.303 - 26.304 - 26.305 -/* 26.306 - * Functions for accessing PCI configuration space with type 2 accesses 26.307 - */ 26.308 - 26.309 -#define PCI_CONF2_ADDRESS(dev, reg) (u16)(0xC000 | (dev << 8) | reg) 26.310 - 26.311 -static int pci_conf2_read (int seg, int bus, int dev, int fn, int reg, int len, u32 *value) 26.312 -{ 26.313 - unsigned long flags; 26.314 - 26.315 - if (bus > 255 || dev > 31 || fn > 7 || reg > 255) 26.316 - return -EINVAL; 26.317 - 26.318 - if (dev & 0x10) 26.319 - return PCIBIOS_DEVICE_NOT_FOUND; 26.320 - 26.321 - spin_lock_irqsave(&pci_config_lock, flags); 26.322 - 26.323 - outb((u8)(0xF0 | (fn << 1)), 0xCF8); 26.324 - outb((u8)bus, 0xCFA); 26.325 - 26.326 - switch (len) { 26.327 - case 1: 26.328 - *value = inb(PCI_CONF2_ADDRESS(dev, reg)); 26.329 - break; 26.330 - case 2: 26.331 - *value = inw(PCI_CONF2_ADDRESS(dev, reg)); 26.332 - break; 26.333 - case 4: 26.334 - *value = inl(PCI_CONF2_ADDRESS(dev, reg)); 26.335 - break; 26.336 - } 26.337 - 26.338 - outb (0, 0xCF8); 26.339 - 26.340 - spin_unlock_irqrestore(&pci_config_lock, flags); 26.341 - 26.342 - return 0; 26.343 -} 26.344 - 26.345 -static int pci_conf2_write (int seg, int bus, int dev, int fn, int reg, int len, u32 value) 26.346 -{ 26.347 - unsigned long flags; 26.348 - 26.349 - if ((bus > 255 || dev > 31 || fn > 7 || reg > 255)) 26.350 - return -EINVAL; 26.351 - 26.352 - if (dev & 0x10) 26.353 - return PCIBIOS_DEVICE_NOT_FOUND; 26.354 - 26.355 - spin_lock_irqsave(&pci_config_lock, flags); 26.356 - 26.357 - outb((u8)(0xF0 | (fn << 1)), 0xCF8); 26.358 - outb((u8)bus, 0xCFA); 26.359 - 26.360 - switch (len) { 26.361 - case 1: 26.362 - outb ((u8)value, PCI_CONF2_ADDRESS(dev, reg)); 26.363 - break; 26.364 - case 2: 26.365 - outw ((u16)value, PCI_CONF2_ADDRESS(dev, reg)); 26.366 - break; 26.367 - case 4: 26.368 - outl ((u32)value, PCI_CONF2_ADDRESS(dev, reg)); 26.369 - break; 26.370 - } 26.371 - 26.372 - outb (0, 0xCF8); 26.373 - 26.374 - spin_unlock_irqrestore(&pci_config_lock, flags); 26.375 - 26.376 - return 0; 26.377 -} 26.378 - 26.379 -#undef PCI_CONF2_ADDRESS 26.380 - 26.381 -static int pci_conf2_read_config_byte(struct pci_dev *dev, int where, u8 *value) 26.382 -{ 26.383 - int result; 26.384 - u32 data; 26.385 - result = pci_conf2_read(0, dev->bus->number, PCI_SLOT(dev->devfn), 26.386 - PCI_FUNC(dev->devfn), where, 1, &data); 26.387 - *value = (u8)data; 26.388 - return result; 26.389 -} 26.390 - 26.391 -static int pci_conf2_read_config_word(struct pci_dev *dev, int where, u16 *value) 26.392 -{ 26.393 - int result; 26.394 - u32 data; 26.395 - result = pci_conf2_read(0, dev->bus->number, PCI_SLOT(dev->devfn), 26.396 - PCI_FUNC(dev->devfn), where, 2, &data); 26.397 - *value = (u16)data; 26.398 - return result; 26.399 -} 26.400 - 26.401 -static int pci_conf2_read_config_dword(struct pci_dev *dev, int where, u32 *value) 26.402 -{ 26.403 - return pci_conf2_read(0, dev->bus->number, PCI_SLOT(dev->devfn), 26.404 - PCI_FUNC(dev->devfn), where, 4, value); 26.405 -} 26.406 - 26.407 -static int pci_conf2_write_config_byte(struct pci_dev *dev, int where, u8 value) 26.408 -{ 26.409 - return pci_conf2_write(0, dev->bus->number, PCI_SLOT(dev->devfn), 26.410 - PCI_FUNC(dev->devfn), where, 1, value); 26.411 -} 26.412 - 26.413 -static int pci_conf2_write_config_word(struct pci_dev *dev, int where, u16 value) 26.414 -{ 26.415 - return pci_conf2_write(0, dev->bus->number, PCI_SLOT(dev->devfn), 26.416 - PCI_FUNC(dev->devfn), where, 2, value); 26.417 -} 26.418 - 26.419 -static int pci_conf2_write_config_dword(struct pci_dev *dev, int where, u32 value) 26.420 -{ 26.421 - return pci_conf2_write(0, dev->bus->number, PCI_SLOT(dev->devfn), 26.422 - PCI_FUNC(dev->devfn), where, 4, value)