1.1 --- a/xen/arch/x86/cpu/mcheck/mce_intel.c	Mon Mar 02 10:31:16 2009 +0000
     1.2 +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c	Mon Mar 02 10:32:32 2009 +0000
     1.3 @@ -359,12 +359,6 @@ static int do_cmci_discover(int i)
     1.4          return 0;
     1.5      }
     1.6      set_bit(i, __get_cpu_var(mce_banks_owned));
     1.7 -    /* Clear Corected Error Counter field, make sure CMCI could 
     1.8 -     * be triggered on the new owner
     1.9 -     */
    1.10 -    msr = MSR_IA32_MC0_STATUS + 4 * i;
    1.11 -    rdmsrl(msr, val);
    1.12 -    wrmsrl(msr, val & ~MCi_STATUS_ERRCOUNT);
    1.13  out:
    1.14      clear_bit(i, __get_cpu_var(no_cmci_banks));
    1.15      return 1;
    1.16 @@ -374,6 +368,7 @@ static void cmci_discover(void)
    1.17  {
    1.18      unsigned long flags;
    1.19      int i;
    1.20 +    struct mc_info *mi = NULL;
    1.21  
    1.22      printk(KERN_DEBUG "CMCI: find owner on CPU%d\n", smp_processor_id());
    1.23  
    1.24 @@ -385,6 +380,18 @@ static void cmci_discover(void)
    1.25  
    1.26      spin_unlock_irqrestore(&cmci_discover_lock, flags);
    1.27  
    1.28 +    /* In case CMCI happended when do owner change.
    1.29 +     * If CMCI happened yet not processed immediately,
    1.30 +     * MCi_status (error_count bit 38~52) is not cleared,
    1.31 +     * the CMCI interrupt will never be triggered again.
    1.32 +     */
    1.33 +    mi = machine_check_poll(MC_FLAG_CMCI);
    1.34 +    if (mi) {
    1.35 +        x86_mcinfo_dump(mi);
    1.36 +        if (dom0 && guest_enabled_event(dom0->vcpu[0], VIRQ_MCA))
    1.37 +            send_guest_global_virq(dom0, VIRQ_MCA);
    1.38 +    }
    1.39 +
    1.40      printk(KERN_DEBUG "CMCI: CPU%d owner_map[%lx], no_cmci_map[%lx]\n", 
    1.41             smp_processor_id(), 
    1.42             *((unsigned long *)__get_cpu_var(mce_banks_owned)), 

     2.1 --- a/xen/arch/x86/cpu/mcheck/x86_mca.h	Mon Mar 02 10:31:16 2009 +0000
     2.2 +++ b/xen/arch/x86/cpu/mcheck/x86_mca.h	Mon Mar 02 10:32:32 2009 +0000
     2.3 @@ -46,8 +46,6 @@
     2.4  #define MCi_STATUS_MSEC         0x00000000ffff0000ULL
     2.5  /* Other information */
     2.6  #define MCi_STATUS_OTHER        0x01ffffff00000000ULL
     2.7 -/*Corrected Error Count*/
     2.8 -#define MCi_STATUS_ERRCOUNT     0x001FFFC0000000000ULL 
     2.9  /* processor context corrupt */
    2.10  #define MCi_STATUS_PCC          0x0200000000000000ULL
    2.11  /* MSR_K8_MCi_ADDR register valid */