ia64/xen-unstable

changeset 16149:16f5672879c8

x86: add option to display last exception records during register dumps
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Keir Fraser <keir@xensource.com>
author Keir Fraser <keir@xensource.com>
date Wed Oct 17 15:37:36 2007 +0100 (2007-10-17)
parents 765600a13e4a
children 2173fe77dcd2
files xen/arch/x86/setup.c xen/arch/x86/smpboot.c xen/arch/x86/traps.c xen/arch/x86/x86_32/traps.c xen/arch/x86/x86_64/traps.c xen/include/asm-x86/msr.h xen/include/asm-x86/system.h
line diff
     1.1 --- a/xen/arch/x86/setup.c	Wed Oct 17 15:19:05 2007 +0100
     1.2 +++ b/xen/arch/x86/setup.c	Wed Oct 17 15:37:36 2007 +0100
     1.3 @@ -104,7 +104,6 @@ unsigned long xenheap_phys_start, xenhea
     1.4  
     1.5  extern void arch_init_memory(void);
     1.6  extern void init_IRQ(void);
     1.7 -extern void trap_init(void);
     1.8  extern void early_time_init(void);
     1.9  extern void early_cpu_init(void);
    1.10  extern void vesa_init(void);
     2.1 --- a/xen/arch/x86/smpboot.c	Wed Oct 17 15:19:05 2007 +0100
     2.2 +++ b/xen/arch/x86/smpboot.c	Wed Oct 17 15:37:36 2007 +0100
     2.3 @@ -492,8 +492,6 @@ void __devinit start_secondary(void *unu
     2.4  	 */
     2.5  	unsigned int cpu = booting_cpu;
     2.6  
     2.7 -	extern void percpu_traps_init(void);
     2.8 -
     2.9  	set_processor_id(cpu);
    2.10  	set_current(idle_vcpu[cpu]);
    2.11  	this_cpu(curr_vcpu) = idle_vcpu[cpu];
     3.1 --- a/xen/arch/x86/traps.c	Wed Oct 17 15:19:05 2007 +0100
     3.2 +++ b/xen/arch/x86/traps.c	Wed Oct 17 15:37:36 2007 +0100
     3.3 @@ -76,6 +76,8 @@ char opt_nmi[10] = "fatal";
     3.4  #endif
     3.5  string_param("nmi", opt_nmi);
     3.6  
     3.7 +DEFINE_PER_CPU(u32, ler_msr);
     3.8 +
     3.9  /* Master table, used by CPU0. */
    3.10  idt_entry_t idt_table[IDT_ENTRIES];
    3.11  
    3.12 @@ -112,6 +114,9 @@ unsigned long do_get_debugreg(int reg);
    3.13  static int debug_stack_lines = 20;
    3.14  integer_param("debug_stack_lines", debug_stack_lines);
    3.15  
    3.16 +static int opt_ler;
    3.17 +boolean_param("ler", opt_ler);
    3.18 +
    3.19  #ifdef CONFIG_X86_32
    3.20  #define stack_words_per_line 8
    3.21  #define ESP_BEFORE_EXCEPTION(regs) ((unsigned long *)&regs->esp)
    3.22 @@ -2098,9 +2103,12 @@ asmlinkage int do_debug(struct cpu_user_
    3.23      /* Save debug status register where guest OS can peek at it */
    3.24      v->arch.guest_context.debugreg[6] = condition;
    3.25  
    3.26 +    ler_enable();
    3.27 +
    3.28      return do_guest_trap(TRAP_debug, regs, 0);
    3.29  
    3.30   out:
    3.31 +    ler_enable();
    3.32      return EXCRET_not_a_fault;
    3.33  }
    3.34  
    3.35 @@ -2146,10 +2154,43 @@ void set_tss_desc(unsigned int n, void *
    3.36  #endif
    3.37  }
    3.38  
    3.39 +void __devinit percpu_traps_init(void)
    3.40 +{
    3.41 +    subarch_percpu_traps_init();
    3.42 +
    3.43 +    if ( !opt_ler )
    3.44 +        return;
    3.45 +
    3.46 +    switch ( boot_cpu_data.x86_vendor )
    3.47 +    {
    3.48 +    case X86_VENDOR_INTEL:
    3.49 +        switch ( boot_cpu_data.x86 )
    3.50 +        {
    3.51 +        case 6:
    3.52 +            this_cpu(ler_msr) = MSR_IA32_LASTINTFROMIP;
    3.53 +            break;
    3.54 +        case 15:
    3.55 +            this_cpu(ler_msr) = MSR_P4_LER_FROM_LIP;
    3.56 +            break;
    3.57 +        }
    3.58 +        break;
    3.59 +    case X86_VENDOR_AMD:
    3.60 +        switch ( boot_cpu_data.x86 )
    3.61 +        {
    3.62 +        case 6:
    3.63 +        case 15:
    3.64 +        case 16:
    3.65 +            this_cpu(ler_msr) = MSR_IA32_LASTINTFROMIP;
    3.66 +            break;
    3.67 +        }
    3.68 +        break;
    3.69 +    }
    3.70 +
    3.71 +    ler_enable();
    3.72 +}
    3.73 +
    3.74  void __init trap_init(void)
    3.75  {
    3.76 -    extern void percpu_traps_init(void);
    3.77 -
    3.78      /*
    3.79       * Note that interrupt gates are always used, rather than trap gates. We 
    3.80       * must have interrupts disabled until DS/ES/FS/GS are saved because the 
     4.1 --- a/xen/arch/x86/x86_32/traps.c	Wed Oct 17 15:19:05 2007 +0100
     4.2 +++ b/xen/arch/x86/x86_32/traps.c	Wed Oct 17 15:37:36 2007 +0100
     4.3 @@ -104,6 +104,14 @@ void show_registers(struct cpu_user_regs
     4.4             "ss: %04x   cs: %04x\n",
     4.5             fault_regs.ds, fault_regs.es, fault_regs.fs,
     4.6             fault_regs.gs, fault_regs.ss, fault_regs.cs);
     4.7 +
     4.8 +    if ( this_cpu(ler_msr) && !guest_mode(regs) )
     4.9 +    {
    4.10 +        u32 from, to, hi;
    4.11 +        rdmsr(this_cpu(ler_msr), from, hi);
    4.12 +        rdmsr(this_cpu(ler_msr) + 1, to, hi);
    4.13 +        printk("ler: %08x -> %08x\n", from, to);
    4.14 +    }
    4.15  }
    4.16  
    4.17  void show_page_walk(unsigned long addr)
    4.18 @@ -250,7 +258,7 @@ unsigned long do_iret(void)
    4.19      return 0;
    4.20  }
    4.21  
    4.22 -void __devinit percpu_traps_init(void)
    4.23 +void __devinit subarch_percpu_traps_init(void)
    4.24  {
    4.25      struct tss_struct *tss = &doublefault_tss;
    4.26      asmlinkage int hypercall(void);
     5.1 --- a/xen/arch/x86/x86_64/traps.c	Wed Oct 17 15:19:05 2007 +0100
     5.2 +++ b/xen/arch/x86/x86_64/traps.c	Wed Oct 17 15:37:36 2007 +0100
     5.3 @@ -112,6 +112,14 @@ void show_registers(struct cpu_user_regs
     5.4             "ss: %04x   cs: %04x\n",
     5.5             fault_regs.ds, fault_regs.es, fault_regs.fs,
     5.6             fault_regs.gs, fault_regs.ss, fault_regs.cs);
     5.7 +
     5.8 +    if ( this_cpu(ler_msr) && !guest_mode(regs) )
     5.9 +    {
    5.10 +        u64 from, to;
    5.11 +        rdmsrl(this_cpu(ler_msr), from);
    5.12 +        rdmsrl(this_cpu(ler_msr) + 1, to);
    5.13 +        printk("ler: %016lx -> %016lx\n", from, to);
    5.14 +    }
    5.15  }
    5.16  
    5.17  void show_page_walk(unsigned long addr)
    5.18 @@ -302,7 +310,7 @@ static int write_stack_trampoline(
    5.19      return 34;
    5.20  }
    5.21  
    5.22 -void __devinit percpu_traps_init(void)
    5.23 +void __devinit subarch_percpu_traps_init(void)
    5.24  {
    5.25      char *stack_bottom, *stack;
    5.26      int   cpu = smp_processor_id();
     6.1 --- a/xen/include/asm-x86/msr.h	Wed Oct 17 15:19:05 2007 +0100
     6.2 +++ b/xen/include/asm-x86/msr.h	Wed Oct 17 15:37:36 2007 +0100
     6.3 @@ -105,6 +105,19 @@ static inline void write_efer(__u64 val)
     6.4      wrmsrl(MSR_EFER, val);
     6.5  }
     6.6  
     6.7 +DECLARE_PER_CPU(u32, ler_msr);
     6.8 +
     6.9 +static inline void ler_enable(void)
    6.10 +{
    6.11 +    u64 debugctl;
    6.12 +    
    6.13 +    if ( !this_cpu(ler_msr) )
    6.14 +        return;
    6.15 +
    6.16 +    rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
    6.17 +    wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl | 1);
    6.18 +}
    6.19 +
    6.20  #endif /* !__ASSEMBLY__ */
    6.21  
    6.22  #endif /* __ASM_MSR_H */
     7.1 --- a/xen/include/asm-x86/system.h	Wed Oct 17 15:19:05 2007 +0100
     7.2 +++ b/xen/include/asm-x86/system.h	Wed Oct 17 15:37:36 2007 +0100
     7.3 @@ -314,4 +314,8 @@ static inline int local_irq_is_enabled(v
     7.4  #define BROKEN_ACPI_Sx		0x0001
     7.5  #define BROKEN_INIT_AFTER_S1	0x0002
     7.6  
     7.7 +void trap_init(void);
     7.8 +void percpu_traps_init(void);
     7.9 +void subarch_percpu_traps_init(void);
    7.10 +
    7.11  #endif