ia64/xen-unstable

changeset 10196:166073f830a3

[IA64] VTI: Optimize thash vtlb algorithm

Signed-off-by: Anthony Xu <anthony.xu@intel.com>
author awilliam@xenbuild.aw
date Tue May 30 10:28:59 2006 -0600 (2006-05-30)
parents 18b087bafac6
children 31ffbf4116ec
files xen/arch/ia64/vmx/vmmu.c xen/arch/ia64/vmx/vmx_interrupt.c xen/arch/ia64/vmx/vmx_ivt.S xen/arch/ia64/vmx/vmx_process.c xen/arch/ia64/vmx/vtlb.c xen/include/asm-ia64/vmmu.h xen/include/asm-ia64/vmx_vcpu.h
line diff
     1.1 --- a/xen/arch/ia64/vmx/vmmu.c	Tue May 30 08:46:21 2006 -0600
     1.2 +++ b/xen/arch/ia64/vmx/vmmu.c	Tue May 30 10:28:59 2006 -0600
     1.3 @@ -338,6 +338,7 @@ fetch_code(VCPU *vcpu, u64 gip, u64 *cod
     1.4  
     1.5  IA64FAULT vmx_vcpu_itc_i(VCPU *vcpu, UINT64 pte, UINT64 itir, UINT64 ifa)
     1.6  {
     1.7 +#ifdef VTLB_DEBUG
     1.8      int slot;
     1.9      u64 ps, va;
    1.10      ps = itir_ps(itir);
    1.11 @@ -348,14 +349,16 @@ IA64FAULT vmx_vcpu_itc_i(VCPU *vcpu, UIN
    1.12          panic_domain(vcpu_regs(vcpu),"Tlb conflict!!");
    1.13          return IA64_FAULT;
    1.14      }
    1.15 +#endif //VTLB_DEBUG    
    1.16      thash_purge_and_insert(vcpu, pte, itir, ifa);
    1.17      return IA64_NO_FAULT;
    1.18  }
    1.19  
    1.20  IA64FAULT vmx_vcpu_itc_d(VCPU *vcpu, UINT64 pte, UINT64 itir, UINT64 ifa)
    1.21  {
    1.22 +#ifdef VTLB_DEBUG    
    1.23      int slot;
    1.24 -    u64 ps, va, gpfn;
    1.25 +    u64 ps, va;
    1.26      ps = itir_ps(itir);
    1.27      va = PAGEALIGN(ifa, ps);
    1.28      slot = vtr_find_overlap(vcpu, va, ps, DSIDE_TLB);
    1.29 @@ -364,9 +367,7 @@ IA64FAULT vmx_vcpu_itc_d(VCPU *vcpu, UIN
    1.30          panic_domain(vcpu_regs(vcpu),"Tlb conflict!!");
    1.31          return IA64_FAULT;
    1.32      }
    1.33 -    gpfn = (pte & _PAGE_PPN_MASK)>> PAGE_SHIFT;
    1.34 -    if(VMX_DOMAIN(vcpu) && __gpfn_is_io(vcpu->domain,gpfn))
    1.35 -        pte |= VTLB_PTE_IO;
    1.36 +#endif //VTLB_DEBUG
    1.37      thash_purge_and_insert(vcpu, pte, itir, ifa);
    1.38      return IA64_NO_FAULT;
    1.39  
    1.40 @@ -377,11 +378,14 @@ IA64FAULT vmx_vcpu_itc_d(VCPU *vcpu, UIN
    1.41  
    1.42  IA64FAULT vmx_vcpu_itr_i(VCPU *vcpu, u64 slot, u64 pte, u64 itir, u64 ifa)
    1.43  {
    1.44 +#ifdef VTLB_DEBUG
    1.45      int index;
    1.46 +#endif    
    1.47      u64 ps, va, rid;
    1.48 -
    1.49 +    thash_data_t * p_itr;
    1.50      ps = itir_ps(itir);
    1.51      va = PAGEALIGN(ifa, ps);
    1.52 +#ifdef VTLB_DEBUG    
    1.53      index = vtr_find_overlap(vcpu, va, ps, ISIDE_TLB);
    1.54      if (index >=0) {
    1.55          // generate MCA.
    1.56 @@ -389,9 +393,11 @@ IA64FAULT vmx_vcpu_itr_i(VCPU *vcpu, u64
    1.57          return IA64_FAULT;
    1.58      }
    1.59      thash_purge_entries(vcpu, va, ps);
    1.60 +#endif    
    1.61      vcpu_get_rr(vcpu, va, &rid);
    1.62      rid = rid& RR_RID_MASK;
    1.63 -    vmx_vcpu_set_tr((thash_data_t *)&vcpu->arch.itrs[slot], pte, itir, va, rid);
    1.64 +    p_itr = (thash_data_t *)&vcpu->arch.itrs[slot];
    1.65 +    vmx_vcpu_set_tr(p_itr, pte, itir, va, rid);
    1.66      vcpu_quick_region_set(PSCBX(vcpu,itr_regions),va);
    1.67      return IA64_NO_FAULT;
    1.68  }
    1.69 @@ -399,11 +405,15 @@ IA64FAULT vmx_vcpu_itr_i(VCPU *vcpu, u64
    1.70  
    1.71  IA64FAULT vmx_vcpu_itr_d(VCPU *vcpu, u64 slot, u64 pte, u64 itir, u64 ifa)
    1.72  {
    1.73 +#ifdef VTLB_DEBUG
    1.74      int index;
    1.75 -    u64 ps, va, gpfn, rid;
    1.76 -
    1.77 +    u64 gpfn;
    1.78 +#endif    
    1.79 +    u64 ps, va, rid;
    1.80 +    thash_data_t * p_dtr;
    1.81      ps = itir_ps(itir);
    1.82      va = PAGEALIGN(ifa, ps);
    1.83 +#ifdef VTLB_DEBUG    
    1.84      index = vtr_find_overlap(vcpu, va, ps, DSIDE_TLB);
    1.85      if (index>=0) {
    1.86          // generate MCA.
    1.87 @@ -412,10 +422,12 @@ IA64FAULT vmx_vcpu_itr_d(VCPU *vcpu, u64
    1.88      }
    1.89      thash_purge_entries(vcpu, va, ps);
    1.90      gpfn = (pte & _PAGE_PPN_MASK)>> PAGE_SHIFT;
    1.91 -    if(__gpfn_is_io(vcpu->domain,gpfn))
    1.92 +    if(VMX_DOMAIN(vcpu) && _gpfn_is_io(vcpu->domain,gpfn))
    1.93          pte |= VTLB_PTE_IO;
    1.94 +#endif    
    1.95      vcpu_get_rr(vcpu, va, &rid);
    1.96      rid = rid& RR_RID_MASK;
    1.97 +    p_dtr = (thash_data_t *)&vcpu->arch.dtrs[slot];
    1.98      vmx_vcpu_set_tr((thash_data_t *)&vcpu->arch.dtrs[slot], pte, itir, va, rid);
    1.99      vcpu_quick_region_set(PSCBX(vcpu,dtr_regions),va);
   1.100      return IA64_NO_FAULT;
   1.101 @@ -432,7 +444,6 @@ IA64FAULT vmx_vcpu_ptr_d(VCPU *vcpu,UINT
   1.102      index = vtr_find_overlap(vcpu, va, ps, DSIDE_TLB);
   1.103      if (index>=0) {
   1.104          vcpu->arch.dtrs[index].pte.p=0;
   1.105 -        index = vtr_find_overlap(vcpu, va, ps, DSIDE_TLB);
   1.106      }
   1.107      thash_purge_entries(vcpu, va, ps);
   1.108      return IA64_NO_FAULT;
   1.109 @@ -447,7 +458,6 @@ IA64FAULT vmx_vcpu_ptr_i(VCPU *vcpu,UINT
   1.110      index = vtr_find_overlap(vcpu, va, ps, ISIDE_TLB);
   1.111      if (index>=0) {
   1.112          vcpu->arch.itrs[index].pte.p=0;
   1.113 -        index = vtr_find_overlap(vcpu, va, ps, ISIDE_TLB);
   1.114      }
   1.115      thash_purge_entries(vcpu, va, ps);
   1.116      return IA64_NO_FAULT;
     2.1 --- a/xen/arch/ia64/vmx/vmx_interrupt.c	Tue May 30 08:46:21 2006 -0600
     2.2 +++ b/xen/arch/ia64/vmx/vmx_interrupt.c	Tue May 30 10:28:59 2006 -0600
     2.3 @@ -390,3 +390,14 @@ page_not_present(VCPU *vcpu, u64 vadr)
     2.4      inject_guest_interruption(vcpu, IA64_PAGE_NOT_PRESENT_VECTOR);
     2.5  }
     2.6  
     2.7 +/* Deal with
     2.8 + *  Data access rights vector
     2.9 + */
    2.10 +void
    2.11 +data_access_rights(VCPU *vcpu, u64 vadr)
    2.12 +{
    2.13 +    /* If vPSR.ic, IFA, ITIR */
    2.14 +    set_ifa_itir_iha (vcpu, vadr, 1, 1, 0);
    2.15 +    inject_guest_interruption(vcpu, IA64_DATA_ACCESS_RIGHTS_VECTOR);
    2.16 +}
    2.17 +
     3.1 --- a/xen/arch/ia64/vmx/vmx_ivt.S	Tue May 30 08:46:21 2006 -0600
     3.2 +++ b/xen/arch/ia64/vmx/vmx_ivt.S	Tue May 30 10:28:59 2006 -0600
     3.3 @@ -141,9 +141,13 @@ ENTRY(vmx_itlb_miss)
     3.4      mov r16 = cr.ifa
     3.5      ;;
     3.6      thash r17 = r16
     3.7 +    ttag r20 = r16
     3.8      ;;
     3.9 -    ttag r20 = r16
    3.10 -    mov r18 = r17	
    3.11 +    mov r18 = r17
    3.12 +    adds r28 = VLE_TITAG_OFFSET,r17
    3.13 +    adds r19 = VLE_CCHAIN_OFFSET, r17
    3.14 +    ;;
    3.15 +    ld8 r17 = [r19]
    3.16      ;;
    3.17  vmx_itlb_loop:
    3.18      cmp.eq p6,p0 = r0, r17
    3.19 @@ -161,43 +165,21 @@ vmx_itlb_loop:
    3.20  (p7)mov r17 = r23;
    3.21  (p7)br.sptk vmx_itlb_loop
    3.22      ;;
    3.23 -    adds r23 = VLE_PGFLAGS_OFFSET, r17
    3.24 -    adds r24 = VLE_ITIR_OFFSET, r17
    3.25 -    ;;
    3.26 -    ld8 r25 = [r23]
    3.27 -    ld8 r26 = [r24]
    3.28 -    ;;
    3.29 -    cmp.eq p6,p7=r18,r17
    3.30 -(p6) br vmx_itlb_loop1
    3.31 -    ;;
    3.32 +    ld8 r25 = [r17]
    3.33      ld8 r27 = [r18]
    3.34 -    ;;
    3.35 -    extr.u r19 = r27, 56, 8
    3.36 -    extr.u r20 = r25, 56, 8
    3.37 +    ld8 r29 = [r28]
    3.38      ;;
    3.39 -    dep r27 = r20, r27, 56, 8
    3.40 -    dep r25 = r19, r25, 56, 8
    3.41 -    ;;
    3.42 -    st8 [r18] = r25,8
    3.43 -    st8 [r23] = r27
    3.44 -    ;;
    3.45 -    ld8 r28 = [r18]
    3.46 +    st8 [r16] = r29
    3.47 +    st8 [r28] = r22
    3.48 +    extr.u r19 = r27, 56, 4
    3.49      ;;
    3.50 -    st8 [r18] = r26,8
    3.51 -    st8 [r24] = r28
    3.52 -    ;;
    3.53 -    ld8 r30 = [r18]
    3.54 +    dep r27 = r0, r27, 56, 4
    3.55 +    dep r25 = r19, r25, 56, 4
    3.56      ;;
    3.57 -    st8 [r18] = r22
    3.58 -    st8 [r16] = r30 
    3.59 -    ;;
    3.60 -vmx_itlb_loop1:
    3.61 -    mov cr.itir = r26
    3.62 +    st8 [r18] = r25
    3.63 +    st8 [r17] = r27
    3.64      ;;
    3.65      itc.i r25
    3.66 -    ;;
    3.67 -    srlz.i
    3.68 -    ;;
    3.69      mov r17=cr.isr
    3.70      mov r23=r31
    3.71      mov r22=b0
    3.72 @@ -219,7 +201,7 @@ vmx_itlb_out:
    3.73      VMX_FAULT(1);
    3.74  END(vmx_itlb_miss)
    3.75  
    3.76 -	.org vmx_ia64_ivt+0x0800
    3.77 +    .org vmx_ia64_ivt+0x0800
    3.78  /////////////////////////////////////////////////////////////////////////////////////////
    3.79  // 0x0800 Entry 2 (size 64 bundles) DTLB (9,48)
    3.80  ENTRY(vmx_dtlb_miss)
    3.81 @@ -232,9 +214,13 @@ ENTRY(vmx_dtlb_miss)
    3.82      mov r16 = cr.ifa
    3.83      ;;
    3.84      thash r17 = r16
    3.85 +    ttag r20 = r16
    3.86      ;;
    3.87 -    ttag r20 = r16
    3.88 -    mov r18 = r17	
    3.89 +    mov r18 = r17
    3.90 +    adds r28 = VLE_TITAG_OFFSET,r17
    3.91 +    adds r19 = VLE_CCHAIN_OFFSET, r17
    3.92 +    ;;
    3.93 +    ld8 r17 = [r19]
    3.94      ;;
    3.95  vmx_dtlb_loop:
    3.96      cmp.eq p6,p0 = r0, r17
    3.97 @@ -252,43 +238,21 @@ vmx_dtlb_loop:
    3.98  (p7)mov r17 = r23;
    3.99  (p7)br.sptk vmx_dtlb_loop
   3.100      ;;
   3.101 -    adds r23 = VLE_PGFLAGS_OFFSET, r17
   3.102 -    adds r24 = VLE_ITIR_OFFSET, r17
   3.103 -    ;;
   3.104 -    ld8 r25 = [r23]
   3.105 -    ld8 r26 = [r24]
   3.106 -    ;;
   3.107 -    cmp.eq p6,p7=r18,r17
   3.108 -(p6) br vmx_dtlb_loop1
   3.109 -    ;;
   3.110 +    ld8 r25 = [r17]
   3.111      ld8 r27 = [r18]
   3.112 -    ;;
   3.113 -    extr.u r19 = r27, 56, 8
   3.114 -    extr.u r20 = r25, 56, 8
   3.115 -    ;;
   3.116 -    dep r27 = r20, r27, 56, 8
   3.117 -    dep r25 = r19, r25, 56, 8
   3.118 +    ld8 r29 = [r28]
   3.119      ;;
   3.120 -    st8 [r18] = r25,8
   3.121 -    st8 [r23] = r27
   3.122 -    ;;
   3.123 -    ld8 r28 = [r18]
   3.124 -    ;;
   3.125 -    st8 [r18] = r26,8
   3.126 -    st8 [r24] = r28
   3.127 -    ;;
   3.128 -    ld8 r30 = [r18]
   3.129 +    st8 [r16] = r29
   3.130 +    st8 [r28] = r22
   3.131 +    extr.u r19 = r27, 56, 4
   3.132      ;;
   3.133 -    st8 [r18] = r22
   3.134 -    st8 [r16] = r30 
   3.135 +    dep r27 = r0, r27, 56, 4
   3.136 +    dep r25 = r19, r25, 56, 4
   3.137      ;;
   3.138 -vmx_dtlb_loop1:
   3.139 -    mov cr.itir = r26
   3.140 -    ;;
   3.141 +    st8 [r18] = r25
   3.142 +    st8 [r17] = r27
   3.143 +    ;;    
   3.144      itc.d r25
   3.145 -    ;;
   3.146 -    srlz.d;
   3.147 -    ;;
   3.148      mov r17=cr.isr
   3.149      mov r23=r31
   3.150      mov r22=b0
   3.151 @@ -310,7 +274,7 @@ vmx_dtlb_out:
   3.152      VMX_FAULT(2);
   3.153  END(vmx_dtlb_miss)
   3.154  
   3.155 -	.org vmx_ia64_ivt+0x0c00
   3.156 +    .org vmx_ia64_ivt+0x0c00
   3.157  /////////////////////////////////////////////////////////////////////////////////////////
   3.158  // 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19)
   3.159  ENTRY(vmx_alt_itlb_miss)
   3.160 @@ -321,88 +285,84 @@ ENTRY(vmx_alt_itlb_miss)
   3.161      tbit.z p6,p7=r29,IA64_PSR_VM_BIT;
   3.162  (p7)br.spnt vmx_fault_3
   3.163  vmx_alt_itlb_miss_1:
   3.164 -	mov r16=cr.ifa		// get address that caused the TLB miss
   3.165 +    mov r16=cr.ifa    // get address that caused the TLB miss
   3.166      ;;
   3.167      tbit.z p6,p7=r16,63
   3.168  (p6)br.spnt vmx_fault_3
   3.169      ;;
   3.170 -	movl r17=PAGE_KERNEL
   3.171 -	mov r24=cr.ipsr
   3.172 -	movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
   3.173 -	;;
   3.174 -	and r19=r19,r16		// clear ed, reserved bits, and PTE control bits
   3.175 -	shr.u r18=r16,55	// move address bit 59 to bit 4
   3.176 -	;;
   3.177 -	and r18=0x10,r18	// bit 4=address-bit(61)
   3.178 -	or r19=r17,r19		// insert PTE control bits into r19
   3.179 -	;;
   3.180 -	movl r20=IA64_GRANULE_SHIFT<<2
   3.181 -	or r19=r19,r18		// set bit 4 (uncached) if the access was to region 6
   3.182 -	;;
   3.183 -	mov cr.itir=r20
   3.184 -	;;
   3.185 -	srlz.i
   3.186 -	;;
   3.187 -	itc.i r19		// insert the TLB entry
   3.188 -	mov pr=r31,-1
   3.189 -	rfi
   3.190 +    movl r17=PAGE_KERNEL
   3.191 +    mov r24=cr.ipsr
   3.192 +    movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
   3.193 +    ;;
   3.194 +    and r19=r19,r16     // clear ed, reserved bits, and PTE control bits
   3.195 +    shr.u r18=r16,55    // move address bit 59 to bit 4
   3.196 +    ;;
   3.197 +    and r18=0x10,r18    // bit 4=address-bit(61)
   3.198 +    or r19=r17,r19      // insert PTE control bits into r19
   3.199 +    ;;
   3.200 +    movl r20=IA64_GRANULE_SHIFT<<2
   3.201 +    or r19=r19,r18	// set bit 4 (uncached) if the access was to region 6
   3.202 +    ;;
   3.203 +    mov cr.itir=r20
   3.204 +    ;;
   3.205 +    itc.i r19		// insert the TLB entry
   3.206 +    mov pr=r31,-1
   3.207 +    rfi
   3.208      VMX_FAULT(3);
   3.209  END(vmx_alt_itlb_miss)
   3.210  
   3.211  
   3.212 -	.org vmx_ia64_ivt+0x1000
   3.213 +    .org vmx_ia64_ivt+0x1000
   3.214  /////////////////////////////////////////////////////////////////////////////////////////
   3.215  // 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46)
   3.216  ENTRY(vmx_alt_dtlb_miss)
   3.217      VMX_DBG_FAULT(4)
   3.218 -	mov r31=pr
   3.219 +    mov r31=pr
   3.220      mov r29=cr.ipsr;
   3.221      ;;
   3.222      tbit.z p6,p7=r29,IA64_PSR_VM_BIT;
   3.223  (p7)br.spnt vmx_fault_4
   3.224  vmx_alt_dtlb_miss_1:
   3.225 -	mov r16=cr.ifa		// get address that caused the TLB miss
   3.226 +    mov r16=cr.ifa		// get address that caused the TLB miss
   3.227      ;;
   3.228  #ifdef CONFIG_VIRTUAL_FRAME_TABLE
   3.229 -	// Test for the address of virtual frame_table
   3.230 -	shr r22=r16,56;;
   3.231 -	cmp.eq p8,p0=((VIRT_FRAME_TABLE_ADDR>>56)&0xff)-0x100,r22
   3.232 -(p8)	br.cond.sptk frametable_miss ;;
   3.233 +    // Test for the address of virtual frame_table
   3.234 +    shr r22=r16,56;;
   3.235 +    cmp.eq p8,p0=((VIRT_FRAME_TABLE_ADDR>>56)&0xff)-0x100,r22
   3.236 +(p8)br.cond.sptk frametable_miss ;;
   3.237  #endif
   3.238      tbit.z p6,p7=r16,63
   3.239  (p6)br.spnt vmx_fault_4
   3.240      ;;
   3.241 -	movl r17=PAGE_KERNEL
   3.242 -	mov r20=cr.isr
   3.243 -	movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
   3.244 -	mov r24=cr.ipsr
   3.245 -	;;
   3.246 -	and r22=IA64_ISR_CODE_MASK,r20		// get the isr.code field
   3.247 -	tbit.nz p6,p7=r20,IA64_ISR_SP_BIT	// is speculation bit on?
   3.248 -	shr.u r18=r16,55			// move address bit 59 to bit 4
   3.249 -	and r19=r19,r16				// clear ed, reserved bits, and PTE control bits
   3.250 -	tbit.nz p9,p0=r20,IA64_ISR_NA_BIT	// is non-access bit on?
   3.251 -	;;
   3.252 -	and r18=0x10,r18	// bit 4=address-bit(61)
   3.253 -(p9) cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22	// check isr.code field
   3.254 -	dep r24=-1,r24,IA64_PSR_ED_BIT,1
   3.255 -	or r19=r19,r17		// insert PTE control bits into r19
   3.256 -	;;
   3.257 -	or r19=r19,r18		// set bit 4 (uncached) if the access was to region 6
   3.258 -(p6) mov cr.ipsr=r24
   3.259 -	movl r20=IA64_GRANULE_SHIFT<<2
   3.260 -	;;
   3.261 -	mov cr.itir=r20
   3.262 -	;;
   3.263 -	srlz.i
   3.264 -	;;
   3.265 -(p7) itc.d r19		// insert the TLB entry
   3.266 -	mov pr=r31,-1
   3.267 -	rfi
   3.268 +    movl r17=PAGE_KERNEL
   3.269 +    mov r20=cr.isr
   3.270 +    movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
   3.271 +    mov r24=cr.ipsr
   3.272 +    ;;
   3.273 +    and r22=IA64_ISR_CODE_MASK,r20		// get the isr.code field
   3.274 +    tbit.nz p6,p7=r20,IA64_ISR_SP_BIT		// is speculation bit on?
   3.275 +    shr.u r18=r16,55				// move address bit 59 to bit 4
   3.276 +    and r19=r19,r16				// clear ed, reserved bits, and PTE control bits
   3.277 +    tbit.nz p9,p0=r20,IA64_ISR_NA_BIT		// is non-access bit on?
   3.278 +    ;;
   3.279 +    and r18=0x10,r18				// bit 4=address-bit(61)
   3.280 +(p9)cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22	// check isr.code field
   3.281 +    dep r24=-1,r24,IA64_PSR_ED_BIT,1
   3.282 +    or r19=r19,r17				// insert PTE control bits into r19
   3.283 +    ;;
   3.284 +    or r19=r19,r18				// set bit 4 (uncached) if the access was to region 6
   3.285 +(p6)mov cr.ipsr=r24
   3.286 +    movl r20=IA64_GRANULE_SHIFT<<2
   3.287 +    ;;
   3.288 +    mov cr.itir=r20
   3.289 +    ;;
   3.290 +(p7)itc.d r19		// insert the TLB entry
   3.291 +    mov pr=r31,-1
   3.292 +    rfi
   3.293      VMX_FAULT(4);
   3.294  END(vmx_alt_dtlb_miss)
   3.295  
   3.296 -	.org vmx_ia64_ivt+0x1400
   3.297 +    .org vmx_ia64_ivt+0x1400
   3.298  /////////////////////////////////////////////////////////////////////////////////////////
   3.299  // 0x1400 Entry 5 (size 64 bundles) Data nested TLB (6,45)
   3.300  ENTRY(vmx_nested_dtlb_miss)
     4.1 --- a/xen/arch/ia64/vmx/vmx_process.c	Tue May 30 08:46:21 2006 -0600
     4.2 +++ b/xen/arch/ia64/vmx/vmx_process.c	Tue May 30 10:28:59 2006 -0600
     4.3 @@ -302,7 +302,7 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
     4.4  {
     4.5      IA64_PSR vpsr;
     4.6      int type=ISIDE_TLB;
     4.7 -    u64 vhpt_adr, gppa;
     4.8 +    u64 vhpt_adr, gppa, pteval, rr, itir;
     4.9      ISR misr;
    4.10  //    REGS *regs;
    4.11      thash_data_t *data;
    4.12 @@ -314,18 +314,6 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
    4.13      vpsr.val = vmx_vcpu_get_psr(v);
    4.14      misr.val=VMX(v,cr_isr);
    4.15  
    4.16 -/*  TODO
    4.17 -    if(v->domain->id && vec == 2 &&
    4.18 -       vpsr.dt == 0 && is_gpa_io(MASK_PMA(vaddr))){
    4.19 -        emulate_ins(&v);
    4.20 -        return;
    4.21 -    }
    4.22 -*/
    4.23 -/*    if(vadr == 0x1ea18c00 ){
    4.24 -        ia64_clear_ic();
    4.25 -        while(1);
    4.26 -    }
    4.27 - */
    4.28      if(is_physical_mode(v)&&(!(vadr<<1>>62))){
    4.29          if(vec==2){
    4.30              if(v->domain!=dom0&&__gpfn_is_io(v->domain,(vadr<<1)>>(PAGE_SHIFT+1))){
    4.31 @@ -338,31 +326,24 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
    4.32      }
    4.33      if(vec == 1) type = ISIDE_TLB;
    4.34      else if(vec == 2) type = DSIDE_TLB;
    4.35 -    else panic_domain(regs,"wrong vec:%0xlx\n",vec);
    4.36 +    else panic_domain(regs,"wrong vec:%lx\n",vec);
    4.37  
    4.38  //    prepare_if_physical_mode(v);
    4.39  
    4.40      if((data=vtlb_lookup(v, vadr,type))!=0){
    4.41 -//	gppa = (vadr&((1UL<<data->ps)-1))+(data->ppn>>(data->ps-12)<<data->ps);
    4.42 -//        if(v->domain!=dom0&&type==DSIDE_TLB && __gpfn_is_io(v->domain,gppa>>PAGE_SHIFT)){
    4.43 +//       gppa = (vadr&((1UL<<data->ps)-1))+(data->ppn>>(data->ps-12)<<data->ps);
    4.44 +//       if(v->domain!=dom0&&type==DSIDE_TLB && __gpfn_is_io(v->domain,gppa>>PAGE_SHIFT)){
    4.45          if(v->domain!=dom0 && data->io && type==DSIDE_TLB ){
    4.46 -        	gppa = (vadr&((1UL<<data->ps)-1))+(data->ppn>>(data->ps-12)<<data->ps);
    4.47 -            emulate_io_inst(v, gppa, data->ma);
    4.48 +            if(data->pl >= ((regs->cr_ipsr>>IA64_PSR_CPL0_BIT)&3)){
    4.49 +                gppa = (vadr&((1UL<<data->ps)-1))+(data->ppn>>(data->ps-12)<<data->ps);
    4.50 +                emulate_io_inst(v, gppa, data->ma);
    4.51 +            }else{
    4.52 +                data_access_rights(v, vadr);
    4.53 +            }
    4.54              return IA64_FAULT;
    4.55          }
    4.56  
    4.57 -//    	if ( data->ps != vrr.ps ) {
    4.58 -//    		machine_tlb_insert(v, data);
    4.59 -//    	}
    4.60 -//    	else {
    4.61 -/*        if ( data->contiguous&&(!data->tc)){
    4.62 -    		machine_tlb_insert(v, data);
    4.63 -        }
    4.64 -        else{
    4.65 - */
    4.66 -            thash_vhpt_insert(&v->arch.vhpt,data->page_flags, data->itir ,vadr);
    4.67 -//        }
    4.68 -//	    }
    4.69 +        thash_vhpt_insert(v,data->page_flags, data->itir ,vadr);
    4.70      }else if(type == DSIDE_TLB){
    4.71          if(!vhpt_enabled(v, vadr, misr.rs?RSE_REF:DATA_REF)){
    4.72              if(vpsr.ic){
    4.73 @@ -381,7 +362,13 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
    4.74              }
    4.75          } else{
    4.76              vmx_vcpu_thash(v, vadr, &vhpt_adr);
    4.77 -            if(vhpt_lookup(vhpt_adr) ||  vtlb_lookup(v, vhpt_adr, DSIDE_TLB)){
    4.78 +            if(!guest_vhpt_lookup(vhpt_adr, &pteval)){
    4.79 +                if (pteval & _PAGE_P){
    4.80 +                    vcpu_get_rr(v, vadr, &rr);
    4.81 +                    itir = rr&(RR_RID_MASK | RR_PS_MASK);
    4.82 +                    thash_purge_and_insert(v, pteval, itir , vadr);
    4.83 +                    return IA64_NO_FAULT;
    4.84 +                }
    4.85                  if(vpsr.ic){
    4.86                      vcpu_set_isr(v, misr.val);
    4.87                      dtlb_fault(v, vadr);
    4.88 @@ -423,7 +410,13 @@ vmx_hpw_miss(u64 vadr , u64 vec, REGS* r
    4.89              return IA64_FAULT;
    4.90          } else{
    4.91              vmx_vcpu_thash(v, vadr, &vhpt_adr);
    4.92 -            if(vhpt_lookup(vhpt_adr) || vtlb_lookup(v, vhpt_adr, DSIDE_TLB)){
    4.93 +            if(!guest_vhpt_lookup(vhpt_adr, &pteval)){
    4.94 +                if (pteval & _PAGE_P){
    4.95 +                    vcpu_get_rr(v, vadr, &rr);
    4.96 +                    itir = rr&(RR_RID_MASK | RR_PS_MASK);
    4.97 +                    thash_purge_and_insert(v, pteval, itir , vadr);
    4.98 +                    return IA64_NO_FAULT;
    4.99 +                }
   4.100                  if(!vpsr.ic){
   4.101                      misr.ni=1;
   4.102                  }
     5.1 --- a/xen/arch/ia64/vmx/vtlb.c	Tue May 30 08:46:21 2006 -0600
     5.2 +++ b/xen/arch/ia64/vmx/vtlb.c	Tue May 30 10:28:59 2006 -0600
     5.3 @@ -36,27 +36,26 @@ thash_data_t *__alloc_chain(thash_cb_t *
     5.4  
     5.5  static void cch_mem_init(thash_cb_t *hcb)
     5.6  {
     5.7 -    thash_data_t *p, *q;
     5.8 +    int num;
     5.9 +    thash_data_t *p;
    5.10  
    5.11      hcb->cch_freelist = p = hcb->cch_buf;
    5.12 -
    5.13 -    for ( q=p+1; (u64)(q + 1) <= (u64)hcb->cch_buf + hcb->cch_sz;
    5.14 -        p++, q++ ) {
    5.15 -        p->next = q;
    5.16 -    }
    5.17 +    num = (hcb->cch_sz/sizeof(thash_data_t))-1;
    5.18 +    do{
    5.19 +        p->next =p+1;
    5.20 +        p++;
    5.21 +        num--;
    5.22 +    }while(num);
    5.23      p->next = NULL;
    5.24  }
    5.25  
    5.26  static thash_data_t *cch_alloc(thash_cb_t *hcb)
    5.27  {
    5.28      thash_data_t *p;
    5.29 -
    5.30      if ( (p = hcb->cch_freelist) != NULL ) {
    5.31          hcb->cch_freelist = p->next;
    5.32 -        return p;
    5.33 -    }else{
    5.34 -        return NULL;
    5.35      }
    5.36 +    return p;
    5.37  }
    5.38  
    5.39  static void cch_free(thash_cb_t *hcb, thash_data_t *cch)
    5.40 @@ -101,17 +100,13 @@ static int
    5.41  static void __rem_hash_head(thash_cb_t *hcb, thash_data_t *hash)
    5.42  {
    5.43      thash_data_t *next=hash->next;
    5.44 -
    5.45 -/*    if ( hcb->remove_notifier ) {
    5.46 -        (hcb->remove_notifier)(hcb,hash);
    5.47 -    } */
    5.48 -    if ( next != NULL ) {
    5.49 +    if ( next) {
    5.50          next->len=hash->len-1;
    5.51          *hash = *next;
    5.52          cch_free (hcb, next);
    5.53      }
    5.54      else {
    5.55 -        INVALIDATE_HASH_HEADER(hcb, hash);
    5.56 +        hash->ti=1;
    5.57      }
    5.58  }
    5.59  
    5.60 @@ -145,125 +140,109 @@ thash_data_t *__vtr_lookup(VCPU *vcpu, u
    5.61  }
    5.62  
    5.63  
    5.64 -/*
    5.65 - * Get the machine format of VHPT entry.
    5.66 - *    PARAS:
    5.67 - *  1: tlb: means the tlb format hash entry converting to VHPT.
    5.68 - *  2: va means the guest virtual address that must be coverd by
    5.69 - *     the translated machine VHPT.
    5.70 - *  3: vhpt: means the machine format VHPT converting from tlb.
    5.71 - *    NOTES:
    5.72 - *  1: In case of the machine address is discontiguous,
    5.73 - *     "tlb" needs to be covered by several machine VHPT. va
    5.74 - *     is used to choice one of them.
    5.75 - *  2: Foreign map is supported in this API.
    5.76 - *    RETURN:
    5.77 - *  0/1: means successful or fail.
    5.78 - *
    5.79 - */
    5.80 -int __tlb_to_vhpt(thash_cb_t *hcb, thash_data_t *vhpt, u64 va)
    5.81 -{
    5.82 -    u64 padr,pte;
    5.83 -    ASSERT ( hcb->ht == THASH_VHPT );
    5.84 -    padr = vhpt->ppn >>(vhpt->ps-ARCH_PAGE_SHIFT)<<vhpt->ps;
    5.85 -    padr += va&((1UL<<vhpt->ps)-1);
    5.86 -    pte=lookup_domain_mpa(current->domain,padr);
    5.87 -    if((pte>>56))
    5.88 -        return 0;
    5.89 -    vhpt->etag = ia64_ttag(va);
    5.90 -    vhpt->ps = PAGE_SHIFT;
    5.91 -    vhpt->ppn = (pte&((1UL<<IA64_MAX_PHYS_BITS)-(1UL<<PAGE_SHIFT)))>>ARCH_PAGE_SHIFT;
    5.92 -    vhpt->next = 0;
    5.93 -    return 1;
    5.94 -}
    5.95 -
    5.96 -static void thash_remove_cch(thash_cb_t *hcb, thash_data_t *hash)
    5.97 +static void thash_recycle_cch(thash_cb_t *hcb, thash_data_t *hash)
    5.98  {
    5.99      thash_data_t *p;
   5.100 -    if(hash->next){
   5.101 -        p=hash->next;
   5.102 -        while(p->next)
   5.103 -            p=p->next;
   5.104 -        p->next=hcb->cch_freelist;
   5.105 -        hcb->cch_freelist=hash->next;
   5.106 -        hash->next=0;
   5.107 -        hash->len=0;
   5.108 +    int i=0;
   5.109 +    
   5.110 +    p=hash;
   5.111 +    for(i=0; i < MAX_CCN_DEPTH; i++){
   5.112 +        p=p->next;
   5.113      }
   5.114 +    p->next=hcb->cch_freelist;
   5.115 +    hcb->cch_freelist=hash->next;
   5.116 +    hash->len=0;
   5.117 +    hash->next=0;
   5.118  }
   5.119  
   5.120 -/*  vhpt only has entries with PAGE_SIZE page size */
   5.121 -
   5.122 -void thash_vhpt_insert(thash_cb_t *hcb, u64 pte, u64 itir, u64 ifa)
   5.123 -{
   5.124 -    thash_data_t   vhpt_entry, *hash_table, *cch;
   5.125 -    vhpt_entry.page_flags = pte & ~PAGE_FLAGS_RV_MASK;
   5.126 -    vhpt_entry.itir=itir;
   5.127  
   5.128 -    if ( !__tlb_to_vhpt(hcb, &vhpt_entry, ifa) ) {
   5.129 -        return;
   5.130 -    //panic("Can't convert to machine VHPT entry\n");
   5.131 -    }
   5.132  
   5.133 -    hash_table = (thash_data_t *)ia64_thash(ifa);
   5.134 -    if( INVALID_VHPT(hash_table) ) {
   5.135 -        *hash_table = vhpt_entry;
   5.136 -        hash_table->next = 0;
   5.137 -	return;
   5.138 +
   5.139 +static void vmx_vhpt_insert(thash_cb_t *hcb, u64 pte, u64 itir, u64 ifa)
   5.140 +{
   5.141 +    u64 tag;
   5.142 +    thash_data_t *head, *cch;
   5.143 +    pte = pte & ~PAGE_FLAGS_RV_MASK;
   5.144 +
   5.145 +    head = (thash_data_t *)ia64_thash(ifa);
   5.146 +    tag = ia64_ttag(ifa);
   5.147 +    if( INVALID_VHPT(head) ) {
   5.148 +        head->page_flags = pte;
   5.149 +        head->etag = tag;
   5.150 +        return;
   5.151      }
   5.152  
   5.153 -    cch = hash_table;
   5.154 -    while(cch){
   5.155 -        if(cch->etag == vhpt_entry.etag){
   5.156 -            if(cch->ppn == vhpt_entry.ppn)
   5.157 -                return;
   5.158 -            else
   5.159 -                while(1);
   5.160 -        }
   5.161 -        cch = cch->next;
   5.162 +    if(head->len>=MAX_CCN_DEPTH){
   5.163 +        thash_recycle_cch(hcb, head);
   5.164 +        cch = cch_alloc(hcb);
   5.165      }
   5.166 -
   5.167 -    if(hash_table->len>=MAX_CCN_DEPTH){
   5.168 -    	thash_remove_cch(hcb, hash_table);
   5.169 -    	cch = cch_alloc(hcb);
   5.170 -    	*cch = *hash_table;
   5.171 -        *hash_table = vhpt_entry;
   5.172 -    	hash_table->len = 1;
   5.173 -        hash_table->next = cch;
   5.174 -    	return;
   5.175 +    else{
   5.176 +        cch = __alloc_chain(hcb);
   5.177      }
   5.178 -
   5.179 -    // TODO: Add collision chain length limitation.
   5.180 -     cch = __alloc_chain(hcb);
   5.181 -     if(cch == NULL){
   5.182 -           *hash_table = vhpt_entry;
   5.183 -            hash_table->next = 0;
   5.184 -     }else{
   5.185 -            *cch = *hash_table;
   5.186 -            *hash_table = vhpt_entry;
   5.187 -            hash_table->next = cch;
   5.188 -    	    hash_table->len = cch->len + 1;
   5.189 -    	    cch->len = 0;
   5.190 -
   5.191 -    }
   5.192 -    return /*hash_table*/;
   5.193 +    cch->page_flags=head->page_flags;
   5.194 +    cch->etag=head->etag;
   5.195 +    cch->next=head->next;
   5.196 +    head->page_flags=pte;
   5.197 +    head->etag=tag;
   5.198 +    head->next = cch;
   5.199 +    head->len = cch->len+1;
   5.200 +    cch->len = 0;
   5.201 +    return;
   5.202  }
   5.203  
   5.204 +void thash_vhpt_insert(VCPU *v, u64 pte, u64 itir, u64 va)
   5.205 +{
   5.206 +    u64 phy_pte;
   5.207 +    phy_pte=translate_phy_pte(v, &pte, itir, va);
   5.208 +    vmx_vhpt_insert(vcpu_get_vhpt(v), phy_pte, itir, va);
   5.209 +}
   5.210  /*
   5.211   *   vhpt lookup
   5.212   */
   5.213  
   5.214  thash_data_t * vhpt_lookup(u64 va)
   5.215  {
   5.216 -    thash_data_t *hash;
   5.217 -    u64 tag;
   5.218 -    hash = (thash_data_t *)ia64_thash(va);
   5.219 +    thash_data_t *hash, *head;
   5.220 +    u64 tag, pte;
   5.221 +    head = (thash_data_t *)ia64_thash(va);
   5.222 +    hash=head;
   5.223      tag = ia64_ttag(va);
   5.224 -    while(hash){
   5.225 -    	if(hash->etag == tag)
   5.226 -	        return hash;
   5.227 +    do{
   5.228 +        if(hash->etag == tag)
   5.229 +            break;
   5.230          hash=hash->next;
   5.231 +    }while(hash);
   5.232 +    if(hash && hash!=head){
   5.233 +        pte = hash->page_flags;
   5.234 +        hash->page_flags = head->page_flags;
   5.235 +        head->page_flags = pte;
   5.236 +        tag = hash->etag;
   5.237 +        hash->etag = head->etag;
   5.238 +        head->etag = tag;
   5.239 +        head->len = hash->len;
   5.240 +        hash->len=0;
   5.241 +        return head;
   5.242      }
   5.243 -    return NULL;
   5.244 +    return hash;
   5.245 +}
   5.246 +
   5.247 +u64 guest_vhpt_lookup(u64 iha, u64 *pte)
   5.248 +{
   5.249 +    u64 ret;
   5.250 +    vhpt_lookup(iha);
   5.251 +    asm volatile ("rsm psr.ic|psr.i;;"
   5.252 +                  "srlz.d;;"
   5.253 +                  "ld8.s r9=[%1];;"
   5.254 +                  "tnat.nz p6,p7=r9;;"
   5.255 +                  "(p6) mov %0=1;"
   5.256 +                  "(p6) mov r9=r0;"
   5.257 +                  "(p7) mov %0=r0;"
   5.258 +                  "(p7) st8 [%2]=r9;;"
   5.259 +                  "ssm psr.ic;;"
   5.260 +                  "srlz.d;;"
   5.261 +                  "ssm psr.i;;"
   5.262 +             : "=r"(ret) : "r"(iha), "r"(pte):"memory");
   5.263 +    return ret;
   5.264  }
   5.265  
   5.266  
   5.267 @@ -310,7 +289,6 @@ static void vtlb_purge(thash_cb_t *hcb, 
   5.268  /*
   5.269   *  purge VHPT and machine TLB
   5.270   */
   5.271 -
   5.272  static void vhpt_purge(thash_cb_t *hcb, u64 va, u64 ps)
   5.273  {
   5.274      thash_data_t *hash_table, *prev, *next;
   5.275 @@ -332,7 +310,7 @@ static void vhpt_purge(thash_cb_t *hcb, 
   5.276                      prev->next=next->next;
   5.277                      cch_free(hcb,next);
   5.278                      hash_table->len--;
   5.279 -                    break;
   5.280 +                    break; 
   5.281                  }
   5.282                  prev=next;
   5.283                  next=next->next;
   5.284 @@ -347,16 +325,21 @@ static void vhpt_purge(thash_cb_t *hcb, 
   5.285   * Recycle all collisions chain in VTLB or VHPT.
   5.286   *
   5.287   */
   5.288 -
   5.289 -void thash_recycle_cch(thash_cb_t *hcb)
   5.290 +void thash_recycle_cch_all(thash_cb_t *hcb)
   5.291  {
   5.292 -    thash_data_t    *hash_table;
   5.293 +    int num;
   5.294 +    thash_data_t *head;
   5.295 +    head=hcb->hash;
   5.296 +    num = (hcb->hash_sz/sizeof(thash_data_t));
   5.297 +    do{
   5.298 +        head->len = 0;
   5.299 +        head->next = 0;
   5.300 +        head++;
   5.301 +        num--;
   5.302 +    }while(num);
   5.303 +    cch_mem_init(hcb);
   5.304 +}
   5.305  
   5.306 -    hash_table = (thash_data_t*)((u64)hcb->hash + hcb->hash_sz);
   5.307 -    for (--hash_table;(u64)hash_table >= (u64)hcb->hash;hash_table--) {
   5.308 -        thash_remove_cch(hcb,hash_table);
   5.309 -    }
   5.310 -}
   5.311  
   5.312  thash_data_t *__alloc_chain(thash_cb_t *hcb)
   5.313  {
   5.314 @@ -364,7 +347,7 @@ thash_data_t *__alloc_chain(thash_cb_t *
   5.315  
   5.316      cch = cch_alloc(hcb);
   5.317      if(cch == NULL){
   5.318 -        thash_recycle_cch(hcb);
   5.319 +        thash_recycle_cch_all(hcb);
   5.320          cch = cch_alloc(hcb);
   5.321      }
   5.322      return cch;
   5.323 @@ -385,51 +368,38 @@ void vtlb_insert(thash_cb_t *hcb, u64 pt
   5.324      /* int flag; */
   5.325      ia64_rr vrr;
   5.326      /* u64 gppn, ppns, ppne; */
   5.327 -    u64 tag, ps;
   5.328 -    ps = itir_ps(itir);
   5.329 +    u64 tag;
   5.330      vcpu_get_rr(current, va, &vrr.rrval);
   5.331 -    if (vrr.ps != ps) {
   5.332 +#ifdef VTLB_DEBUG    
   5.333 +    if (vrr.ps != itir_ps(itir)) {
   5.334  //        machine_tlb_insert(hcb->vcpu, entry);
   5.335          panic_domain(NULL, "not preferred ps with va: 0x%lx vrr.ps=%d ps=%ld\n",
   5.336 -                     va, vrr.ps, ps);
   5.337 +             va, vrr.ps, itir_ps(itir));
   5.338          return;
   5.339      }
   5.340 +#endif
   5.341      hash_table = vsa_thash(hcb->pta, va, vrr.rrval, &tag);
   5.342      if( INVALID_TLB(hash_table) ) {
   5.343          hash_table->page_flags = pte;
   5.344          hash_table->itir=itir;
   5.345          hash_table->etag=tag;
   5.346          hash_table->next = 0;
   5.347 +        return;
   5.348      }
   5.349 -    else if (hash_table->len>=MAX_CCN_DEPTH){
   5.350 -        thash_remove_cch(hcb, hash_table);
   5.351 +    if (hash_table->len>=MAX_CCN_DEPTH){
   5.352 +        thash_recycle_cch(hcb, hash_table);
   5.353          cch = cch_alloc(hcb);
   5.354 -        *cch = *hash_table;
   5.355 -        hash_table->page_flags = pte;
   5.356 -        hash_table->itir=itir;
   5.357 -        hash_table->etag=tag;
   5.358 -        hash_table->len = 1;
   5.359 -        hash_table->next = cch;
   5.360      }
   5.361 -
   5.362      else {
   5.363 -        // TODO: Add collision chain length limitation.
   5.364          cch = __alloc_chain(hcb);
   5.365 -        if(cch == NULL){
   5.366 -            hash_table->page_flags = pte;
   5.367 -            hash_table->itir=itir;
   5.368 -            hash_table->etag=tag;
   5.369 -            hash_table->next = 0;
   5.370 -        }else{
   5.371 -            *cch = *hash_table;
   5.372 -            hash_table->page_flags = pte;
   5.373 -            hash_table->itir=itir;
   5.374 -            hash_table->etag=tag;
   5.375 -            hash_table->next = cch;
   5.376 -            hash_table->len = cch->len + 1;
   5.377 -            cch->len = 0;
   5.378 -        }
   5.379      }
   5.380 +    *cch = *hash_table;
   5.381 +    hash_table->page_flags = pte;
   5.382 +    hash_table->itir=itir;
   5.383 +    hash_table->etag=tag;
   5.384 +    hash_table->next = cch;
   5.385 +    hash_table->len = cch->len + 1;
   5.386 +    cch->len = 0;
   5.387      return ;
   5.388  }
   5.389  
   5.390 @@ -473,6 +443,23 @@ void thash_purge_entries(VCPU *v, u64 va
   5.391      vhpt_purge(&v->arch.vhpt, va, ps);
   5.392  }
   5.393  
   5.394 +u64 translate_phy_pte(VCPU *v, u64 *pte, u64 itir, u64 va)
   5.395 +{
   5.396 +    u64 ps, addr;
   5.397 +    union pte_flags phy_pte;
   5.398 +    ps = itir_ps(itir);
   5.399 +    phy_pte.val = *pte;
   5.400 +    addr = *pte;
   5.401 +    addr = ((addr & _PAGE_PPN_MASK)>>ps<<ps)|(va&((1UL<<ps)-1));
   5.402 +    addr = lookup_domain_mpa(v->domain, addr);
   5.403 +    if(addr & GPFN_IO_MASK){
   5.404 +        *pte |= VTLB_PTE_IO;
   5.405 +        return -1;
   5.406 +    }
   5.407 +    phy_pte.ppn = addr >> ARCH_PAGE_SHIFT;
   5.408 +    return phy_pte.val;
   5.409 +}
   5.410 +
   5.411  
   5.412  /*
   5.413   * Purge overlap TCs and then insert the new entry to emulate itc ops.
   5.414 @@ -480,59 +467,79 @@ void thash_purge_entries(VCPU *v, u64 va
   5.415   */
   5.416  void thash_purge_and_insert(VCPU *v, u64 pte, u64 itir, u64 ifa)
   5.417  {
   5.418 -    u64 ps, va;
   5.419 +    u64 ps;//, va;
   5.420 +    u64 phy_pte;
   5.421      ps = itir_ps(itir);
   5.422 -    va = PAGEALIGN(ifa,ps);
   5.423 -    if(vcpu_quick_region_check(v->arch.tc_regions,va))
   5.424 -        vtlb_purge(&v->arch.vtlb, va, ps);
   5.425 -    vhpt_purge(&v->arch.vhpt, va, ps);
   5.426 -    if((ps!=PAGE_SHIFT)||(pte&VTLB_PTE_IO)){
   5.427 -        vtlb_insert(&v->arch.vtlb, pte, itir, va);
   5.428 -	vcpu_quick_region_set(PSCBX(v,tc_regions),va);
   5.429 -    }	
   5.430 -    if(!(pte&VTLB_PTE_IO)){
   5.431 -        va = PAGEALIGN(ifa,PAGE_SHIFT);
   5.432 -        thash_vhpt_insert(&v->arch.vhpt, pte, itir, va);
   5.433 +
   5.434 +    if(VMX_DOMAIN(v)){
   5.435 +        phy_pte = translate_phy_pte(v, &pte, itir, ifa);
   5.436 +        if(ps==PAGE_SHIFT){
   5.437 +            if(!(pte&VTLB_PTE_IO)){
   5.438 +                vhpt_purge(&v->arch.vhpt, ifa, ps);
   5.439 +                vmx_vhpt_insert(&v->arch.vhpt, phy_pte, itir, ifa);
   5.440 +            }
   5.441 +            else{
   5.442 +                vhpt_purge(&v->arch.vhpt, ifa, ps);
   5.443 +                vtlb_insert(&v->arch.vtlb, pte, itir, ifa);
   5.444 +                vcpu_quick_region_set(PSCBX(v,tc_regions),ifa);
   5.445 +            }
   5.446 +        }
   5.447 +        else{
   5.448 +            vhpt_purge(&v->arch.vhpt, ifa, ps);
   5.449 +            vtlb_insert(&v->arch.vtlb, pte, itir, ifa);
   5.450 +            vcpu_quick_region_set(PSCBX(v,tc_regions),ifa);
   5.451 +            if(!(pte&VTLB_PTE_IO)){
   5.452 +                vmx_vhpt_insert(&v->arch.vhpt, phy_pte, itir, ifa);
   5.453 +            }
   5.454 +        }
   5.455 +    }
   5.456 +    else{
   5.457 +        phy_pte = translate_phy_pte(v, &pte, itir, ifa);
   5.458 +        if(ps!=PAGE_SHIFT){
   5.459 +            vtlb_insert(&v->arch.vtlb, pte, itir, ifa);
   5.460 +            vcpu_quick_region_set(PSCBX(v,tc_regions),ifa);
   5.461 +        }
   5.462 +        machine_tlb_purge(ifa, ps);
   5.463 +        vmx_vhpt_insert(&v->arch.vhpt, phy_pte, itir, ifa);
   5.464      }
   5.465  }
   5.466  
   5.467 -
   5.468 -
   5.469  /*
   5.470   * Purge all TCs or VHPT entries including those in Hash table.
   5.471   *
   5.472   */
   5.473  
   5.474 -// TODO: add sections.
   5.475 +//TODO: add sections.
   5.476  void thash_purge_all(VCPU *v)
   5.477  {
   5.478 -    thash_data_t    *hash_table;
   5.479 -    /* thash_data_t    *entry; */
   5.480 -    thash_cb_t  *hcb,*vhpt;
   5.481 -    /* u64 i, start, end; */
   5.482 -    hcb =&v->arch.vtlb;
   5.483 +    int num;
   5.484 +    thash_data_t *head;
   5.485 +    thash_cb_t  *vtlb,*vhpt;
   5.486 +    vtlb =&v->arch.vtlb;
   5.487      vhpt =&v->arch.vhpt;
   5.488 -#ifdef  VTLB_DEBUG
   5.489 -	extern u64  sanity_check;
   5.490 -    static u64 statistics_before_purge_all=0;
   5.491 -    if ( statistics_before_purge_all ) {
   5.492 -    	sanity_check = 1;
   5.493 -        check_vtlb_sanity(hcb);
   5.494 -    }
   5.495 -#endif
   5.496 -    ASSERT ( hcb->ht == THASH_TLB );
   5.497  
   5.498 -    hash_table = (thash_data_t*)((u64)hcb->hash + hcb->hash_sz);
   5.499 -    for (--hash_table;(u64)hash_table >= (u64)hcb->hash;hash_table--) {
   5.500 -        INVALIDATE_TLB_HEADER(hash_table);
   5.501 -    }
   5.502 -    cch_mem_init (hcb);
   5.503 +    head=vtlb->hash;
   5.504 +    num = (vtlb->hash_sz/sizeof(thash_data_t));
   5.505 +    do{
   5.506 +        head->page_flags = 0;
   5.507 +        head->etag = 1UL<<63;
   5.508 +        head->next = 0;
   5.509 +        head++;
   5.510 +        num--;
   5.511 +    }while(num);
   5.512 +    cch_mem_init(vtlb);
   5.513 +    
   5.514 +    head=vhpt->hash;
   5.515 +    num = (vhpt->hash_sz/sizeof(thash_data_t));
   5.516 +    do{
   5.517 +        head->page_flags = 0;
   5.518 +        head->etag = 1UL<<63;
   5.519 +        head->next = 0;
   5.520 +        head++;
   5.521 +        num--;
   5.522 +    }while(num);
   5.523 +    cch_mem_init(vhpt);
   5.524  
   5.525 -    hash_table = (thash_data_t*)((u64)vhpt->hash + vhpt->hash_sz);
   5.526 -    for (--hash_table;(u64)hash_table >= (u64)vhpt->hash;hash_table--) {
   5.527 -        INVALIDATE_VHPT_HEADER(hash_table);
   5.528 -    }
   5.529 -    cch_mem_init (vhpt);
   5.530      local_flush_tlb_all();
   5.531  }
   5.532  
   5.533 @@ -547,7 +554,7 @@ void thash_purge_all(VCPU *v)
   5.534  
   5.535  thash_data_t *vtlb_lookup(VCPU *v, u64 va,int is_data)
   5.536  {
   5.537 -    thash_data_t    *hash_table, *cch;
   5.538 +    thash_data_t  *cch;
   5.539      u64     tag;
   5.540      ia64_rr vrr;
   5.541      thash_cb_t * hcb= &v->arch.vtlb;
   5.542 @@ -559,18 +566,14 @@ thash_data_t *vtlb_lookup(VCPU *v, u64 v
   5.543      if(vcpu_quick_region_check(v->arch.tc_regions,va)==0)
   5.544          return NULL;
   5.545      
   5.546 -
   5.547      vcpu_get_rr(v,va,&vrr.rrval);
   5.548 -    hash_table = vsa_thash( hcb->pta, va, vrr.rrval, &tag);
   5.549 +    cch = vsa_thash( hcb->pta, va, vrr.rrval, &tag);
   5.550  
   5.551 -    if ( INVALID_ENTRY(hcb, hash_table ) )
   5.552 -        return NULL;
   5.553 -
   5.554 -
   5.555 -    for (cch=hash_table; cch; cch = cch->next) {
   5.556 +    do{
   5.557          if(cch->etag == tag)
   5.558              return cch;
   5.559 -    }
   5.560 +        cch = cch->next;
   5.561 +    }while(cch);
   5.562      return NULL;
   5.563  }
   5.564  
   5.565 @@ -580,198 +583,32 @@ thash_data_t *vtlb_lookup(VCPU *v, u64 v
   5.566   */
   5.567  void thash_init(thash_cb_t *hcb, u64 sz)
   5.568  {
   5.569 -    thash_data_t    *hash_table;
   5.570 +    int num;
   5.571 +    thash_data_t *head, *p;
   5.572  
   5.573 -    cch_mem_init (hcb);
   5.574      hcb->pta.val = (unsigned long)hcb->hash;
   5.575      hcb->pta.vf = 1;
   5.576      hcb->pta.ve = 1;
   5.577      hcb->pta.size = sz;
   5.578 -//    hcb->get_rr_fn = vmmu_get_rr;
   5.579 -    ASSERT ( hcb->hash_sz % sizeof(thash_data_t) == 0 );
   5.580 -    hash_table = (thash_data_t*)((u64)hcb->hash + hcb->hash_sz);
   5.581 -
   5.582 -    for (--hash_table;(u64)hash_table >= (u64)hcb->hash;hash_table--) {
   5.583 -        INVALIDATE_HASH_HEADER(hcb,hash_table);
   5.584 -    }
   5.585 -}
   5.586 -
   5.587 -#ifdef  VTLB_DEBUG
   5.588 -/*
   5.589 -static  u64 cch_length_statistics[MAX_CCH_LENGTH+1];
   5.590 -u64  sanity_check=0;
   5.591 -u64 vtlb_chain_sanity(thash_cb_t *vtlb, thash_cb_t *vhpt, thash_data_t *hash)
   5.592 -{
   5.593 -    thash_data_t *cch;
   5.594 -    thash_data_t    *ovl;
   5.595 -    search_section_t s_sect;
   5.596 -    u64     num=0;
   5.597 -
   5.598 -    s_sect.v = 0;
   5.599 -    for (cch=hash; cch; cch=cch->next) {
   5.600 -        ovl = thash_find_overlap(vhpt, cch, s_sect);
   5.601 -        while ( ovl != NULL ) {
   5.602 -            ovl->checked = 1;
   5.603 -            ovl = (vhpt->next_overlap)(vhpt);
   5.604 -        };
   5.605 -        num ++;
   5.606 -    }
   5.607 -    if ( num >= MAX_CCH_LENGTH ) {
   5.608 -    	cch_length_statistics[MAX_CCH_LENGTH] ++;
   5.609 -    }
   5.610 -    else {
   5.611 -    	cch_length_statistics[num] ++;
   5.612 -    }
   5.613 -    return num;
   5.614 +    hcb->cch_rec_head = hcb->hash;
   5.615 +    
   5.616 +    head=hcb->hash;
   5.617 +    num = (hcb->hash_sz/sizeof(thash_data_t));
   5.618 +    do{
   5.619 +        head->itir = PAGE_SHIFT<<2;
   5.620 +        head->next = 0;
   5.621 +        head++;
   5.622 +        num--;
   5.623 +    }while(num);
   5.624 +    
   5.625 +    hcb->cch_freelist = p = hcb->cch_buf;
   5.626 +    num = (hcb->cch_sz/sizeof(thash_data_t))-1;
   5.627 +    do{
   5.628 +        p->itir = PAGE_SHIFT<<2;
   5.629 +        p->next =p+1;
   5.630 +        p++;
   5.631 +        num--;
   5.632 +    }while(num);
   5.633 +    p->itir = PAGE_SHIFT<<2;
   5.634 +    p->next = NULL;
   5.635  }
   5.636 -
   5.637 -void check_vtlb_sanity(thash_cb_t *vtlb)
   5.638 -{
   5.639 -//    struct page_info *page;
   5.640 -    u64  hash_num, i, psr;
   5.641 -    static u64 check_ok_num, check_fail_num,check_invalid;
   5.642 -//  void *vb1, *vb2;
   5.643 -    thash_data_t  *hash, *cch;
   5.644 -    thash_data_t    *ovl;
   5.645 -    search_section_t s_sect;
   5.646 -    thash_cb_t *vhpt = vtlb->vhpt;
   5.647 -    u64   invalid_ratio;
   5.648 - 
   5.649 -    if ( sanity_check == 0 ) return;
   5.650 -    sanity_check --;
   5.651 -    s_sect.v = 0;
   5.652 -//    page = alloc_domheap_pages (NULL, VCPU_TLB_ORDER, 0);
   5.653 -//    if ( page == NULL ) {
   5.654 -//        panic("No enough contiguous memory for init_domain_mm\n");
   5.655 -//    };
   5.656 -//    vb1 = page_to_virt(page);
   5.657 -//    printf("Allocated page=%lp vbase=%lp\n", page, vb1);
   5.658 -//    vb2 = vb1 + vtlb->hash_sz;
   5.659 -    hash_num = vhpt->hash_sz / sizeof(thash_data_t);
   5.660 -//    printf("vb2=%lp, size=%lx hash_num=%lx\n", vb2, vhpt->hash_sz, hash_num);
   5.661 -    printf("vtlb=%p, hash=%p size=0x%lx; vhpt=%p, hash=%p size=0x%lx\n", 
   5.662 -                vtlb, vtlb->hash,vtlb->hash_sz,
   5.663 -                vhpt, vhpt->hash, vhpt->hash_sz);
   5.664 -    //memcpy(vb1, vtlb->hash, vtlb->hash_sz);
   5.665 -    //memcpy(vb2, vhpt->hash, vhpt->hash_sz);
   5.666 -    for ( i=0; i < sizeof(cch_length_statistics)/sizeof(cch_length_statistics[0]); i++ ) {
   5.667 -    	cch_length_statistics[i] = 0;
   5.668 -    }
   5.669 -
   5.670 -    local_irq_save(psr);
   5.671 -
   5.672 -    hash = vhpt->hash;
   5.673 -    for (i=0; i < hash_num; i++) {
   5.674 -        if ( !INVALID_ENTRY(vhpt, hash) ) {
   5.675 -            for ( cch= hash; cch; cch=cch->next) {
   5.676 -                cch->checked = 0;
   5.677 -            }
   5.678 -        }
   5.679 -        hash ++;
   5.680 -    }
   5.681 -    printf("Done vhpt clear checked flag, hash_num=0x%lx\n", hash_num);
   5.682 -    check_invalid = 0;
   5.683 -    check_ok_num=0;
   5.684 -    hash = vtlb->hash;
   5.685 -    for ( i=0; i< hash_num; i++ ) {
   5.686 -        if ( !INVALID_ENTRY(vtlb, hash) ) {
   5.687 -            check_ok_num += vtlb_chain_sanity(vtlb, vhpt, hash);
   5.688 -        }
   5.689 -        else {
   5.690 -            check_invalid++;
   5.691 -        }
   5.692 -        hash ++;
   5.693 -    }
   5.694 -    printf("Done vtlb entry check, hash=%p\n", hash);
   5.695 -    printf("check_ok_num = 0x%lx check_invalid=0x%lx\n", check_ok_num,check_invalid);
   5.696 -    invalid_ratio = 1000*check_invalid / hash_num;
   5.697 -    printf("%02ld.%01ld%% entries are invalid\n", 
   5.698 -		invalid_ratio/10, invalid_ratio % 10 );
   5.699 -    for (i=0; i<NDTRS; i++) {
   5.700 -        ovl = thash_find_overlap(vhpt, &vtlb->ts->dtr[i], s_sect);
   5.701 -        while ( ovl != NULL ) {
   5.702 -            ovl->checked = 1;
   5.703 -            ovl = (vhpt->next_overlap)(vhpt);
   5.704 -        };
   5.705 -    }
   5.706 -    printf("Done dTR\n");
   5.707 -    for (i=0; i<NITRS; i++) {
   5.708 -        ovl = thash_find_overlap(vhpt, &vtlb->ts->itr[i], s_sect);
   5.709 -        while ( ovl != NULL ) {
   5.710 -            ovl->checked = 1;
   5.711 -            ovl = (vhpt->next_overlap)(vhpt);
   5.712 -        };
   5.713 -    }
   5.714 -    printf("Done iTR\n");
   5.715 -    check_fail_num = 0;
   5.716 -    check_invalid = 0;
   5.717 -    check_ok_num=0;
   5.718 -    hash = vhpt->hash;
   5.719 -    for (i=0; i < hash_num; i++) {
   5.720 -        if ( !INVALID_ENTRY(vhpt, hash) ) {
   5.721 -            for ( cch= hash; cch; cch=cch->next) {
   5.722 -                if ( !cch->checked ) {
   5.723 -                    printf ("!!!Hash=%p cch=%p not within vtlb\n", hash, cch);
   5.724 -                    check_fail_num ++;
   5.725 -                }
   5.726 -                else {
   5.727 -                    check_ok_num++;
   5.728 -                }
   5.729 -            }
   5.730 -        }
   5.731 -        else {
   5.732 -            check_invalid ++;
   5.733 -        }
   5.734 -        hash ++;
   5.735 -    }
   5.736 -    local_irq_restore(psr);
   5.737 -    printf("check_ok_num=0x%lx check_fail_num=0x%lx check_invalid=0x%lx\n", 
   5.738 -            check_ok_num, check_fail_num, check_invalid);
   5.739 -    //memcpy(vtlb->hash, vb1, vtlb->hash_sz);
   5.740 -    //memcpy(vhpt->hash, vb2, vhpt->hash_sz);
   5.741 -    printf("The statistics of collision chain length is listed\n");
   5.742 -    for ( i=0; i < sizeof(cch_length_statistics)/sizeof(cch_length_statistics[0]); i++ ) {
   5.743 -    	printf("CCH length=%02ld, chain number=%ld\n", i, cch_length_statistics[i]);
   5.744 -    }
   5.745 -//    free_domheap_pages(page, VCPU_TLB_ORDER);
   5.746 -    printf("Done check_vtlb\n");
   5.747 -}
   5.748 -
   5.749 -void dump_vtlb(thash_cb_t *vtlb)
   5.750 -{
   5.751 -    static u64  dump_vtlb=0;
   5.752 -    thash_data_t  *hash, *cch, *tr;
   5.753 -    u64     hash_num,i;
   5.754 -
   5.755 -    if ( dump_vtlb == 0 ) return;
   5.756 -    dump_vtlb --;
   5.757 -    hash_num = vtlb->hash_sz / sizeof(thash_data_t);
   5.758 -    hash = vtlb->hash;
   5.759 -
   5.760 -    printf("Dump vTC\n");
   5.761 -    for ( i = 0; i < hash_num; i++ ) {
   5.762 -        if ( !INVALID_ENTRY(vtlb, hash) ) {
   5.763 -            printf("VTLB at hash=%p\n", hash);
   5.764 -            for (cch=hash; cch; cch=cch->next) {
   5.765 -                printf("Entry %p va=%lx ps=%d rid=%d\n",
   5.766 -                    cch, cch->vadr, cch->ps, cch->rid);
   5.767 -            }
   5.768 -        }
   5.769 -        hash ++;
   5.770 -    }
   5.771 -    printf("Dump vDTR\n");
   5.772 -    for (i=0; i<NDTRS; i++) {
   5.773 -        tr = &DTR(vtlb,i);
   5.774 -        printf("Entry %p va=%lx ps=%d rid=%d\n",
   5.775 -                    tr, tr->vadr, tr->ps, tr->rid);
   5.776 -    }
   5.777 -    printf("Dump vITR\n");
   5.778 -    for (i=0; i<NITRS; i++) {
   5.779 -        tr = &ITR(vtlb,i);
   5.780 -        printf("Entry %p va=%lx ps=%d rid=%d\n",
   5.781 -                    tr, tr->vadr, tr->ps, tr->rid);
   5.782 -    }
   5.783 -    printf("End of vTLB dump\n");
   5.784 -}
   5.785 -*/
   5.786 -#endif
     6.1 --- a/xen/include/asm-ia64/vmmu.h	Tue May 30 08:46:21 2006 -0600
     6.2 +++ b/xen/include/asm-ia64/vmmu.h	Tue May 30 10:28:59 2006 -0600
     6.3 @@ -137,22 +137,20 @@ typedef struct thash_data {
     6.4  } thash_data_t;
     6.5  
     6.6  #define INVALIDATE_VHPT_HEADER(hdata)   \
     6.7 -{	((hdata)->page_flags)=0;	\
     6.8 -	((hdata)->ti)=1;	\
     6.9 -	((hdata)->next)=0; }
    6.10 +{   ((hdata)->page_flags)=0;            \
    6.11 +    ((hdata)->itir)=PAGE_SHIFT<<2;      \
    6.12 +    ((hdata)->etag)=1UL<<63;            \
    6.13 +    ((hdata)->next)=0;}
    6.14  
    6.15 -#define INVALIDATE_TLB_HEADER(hdata)   \
    6.16 -{	((hdata)->page_flags)=0;	\
    6.17 -	((hdata)->ti)=1;		\
    6.18 -	((hdata)->next)=0; }
    6.19 +#define INVALIDATE_TLB_HEADER(hash)   INVALIDATE_VHPT_HEADER(hash)
    6.20 +
    6.21 +#define INVALIDATE_HASH_HEADER(hcb,hash)    INVALIDATE_VHPT_HEADER(hash)
    6.22  
    6.23  #define INVALID_VHPT(hdata)     ((hdata)->ti)
    6.24  #define INVALID_TLB(hdata)      ((hdata)->ti)
    6.25  #define INVALID_TR(hdata)      (!(hdata)->p)
    6.26  #define INVALID_ENTRY(hcb, hdata)       INVALID_VHPT(hdata)
    6.27  
    6.28 -/*        ((hcb)->ht==THASH_TLB ? INVALID_TLB(hdata) : INVALID_VHPT(hdata)) */
    6.29 -
    6.30  
    6.31  /*
    6.32   * Architecture ppn is in 4KB unit while XEN
    6.33 @@ -189,81 +187,18 @@ typedef thash_data_t *(FIND_NEXT_OVL_FN)
    6.34  typedef void (REM_THASH_FN)(struct thash_cb *hcb, thash_data_t *entry);
    6.35  typedef void (INS_THASH_FN)(struct thash_cb *hcb, thash_data_t *entry, u64 va);
    6.36  
    6.37 -//typedef struct tlb_special {
    6.38 -//        thash_data_t     itr[NITRS];
    6.39 -//        thash_data_t     dtr[NDTRS];
    6.40 -//        struct thash_cb  *vhpt;
    6.41 -//} tlb_special_t;
    6.42  
    6.43 -//typedef struct vhpt_cb {
    6.44 -        //u64     pta;    // pta value.
    6.45 -//        GET_MFN_FN      *get_mfn;
    6.46 -//        TTAG_FN         *tag_func;
    6.47 -//} vhpt_special;
    6.48 -/*
    6.49 -typedef struct thash_internal {
    6.50 -        thash_data_t *hash_base;
    6.51 -        thash_data_t *cur_cch;  // head of overlap search
    6.52 -        int     rid;
    6.53 -        int     ps;
    6.54 -        union {
    6.55 -            u64  tag;           // for VHPT
    6.56 -            struct {            // for TLB
    6.57 -                char    _tr_idx;        // -1: means done of TR search
    6.58 -                char    cl;
    6.59 -                search_section_t s_sect;   // search section combinations
    6.60 -            };
    6.61 -        };
    6.62 -        u64     _curva;         // current address to search
    6.63 -        u64     _eva;
    6.64 -} thash_internal_t;
    6.65 - */
    6.66 -//#define  THASH_CB_MAGIC         0x55aa00aa55aa55aaUL
    6.67  typedef struct thash_cb {
    6.68 -        /* THASH base information */
    6.69 -//        THASH_TYPE      ht;     // For TLB or VHPT
    6.70 -//        u64             magic;
    6.71 -        thash_data_t    *hash; // hash table pointer, aligned at thash_sz.
    6.72 -        u64     hash_sz;        // size of above data.
    6.73 -        void    *cch_buf;       // base address of collision chain.
    6.74 -        u64     cch_sz;         // size of above data.
    6.75 -//        THASH_FN        *hash_func;
    6.76 -//        GET_RR_FN       *get_rr_fn;
    6.77 -//        RECYCLE_FN      *recycle_notifier;
    6.78 -        thash_data_t *cch_freelist;
    6.79 -//        struct vcpu *vcpu;
    6.80 -        PTA     pta;
    6.81 -//        struct thash_cb *vhpt;
    6.82 -        /* VTLB/VHPT common information */
    6.83 -//        FIND_OVERLAP_FN *find_overlap;
    6.84 -//        FIND_NEXT_OVL_FN *next_overlap;
    6.85 -//        REM_THASH_FN    *rem_hash; // remove hash entry.
    6.86 -//        INS_THASH_FN    *ins_hash; // insert hash entry.
    6.87 -//        REM_NOTIFIER_FN *remove_notifier;
    6.88 -        /* private information */
    6.89 -//        thash_internal_t  priv;
    6.90 -//        union {
    6.91 -//                tlb_special_t  *ts;
    6.92 -//                vhpt_special   *vs;
    6.93 -//        };
    6.94 -        // Internal positon information, buffer and storage etc. TBD
    6.95 +    /* THASH base information */
    6.96 +    thash_data_t    *hash; // hash table pointer, aligned at thash_sz.
    6.97 +    u64     hash_sz;        // size of above data.
    6.98 +    void    *cch_buf;       // base address of collision chain.
    6.99 +    u64     cch_sz;         // size of above data.
   6.100 +    thash_data_t *cch_freelist;
   6.101 +    thash_data_t *cch_rec_head;  // cch recycle header
   6.102 +    PTA     pta;
   6.103  } thash_cb_t;
   6.104  
   6.105 -//#define ITR(hcb,id)             ((hcb)->ts->itr[id])
   6.106 -//#define DTR(hcb,id)             ((hcb)->ts->dtr[id])
   6.107 -#define INVALIDATE_HASH_HEADER(hcb,hash)    INVALIDATE_TLB_HEADER(hash)
   6.108 -/*              \
   6.109 -{           if ((hcb)->ht==THASH_TLB){            \
   6.110 -            INVALIDATE_TLB_HEADER(hash);             \
   6.111 -           }else{                                 \
   6.112 -             INVALIDATE_VHPT_HEADER(hash);            \
   6.113 -            }                                       \
   6.114 -}
   6.115 - */
   6.116 -#define PURGABLE_ENTRY(hcb,en)  1
   6.117 -//		((hcb)->ht == THASH_VHPT || ( (en)->tc && !(en->locked)) )
   6.118 -
   6.119 -
   6.120  /*
   6.121   * Initialize internal control data before service.
   6.122   */
   6.123 @@ -281,7 +216,6 @@ extern void thash_init(thash_cb_t *hcb, 
   6.124   *      4: Return the entry in hash table or collision chain.
   6.125   *
   6.126   */
   6.127 -extern void thash_vhpt_insert(thash_cb_t *hcb, u64 pte, u64 itir, u64 ifa);
   6.128  //extern void thash_insert(thash_cb_t *hcb, thash_data_t *entry, u64 va);
   6.129  //extern void thash_tr_insert(thash_cb_t *hcb, thash_data_t *entry, u64 va, int idx);
   6.130  extern int vtr_find_overlap(struct vcpu *vcpu, u64 va, u64 ps, int is_data);
   6.131 @@ -368,6 +302,10 @@ extern void machine_tlb_purge(u64 va, u6
   6.132  extern int fetch_code(struct vcpu *vcpu, u64 gip, u64 *code1, u64 *code2);
   6.133  extern void emulate_io_inst(struct vcpu *vcpu, u64 padr, u64 ma);
   6.134  extern int vhpt_enabled(struct vcpu *vcpu, uint64_t vadr, vhpt_ref_t ref);
   6.135 +extern void  vtlb_insert(thash_cb_t *hcb, u64 pte, u64 itir, u64 va);
   6.136 +extern u64 translate_phy_pte(struct vcpu *v, u64 *pte, u64 itir, u64 va);
   6.137 +extern void thash_vhpt_insert(struct vcpu *v, u64 pte, u64 itir, u64 ifa);
   6.138 +extern u64 guest_vhpt_lookup(u64 iha, u64 *pte);
   6.139  
   6.140  static inline void vmx_vcpu_set_tr (thash_data_t *trp, u64 pte, u64 itir, u64 va, u64 rid)
   6.141  {
   6.142 @@ -377,13 +315,6 @@ static inline void vmx_vcpu_set_tr (thas
   6.143      trp->rid = rid;
   6.144  }
   6.145  
   6.146 -
   6.147 -//#define   VTLB_DEBUG
   6.148 -#ifdef   VTLB_DEBUG
   6.149 -extern void check_vtlb_sanity(thash_cb_t *vtlb);
   6.150 -extern void dump_vtlb(thash_cb_t *vtlb);
   6.151 -#endif
   6.152 -
   6.153  #endif  /* __ASSEMBLY__ */
   6.154  
   6.155  #endif  /* XEN_TLBthash_H */
     7.1 --- a/xen/include/asm-ia64/vmx_vcpu.h	Tue May 30 08:46:21 2006 -0600
     7.2 +++ b/xen/include/asm-ia64/vmx_vcpu.h	Tue May 30 10:28:59 2006 -0600
     7.3 @@ -121,6 +121,7 @@ extern void alt_dtlb (VCPU *vcpu, u64 va
     7.4  extern void dvhpt_fault (VCPU *vcpu, u64 vadr);
     7.5  extern void dnat_page_consumption (VCPU *vcpu, uint64_t vadr);
     7.6  extern void page_not_present(VCPU *vcpu, u64 vadr);
     7.7 +extern void data_access_rights(VCPU *vcpu, u64 vadr);
     7.8  
     7.9  /**************************************************************************
    7.10   VCPU control register access routines