ia64/xen-unstable

changeset 586:125f43340354

bitkeeper revision 1.326 (3f0d2a81wsMWUhlREHQXAurCbmEVEQ)

Merge labyrinth.cl.cam.ac.uk:/auto/groups/xeno/BK/xeno.bk
into labyrinth.cl.cam.ac.uk:/auto/groups/xeno/users/rac61/xeno.bk
author rac61@labyrinth.cl.cam.ac.uk
date Thu Jul 10 08:57:37 2003 +0000 (2003-07-10)
parents e5cb8bd7ebfe 4480b471191c
children a50c94715247 5ed7375f954a
files .rootkeys xen/drivers/net/8139too.c xen/drivers/net/Makefile xen/drivers/net/SUPPORTED_CARDS xen/drivers/net/e100/LICENSE xen/drivers/net/e100/Makefile xen/drivers/net/e100/e100.h xen/drivers/net/e100/e100_config.c xen/drivers/net/e100/e100_config.h xen/drivers/net/e100/e100_eeprom.c xen/drivers/net/e100/e100_main.c xen/drivers/net/e100/e100_phy.c xen/drivers/net/e100/e100_phy.h xen/drivers/net/e100/e100_test.c xen/drivers/net/e100/e100_ucode.h xen/drivers/net/ne/8390.c xen/drivers/net/ne/8390.h xen/drivers/net/ne/Makefile xen/drivers/net/ne/ne.c xen/drivers/net/net_init.c xen/drivers/net/pcnet32.c xen/drivers/net/tulip/21142.c xen/drivers/net/tulip/ChangeLog xen/drivers/net/tulip/Makefile xen/drivers/net/tulip/eeprom.c xen/drivers/net/tulip/interrupt.c xen/drivers/net/tulip/media.c xen/drivers/net/tulip/pnic.c xen/drivers/net/tulip/pnic2.c xen/drivers/net/tulip/timer.c xen/drivers/net/tulip/tulip.h xen/drivers/net/tulip/tulip_core.c xen/drivers/net/via-rhine.c xen/include/xeno/crc32.h xen/include/xeno/mii.h xen/include/xeno/netdevice.h xen/include/xeno/skbuff.h xen/net/dev.c xen/net/skbuff.c
line diff
     1.1 --- a/.rootkeys	Thu Jul 10 08:45:03 2003 +0000
     1.2 +++ b/.rootkeys	Thu Jul 10 08:57:37 2003 +0000
     1.3 @@ -222,8 +222,21 @@ 3ddb79bdkDY1bSOYkToP1Cc49VdBxg xen/drive
     1.4  3ddb79bdPyAvT_WZTAFhaX0jp-yXSw xen/drivers/ide/ide_modes.h
     1.5  3e4a8d401aSwOzCScQXR3lsmNlAwUQ xen/drivers/ide/piix.c
     1.6  3ddb79bfMlOcWUwjtg6oMYhGySHDDw xen/drivers/net/3c59x.c
     1.7 +3f0c423bjmEpn1Nbk1Q8fv8ElccwAA xen/drivers/net/8139too.c
     1.8  3ddb79c0tWiE8xIFHszxipeVCGKTSA xen/drivers/net/Makefile
     1.9 +3f0c4247730LYUgz3p5ziYqy-s_glw xen/drivers/net/SUPPORTED_CARDS
    1.10  3ddb79bfU-H1Hms4BuJEPPydjXUEaQ xen/drivers/net/Space.c
    1.11 +3f0c428e41JP96bh-J0jnX59vJyUeQ xen/drivers/net/e100/LICENSE
    1.12 +3f0c428es_xrZnnZQXXHhjzuqj9CTg xen/drivers/net/e100/Makefile
    1.13 +3f0c428eCEnifr-r6XCZKUkzIEHdYw xen/drivers/net/e100/e100.h
    1.14 +3f0c428eyYDJIqvO7W_QbgnGnbgPqA xen/drivers/net/e100/e100_config.c
    1.15 +3f0c428e-NvNXlOyIw8H3YllFL6lfA xen/drivers/net/e100/e100_config.h
    1.16 +3f0c428ecPXSlA_4rp_-6O09uQqHbg xen/drivers/net/e100/e100_eeprom.c
    1.17 +3f0c428eWlXUzaulDjS1UpUP7Ckejg xen/drivers/net/e100/e100_main.c
    1.18 +3f0c428eKW1sEaCen-HIMUwMtQXnVQ xen/drivers/net/e100/e100_phy.c
    1.19 +3f0c428eR00XnyLIZKb5H5QF_I9QDg xen/drivers/net/e100/e100_phy.h
    1.20 +3f0c428eII-G2i_Qv_aCQjLzHcDKEQ xen/drivers/net/e100/e100_test.c
    1.21 +3f0c428eJ_gqbOFzS3bWSI7geA--Eg xen/drivers/net/e100/e100_ucode.h
    1.22  3e4540ccS4bfbx9rLiLElP0F1OVwZA xen/drivers/net/e1000/LICENSE
    1.23  3e4540ccXG6af_6-u0IiKKvtdGHJyA xen/drivers/net/e1000/Makefile
    1.24  3e4540ccoY2eo4VIkbR4sCOj0bVzSA xen/drivers/net/e1000/e1000.h
    1.25 @@ -233,14 +246,23 @@ 3e4540cczrrQVyyj-s1-viyX1kMUlA xen/drive
    1.26  3e4540ccvQ9Dtoh9tV-L3ULUwN9X7g xen/drivers/net/e1000/e1000_main.c
    1.27  3e4540cc3t7_y-YLeyMG2pX9xtdXPA xen/drivers/net/e1000/e1000_osdep.h
    1.28  3e4540cct_8Ig-Y1W_vM2gS_u7mC0A xen/drivers/net/e1000/e1000_param.c
    1.29 -3e465c00t2nochqR27eEY_FBjxsUCw xen/drivers/net/ne/8390.c
    1.30 -3e465c00AIRmk20x1vYETtnL71eGvA xen/drivers/net/ne/8390.h
    1.31 -3e465c00UIvPTAtAcgcQWCVFa2bwww xen/drivers/net/ne/Makefile
    1.32 -3e465c00rWSHiXmHuOWLRf7r2n8S3g xen/drivers/net/ne/ne.c
    1.33  3ddb79bfKvn9mt0kofpkw0QaWjxO6A xen/drivers/net/net_init.c
    1.34 +3f0c428exbF4as5zi8GyGyDSUITmxg xen/drivers/net/pcnet32.c
    1.35  3ddb79bf_CBcu3QWYwq4bNAOnM2RqQ xen/drivers/net/setup.c
    1.36  3e45a0c6u66EL2AI36eLOmf_abXs7g xen/drivers/net/tg3.c
    1.37  3e45a0c6yrXj5pmQT0PvVSJ01YLABQ xen/drivers/net/tg3.h
    1.38 +3f0c428e0tn3ZknveWidRNtHYcyHzw xen/drivers/net/tulip/21142.c
    1.39 +3f0c428esCXQWoJHSJ5zUZ7iQc_rlQ xen/drivers/net/tulip/ChangeLog
    1.40 +3f0c428eB8pVjwDolFZDa0YZMQW1rw xen/drivers/net/tulip/Makefile
    1.41 +3f0c428el4rtJgjSoK_K04g5Udg2Tw xen/drivers/net/tulip/eeprom.c
    1.42 +3f0c428eYyDHq5AnrB60p3g0uXWYwA xen/drivers/net/tulip/interrupt.c
    1.43 +3f0c428eI99GG-HH2aQCIQ4tyISe8w xen/drivers/net/tulip/media.c
    1.44 +3f0c428eErjUSQiTzPJJlSrR0ORJog xen/drivers/net/tulip/pnic.c
    1.45 +3f0c428eyyo0-aI_fj4gDBiNYe-Idw xen/drivers/net/tulip/pnic2.c
    1.46 +3f0c428eZQhoTueBPxOO5YbuzoTofw xen/drivers/net/tulip/timer.c
    1.47 +3f0c428eoDFGJZJrBRnA7918Yovt0A xen/drivers/net/tulip/tulip.h
    1.48 +3f0c428e46klSV-upTm6D8tCdzQs8Q xen/drivers/net/tulip/tulip_core.c
    1.49 +3f0c428eu_CTRPhmTgGIjoiGI_PmrA xen/drivers/net/via-rhine.c
    1.50  3ddb79beUWngyIhMHgyPtuTem4o4JA xen/drivers/pci/Makefile
    1.51  3ddb79beU9td0Mnm0VUMklerBa37qQ xen/drivers/pci/compat.c
    1.52  3ddb79beHkGQE58z5t5gyUCYiwOxvw xen/drivers/pci/gen-devlist.c
    1.53 @@ -406,6 +428,7 @@ 3ddb79c0c0cX_DZE209-Bb-Rx1v-Aw xen/inclu
    1.54  3e9c248aEG_nCngztiFmv5CfayNkcA xen/include/xeno/cdrom.h
    1.55  3ddb79c259jh8hE7vre_8NuE7nwNSA xen/include/xeno/config.h
    1.56  3eb165e0eawr3R-p2ZQtSdLWtLRN_A xen/include/xeno/console.h
    1.57 +3f0c428eIwGr7n9fj4FkBdX2YvA_Rw xen/include/xeno/crc32.h
    1.58  3ddb79c1V44RD26YqCUm-kqIupM37A xen/include/xeno/ctype.h
    1.59  3ddb79c05DdHQ0UxX_jKsXdR4QlMCA xen/include/xeno/delay.h
    1.60  3e6377eaioRoNm0m_HSDEAd4Vqrq_w xen/include/xeno/dom_mem_ops.h
     2.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     2.2 +++ b/xen/drivers/net/8139too.c	Thu Jul 10 08:57:37 2003 +0000
     2.3 @@ -0,0 +1,2671 @@
     2.4 +/*
     2.5 +
     2.6 +	8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
     2.7 +
     2.8 +	Maintained by Jeff Garzik <jgarzik@pobox.com>
     2.9 +	Copyright 2000-2002 Jeff Garzik
    2.10 +
    2.11 +	Much code comes from Donald Becker's rtl8139.c driver,
    2.12 +	versions 1.13 and older.  This driver was originally based
    2.13 +	on rtl8139.c version 1.07.  Header of rtl8139.c version 1.13:
    2.14 +
    2.15 +	-----<snip>-----
    2.16 +
    2.17 +        	Written 1997-2001 by Donald Becker.
    2.18 +		This software may be used and distributed according to the
    2.19 +		terms of the GNU General Public License (GPL), incorporated
    2.20 +		herein by reference.  Drivers based on or derived from this
    2.21 +		code fall under the GPL and must retain the authorship,
    2.22 +		copyright and license notice.  This file is not a complete
    2.23 +		program and may only be used when the entire operating
    2.24 +		system is licensed under the GPL.
    2.25 +
    2.26 +		This driver is for boards based on the RTL8129 and RTL8139
    2.27 +		PCI ethernet chips.
    2.28 +
    2.29 +		The author may be reached as becker@scyld.com, or C/O Scyld
    2.30 +		Computing Corporation 410 Severn Ave., Suite 210 Annapolis
    2.31 +		MD 21403
    2.32 +
    2.33 +		Support and updates available at
    2.34 +		http://www.scyld.com/network/rtl8139.html
    2.35 +
    2.36 +		Twister-tuning table provided by Kinston
    2.37 +		<shangh@realtek.com.tw>.
    2.38 +
    2.39 +	-----<snip>-----
    2.40 +
    2.41 +	This software may be used and distributed according to the terms
    2.42 +	of the GNU General Public License, incorporated herein by reference.
    2.43 +
    2.44 +	Contributors:
    2.45 +
    2.46 +		Donald Becker - he wrote the original driver, kudos to him!
    2.47 +		(but please don't e-mail him for support, this isn't his driver)
    2.48 +
    2.49 +		Tigran Aivazian - bug fixes, skbuff free cleanup
    2.50 +
    2.51 +		Martin Mares - suggestions for PCI cleanup
    2.52 +
    2.53 +		David S. Miller - PCI DMA and softnet updates
    2.54 +
    2.55 +		Ernst Gill - fixes ported from BSD driver
    2.56 +
    2.57 +		Daniel Kobras - identified specific locations of
    2.58 +			posted MMIO write bugginess
    2.59 +
    2.60 +		Gerard Sharp - bug fix, testing and feedback
    2.61 +
    2.62 +		David Ford - Rx ring wrap fix
    2.63 +
    2.64 +		Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
    2.65 +		to find and fix a crucial bug on older chipsets.
    2.66 +
    2.67 +		Donald Becker/Chris Butterworth/Marcus Westergren -
    2.68 +		Noticed various Rx packet size-related buglets.
    2.69 +
    2.70 +		Santiago Garcia Mantinan - testing and feedback
    2.71 +
    2.72 +		Jens David - 2.2.x kernel backports
    2.73 +
    2.74 +		Martin Dennett - incredibly helpful insight on undocumented
    2.75 +		features of the 8139 chips
    2.76 +
    2.77 +		Jean-Jacques Michel - bug fix
    2.78 +
    2.79 +		Tobias Ringström - Rx interrupt status checking suggestion
    2.80 +
    2.81 +		Andrew Morton - Clear blocked signals, avoid
    2.82 +		buffer overrun setting current->comm.
    2.83 +
    2.84 +		Kalle Olavi Niemitalo - Wake-on-LAN ioctls
    2.85 +
    2.86 +		Robert Kuebel - Save kernel thread from dying on any signal.
    2.87 +
    2.88 +	Submitting bug reports:
    2.89 +
    2.90 +		"rtl8139-diag -mmmaaavvveefN" output
    2.91 +		enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
    2.92 +
    2.93 +		See 8139too.txt for more details.
    2.94 +
    2.95 +*/
    2.96 +
    2.97 +#define DRV_NAME	"8139too"
    2.98 +#define DRV_VERSION	"0.9.26"
    2.99 +
   2.100 +#include <linux/config.h>
   2.101 +#include <linux/module.h>
   2.102 +#include <linux/kernel.h>
   2.103 +#include <linux/lib.h>
   2.104 +#include <linux/timer.h>
   2.105 +#include <linux/pci.h>
   2.106 +#include <linux/init.h>
   2.107 +#include <linux/ioport.h>
   2.108 +#include <linux/netdevice.h>
   2.109 +#include <linux/etherdevice.h>
   2.110 +#include <linux/delay.h>
   2.111 +#include <linux/ethtool.h>
   2.112 +#include <linux/mii.h>
   2.113 +#include <linux/crc32.h>
   2.114 +#include <asm/io.h>
   2.115 +#include <asm/uaccess.h>
   2.116 +
   2.117 +/* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
   2.118 +static int next_tick = 3 * HZ;
   2.119 +
   2.120 +#define RTL8139_DRIVER_NAME   DRV_NAME " Fast Ethernet driver " DRV_VERSION
   2.121 +#define PFX DRV_NAME ": "
   2.122 +
   2.123 +
   2.124 +/* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */
   2.125 +#ifdef CONFIG_8139TOO_PIO
   2.126 +#define USE_IO_OPS 1
   2.127 +#endif
   2.128 +
   2.129 +/* define to 1 to enable copious debugging info */
   2.130 +#undef RTL8139_DEBUG
   2.131 +
   2.132 +/* define to 1 to disable lightweight runtime debugging checks */
   2.133 +#undef RTL8139_NDEBUG
   2.134 +
   2.135 +
   2.136 +#ifdef RTL8139_DEBUG
   2.137 +/* note: prints function name for you */
   2.138 +#  define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
   2.139 +#else
   2.140 +#  define DPRINTK(fmt, args...)
   2.141 +#endif
   2.142 +
   2.143 +#ifdef RTL8139_NDEBUG
   2.144 +#  define assert(expr) do {} while (0)
   2.145 +#else
   2.146 +#  define assert(expr) \
   2.147 +        if(!(expr)) {					\
   2.148 +        printk( "Assertion failed! %s,%s,%s,line=%d\n",	\
   2.149 +        #expr,__FILE__,__FUNCTION__,__LINE__);		\
   2.150 +        }
   2.151 +#endif
   2.152 +
   2.153 +
   2.154 +/* A few user-configurable values. */
   2.155 +/* media options */
   2.156 +#define MAX_UNITS 8
   2.157 +static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
   2.158 +static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
   2.159 +
   2.160 +/* Maximum events (Rx packets, etc.) to handle at each interrupt. */
   2.161 +static int max_interrupt_work = 20;
   2.162 +
   2.163 +/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
   2.164 +   The RTL chips use a 64 element hash table based on the Ethernet CRC.  */
   2.165 +static int multicast_filter_limit = 32;
   2.166 +
   2.167 +#if 0
   2.168 +/* bitmapped message enable number */
   2.169 +static int debug = -1;
   2.170 +#endif
   2.171 +
   2.172 +/* Size of the in-memory receive ring. */
   2.173 +#define RX_BUF_LEN_IDX	2	/* 0==8K, 1==16K, 2==32K, 3==64K */
   2.174 +#define RX_BUF_LEN	(8192 << RX_BUF_LEN_IDX)
   2.175 +#define RX_BUF_PAD	16
   2.176 +#define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
   2.177 +#define RX_BUF_TOT_LEN	(RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
   2.178 +
   2.179 +/* Number of Tx descriptor registers. */
   2.180 +#define NUM_TX_DESC	4
   2.181 +
   2.182 +/* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
   2.183 +#define MAX_ETH_FRAME_SIZE	1536
   2.184 +
   2.185 +/* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
   2.186 +#define TX_BUF_SIZE	MAX_ETH_FRAME_SIZE
   2.187 +#define TX_BUF_TOT_LEN	(TX_BUF_SIZE * NUM_TX_DESC)
   2.188 +
   2.189 +/* PCI Tuning Parameters
   2.190 +   Threshold is bytes transferred to chip before transmission starts. */
   2.191 +#define TX_FIFO_THRESH 256	/* In bytes, rounded down to 32 byte units. */
   2.192 +
   2.193 +/* The following settings are log_2(bytes)-4:  0 == 16 bytes .. 6==1024, 7==end of packet. */
   2.194 +#define RX_FIFO_THRESH	7	/* Rx buffer level before first PCI xfer.  */
   2.195 +#define RX_DMA_BURST	7	/* Maximum PCI burst, '6' is 1024 */
   2.196 +#define TX_DMA_BURST	6	/* Maximum PCI burst, '6' is 1024 */
   2.197 +#define TX_RETRY	8	/* 0-15.  retries = 16 + (TX_RETRY * 16) */
   2.198 +
   2.199 +/* Operational parameters that usually are not changed. */
   2.200 +/* Time in jiffies before concluding the transmitter is hung. */
   2.201 +#define TX_TIMEOUT  (6*HZ)
   2.202 +
   2.203 +
   2.204 +enum {
   2.205 +	HAS_MII_XCVR = 0x010000,
   2.206 +	HAS_CHIP_XCVR = 0x020000,
   2.207 +	HAS_LNK_CHNG = 0x040000,
   2.208 +};
   2.209 +
   2.210 +#define RTL_NUM_STATS 4		/* number of ETHTOOL_GSTATS u64's */
   2.211 +#define RTL_REGS_VER 1		/* version of reg. data in ETHTOOL_GREGS */
   2.212 +#define RTL_MIN_IO_SIZE 0x80
   2.213 +#define RTL8139B_IO_SIZE 256
   2.214 +
   2.215 +#define RTL8129_CAPS	HAS_MII_XCVR
   2.216 +#define RTL8139_CAPS	HAS_CHIP_XCVR|HAS_LNK_CHNG
   2.217 +
   2.218 +typedef enum {
   2.219 +	RTL8139 = 0,
   2.220 +	RTL8139_CB,
   2.221 +	SMC1211TX,
   2.222 +	/*MPX5030,*/
   2.223 +	DELTA8139,
   2.224 +	ADDTRON8139,
   2.225 +	DFE538TX,
   2.226 +	DFE690TXD,
   2.227 +	FE2000VX,
   2.228 +	ALLIED8139,
   2.229 +	RTL8129,
   2.230 +	FNW3603TX,
   2.231 +	FNW3800TX,
   2.232 +} board_t;
   2.233 +
   2.234 +
   2.235 +/* indexed by board_t, above */
   2.236 +static struct {
   2.237 +	const char *name;
   2.238 +	u32 hw_flags;
   2.239 +} board_info[] __devinitdata = {
   2.240 +	{ "RealTek RTL8139 Fast Ethernet", RTL8139_CAPS },
   2.241 +	{ "RealTek RTL8139B PCI/CardBus", RTL8139_CAPS },
   2.242 +	{ "SMC1211TX EZCard 10/100 (RealTek RTL8139)", RTL8139_CAPS },
   2.243 +/*	{ MPX5030, "Accton MPX5030 (RealTek RTL8139)", RTL8139_CAPS },*/
   2.244 +	{ "Delta Electronics 8139 10/100BaseTX", RTL8139_CAPS },
   2.245 +	{ "Addtron Technolgy 8139 10/100BaseTX", RTL8139_CAPS },
   2.246 +	{ "D-Link DFE-538TX (RealTek RTL8139)", RTL8139_CAPS },
   2.247 +	{ "D-Link DFE-690TXD (RealTek RTL8139)", RTL8139_CAPS },
   2.248 +	{ "AboCom FE2000VX (RealTek RTL8139)", RTL8139_CAPS },
   2.249 +	{ "Allied Telesyn 8139 CardBus", RTL8139_CAPS },
   2.250 +	{ "RealTek RTL8129", RTL8129_CAPS },
   2.251 +	{ "Planex FNW-3603-TX 10/100 CardBus", RTL8139_CAPS },
   2.252 +	{ "Planex FNW-3800-TX 10/100 CardBus", RTL8139_CAPS },
   2.253 +};
   2.254 +
   2.255 +
   2.256 +static struct pci_device_id rtl8139_pci_tbl[] __devinitdata = {
   2.257 +	{0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
   2.258 +	{0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139_CB },
   2.259 +	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, SMC1211TX },
   2.260 +/*	{0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, MPX5030 },*/
   2.261 +	{0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DELTA8139 },
   2.262 +	{0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ADDTRON8139 },
   2.263 +	{0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DFE538TX },
   2.264 +	{0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, DFE690TXD },
   2.265 +	{0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, FE2000VX },
   2.266 +	{0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ALLIED8139 },
   2.267 +	{0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, FNW3603TX },
   2.268 +	{0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, FNW3800TX },
   2.269 +
   2.270 +#ifdef CONFIG_8139TOO_8129
   2.271 +	{0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
   2.272 +#endif
   2.273 +
   2.274 +	/* some crazy cards report invalid vendor ids like
   2.275 +	 * 0x0001 here.  The other ids are valid and constant,
   2.276 +	 * so we simply don't match on the main vendor id.
   2.277 +	 */
   2.278 +	{PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
   2.279 +	{PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, DFE538TX },
   2.280 +	{PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, FE2000VX },
   2.281 +
   2.282 +	{0,}
   2.283 +};
   2.284 +MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
   2.285 +
   2.286 +#if 0
   2.287 +static struct {
   2.288 +	const char str[ETH_GSTRING_LEN];
   2.289 +} ethtool_stats_keys[] = {
   2.290 +	{ "early_rx" },
   2.291 +	{ "tx_buf_mapped" },
   2.292 +	{ "tx_timeouts" },
   2.293 +	{ "rx_lost_in_ring" },
   2.294 +};
   2.295 +#endif
   2.296 +
   2.297 +/* The rest of these values should never change. */
   2.298 +
   2.299 +/* Symbolic offsets to registers. */
   2.300 +enum RTL8139_registers {
   2.301 +	MAC0 = 0,		/* Ethernet hardware address. */
   2.302 +	MAR0 = 8,		/* Multicast filter. */
   2.303 +	TxStatus0 = 0x10,	/* Transmit status (Four 32bit registers). */
   2.304 +	TxAddr0 = 0x20,		/* Tx descriptors (also four 32bit). */
   2.305 +	RxBuf = 0x30,
   2.306 +	ChipCmd = 0x37,
   2.307 +	RxBufPtr = 0x38,
   2.308 +	RxBufAddr = 0x3A,
   2.309 +	IntrMask = 0x3C,
   2.310 +	IntrStatus = 0x3E,
   2.311 +	TxConfig = 0x40,
   2.312 +	ChipVersion = 0x43,
   2.313 +	RxConfig = 0x44,
   2.314 +	Timer = 0x48,		/* A general-purpose counter. */
   2.315 +	RxMissed = 0x4C,	/* 24 bits valid, write clears. */
   2.316 +	Cfg9346 = 0x50,
   2.317 +	Config0 = 0x51,
   2.318 +	Config1 = 0x52,
   2.319 +	FlashReg = 0x54,
   2.320 +	MediaStatus = 0x58,
   2.321 +	Config3 = 0x59,
   2.322 +	Config4 = 0x5A,		/* absent on RTL-8139A */
   2.323 +	HltClk = 0x5B,
   2.324 +	MultiIntr = 0x5C,
   2.325 +	TxSummary = 0x60,
   2.326 +	BasicModeCtrl = 0x62,
   2.327 +	BasicModeStatus = 0x64,
   2.328 +	NWayAdvert = 0x66,
   2.329 +	NWayLPAR = 0x68,
   2.330 +	NWayExpansion = 0x6A,
   2.331 +	/* Undocumented registers, but required for proper operation. */
   2.332 +	FIFOTMS = 0x70,		/* FIFO Control and test. */
   2.333 +	CSCR = 0x74,		/* Chip Status and Configuration Register. */
   2.334 +	PARA78 = 0x78,
   2.335 +	PARA7c = 0x7c,		/* Magic transceiver parameter register. */
   2.336 +	Config5 = 0xD8,		/* absent on RTL-8139A */
   2.337 +};
   2.338 +
   2.339 +enum ClearBitMasks {
   2.340 +	MultiIntrClear = 0xF000,
   2.341 +	ChipCmdClear = 0xE2,
   2.342 +	Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
   2.343 +};
   2.344 +
   2.345 +enum ChipCmdBits {
   2.346 +	CmdReset = 0x10,
   2.347 +	CmdRxEnb = 0x08,
   2.348 +	CmdTxEnb = 0x04,
   2.349 +	RxBufEmpty = 0x01,
   2.350 +};
   2.351 +
   2.352 +/* Interrupt register bits, using my own meaningful names. */
   2.353 +enum IntrStatusBits {
   2.354 +	PCIErr = 0x8000,
   2.355 +	PCSTimeout = 0x4000,
   2.356 +	RxFIFOOver = 0x40,
   2.357 +	RxUnderrun = 0x20,
   2.358 +	RxOverflow = 0x10,
   2.359 +	TxErr = 0x08,
   2.360 +	TxOK = 0x04,
   2.361 +	RxErr = 0x02,
   2.362 +	RxOK = 0x01,
   2.363 +
   2.364 +	RxAckBits = RxFIFOOver | RxOverflow | RxOK,
   2.365 +};
   2.366 +
   2.367 +enum TxStatusBits {
   2.368 +	TxHostOwns = 0x2000,
   2.369 +	TxUnderrun = 0x4000,
   2.370 +	TxStatOK = 0x8000,
   2.371 +	TxOutOfWindow = 0x20000000,
   2.372 +	TxAborted = 0x40000000,
   2.373 +	TxCarrierLost = 0x80000000,
   2.374 +};
   2.375 +enum RxStatusBits {
   2.376 +	RxMulticast = 0x8000,
   2.377 +	RxPhysical = 0x4000,
   2.378 +	RxBroadcast = 0x2000,
   2.379 +	RxBadSymbol = 0x0020,
   2.380 +	RxRunt = 0x0010,
   2.381 +	RxTooLong = 0x0008,
   2.382 +	RxCRCErr = 0x0004,
   2.383 +	RxBadAlign = 0x0002,
   2.384 +	RxStatusOK = 0x0001,
   2.385 +};
   2.386 +
   2.387 +/* Bits in RxConfig. */
   2.388 +enum rx_mode_bits {
   2.389 +	AcceptErr = 0x20,
   2.390 +	AcceptRunt = 0x10,
   2.391 +	AcceptBroadcast = 0x08,
   2.392 +	AcceptMulticast = 0x04,
   2.393 +	AcceptMyPhys = 0x02,
   2.394 +	AcceptAllPhys = 0x01,
   2.395 +};
   2.396 +
   2.397 +/* Bits in TxConfig. */
   2.398 +enum tx_config_bits {
   2.399 +	TxIFG1 = (1 << 25),	/* Interframe Gap Time */
   2.400 +	TxIFG0 = (1 << 24),	/* Enabling these bits violates IEEE 802.3 */
   2.401 +	TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
   2.402 +	TxCRC = (1 << 16),	/* DISABLE appending CRC to end of Tx packets */
   2.403 +	TxClearAbt = (1 << 0),	/* Clear abort (WO) */
   2.404 +	TxDMAShift = 8,		/* DMA burst value (0-7) is shifted this many bits */
   2.405 +	TxRetryShift = 4,	/* TXRR value (0-15) is shifted this many bits */
   2.406 +
   2.407 +	TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
   2.408 +};
   2.409 +
   2.410 +/* Bits in Config1 */
   2.411 +enum Config1Bits {
   2.412 +	Cfg1_PM_Enable = 0x01,
   2.413 +	Cfg1_VPD_Enable = 0x02,
   2.414 +	Cfg1_PIO = 0x04,
   2.415 +	Cfg1_MMIO = 0x08,
   2.416 +	LWAKE = 0x10,		/* not on 8139, 8139A */
   2.417 +	Cfg1_Driver_Load = 0x20,
   2.418 +	Cfg1_LED0 = 0x40,
   2.419 +	Cfg1_LED1 = 0x80,
   2.420 +	SLEEP = (1 << 1),	/* only on 8139, 8139A */
   2.421 +	PWRDN = (1 << 0),	/* only on 8139, 8139A */
   2.422 +};
   2.423 +
   2.424 +/* Bits in Config3 */
   2.425 +enum Config3Bits {
   2.426 +	Cfg3_FBtBEn    = (1 << 0), /* 1 = Fast Back to Back */
   2.427 +	Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
   2.428 +	Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
   2.429 +	Cfg3_CardB_En  = (1 << 3), /* 1 = enable CardBus registers */
   2.430 +	Cfg3_LinkUp    = (1 << 4), /* 1 = wake up on link up */
   2.431 +	Cfg3_Magic     = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
   2.432 +	Cfg3_PARM_En   = (1 << 6), /* 0 = software can set twister parameters */
   2.433 +	Cfg3_GNTSel    = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
   2.434 +};
   2.435 +
   2.436 +/* Bits in Config4 */
   2.437 +enum Config4Bits {
   2.438 +	LWPTN = (1 << 2),	/* not on 8139, 8139A */
   2.439 +};
   2.440 +
   2.441 +/* Bits in Config5 */
   2.442 +enum Config5Bits {
   2.443 +	Cfg5_PME_STS     = (1 << 0), /* 1 = PCI reset resets PME_Status */
   2.444 +	Cfg5_LANWake     = (1 << 1), /* 1 = enable LANWake signal */
   2.445 +	Cfg5_LDPS        = (1 << 2), /* 0 = save power when link is down */
   2.446 +	Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
   2.447 +	Cfg5_UWF         = (1 << 4), /* 1 = accept unicast wakeup frame */
   2.448 +	Cfg5_MWF         = (1 << 5), /* 1 = accept multicast wakeup frame */
   2.449 +	Cfg5_BWF         = (1 << 6), /* 1 = accept broadcast wakeup frame */
   2.450 +};
   2.451 +
   2.452 +enum RxConfigBits {
   2.453 +	/* rx fifo threshold */
   2.454 +	RxCfgFIFOShift = 13,
   2.455 +	RxCfgFIFONone = (7 << RxCfgFIFOShift),
   2.456 +
   2.457 +	/* Max DMA burst */
   2.458 +	RxCfgDMAShift = 8,
   2.459 +	RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
   2.460 +
   2.461 +	/* rx ring buffer length */
   2.462 +	RxCfgRcv8K = 0,
   2.463 +	RxCfgRcv16K = (1 << 11),
   2.464 +	RxCfgRcv32K = (1 << 12),
   2.465 +	RxCfgRcv64K = (1 << 11) | (1 << 12),
   2.466 +
   2.467 +	/* Disable packet wrap at end of Rx buffer */
   2.468 +	RxNoWrap = (1 << 7),
   2.469 +};
   2.470 +
   2.471 +
   2.472 +/* Twister tuning parameters from RealTek.
   2.473 +   Completely undocumented, but required to tune bad links on some boards. */
   2.474 +enum CSCRBits {
   2.475 +	CSCR_LinkOKBit = 0x0400,
   2.476 +	CSCR_LinkChangeBit = 0x0800,
   2.477 +	CSCR_LinkStatusBits = 0x0f000,
   2.478 +	CSCR_LinkDownOffCmd = 0x003c0,
   2.479 +	CSCR_LinkDownCmd = 0x0f3c0,
   2.480 +};
   2.481 +
   2.482 +
   2.483 +enum Cfg9346Bits {
   2.484 +	Cfg9346_Lock = 0x00,
   2.485 +	Cfg9346_Unlock = 0xC0,
   2.486 +};
   2.487 +
   2.488 +#ifdef CONFIG_8139TOO_TUNE_TWISTER
   2.489 +
   2.490 +enum TwisterParamVals {
   2.491 +	PARA78_default	= 0x78fa8388,
   2.492 +	PARA7c_default	= 0xcb38de43,	/* param[0][3] */
   2.493 +	PARA7c_xxx	= 0xcb38de43,
   2.494 +};
   2.495 +
   2.496 +static const unsigned long param[4][4] = {
   2.497 +	{0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
   2.498 +	{0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
   2.499 +	{0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
   2.500 +	{0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
   2.501 +};
   2.502 +
   2.503 +#endif /* CONFIG_8139TOO_TUNE_TWISTER */
   2.504 +
   2.505 +typedef enum {
   2.506 +	CH_8139 = 0,
   2.507 +	CH_8139_K,
   2.508 +	CH_8139A,
   2.509 +	CH_8139B,
   2.510 +	CH_8130,
   2.511 +	CH_8139C,
   2.512 +} chip_t;
   2.513 +
   2.514 +enum chip_flags {
   2.515 +	HasHltClk = (1 << 0),
   2.516 +	HasLWake = (1 << 1),
   2.517 +};
   2.518 +
   2.519 +
   2.520 +/* directly indexed by chip_t, above */
   2.521 +const static struct {
   2.522 +	const char *name;
   2.523 +	u8 version; /* from RTL8139C docs */
   2.524 +	u32 RxConfigMask; /* should clear the bits supported by this chip */
   2.525 +	u32 flags;
   2.526 +} rtl_chip_info[] = {
   2.527 +	{ "RTL-8139",
   2.528 +	  0x40,
   2.529 +	  0xf0fe0040, /* XXX copied from RTL8139A, verify */
   2.530 +	  HasHltClk,
   2.531 +	},
   2.532 +
   2.533 +	{ "RTL-8139 rev K",
   2.534 +	  0x60,
   2.535 +	  0xf0fe0040,
   2.536 +	  HasHltClk,
   2.537 +	},
   2.538 +
   2.539 +	{ "RTL-8139A",
   2.540 +	  0x70,
   2.541 +	  0xf0fe0040,
   2.542 +	  HasHltClk, /* XXX undocumented? */
   2.543 +	},
   2.544 +
   2.545 +	{ "RTL-8139B",
   2.546 +	  0x78,
   2.547 +	  0xf0fc0040,
   2.548 +	  HasLWake,
   2.549 +	},
   2.550 +
   2.551 +	{ "RTL-8130",
   2.552 +	  0x7C,
   2.553 +	  0xf0fe0040, /* XXX copied from RTL8139A, verify */
   2.554 +	  HasLWake,
   2.555 +	},
   2.556 +
   2.557 +	{ "RTL-8139C",
   2.558 +	  0x74,
   2.559 +	  0xf0fc0040, /* XXX copied from RTL8139B, verify */
   2.560 +	  HasLWake,
   2.561 +	},
   2.562 +
   2.563 +};
   2.564 +
   2.565 +struct rtl_extra_stats {
   2.566 +	unsigned long early_rx;
   2.567 +	unsigned long tx_buf_mapped;
   2.568 +	unsigned long tx_timeouts;
   2.569 +	unsigned long rx_lost_in_ring;
   2.570 +};
   2.571 +
   2.572 +struct rtl8139_private {
   2.573 +	void *mmio_addr;
   2.574 +	int drv_flags;
   2.575 +	struct pci_dev *pci_dev;
   2.576 +	struct net_device_stats stats;
   2.577 +	unsigned char *rx_ring;
   2.578 +	unsigned int cur_rx;	/* Index into the Rx buffer of next Rx pkt. */
   2.579 +	unsigned int tx_flag;
   2.580 +	unsigned long cur_tx;
   2.581 +	unsigned long dirty_tx;
   2.582 +	unsigned char *tx_buf[NUM_TX_DESC];	/* Tx bounce buffers */
   2.583 +	unsigned char *tx_bufs;	/* Tx bounce buffer region. */
   2.584 +	dma_addr_t rx_ring_dma;
   2.585 +	dma_addr_t tx_bufs_dma;
   2.586 +	signed char phys[4];		/* MII device addresses. */
   2.587 +	char twistie, twist_row, twist_col;	/* Twister tune state. */
   2.588 +	unsigned int default_port:4;	/* Last dev->if_port value. */
   2.589 +	spinlock_t lock;
   2.590 +	chip_t chipset;
   2.591 +#if 0
   2.592 +	pid_t thr_pid;
   2.593 +	wait_queue_head_t thr_wait;
   2.594 +	struct completion thr_exited;
   2.595 +#else
   2.596 +	struct timer_list timer;
   2.597 +#endif
   2.598 +	u32 rx_config;
   2.599 +	struct rtl_extra_stats xstats;
   2.600 +	int time_to_die;
   2.601 +	struct mii_if_info mii;
   2.602 +	unsigned int regs_len;
   2.603 +};
   2.604 +
   2.605 +MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
   2.606 +MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
   2.607 +MODULE_LICENSE("GPL");
   2.608 +
   2.609 +MODULE_PARM (multicast_filter_limit, "i");
   2.610 +MODULE_PARM (max_interrupt_work, "i");
   2.611 +MODULE_PARM (media, "1-" __MODULE_STRING(MAX_UNITS) "i");
   2.612 +MODULE_PARM (full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
   2.613 +MODULE_PARM (debug, "i");
   2.614 +MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
   2.615 +MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
   2.616 +MODULE_PARM_DESC (max_interrupt_work, "8139too maximum events handled per interrupt");
   2.617 +MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
   2.618 +MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
   2.619 +
   2.620 +static int read_eeprom (void *ioaddr, int location, int addr_len);
   2.621 +static int rtl8139_open (struct net_device *dev);
   2.622 +static int mdio_read (struct net_device *dev, int phy_id, int location);
   2.623 +static void mdio_write (struct net_device *dev, int phy_id, int location,
   2.624 +			int val);
   2.625 +#if 0
   2.626 +static int rtl8139_thread (void *data);
   2.627 +#else
   2.628 +static void rtl8139_timer (unsigned long arg);
   2.629 +#endif
   2.630 +static void rtl8139_tx_timeout (struct net_device *dev);
   2.631 +static void rtl8139_init_ring (struct net_device *dev);
   2.632 +static int rtl8139_start_xmit (struct sk_buff *skb,
   2.633 +			       struct net_device *dev);
   2.634 +static void rtl8139_interrupt (int irq, void *dev_instance,
   2.635 +			       struct pt_regs *regs);
   2.636 +static int rtl8139_close (struct net_device *dev);
   2.637 +#if 0
   2.638 +static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
   2.639 +#endif
   2.640 +static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
   2.641 +static void rtl8139_set_rx_mode (struct net_device *dev);
   2.642 +static void __set_rx_mode (struct net_device *dev);
   2.643 +static void rtl8139_hw_start (struct net_device *dev);
   2.644 +
   2.645 +#ifdef USE_IO_OPS
   2.646 +
   2.647 +#define RTL_R8(reg)		inb (((unsigned long)ioaddr) + (reg))
   2.648 +#define RTL_R16(reg)		inw (((unsigned long)ioaddr) + (reg))
   2.649 +#define RTL_R32(reg)		((unsigned long) inl (((unsigned long)ioaddr) + (reg)))
   2.650 +#define RTL_W8(reg, val8)	outb ((val8), ((unsigned long)ioaddr) + (reg))
   2.651 +#define RTL_W16(reg, val16)	outw ((val16), ((unsigned long)ioaddr) + (reg))
   2.652 +#define RTL_W32(reg, val32)	outl ((val32), ((unsigned long)ioaddr) + (reg))
   2.653 +#define RTL_W8_F		RTL_W8
   2.654 +#define RTL_W16_F		RTL_W16
   2.655 +#define RTL_W32_F		RTL_W32
   2.656 +#undef readb
   2.657 +#undef readw
   2.658 +#undef readl
   2.659 +#undef writeb
   2.660 +#undef writew
   2.661 +#undef writel
   2.662 +#define readb(addr) inb((unsigned long)(addr))
   2.663 +#define readw(addr) inw((unsigned long)(addr))
   2.664 +#define readl(addr) inl((unsigned long)(addr))
   2.665 +#define writeb(val,addr) outb((val),(unsigned long)(addr))
   2.666 +#define writew(val,addr) outw((val),(unsigned long)(addr))
   2.667 +#define writel(val,addr) outl((val),(unsigned long)(addr))
   2.668 +
   2.669 +#else
   2.670 +
   2.671 +/* write MMIO register, with flush */
   2.672 +/* Flush avoids rtl8139 bug w/ posted MMIO writes */
   2.673 +#define RTL_W8_F(reg, val8)	do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
   2.674 +#define RTL_W16_F(reg, val16)	do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
   2.675 +#define RTL_W32_F(reg, val32)	do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
   2.676 +
   2.677 +
   2.678 +#define MMIO_FLUSH_AUDIT_COMPLETE 1
   2.679 +#if MMIO_FLUSH_AUDIT_COMPLETE
   2.680 +
   2.681 +/* write MMIO register */
   2.682 +#define RTL_W8(reg, val8)	writeb ((val8), ioaddr + (reg))
   2.683 +#define RTL_W16(reg, val16)	writew ((val16), ioaddr + (reg))
   2.684 +#define RTL_W32(reg, val32)	writel ((val32), ioaddr + (reg))
   2.685 +
   2.686 +#else
   2.687 +
   2.688 +/* write MMIO register, then flush */
   2.689 +#define RTL_W8		RTL_W8_F
   2.690 +#define RTL_W16		RTL_W16_F
   2.691 +#define RTL_W32		RTL_W32_F
   2.692 +
   2.693 +#endif /* MMIO_FLUSH_AUDIT_COMPLETE */
   2.694 +
   2.695 +/* read MMIO register */
   2.696 +#define RTL_R8(reg)		readb (ioaddr + (reg))
   2.697 +#define RTL_R16(reg)		readw (ioaddr + (reg))
   2.698 +#define RTL_R32(reg)		((unsigned long) readl (ioaddr + (reg)))
   2.699 +
   2.700 +#endif /* USE_IO_OPS */
   2.701 +
   2.702 +
   2.703 +static const u16 rtl8139_intr_mask =
   2.704 +	PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
   2.705 +	TxErr | TxOK | RxErr | RxOK;
   2.706 +
   2.707 +static const unsigned int rtl8139_rx_config =
   2.708 +	RxCfgRcv32K | RxNoWrap |
   2.709 +	(RX_FIFO_THRESH << RxCfgFIFOShift) |
   2.710 +	(RX_DMA_BURST << RxCfgDMAShift);
   2.711 +
   2.712 +static const unsigned int rtl8139_tx_config =
   2.713 +	(TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
   2.714 +
   2.715 +static void __rtl8139_cleanup_dev (struct net_device *dev)
   2.716 +{
   2.717 +	struct rtl8139_private *tp;
   2.718 +	struct pci_dev *pdev;
   2.719 +
   2.720 +	assert (dev != NULL);
   2.721 +	assert (dev->priv != NULL);
   2.722 +
   2.723 +	tp = dev->priv;
   2.724 +	assert (tp->pci_dev != NULL);
   2.725 +	pdev = tp->pci_dev;
   2.726 +
   2.727 +#ifndef USE_IO_OPS
   2.728 +	if (tp->mmio_addr)
   2.729 +		iounmap (tp->mmio_addr);
   2.730 +#endif /* !USE_IO_OPS */
   2.731 +
   2.732 +	/* it's ok to call this even if we have no regions to free */
   2.733 +	pci_release_regions (pdev);
   2.734 +
   2.735 +#ifndef RTL8139_NDEBUG
   2.736 +	/* poison memory before freeing */
   2.737 +	memset (dev, 0xBC,
   2.738 +		sizeof (struct net_device) +
   2.739 +		sizeof (struct rtl8139_private));
   2.740 +#endif /* RTL8139_NDEBUG */
   2.741 +
   2.742 +	kfree (dev);
   2.743 +
   2.744 +	pci_set_drvdata (pdev, NULL);
   2.745 +}
   2.746 +
   2.747 +
   2.748 +static void rtl8139_chip_reset (void *ioaddr)
   2.749 +{
   2.750 +	int i;
   2.751 +
   2.752 +	/* Soft reset the chip. */
   2.753 +	RTL_W8 (ChipCmd, CmdReset);
   2.754 +
   2.755 +	/* Check that the chip has finished the reset. */
   2.756 +	for (i = 1000; i > 0; i--) {
   2.757 +		barrier();
   2.758 +		if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
   2.759 +			break;
   2.760 +		udelay (10);
   2.761 +	}
   2.762 +}
   2.763 +
   2.764 +
   2.765 +static int __devinit rtl8139_init_board (struct pci_dev *pdev,
   2.766 +					 struct net_device **dev_out)
   2.767 +{
   2.768 +	void *ioaddr;
   2.769 +	struct net_device *dev;
   2.770 +	struct rtl8139_private *tp;
   2.771 +	u8 tmp8;
   2.772 +	int rc;
   2.773 +	unsigned int i;
   2.774 +	u32 pio_start, pio_end, pio_flags, pio_len;
   2.775 +	unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
   2.776 +	u32 tmp;
   2.777 +
   2.778 +	assert (pdev != NULL);
   2.779 +
   2.780 +	*dev_out = NULL;
   2.781 +
   2.782 +	/* dev and dev->priv zeroed in alloc_etherdev */
   2.783 +	dev = alloc_etherdev (sizeof (*tp));
   2.784 +	if (dev == NULL) {
   2.785 +		printk (KERN_ERR PFX "%s: Unable to alloc new net device\n", pdev->slot_name);
   2.786 +		return -ENOMEM;
   2.787 +	}
   2.788 +	SET_MODULE_OWNER(dev);
   2.789 +	tp = dev->priv;
   2.790 +	tp->pci_dev = pdev;
   2.791 +
   2.792 +	/* enable device (incl. PCI PM wakeup and hotplug setup) */
   2.793 +	rc = pci_enable_device (pdev);
   2.794 +	if (rc)
   2.795 +		goto err_out;
   2.796 +
   2.797 +	pio_start = pci_resource_start (pdev, 0);
   2.798 +	pio_end = pci_resource_end (pdev, 0);
   2.799 +	pio_flags = pci_resource_flags (pdev, 0);
   2.800 +	pio_len = pci_resource_len (pdev, 0);
   2.801 +
   2.802 +	mmio_start = pci_resource_start (pdev, 1);
   2.803 +	mmio_end = pci_resource_end (pdev, 1);
   2.804 +	mmio_flags = pci_resource_flags (pdev, 1);
   2.805 +	mmio_len = pci_resource_len (pdev, 1);
   2.806 +
   2.807 +	/* set this immediately, we need to know before
   2.808 +	 * we talk to the chip directly */
   2.809 +	DPRINTK("PIO region size == 0x%02X\n", pio_len);
   2.810 +	DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
   2.811 +
   2.812 +#ifdef USE_IO_OPS
   2.813 +	/* make sure PCI base addr 0 is PIO */
   2.814 +	if (!(pio_flags & IORESOURCE_IO)) {
   2.815 +		printk (KERN_ERR PFX "%s: region #0 not a PIO resource, aborting\n", pdev->slot_name);
   2.816 +		rc = -ENODEV;
   2.817 +		goto err_out;
   2.818 +	}
   2.819 +	/* check for weird/broken PCI region reporting */
   2.820 +	if (pio_len < RTL_MIN_IO_SIZE) {
   2.821 +		printk (KERN_ERR PFX "%s: Invalid PCI I/O region size(s), aborting\n", pdev->slot_name);
   2.822 +		rc = -ENODEV;
   2.823 +		goto err_out;
   2.824 +	}
   2.825 +#else
   2.826 +	/* make sure PCI base addr 1 is MMIO */
   2.827 +	if (!(mmio_flags & IORESOURCE_MEM)) {
   2.828 +		printk (KERN_ERR PFX "%s: region #1 not an MMIO resource, aborting\n", pdev->slot_name);
   2.829 +		rc = -ENODEV;
   2.830 +		goto err_out;
   2.831 +	}
   2.832 +	if (mmio_len < RTL_MIN_IO_SIZE) {
   2.833 +		printk (KERN_ERR PFX "%s: Invalid PCI mem region size(s), aborting\n", pdev->slot_name);
   2.834 +		rc = -ENODEV;
   2.835 +		goto err_out;
   2.836 +	}
   2.837 +#endif
   2.838 +
   2.839 +	rc = pci_request_regions (pdev, "8139too");
   2.840 +	if (rc)
   2.841 +		goto err_out;
   2.842 +
   2.843 +	/* enable PCI bus-mastering */
   2.844 +	pci_set_master (pdev);
   2.845 +
   2.846 +#ifdef USE_IO_OPS
   2.847 +	ioaddr = (void *) pio_start;
   2.848 +	dev->base_addr = pio_start;
   2.849 +	tp->mmio_addr = ioaddr;
   2.850 +	tp->regs_len = pio_len;
   2.851 +#else
   2.852 +	/* ioremap MMIO region */
   2.853 +	ioaddr = ioremap (mmio_start, mmio_len);
   2.854 +	if (ioaddr == NULL) {
   2.855 +		printk (KERN_ERR PFX "%s: cannot remap MMIO, aborting\n", pdev->slot_name);
   2.856 +		rc = -EIO;
   2.857 +		goto err_out;
   2.858 +	}
   2.859 +	dev->base_addr = (long) ioaddr;
   2.860 +	tp->mmio_addr = ioaddr;
   2.861 +	tp->regs_len = mmio_len;
   2.862 +#endif /* USE_IO_OPS */
   2.863 +
   2.864 +	/* Bring old chips out of low-power mode. */
   2.865 +	RTL_W8 (HltClk, 'R');
   2.866 +
   2.867 +	/* check for missing/broken hardware */
   2.868 +	if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
   2.869 +		printk (KERN_ERR PFX "%s: Chip not responding, ignoring board\n",
   2.870 +			pdev->slot_name);
   2.871 +		rc = -EIO;
   2.872 +		goto err_out;
   2.873 +	}
   2.874 +
   2.875 +	/* identify chip attached to board */
   2.876 +	tmp = RTL_R8 (ChipVersion);
   2.877 +	for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
   2.878 +		if (tmp == rtl_chip_info[i].version) {
   2.879 +			tp->chipset = i;
   2.880 +			goto match;
   2.881 +		}
   2.882 +
   2.883 +	/* if unknown chip, assume array element #0, original RTL-8139 in this case */
   2.884 +	printk (KERN_DEBUG PFX "%s: unknown chip version, assuming RTL-8139\n",
   2.885 +		pdev->slot_name);
   2.886 +	printk (KERN_DEBUG PFX "%s: TxConfig = 0x%lx\n", pdev->slot_name, RTL_R32 (TxConfig));
   2.887 +	tp->chipset = 0;
   2.888 +
   2.889 +match:
   2.890 +	DPRINTK ("chipset id (%d) == index %d, '%s'\n",
   2.891 +		tmp,
   2.892 +		tp->chipset,
   2.893 +		rtl_chip_info[tp->chipset].name);
   2.894 +
   2.895 +	if (tp->chipset >= CH_8139B) {
   2.896 +		u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
   2.897 +		DPRINTK("PCI PM wakeup\n");
   2.898 +		if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
   2.899 +		    (tmp8 & LWAKE))
   2.900 +			new_tmp8 &= ~LWAKE;
   2.901 +		new_tmp8 |= Cfg1_PM_Enable;
   2.902 +		if (new_tmp8 != tmp8) {
   2.903 +			RTL_W8 (Cfg9346, Cfg9346_Unlock);
   2.904 +			RTL_W8 (Config1, tmp8);
   2.905 +			RTL_W8 (Cfg9346, Cfg9346_Lock);
   2.906 +		}
   2.907 +		if (rtl_chip_info[tp->chipset].flags & HasLWake) {
   2.908 +			tmp8 = RTL_R8 (Config4);
   2.909 +			if (tmp8 & LWPTN)
   2.910 +				RTL_W8 (Config4, tmp8 & ~LWPTN);
   2.911 +		}
   2.912 +	} else {
   2.913 +		DPRINTK("Old chip wakeup\n");
   2.914 +		tmp8 = RTL_R8 (Config1);
   2.915 +		tmp8 &= ~(SLEEP | PWRDN);
   2.916 +		RTL_W8 (Config1, tmp8);
   2.917 +	}
   2.918 +
   2.919 +	rtl8139_chip_reset (ioaddr);
   2.920 +
   2.921 +	*dev_out = dev;
   2.922 +	return 0;
   2.923 +
   2.924 +err_out:
   2.925 +	__rtl8139_cleanup_dev (dev);
   2.926 +	return rc;
   2.927 +}
   2.928 +
   2.929 +
   2.930 +static int __devinit rtl8139_init_one (struct pci_dev *pdev,
   2.931 +				       const struct pci_device_id *ent)
   2.932 +{
   2.933 +	struct net_device *dev = NULL;
   2.934 +	struct rtl8139_private *tp;
   2.935 +	int i, addr_len, option;
   2.936 +	void *ioaddr;
   2.937 +	static int board_idx = -1;
   2.938 +	u8 pci_rev;
   2.939 +
   2.940 +	assert (pdev != NULL);
   2.941 +	assert (ent != NULL);
   2.942 +
   2.943 +	board_idx++;
   2.944 +
   2.945 +	/* when we're built into the kernel, the driver version message
   2.946 +	 * is only printed if at least one 8139 board has been found
   2.947 +	 */
   2.948 +#ifndef MODULE
   2.949 +	{
   2.950 +		static int printed_version;
   2.951 +		if (!printed_version++)
   2.952 +			printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
   2.953 +	}
   2.954 +#endif
   2.955 +
   2.956 +	pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
   2.957 +
   2.958 +	if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
   2.959 +	    pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev >= 0x20) {
   2.960 +		printk(KERN_INFO PFX "pci dev %s (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
   2.961 +		       pdev->slot_name, pdev->vendor, pdev->device, pci_rev);
   2.962 +		printk(KERN_INFO PFX "Use the \"8139cp\" driver for improved performance and stability.\n");
   2.963 +	}
   2.964 +
   2.965 +	i = rtl8139_init_board (pdev, &dev);
   2.966 +	if (i < 0)
   2.967 +		return i;
   2.968 +
   2.969 +	tp = dev->priv;
   2.970 +	ioaddr = tp->mmio_addr;
   2.971 +
   2.972 +	assert (ioaddr != NULL);
   2.973 +	assert (dev != NULL);
   2.974 +	assert (tp != NULL);
   2.975 +
   2.976 +	addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
   2.977 +	for (i = 0; i < 3; i++)
   2.978 +		((u16 *) (dev->dev_addr))[i] =
   2.979 +		    le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
   2.980 +
   2.981 +	/* The Rtl8139-specific entries in the device structure. */
   2.982 +	dev->open = rtl8139_open;
   2.983 +	dev->hard_start_xmit = rtl8139_start_xmit;
   2.984 +	dev->stop = rtl8139_close;
   2.985 +	dev->get_stats = rtl8139_get_stats;
   2.986 +	dev->set_multicast_list = rtl8139_set_rx_mode;
   2.987 +#if 0
   2.988 +	dev->do_ioctl = netdev_ioctl;
   2.989 +#endif
   2.990 +	dev->tx_timeout = rtl8139_tx_timeout;
   2.991 +	dev->watchdog_timeo = TX_TIMEOUT;
   2.992 +
   2.993 +	/* note: the hardware is not capable of sg/csum/highdma, however
   2.994 +	 * through the use of skb_copy_and_csum_dev we enable these
   2.995 +	 * features
   2.996 +	 */
   2.997 +	dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
   2.998 +
   2.999 +	dev->irq = pdev->irq;
  2.1000 +
  2.1001 +	/* dev->priv/tp zeroed and aligned in init_etherdev */
  2.1002 +	tp = dev->priv;
  2.1003 +
  2.1004 +	/* note: tp->chipset set in rtl8139_init_board */
  2.1005 +	tp->drv_flags = board_info[ent->driver_data].hw_flags;
  2.1006 +	tp->mmio_addr = ioaddr;
  2.1007 +	spin_lock_init (&tp->lock);
  2.1008 +#if 0
  2.1009 +	init_waitqueue_head (&tp->thr_wait);
  2.1010 +	init_completion (&tp->thr_exited);
  2.1011 +#endif
  2.1012 +	tp->mii.dev = dev;
  2.1013 +	tp->mii.mdio_read = mdio_read;
  2.1014 +	tp->mii.mdio_write = mdio_write;
  2.1015 +	tp->mii.phy_id_mask = 0x3f;
  2.1016 +	tp->mii.reg_num_mask = 0x1f;
  2.1017 +
  2.1018 +	/* dev is fully set up and ready to use now */
  2.1019 +	DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
  2.1020 +	i = register_netdev (dev);
  2.1021 +	if (i) goto err_out;
  2.1022 +
  2.1023 +	pci_set_drvdata (pdev, dev);
  2.1024 +
  2.1025 +	printk (KERN_INFO "%s: %s at 0x%lx, "
  2.1026 +		"%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
  2.1027 +		"IRQ %d\n",
  2.1028 +		dev->name,
  2.1029 +		board_info[ent->driver_data].name,
  2.1030 +		dev->base_addr,
  2.1031 +		dev->dev_addr[0], dev->dev_addr[1],
  2.1032 +		dev->dev_addr[2], dev->dev_addr[3],
  2.1033 +		dev->dev_addr[4], dev->dev_addr[5],
  2.1034 +		dev->irq);
  2.1035 +
  2.1036 +	printk (KERN_DEBUG "%s:  Identified 8139 chip type '%s'\n",
  2.1037 +		dev->name, rtl_chip_info[tp->chipset].name);
  2.1038 +
  2.1039 +	/* Find the connected MII xcvrs.
  2.1040 +	   Doing this in open() would allow detecting external xcvrs later, but
  2.1041 +	   takes too much time. */
  2.1042 +#ifdef CONFIG_8139TOO_8129
  2.1043 +	if (tp->drv_flags & HAS_MII_XCVR) {
  2.1044 +		int phy, phy_idx = 0;
  2.1045 +		for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
  2.1046 +			int mii_status = mdio_read(dev, phy, 1);
  2.1047 +			if (mii_status != 0xffff  &&  mii_status != 0x0000) {
  2.1048 +				u16 advertising = mdio_read(dev, phy, 4);
  2.1049 +				tp->phys[phy_idx++] = phy;
  2.1050 +				printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
  2.1051 +					   "advertising %4.4x.\n",
  2.1052 +					   dev->name, phy, mii_status, advertising);
  2.1053 +			}
  2.1054 +		}
  2.1055 +		if (phy_idx == 0) {
  2.1056 +			printk(KERN_INFO "%s: No MII transceivers found!  Assuming SYM "
  2.1057 +				   "transceiver.\n",
  2.1058 +				   dev->name);
  2.1059 +			tp->phys[0] = 32;
  2.1060 +		}
  2.1061 +	} else
  2.1062 +#endif
  2.1063 +		tp->phys[0] = 32;
  2.1064 +	tp->mii.phy_id = tp->phys[0];
  2.1065 +
  2.1066 +	/* The lower four bits are the media type. */
  2.1067 +	option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
  2.1068 +	if (option > 0) {
  2.1069 +		tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
  2.1070 +		tp->default_port = option & 0xFF;
  2.1071 +		if (tp->default_port)
  2.1072 +			tp->mii.force_media = 1;
  2.1073 +	}
  2.1074 +	if (board_idx < MAX_UNITS  &&  full_duplex[board_idx] > 0)
  2.1075 +		tp->mii.full_duplex = full_duplex[board_idx];
  2.1076 +	if (tp->mii.full_duplex) {
  2.1077 +		printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
  2.1078 +		/* Changing the MII-advertised media because might prevent
  2.1079 +		   re-connection. */
  2.1080 +		tp->mii.force_media = 1;
  2.1081 +	}
  2.1082 +	if (tp->default_port) {
  2.1083 +		printk(KERN_INFO "  Forcing %dMbps %s-duplex operation.\n",
  2.1084 +			   (option & 0x20 ? 100 : 10),
  2.1085 +			   (option & 0x10 ? "full" : "half"));
  2.1086 +		mdio_write(dev, tp->phys[0], 0,
  2.1087 +				   ((option & 0x20) ? 0x2000 : 0) | 	/* 100Mbps? */
  2.1088 +				   ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
  2.1089 +	}
  2.1090 +
  2.1091 +	/* Put the chip into low-power mode. */
  2.1092 +	if (rtl_chip_info[tp->chipset].flags & HasHltClk)
  2.1093 +		RTL_W8 (HltClk, 'H');	/* 'R' would leave the clock running. */
  2.1094 +
  2.1095 +        alert_slow_netdevice(dev, (char *)board_info[ent->driver_data].name);
  2.1096 +
  2.1097 +	return 0;
  2.1098 +
  2.1099 +err_out:
  2.1100 +	__rtl8139_cleanup_dev (dev);
  2.1101 +	return i;
  2.1102 +}
  2.1103 +
  2.1104 +
  2.1105 +static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
  2.1106 +{
  2.1107 +	struct net_device *dev = pci_get_drvdata (pdev);
  2.1108 +	struct rtl8139_private *np;
  2.1109 +
  2.1110 +	assert (dev != NULL);
  2.1111 +	np = dev->priv;
  2.1112 +	assert (np != NULL);
  2.1113 +
  2.1114 +	unregister_netdev (dev);
  2.1115 +
  2.1116 +	__rtl8139_cleanup_dev (dev);
  2.1117 +}
  2.1118 +
  2.1119 +
  2.1120 +/* Serial EEPROM section. */
  2.1121 +
  2.1122 +/*  EEPROM_Ctrl bits. */
  2.1123 +#define EE_SHIFT_CLK	0x04	/* EEPROM shift clock. */
  2.1124 +#define EE_CS			0x08	/* EEPROM chip select. */
  2.1125 +#define EE_DATA_WRITE	0x02	/* EEPROM chip data in. */
  2.1126 +#define EE_WRITE_0		0x00
  2.1127 +#define EE_WRITE_1		0x02
  2.1128 +#define EE_DATA_READ	0x01	/* EEPROM chip data out. */
  2.1129 +#define EE_ENB			(0x80 | EE_CS)
  2.1130 +
  2.1131 +/* Delay between EEPROM clock transitions.
  2.1132 +   No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
  2.1133 + */
  2.1134 +
  2.1135 +#define eeprom_delay()	readl(ee_addr)
  2.1136 +
  2.1137 +/* The EEPROM commands include the alway-set leading bit. */
  2.1138 +#define EE_WRITE_CMD	(5)
  2.1139 +#define EE_READ_CMD		(6)
  2.1140 +#define EE_ERASE_CMD	(7)
  2.1141 +
  2.1142 +static int __devinit read_eeprom (void *ioaddr, int location, int addr_len)
  2.1143 +{
  2.1144 +	int i;
  2.1145 +	unsigned retval = 0;
  2.1146 +	void *ee_addr = ioaddr + Cfg9346;
  2.1147 +	int read_cmd = location | (EE_READ_CMD << addr_len);
  2.1148 +
  2.1149 +	writeb (EE_ENB & ~EE_CS, ee_addr);
  2.1150 +	writeb (EE_ENB, ee_addr);
  2.1151 +	eeprom_delay ();
  2.1152 +
  2.1153 +	/* Shift the read command bits out. */
  2.1154 +	for (i = 4 + addr_len; i >= 0; i--) {
  2.1155 +		int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
  2.1156 +		writeb (EE_ENB | dataval, ee_addr);
  2.1157 +		eeprom_delay ();
  2.1158 +		writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
  2.1159 +		eeprom_delay ();
  2.1160 +	}
  2.1161 +	writeb (EE_ENB, ee_addr);
  2.1162 +	eeprom_delay ();
  2.1163 +
  2.1164 +	for (i = 16; i > 0; i--) {
  2.1165 +		writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
  2.1166 +		eeprom_delay ();
  2.1167 +		retval =
  2.1168 +		    (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
  2.1169 +				     0);
  2.1170 +		writeb (EE_ENB, ee_addr);
  2.1171 +		eeprom_delay ();
  2.1172 +	}
  2.1173 +
  2.1174 +	/* Terminate the EEPROM access. */
  2.1175 +	writeb (~EE_CS, ee_addr);
  2.1176 +	eeprom_delay ();
  2.1177 +
  2.1178 +	return retval;
  2.1179 +}
  2.1180 +
  2.1181 +/* MII serial management: mostly bogus for now. */
  2.1182 +/* Read and write the MII management registers using software-generated
  2.1183 +   serial MDIO protocol.
  2.1184 +   The maximum data clock rate is 2.5 Mhz.  The minimum timing is usually
  2.1185 +   met by back-to-back PCI I/O cycles, but we insert a delay to avoid
  2.1186 +   "overclocking" issues. */
  2.1187 +#define MDIO_DIR		0x80
  2.1188 +#define MDIO_DATA_OUT	0x04
  2.1189 +#define MDIO_DATA_IN	0x02
  2.1190 +#define MDIO_CLK		0x01
  2.1191 +#define MDIO_WRITE0 (MDIO_DIR)
  2.1192 +#define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
  2.1193 +
  2.1194 +#define mdio_delay(mdio_addr)	readb(mdio_addr)
  2.1195 +
  2.1196 +
  2.1197 +static char mii_2_8139_map[8] = {
  2.1198 +	BasicModeCtrl,
  2.1199 +	BasicModeStatus,
  2.1200 +	0,
  2.1201 +	0,
  2.1202 +	NWayAdvert,
  2.1203 +	NWayLPAR,
  2.1204 +	NWayExpansion,
  2.1205 +	0
  2.1206 +};
  2.1207 +
  2.1208 +
  2.1209 +#ifdef CONFIG_8139TOO_8129
  2.1210 +/* Syncronize the MII management interface by shifting 32 one bits out. */
  2.1211 +static void mdio_sync (void *mdio_addr)
  2.1212 +{
  2.1213 +	int i;
  2.1214 +
  2.1215 +	for (i = 32; i >= 0; i--) {
  2.1216 +		writeb (MDIO_WRITE1, mdio_addr);
  2.1217 +		mdio_delay (mdio_addr);
  2.1218 +		writeb (MDIO_WRITE1 | MDIO_CLK, mdio_addr);
  2.1219 +		mdio_delay (mdio_addr);
  2.1220 +	}
  2.1221 +}
  2.1222 +#endif
  2.1223 +
  2.1224 +static int mdio_read (struct net_device *dev, int phy_id, int location)
  2.1225 +{
  2.1226 +	struct rtl8139_private *tp = dev->priv;
  2.1227 +	int retval = 0;
  2.1228 +#ifdef CONFIG_8139TOO_8129
  2.1229 +	void *mdio_addr = tp->mmio_addr + Config4;
  2.1230 +	int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
  2.1231 +	int i;
  2.1232 +#endif
  2.1233 +
  2.1234 +	if (phy_id > 31) {	/* Really a 8139.  Use internal registers. */
  2.1235 +		return location < 8 && mii_2_8139_map[location] ?
  2.1236 +		    readw (tp->mmio_addr + mii_2_8139_map[location]) : 0;
  2.1237 +	}
  2.1238 +
  2.1239 +#ifdef CONFIG_8139TOO_8129
  2.1240 +	mdio_sync (mdio_addr);
  2.1241 +	/* Shift the read command bits out. */
  2.1242 +	for (i = 15; i >= 0; i--) {
  2.1243 +		int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
  2.1244 +
  2.1245 +		writeb (MDIO_DIR | dataval, mdio_addr);
  2.1246 +		mdio_delay (mdio_addr);
  2.1247 +		writeb (MDIO_DIR | dataval | MDIO_CLK, mdio_addr);
  2.1248 +		mdio_delay (mdio_addr);
  2.1249 +	}
  2.1250 +
  2.1251 +	/* Read the two transition, 16 data, and wire-idle bits. */
  2.1252 +	for (i = 19; i > 0; i--) {
  2.1253 +		writeb (0, mdio_addr);
  2.1254 +		mdio_delay (mdio_addr);
  2.1255 +		retval = (retval << 1) | ((readb (mdio_addr) & MDIO_DATA_IN) ? 1 : 0);
  2.1256 +		writeb (MDIO_CLK, mdio_addr);
  2.1257 +		mdio_delay (mdio_addr);
  2.1258 +	}
  2.1259 +#endif
  2.1260 +
  2.1261 +	return (retval >> 1) & 0xffff;
  2.1262 +}
  2.1263 +
  2.1264 +
  2.1265 +static void mdio_write (struct net_device *dev, int phy_id, int location,
  2.1266 +			int value)
  2.1267 +{
  2.1268 +	struct rtl8139_private *tp = dev->priv;
  2.1269 +#ifdef CONFIG_8139TOO_8129
  2.1270 +	void *mdio_addr = tp->mmio_addr + Config4;
  2.1271 +	int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
  2.1272 +	int i;
  2.1273 +#endif
  2.1274 +
  2.1275 +	if (phy_id > 31) {	/* Really a 8139.  Use internal registers. */
  2.1276 +		void *ioaddr = tp->mmio_addr;
  2.1277 +		if (location == 0) {
  2.1278 +			RTL_W8 (Cfg9346, Cfg9346_Unlock);
  2.1279 +			RTL_W16 (BasicModeCtrl, value);
  2.1280 +			RTL_W8 (Cfg9346, Cfg9346_Lock);
  2.1281 +		} else if (location < 8 && mii_2_8139_map[location])
  2.1282 +			RTL_W16 (mii_2_8139_map[location], value);
  2.1283 +		return;
  2.1284 +	}
  2.1285 +
  2.1286 +#ifdef CONFIG_8139TOO_8129
  2.1287 +	mdio_sync (mdio_addr);
  2.1288 +
  2.1289 +	/* Shift the command bits out. */
  2.1290 +	for (i = 31; i >= 0; i--) {
  2.1291 +		int dataval =
  2.1292 +		    (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
  2.1293 +		writeb (dataval, mdio_addr);
  2.1294 +		mdio_delay (mdio_addr);
  2.1295 +		writeb (dataval | MDIO_CLK, mdio_addr);
  2.1296 +		mdio_delay (mdio_addr);
  2.1297 +	}
  2.1298 +	/* Clear out extra bits. */
  2.1299 +	for (i = 2; i > 0; i--) {
  2.1300 +		writeb (0, mdio_addr);
  2.1301 +		mdio_delay (mdio_addr);
  2.1302 +		writeb (MDIO_CLK, mdio_addr);
  2.1303 +		mdio_delay (mdio_addr);
  2.1304 +	}
  2.1305 +#endif
  2.1306 +}
  2.1307 +
  2.1308 +
  2.1309 +static int rtl8139_open (struct net_device *dev)
  2.1310 +{
  2.1311 +	struct rtl8139_private *tp = dev->priv;
  2.1312 +	int retval;
  2.1313 +#ifdef RTL8139_DEBUG
  2.1314 +	void *ioaddr = tp->mmio_addr;
  2.1315 +#endif
  2.1316 +
  2.1317 +	retval = request_irq (dev->irq, rtl8139_interrupt, SA_SHIRQ, dev->name, dev);
  2.1318 +	if (retval)
  2.1319 +		return retval;
  2.1320 +
  2.1321 +	tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
  2.1322 +					   &tp->tx_bufs_dma);
  2.1323 +	tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
  2.1324 +					   &tp->rx_ring_dma);
  2.1325 +	if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
  2.1326 +		free_irq(dev->irq, dev);
  2.1327 +
  2.1328 +		if (tp->tx_bufs)
  2.1329 +			pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
  2.1330 +					    tp->tx_bufs, tp->tx_bufs_dma);
  2.1331 +		if (tp->rx_ring)
  2.1332 +			pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
  2.1333 +					    tp->rx_ring, tp->rx_ring_dma);
  2.1334 +
  2.1335 +		return -ENOMEM;
  2.1336 +
  2.1337 +	}
  2.1338 +
  2.1339 +	tp->mii.full_duplex = tp->mii.force_media;
  2.1340 +	tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
  2.1341 +	tp->twistie = (tp->chipset == CH_8139_K) ? 1 : 0;
  2.1342 +	tp->time_to_die = 0;
  2.1343 +
  2.1344 +	rtl8139_init_ring (dev);
  2.1345 +	rtl8139_hw_start (dev);
  2.1346 +
  2.1347 +	DPRINTK ("%s: rtl8139_open() ioaddr %#lx IRQ %d"
  2.1348 +			" GP Pins %2.2x %s-duplex.\n",
  2.1349 +			dev->name, pci_resource_start (tp->pci_dev, 1),
  2.1350 +			dev->irq, RTL_R8 (MediaStatus),
  2.1351 +			tp->mii.full_duplex ? "full" : "half");
  2.1352 +
  2.1353 +#if 0
  2.1354 +	tp->thr_pid = kernel_thread (rtl8139_thread, dev, CLONE_FS | CLONE_FILES);
  2.1355 +	if (tp->thr_pid < 0)
  2.1356 +		printk (KERN_WARNING "%s: unable to start kernel thread\n",
  2.1357 +			dev->name);
  2.1358 +#else
  2.1359 +	init_timer(&tp->timer);
  2.1360 +	tp->timer.expires = jiffies + next_tick;
  2.1361 +	tp->timer.data = (unsigned long)dev;
  2.1362 +	tp->timer.function = rtl8139_timer;
  2.1363 +	add_timer(&tp->timer);
  2.1364 +#endif
  2.1365 +
  2.1366 +	return 0;
  2.1367 +}
  2.1368 +
  2.1369 +
  2.1370 +static void rtl_check_media (struct net_device *dev)
  2.1371 +{
  2.1372 +	struct rtl8139_private *tp = dev->priv;
  2.1373 +
  2.1374 +	if (tp->phys[0] >= 0) {
  2.1375 +		u16 mii_lpa = mdio_read(dev, tp->phys[0], MII_LPA);
  2.1376 +		if (mii_lpa == 0xffff)
  2.1377 +			;					/* Not there */
  2.1378 +		else if ((mii_lpa & LPA_100FULL) == LPA_100FULL
  2.1379 +				 || (mii_lpa & 0x00C0) == LPA_10FULL)
  2.1380 +			tp->mii.full_duplex = 1;
  2.1381 +
  2.1382 +		printk (KERN_INFO"%s: Setting %s%s-duplex based on"
  2.1383 +				" auto-negotiated partner ability %4.4x.\n",
  2.1384 +		        dev->name, mii_lpa == 0 ? "" :
  2.1385 +				(mii_lpa & 0x0180) ? "100mbps " : "10mbps ",
  2.1386 +			tp->mii.full_duplex ? "full" : "half", mii_lpa);
  2.1387 +	}
  2.1388 +}
  2.1389 +
  2.1390 +/* Start the hardware at open or resume. */
  2.1391 +static void rtl8139_hw_start (struct net_device *dev)
  2.1392 +{
  2.1393 +	struct rtl8139_private *tp = dev->priv;
  2.1394 +	void *ioaddr = tp->mmio_addr;
  2.1395 +	u32 i;
  2.1396 +	u8 tmp;
  2.1397 +
  2.1398 +	/* Bring old chips out of low-power mode. */
  2.1399 +	if (rtl_chip_info[tp->chipset].flags & HasHltClk)
  2.1400 +		RTL_W8 (HltClk, 'R');
  2.1401 +
  2.1402 +	rtl8139_chip_reset (ioaddr);
  2.1403 +
  2.1404 +	/* unlock Config[01234] and BMCR register writes */
  2.1405 +	RTL_W8_F (Cfg9346, Cfg9346_Unlock);
  2.1406 +	/* Restore our idea of the MAC address. */
  2.1407 +	RTL_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
  2.1408 +	RTL_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
  2.1409 +
  2.1410 +	/* Must enable Tx/Rx before setting transfer thresholds! */
  2.1411 +	RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
  2.1412 +
  2.1413 +	tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
  2.1414 +	RTL_W32 (RxConfig, tp->rx_config);
  2.1415 +
  2.1416 +	/* Check this value: the documentation for IFG contradicts ifself. */
  2.1417 +	RTL_W32 (TxConfig, rtl8139_tx_config);
  2.1418 +
  2.1419 +	tp->cur_rx = 0;
  2.1420 +
  2.1421 +	rtl_check_media (dev);
  2.1422 +
  2.1423 +	if (tp->chipset >= CH_8139B) {
  2.1424 +		/* Disable magic packet scanning, which is enabled
  2.1425 +		 * when PM is enabled in Config1.  It can be reenabled
  2.1426 +		 * via ETHTOOL_SWOL if desired.  */
  2.1427 +		RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
  2.1428 +	}
  2.1429 +
  2.1430 +	DPRINTK("init buffer addresses\n");
  2.1431 +
  2.1432 +	/* Lock Config[01234] and BMCR register writes */
  2.1433 +	RTL_W8 (Cfg9346, Cfg9346_Lock);
  2.1434 +
  2.1435 +	/* init Rx ring buffer DMA address */
  2.1436 +	RTL_W32_F (RxBuf, tp->rx_ring_dma);
  2.1437 +
  2.1438 +	/* init Tx buffer DMA addresses */
  2.1439 +	for (i = 0; i < NUM_TX_DESC; i++)
  2.1440 +		RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
  2.1441 +
  2.1442 +	RTL_W32 (RxMissed, 0);
  2.1443 +
  2.1444 +	rtl8139_set_rx_mode (dev);
  2.1445 +
  2.1446 +	/* no early-rx interrupts */
  2.1447 +	RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
  2.1448 +
  2.1449 +	/* make sure RxTx has started */
  2.1450 +	tmp = RTL_R8 (ChipCmd);
  2.1451 +	if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
  2.1452 +		RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
  2.1453 +
  2.1454 +	/* Enable all known interrupts by setting the interrupt mask. */
  2.1455 +	RTL_W16 (IntrMask, rtl8139_intr_mask);
  2.1456 +
  2.1457 +	netif_start_queue (dev);
  2.1458 +}
  2.1459 +
  2.1460 +
  2.1461 +/* Initialize the Rx and Tx rings, along with various 'dev' bits. */
  2.1462 +static void rtl8139_init_ring (struct net_device *dev)
  2.1463 +{
  2.1464 +	struct rtl8139_private *tp = dev->priv;
  2.1465 +	int i;
  2.1466 +
  2.1467 +	tp->cur_rx = 0;
  2.1468 +	tp->cur_tx = 0;
  2.1469 +	tp->dirty_tx = 0;
  2.1470 +
  2.1471 +	for (i = 0; i < NUM_TX_DESC; i++)
  2.1472 +		tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
  2.1473 +}
  2.1474 +
  2.1475 +
  2.1476 +#ifndef CONFIG_8139TOO_TUNE_TWISTER
  2.1477 +static inline void rtl8139_tune_twister (struct net_device *dev,
  2.1478 +				  struct rtl8139_private *tp) {}
  2.1479 +#else
  2.1480 +static void rtl8139_tune_twister (struct net_device *dev,
  2.1481 +				  struct rtl8139_private *tp)
  2.1482 +{
  2.1483 +	int linkcase;
  2.1484 +	void *ioaddr = tp->mmio_addr;
  2.1485 +
  2.1486 +	/* This is a complicated state machine to configure the "twister" for
  2.1487 +	   impedance/echos based on the cable length.
  2.1488 +	   All of this is magic and undocumented.
  2.1489 +	 */
  2.1490 +	switch (tp->twistie) {
  2.1491 +	case 1:
  2.1492 +		if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
  2.1493 +			/* We have link beat, let us tune the twister. */
  2.1494 +			RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
  2.1495 +			tp->twistie = 2;	/* Change to state 2. */
  2.1496 +			next_tick = HZ / 10;
  2.1497 +		} else {
  2.1498 +			/* Just put in some reasonable defaults for when beat returns. */
  2.1499 +			RTL_W16 (CSCR, CSCR_LinkDownCmd);
  2.1500 +			RTL_W32 (FIFOTMS, 0x20);	/* Turn on cable test mode. */
  2.1501 +			RTL_W32 (PARA78, PARA78_default);
  2.1502 +			RTL_W32 (PARA7c, PARA7c_default);
  2.1503 +			tp->twistie = 0;	/* Bail from future actions. */
  2.1504 +		}
  2.1505 +		break;
  2.1506 +	case 2:
  2.1507 +		/* Read how long it took to hear the echo. */
  2.1508 +		linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
  2.1509 +		if (linkcase == 0x7000)
  2.1510 +			tp->twist_row = 3;
  2.1511 +		else if (linkcase == 0x3000)
  2.1512 +			tp->twist_row = 2;
  2.1513 +		else if (linkcase == 0x1000)
  2.1514 +			tp->twist_row = 1;
  2.1515 +		else
  2.1516 +			tp->twist_row = 0;
  2.1517 +		tp->twist_col = 0;
  2.1518 +		tp->twistie = 3;	/* Change to state 2. */
  2.1519 +		next_tick = HZ / 10;
  2.1520 +		break;
  2.1521 +	case 3:
  2.1522 +		/* Put out four tuning parameters, one per 100msec. */
  2.1523 +		if (tp->twist_col == 0)
  2.1524 +			RTL_W16 (FIFOTMS, 0);
  2.1525 +		RTL_W32 (PARA7c, param[(int) tp->twist_row]
  2.1526 +			 [(int) tp->twist_col]);
  2.1527 +		next_tick = HZ / 10;
  2.1528 +		if (++tp->twist_col >= 4) {
  2.1529 +			/* For short cables we are done.
  2.1530 +			   For long cables (row == 3) check for mistune. */
  2.1531 +			tp->twistie =
  2.1532 +			    (tp->twist_row == 3) ? 4 : 0;
  2.1533 +		}
  2.1534 +		break;
  2.1535 +	case 4:
  2.1536 +		/* Special case for long cables: check for mistune. */
  2.1537 +		if ((RTL_R16 (CSCR) &
  2.1538 +		     CSCR_LinkStatusBits) == 0x7000) {
  2.1539 +			tp->twistie = 0;
  2.1540 +			break;
  2.1541 +		} else {
  2.1542 +			RTL_W32 (PARA7c, 0xfb38de03);
  2.1543 +			tp->twistie = 5;
  2.1544 +			next_tick = HZ / 10;
  2.1545 +		}
  2.1546 +		break;
  2.1547 +	case 5:
  2.1548 +		/* Retune for shorter cable (column 2). */
  2.1549 +		RTL_W32 (FIFOTMS, 0x20);
  2.1550 +		RTL_W32 (PARA78, PARA78_default);
  2.1551 +		RTL_W32 (PARA7c, PARA7c_default);
  2.1552 +		RTL_W32 (FIFOTMS, 0x00);
  2.1553 +		tp->twist_row = 2;
  2.1554 +		tp->twist_col = 0;
  2.1555 +		tp->twistie = 3;
  2.1556 +		next_tick = HZ / 10;
  2.1557 +		break;
  2.1558 +
  2.1559 +	default:
  2.1560 +		/* do nothing */
  2.1561 +		break;
  2.1562 +	}
  2.1563 +}
  2.1564 +#endif /* CONFIG_8139TOO_TUNE_TWISTER */
  2.1565 +
  2.1566 +
  2.1567 +static inline void rtl8139_thread_iter (struct net_device *dev,
  2.1568 +				 struct rtl8139_private *tp,
  2.1569 +				 void *ioaddr)
  2.1570 +{
  2.1571 +	int mii_lpa;
  2.1572 +
  2.1573 +	mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
  2.1574 +
  2.1575 +	if (!tp->mii.force_media && mii_lpa != 0xffff) {
  2.1576 +		int duplex = (mii_lpa & LPA_100FULL)
  2.1577 +		    || (mii_lpa & 0x01C0) == 0x0040;
  2.1578 +		if (tp->mii.full_duplex != duplex) {
  2.1579 +			tp->mii.full_duplex = duplex;
  2.1580 +
  2.1581 +			if (mii_lpa) {
  2.1582 +				printk (KERN_INFO
  2.1583 +					"%s: Setting %s-duplex based on MII #%d link"
  2.1584 +					" partner ability of %4.4x.\n",
  2.1585 +					dev->name,
  2.1586 +					tp->mii.full_duplex ? "full" : "half",
  2.1587 +					tp->phys[0], mii_lpa);
  2.1588 +			} else {
  2.1589 +				printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
  2.1590 +				       dev->name);
  2.1591 +			}
  2.1592 +#if 0
  2.1593 +			RTL_W8 (Cfg9346, Cfg9346_Unlock);
  2.1594 +			RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
  2.1595 +			RTL_W8 (Cfg9346, Cfg9346_Lock);
  2.1596 +#endif
  2.1597 +		}
  2.1598 +	}
  2.1599 +
  2.1600 +	next_tick = HZ * 60;
  2.1601 +
  2.1602 +	rtl8139_tune_twister (dev, tp);
  2.1603 +
  2.1604 +	DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
  2.1605 +		 dev->name, RTL_R16 (NWayLPAR));
  2.1606 +	DPRINTK ("%s:  Other registers are IntMask %4.4x IntStatus %4.4x\n",
  2.1607 +		 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
  2.1608 +	DPRINTK ("%s:  Chip config %2.2x %2.2x.\n",
  2.1609 +		 dev->name, RTL_R8 (Config0),
  2.1610 +		 RTL_R8 (Config1));
  2.1611 +}
  2.1612 +
  2.1613 +
  2.1614 +#if 0
  2.1615 +static int rtl8139_thread (void *data)
  2.1616 +{
  2.1617 +	struct net_device *dev = data;
  2.1618 +	struct rtl8139_private *tp = dev->priv;
  2.1619 +	unsigned long timeout;
  2.1620 +
  2.1621 +	daemonize ();
  2.1622 +	reparent_to_init();
  2.1623 +	spin_lock_irq(&current->sigmask_lock);
  2.1624 +	sigemptyset(&current->blocked);
  2.1625 +	recalc_sigpending(current);
  2.1626 +	spin_unlock_irq(&current->sigmask_lock);
  2.1627 +
  2.1628 +	strncpy (current->comm, dev->name, sizeof(current->comm) - 1);
  2.1629 +	current->comm[sizeof(current->comm) - 1] = '\0';
  2.1630 +
  2.1631 +	while (1) {
  2.1632 +		timeout = next_tick;
  2.1633 +		do {
  2.1634 +			timeout = interruptible_sleep_on_timeout (&tp->thr_wait, timeout);
  2.1635 +		} while (!signal_pending (current) && (timeout > 0));
  2.1636 +
  2.1637 +		if (signal_pending (current)) {
  2.1638 +			spin_lock_irq(&current->sigmask_lock);
  2.1639 +			flush_signals(current);
  2.1640 +			spin_unlock_irq(&current->sigmask_lock);
  2.1641 +		}
  2.1642 +
  2.1643 +		if (tp->time_to_die)
  2.1644 +			break;
  2.1645 +
  2.1646 +		rtnl_lock ();
  2.1647 +		rtl8139_thread_iter (dev, tp, tp->mmio_addr);
  2.1648 +		rtnl_unlock ();
  2.1649 +	}
  2.1650 +
  2.1651 +	complete_and_exit (&tp->thr_exited, 0);
  2.1652 +}
  2.1653 +#else
  2.1654 +static void rtl8139_timer(unsigned long arg)
  2.1655 +{
  2.1656 +	struct net_device *dev = (struct net_device *)arg;
  2.1657 +	struct rtl8139_private *tp = dev->priv;
  2.1658 +	rtl8139_thread_iter (dev, tp, tp->mmio_addr);
  2.1659 +	mod_timer(&tp->timer, jiffies + next_tick);
  2.1660 +}
  2.1661 +#endif
  2.1662 +
  2.1663 +
  2.1664 +static void rtl8139_tx_clear (struct rtl8139_private *tp)
  2.1665 +{
  2.1666 +	tp->cur_tx = 0;
  2.1667 +	tp->dirty_tx = 0;
  2.1668 +
  2.1669 +	/* XXX account for unsent Tx packets in tp->stats.tx_dropped */
  2.1670 +}
  2.1671 +
  2.1672 +
  2.1673 +static void rtl8139_tx_timeout (struct net_device *dev)
  2.1674 +{
  2.1675 +	struct rtl8139_private *tp = dev->priv;
  2.1676 +	void *ioaddr = tp->mmio_addr;
  2.1677 +	int i;
  2.1678 +	u8 tmp8;
  2.1679 +	unsigned long flags;
  2.1680 +
  2.1681 +	DPRINTK ("%s: Transmit timeout, status %2.2x %4.4x "
  2.1682 +		 "media %2.2x.\n", dev->name,
  2.1683 +		 RTL_R8 (ChipCmd),
  2.1684 +		 RTL_R16 (IntrStatus),
  2.1685 +		 RTL_R8 (MediaStatus));
  2.1686 +
  2.1687 +	tp->xstats.tx_timeouts++;
  2.1688 +
  2.1689 +	/* disable Tx ASAP, if not already */
  2.1690 +	tmp8 = RTL_R8 (ChipCmd);
  2.1691 +	if (tmp8 & CmdTxEnb)
  2.1692 +		RTL_W8 (ChipCmd, CmdRxEnb);
  2.1693 +
  2.1694 +	/* Disable interrupts by clearing the interrupt mask. */
  2.1695 +	RTL_W16 (IntrMask, 0x0000);
  2.1696 +
  2.1697 +	/* Emit info to figure out what went wrong. */
  2.1698 +	printk (KERN_DEBUG "%s: Tx queue start entry %ld  dirty entry %ld.\n",
  2.1699 +		dev->name, tp->cur_tx, tp->dirty_tx);
  2.1700 +	for (i = 0; i < NUM_TX_DESC; i++)
  2.1701 +		printk (KERN_DEBUG "%s:  Tx descriptor %d is %8.8lx.%s\n",
  2.1702 +			dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
  2.1703 +			i == tp->dirty_tx % NUM_TX_DESC ?
  2.1704 +				" (queue head)" : "");
  2.1705 +
  2.1706 +	/* Stop a shared interrupt from scavenging while we are. */
  2.1707 +	spin_lock_irqsave (&tp->lock, flags);
  2.1708 +	rtl8139_tx_clear (tp);
  2.1709 +	spin_unlock_irqrestore (&tp->lock, flags);
  2.1710 +
  2.1711 +	/* ...and finally, reset everything */
  2.1712 +	rtl8139_hw_start (dev);
  2.1713 +
  2.1714 +	netif_wake_queue (dev);
  2.1715 +}
  2.1716 +
  2.1717 +
  2.1718 +static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
  2.1719 +{
  2.1720 +	struct rtl8139_private *tp = dev->priv;
  2.1721 +	void *ioaddr = tp->mmio_addr;
  2.1722 +	unsigned int entry;
  2.1723 +	unsigned int len = skb->len;
  2.1724 +
  2.1725 +	/* Calculate the next Tx descriptor entry. */
  2.1726 +	entry = tp->cur_tx % NUM_TX_DESC;
  2.1727 +
  2.1728 +	if (likely(len < TX_BUF_SIZE)) {
  2.1729 +		if(len < ETH_ZLEN)
  2.1730 +			memset(tp->tx_buf[entry], 0, ETH_ZLEN);
  2.1731 +#if 0
  2.1732 +		skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
  2.1733 +#else
  2.1734 +		skb_copy_bits(skb, 0, tp->tx_buf[entry], skb->len);
  2.1735 +#endif
  2.1736 +		dev_kfree_skb(skb);
  2.1737 +	} else {
  2.1738 +		dev_kfree_skb(skb);
  2.1739 +		tp->stats.tx_dropped++;
  2.1740 +		return 0;
  2.1741 +	}
  2.1742 +
  2.1743 +	/* Note: the chip doesn't have auto-pad! */
  2.1744 +	spin_lock_irq(&tp->lock);
  2.1745 +	RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
  2.1746 +		   tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
  2.1747 +
  2.1748 +	dev->trans_start = jiffies;
  2.1749 +
  2.1750 +	tp->cur_tx++;
  2.1751 +	wmb();
  2.1752 +
  2.1753 +	if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
  2.1754 +		netif_stop_queue (dev);
  2.1755 +	spin_unlock_irq(&tp->lock);
  2.1756 +
  2.1757 +	DPRINTK ("%s: Queued Tx packet size %u to slot %d.\n",
  2.1758 +		 dev->name, len, entry);
  2.1759 +
  2.1760 +	return 0;
  2.1761 +}
  2.1762 +
  2.1763 +
  2.1764 +static void rtl8139_tx_interrupt (struct net_device *dev,
  2.1765 +				  struct rtl8139_private *tp,
  2.1766 +				  void *ioaddr)
  2.1767 +{
  2.1768 +	unsigned long dirty_tx, tx_left;
  2.1769 +
  2.1770 +	assert (dev != NULL);
  2.1771 +	assert (tp != NULL);
  2.1772 +	assert (ioaddr != NULL);
  2.1773 +
  2.1774 +	dirty_tx = tp->dirty_tx;
  2.1775 +	tx_left = tp->cur_tx - dirty_tx;
  2.1776 +	while (tx_left > 0) {
  2.1777 +		int entry = dirty_tx % NUM_TX_DESC;
  2.1778 +		int txstatus;
  2.1779 +
  2.1780 +		txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
  2.1781 +
  2.1782 +		if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
  2.1783 +			break;	/* It still hasn't been Txed */
  2.1784 +
  2.1785 +		/* Note: TxCarrierLost is always asserted at 100mbps. */
  2.1786 +		if (txstatus & (TxOutOfWindow | TxAborted)) {
  2.1787 +			/* There was an major error, log it. */
  2.1788 +			DPRINTK ("%s: Transmit error, Tx status %8.8x.\n",
  2.1789 +				 dev->name, txstatus);
  2.1790 +			tp->stats.tx_errors++;
  2.1791 +			if (txstatus & TxAborted) {
  2.1792 +				tp->stats.tx_aborted_errors++;
  2.1793 +				RTL_W32 (TxConfig, TxClearAbt);
  2.1794 +				RTL_W16 (IntrStatus, TxErr);
  2.1795 +				wmb();
  2.1796 +			}
  2.1797 +			if (txstatus & TxCarrierLost)
  2.1798 +				tp->stats.tx_carrier_errors++;
  2.1799 +			if (txstatus & TxOutOfWindow)
  2.1800 +				tp->stats.tx_window_errors++;
  2.1801 +		} else {
  2.1802 +			if (txstatus & TxUnderrun) {
  2.1803 +				/* Add 64 to the Tx FIFO threshold. */
  2.1804 +				if (tp->tx_flag < 0x00300000)
  2.1805 +					tp->tx_flag += 0x00020000;
  2.1806 +				tp->stats.tx_fifo_errors++;
  2.1807 +			}
  2.1808 +			tp->stats.collisions += (txstatus >> 24) & 15;
  2.1809 +			tp->stats.tx_bytes += txstatus & 0x7ff;
  2.1810 +			tp->stats.tx_packets++;
  2.1811 +		}
  2.1812 +
  2.1813 +		dirty_tx++;
  2.1814 +		tx_left--;
  2.1815 +	}
  2.1816 +
  2.1817 +#ifndef RTL8139_NDEBUG
  2.1818 +	if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
  2.1819 +		printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
  2.1820 +		        dev->name, dirty_tx, tp->cur_tx);
  2.1821 +		dirty_tx += NUM_TX_DESC;
  2.1822 +	}
  2.1823 +#endif /* RTL8139_NDEBUG */
  2.1824 +
  2.1825 +	/* only wake the queue if we did work, and the queue is stopped */
  2.1826 +	if (tp->dirty_tx != dirty_tx) {
  2.1827 +		tp->dirty_tx = dirty_tx;
  2.1828 +		mb();
  2.1829 +		if (netif_queue_stopped (dev))
  2.1830 +			netif_wake_queue (dev);
  2.1831 +	}
  2.1832 +}
  2.1833 +
  2.1834 +
  2.1835 +/* TODO: clean this up!  Rx reset need not be this intensive */
  2.1836 +static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
  2.1837 +			    struct rtl8139_private *tp, void *ioaddr)
  2.1838 +{
  2.1839 +	u8 tmp8;
  2.1840 +#ifdef CONFIG_8139_OLD_RX_RESET
  2.1841 +	int tmp_work;
  2.1842 +#endif
  2.1843 +
  2.1844 +	DPRINTK ("%s: Ethernet frame had errors, status %8.8x.\n",
  2.1845 +	         dev->name, rx_status);
  2.1846 +	tp->stats.rx_errors++;
  2.1847 +	if (!(rx_status & RxStatusOK)) {
  2.1848 +		if (rx_status & RxTooLong) {
  2.1849 +			DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
  2.1850 +			 	dev->name, rx_status);
  2.1851 +			/* A.C.: The chip hangs here. */
  2.1852 +		}
  2.1853 +		if (rx_status & (RxBadSymbol | RxBadAlign))
  2.1854 +			tp->stats.rx_frame_errors++;
  2.1855 +		if (rx_status & (RxRunt | RxTooLong))
  2.1856 +			tp->stats.rx_length_errors++;
  2.1857 +		if (rx_status & RxCRCErr)
  2.1858 +			tp->stats.rx_crc_errors++;
  2.1859 +	} else {
  2.1860 +		tp->xstats.rx_lost_in_ring++;
  2.1861 +	}
  2.1862 +
  2.1863 +#ifndef CONFIG_8139_OLD_RX_RESET
  2.1864 +	tmp8 = RTL_R8 (ChipCmd);
  2.1865 +	RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
  2.1866 +	RTL_W8 (ChipCmd, tmp8);
  2.1867 +	RTL_W32 (RxConfig, tp->rx_config);
  2.1868 +	tp->cur_rx = 0;
  2.1869 +#else
  2.1870 +	/* Reset the receiver, based on RealTek recommendation. (Bug?) */
  2.1871 +
  2.1872 +	/* disable receive */
  2.1873 +	RTL_W8_F (ChipCmd, CmdTxEnb);
  2.1874 +	tmp_work = 200;
  2.1875 +	while (--tmp_work > 0) {
  2.1876 +		udelay(1);
  2.1877 +		tmp8 = RTL_R8 (ChipCmd);
  2.1878 +		if (!(tmp8 & CmdRxEnb))
  2.1879 +			break;
  2.1880 +	}
  2.1881 +	if (tmp_work <= 0)
  2.1882 +		printk (KERN_WARNING PFX "rx stop wait too long\n");
  2.1883 +	/* restart receive */
  2.1884 +	tmp_work = 200;
  2.1885 +	while (--tmp_work > 0) {
  2.1886 +		RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
  2.1887 +		udelay(1);
  2.1888 +		tmp8 = RTL_R8 (ChipCmd);
  2.1889 +		if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
  2.1890 +			break;
  2.1891 +	}
  2.1892 +	if (tmp_work <= 0)
  2.1893 +		printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
  2.1894 +
  2.1895 +	/* and reinitialize all rx related registers */
  2.1896 +	RTL_W8_F (Cfg9346, Cfg9346_Unlock);
  2.1897 +	/* Must enable Tx/Rx before setting transfer thresholds! */
  2.1898 +	RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
  2.1899 +
  2.1900 +	tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
  2.1901 +	RTL_W32 (RxConfig, tp->rx_config);
  2.1902 +	tp->cur_rx = 0;
  2.1903 +
  2.1904 +	DPRINTK("init buffer addresses\n");
  2.1905 +
  2.1906 +	/* Lock Config[01234] and BMCR register writes */
  2.1907 +	RTL_W8 (Cfg9346, Cfg9346_Lock);
  2.1908 +
  2.1909 +	/* init Rx ring buffer DMA address */
  2.1910 +	RTL_W32_F (RxBuf, tp->rx_ring_dma);
  2.1911 +
  2.1912 +	/* A.C.: Reset the multicast list. */
  2.1913 +	__set_rx_mode (dev);
  2.1914 +#endif
  2.1915 +}
  2.1916 +
  2.1917 +static void rtl8139_rx_interrupt (struct net_device *dev,
  2.1918 +				  struct rtl8139_private *tp, void *ioaddr)
  2.1919 +{
  2.1920 +	unsigned char *rx_ring;
  2.1921 +	u16 cur_rx;
  2.1922 +
  2.1923 +	assert (dev != NULL);
  2.1924 +	assert (tp != NULL);
  2.1925 +	assert (ioaddr != NULL);
  2.1926 +
  2.1927 +	rx_ring = tp->rx_ring;
  2.1928 +	cur_rx = tp->cur_rx;
  2.1929 +
  2.1930 +	DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
  2.1931 +		 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
  2.1932 +		 RTL_R16 (RxBufAddr),
  2.1933 +		 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
  2.1934 +
  2.1935 +	while ((RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
  2.1936 +		int ring_offset = cur_rx % RX_BUF_LEN;
  2.1937 +		u32 rx_status;
  2.1938 +		unsigned int rx_size;
  2.1939 +		unsigned int pkt_size;
  2.1940 +		struct sk_buff *skb;
  2.1941 +
  2.1942 +		rmb();
  2.1943 +
  2.1944 +		/* read size+status of next frame from DMA ring buffer */
  2.1945 +		rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
  2.1946 +		rx_size = rx_status >> 16;
  2.1947 +		pkt_size = rx_size - 4;
  2.1948 +
  2.1949 +		DPRINTK ("%s:  rtl8139_rx() status %4.4x, size %4.4x,"
  2.1950 +			 " cur %4.4x.\n", dev->name, rx_status,
  2.1951 +			 rx_size, cur_rx);
  2.1952 +#if RTL8139_DEBUG > 2
  2.1953 +		{
  2.1954 +			int i;
  2.1955 +			DPRINTK ("%s: Frame contents ", dev->name);
  2.1956 +			for (i = 0; i < 70; i++)
  2.1957 +				printk (" %2.2x",
  2.1958 +					rx_ring[ring_offset + i]);
  2.1959 +			printk (".\n");
  2.1960 +		}
  2.1961 +#endif
  2.1962 +
  2.1963 +		/* Packet copy from FIFO still in progress.
  2.1964 +		 * Theoretically, this should never happen
  2.1965 +		 * since EarlyRx is disabled.
  2.1966 +		 */
  2.1967 +		if (rx_size == 0xfff0) {
  2.1968 +			tp->xstats.early_rx++;
  2.1969 +			break;
  2.1970 +		}
  2.1971 +
  2.1972 +		/* If Rx err or invalid rx_size/rx_status received
  2.1973 +		 * (which happens if we get lost in the ring),
  2.1974 +		 * Rx process gets reset, so we abort any further
  2.1975 +		 * Rx processing.
  2.1976 +		 */
  2.1977 +		if ((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
  2.1978 +		    (rx_size < 8) ||
  2.1979 +		    (!(rx_status & RxStatusOK))) {
  2.1980 +			rtl8139_rx_err (rx_status, dev, tp, ioaddr);
  2.1981 +			return;
  2.1982 +		}
  2.1983 +
  2.1984 +		/* Malloc up new buffer, compatible with net-2e. */
  2.1985 +		/* Omit the four octet CRC from the length. */
  2.1986 +
  2.1987 +		/* TODO: consider allocating skb's outside of
  2.1988 +		 * interrupt context, both to speed interrupt processing,
  2.1989 +		 * and also to reduce the chances of having to
  2.1990 +		 * drop packets here under memory pressure.
  2.1991 +		 */
  2.1992 +
  2.1993 +		skb = dev_alloc_skb (pkt_size + 2);
  2.1994 +		if (skb) {
  2.1995 +			skb->dev = dev;
  2.1996 +			skb_reserve (skb, 2);	/* 16 byte align the IP fields. */
  2.1997 +
  2.1998 +			eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
  2.1999 +			skb_put (skb, pkt_size);
  2.2000 +
  2.2001 +			skb->protocol = eth_type_trans (skb, dev);
  2.2002 +			netif_rx (skb);
  2.2003 +			dev->last_rx = jiffies;
  2.2004 +			tp->stats.rx_bytes += pkt_size;
  2.2005 +			tp->stats.rx_packets++;
  2.2006 +		} else {
  2.2007 +			printk (KERN_WARNING
  2.2008 +				"%s: Memory squeeze, dropping packet.\n",
  2.2009 +				dev->name);
  2.2010 +			tp->stats.rx_dropped++;
  2.2011 +		}
  2.2012 +
  2.2013 +		cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
  2.2014 +		RTL_W16 (RxBufPtr, cur_rx - 16);
  2.2015 +
  2.2016 +		if (RTL_R16 (IntrStatus) & RxAckBits)
  2.2017 +			RTL_W16_F (IntrStatus, RxAckBits);
  2.2018 +	}
  2.2019 +
  2.2020 +	DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
  2.2021 +		 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
  2.2022 +		 RTL_R16 (RxBufAddr),
  2.2023 +		 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
  2.2024 +
  2.2025 +	tp->cur_rx = cur_rx;
  2.2026 +}
  2.2027 +
  2.2028 +
  2.2029 +static void rtl8139_weird_interrupt (struct net_device *dev,
  2.2030 +				     struct rtl8139_private *tp,
  2.2031 +				     void *ioaddr,
  2.2032 +				     int status, int link_changed)
  2.2033 +{
  2.2034 +	DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
  2.2035 +		 dev->name, status);
  2.2036 +
  2.2037 +	assert (dev != NULL);
  2.2038 +	assert (tp != NULL);
  2.2039 +	assert (ioaddr != NULL);
  2.2040 +
  2.2041 +	/* Update the error count. */
  2.2042 +	tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
  2.2043 +	RTL_W32 (RxMissed, 0);
  2.2044 +
  2.2045 +	if ((status & RxUnderrun) && link_changed &&
  2.2046 +	    (tp->drv_flags & HAS_LNK_CHNG)) {
  2.2047 +		/* Really link-change on new chips. */
  2.2048 +		int lpar = RTL_R16 (NWayLPAR);
  2.2049 +		int duplex = (lpar & LPA_100FULL) || (lpar & 0x01C0) == 0x0040
  2.2050 +				|| tp->mii.force_media;
  2.2051 +		if (tp->mii.full_duplex != duplex) {
  2.2052 +			tp->mii.full_duplex = duplex;
  2.2053 +#if 0
  2.2054 +			RTL_W8 (Cfg9346, Cfg9346_Unlock);
  2.2055 +			RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
  2.2056 +			RTL_W8 (Cfg9346, Cfg9346_Lock);
  2.2057 +#endif
  2.2058 +		}
  2.2059 +		status &= ~RxUnderrun;
  2.2060 +	}
  2.2061 +
  2.2062 +	/* XXX along with rtl8139_rx_err, are we double-counting errors? */
  2.2063 +	if (status &
  2.2064 +	    (RxUnderrun | RxOverflow | RxErr | RxFIFOOver))
  2.2065 +		tp->stats.rx_errors++;
  2.2066 +
  2.2067 +	if (status & PCSTimeout)
  2.2068 +		tp->stats.rx_length_errors++;
  2.2069 +	if (status & (RxUnderrun | RxFIFOOver))
  2.2070 +		tp->stats.rx_fifo_errors++;
  2.2071 +	if (status & PCIErr) {
  2.2072 +		u16 pci_cmd_status;
  2.2073 +		pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
  2.2074 +		pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
  2.2075 +
  2.2076 +		printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
  2.2077 +			dev->name, pci_cmd_status);
  2.2078 +	}
  2.2079 +}
  2.2080 +
  2.2081 +
  2.2082 +/* The interrupt handler does all of the Rx thread work and cleans up
  2.2083 +   after the Tx thread. */
  2.2084 +static void rtl8139_interrupt (int irq, void *dev_instance,
  2.2085 +			       struct pt_regs *regs)
  2.2086 +{
  2.2087 +	struct net_device *dev = (struct net_device *) dev_instance;
  2.2088 +	struct rtl8139_private *tp = dev->priv;
  2.2089 +	int boguscnt = max_interrupt_work;
  2.2090 +	void *ioaddr = tp->mmio_addr;
  2.2091 +	int ackstat, status;
  2.2092 +	int link_changed = 0; /* avoid bogus "uninit" warning */
  2.2093 +
  2.2094 +	spin_lock (&tp->lock);
  2.2095 +
  2.2096 +	do {
  2.2097 +		status = RTL_R16 (IntrStatus);
  2.2098 +
  2.2099 +		/* h/w no longer present (hotplug?) or major error, bail */
  2.2100 +		if (status == 0xFFFF)
  2.2101 +			break;
  2.2102 +
  2.2103 +		if ((status &
  2.2104 +		     (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
  2.2105 +		      RxFIFOOver | TxErr | TxOK | RxErr | RxOK)) == 0)
  2.2106 +			break;
  2.2107 +
  2.2108 +		/* Acknowledge all of the current interrupt sources ASAP, but
  2.2109 +		   an first get an additional status bit from CSCR. */
  2.2110 +		if (status & RxUnderrun)
  2.2111 +			link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
  2.2112 +
  2.2113 +		/* The chip takes special action when we clear RxAckBits,
  2.2114 +		 * so we clear them later in rtl8139_rx_interrupt
  2.2115 +		 */
  2.2116 +		ackstat = status & ~(RxAckBits | TxErr);
  2.2117 +		RTL_W16 (IntrStatus, ackstat);
  2.2118 +
  2.2119 +		DPRINTK ("%s: interrupt  status=%#4.4x ackstat=%#4.4x new intstat=%#4.4x.\n",
  2.2120 +			 dev->name, ackstat, status, RTL_R16 (IntrStatus));
  2.2121 +
  2.2122 +		if (netif_running (dev) && (status & RxAckBits))
  2.2123 +			rtl8139_rx_interrupt (dev, tp, ioaddr);
  2.2124 +
  2.2125 +		/* Check uncommon events with one test. */
  2.2126 +		if (status & (PCIErr | PCSTimeout | RxUnderrun | RxOverflow |
  2.2127 +		  	      RxFIFOOver | RxErr))
  2.2128 +			rtl8139_weird_interrupt (dev, tp, ioaddr,
  2.2129 +						 status, link_changed);
  2.2130 +
  2.2131 +		if (netif_running (dev) && (status & (TxOK | TxErr))) {
  2.2132 +			rtl8139_tx_interrupt (dev, tp, ioaddr);
  2.2133 +			if (status & TxErr)
  2.2134 +				RTL_W16 (IntrStatus, TxErr);
  2.2135 +		}
  2.2136 +
  2.2137 +		boguscnt--;
  2.2138 +	} while (boguscnt > 0);
  2.2139 +
  2.2140 +	if (boguscnt <= 0) {
  2.2141 +		printk (KERN_WARNING "%s: Too much work at interrupt, "
  2.2142 +			"IntrStatus=0x%4.4x.\n", dev->name, status);
  2.2143 +
  2.2144 +		/* Clear all interrupt sources. */
  2.2145 +		RTL_W16 (IntrStatus, 0xffff);
  2.2146 +	}
  2.2147 +
  2.2148 +	spin_unlock (&tp->lock);
  2.2149 +
  2.2150 +	DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
  2.2151 +		 dev->name, RTL_R16 (IntrStatus));
  2.2152 +}
  2.2153 +
  2.2154 +
  2.2155 +static int rtl8139_close (struct net_device *dev)
  2.2156 +{
  2.2157 +	struct rtl8139_private *tp = dev->priv;
  2.2158 +	void *ioaddr = tp->mmio_addr;
  2.2159 +#if 0
  2.2160 +	int ret = 0;
  2.2161 +#endif
  2.2162 +	unsigned long flags;
  2.2163 +
  2.2164 +	netif_stop_queue (dev);
  2.2165 +
  2.2166 +#if 0
  2.2167 +	if (tp->thr_pid >= 0) {
  2.2168 +		tp->time_to_die = 1;
  2.2169 +		wmb();
  2.2170 +		ret = kill_proc (tp->thr_pid, SIGTERM, 1);
  2.2171 +		if (ret) {
  2.2172 +			printk (KERN_ERR "%s: unable to signal thread\n", dev->name);
  2.2173 +			return ret;
  2.2174 +		}
  2.2175 +		wait_for_completion (&tp->thr_exited);
  2.2176 +	}
  2.2177 +#else
  2.2178 +	del_timer_sync(&tp->timer);
  2.2179 +#endif
  2.2180 +
  2.2181 +	DPRINTK ("%s: Shutting down ethercard, status was 0x%4.4x.\n",
  2.2182 +			dev->name, RTL_R16 (IntrStatus));
  2.2183 +
  2.2184 +	spin_lock_irqsave (&tp->lock, flags);
  2.2185 +
  2.2186 +	/* Stop the chip's Tx and Rx DMA processes. */
  2.2187 +	RTL_W8 (ChipCmd, 0);
  2.2188 +
  2.2189 +	/* Disable interrupts by clearing the interrupt mask. */
  2.2190 +	RTL_W16 (IntrMask, 0);
  2.2191 +
  2.2192 +	/* Update the error counts. */
  2.2193 +	tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
  2.2194 +	RTL_W32 (RxMissed, 0);
  2.2195 +
  2.2196 +	spin_unlock_irqrestore (&tp->lock, flags);
  2.2197 +
  2.2198 +	synchronize_irq ();
  2.2199 +	free_irq (dev->irq, dev);
  2.2200 +
  2.2201 +	rtl8139_tx_clear (tp);
  2.2202 +
  2.2203 +	pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
  2.2204 +			    tp->rx_ring, tp->rx_ring_dma);
  2.2205 +	pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
  2.2206 +			    tp->tx_bufs, tp->tx_bufs_dma);
  2.2207 +	tp->rx_ring = NULL;
  2.2208 +	tp->tx_bufs = NULL;
  2.2209 +
  2.2210 +	/* Green! Put the chip in low-power mode. */
  2.2211 +	RTL_W8 (Cfg9346, Cfg9346_Unlock);
  2.2212 +
  2.2213 +	if (rtl_chip_info[tp->chipset].flags & HasHltClk)
  2.2214 +		RTL_W8 (HltClk, 'H');	/* 'R' would leave the clock running. */
  2.2215 +
  2.2216 +	return 0;
  2.2217 +}
  2.2218 +
  2.2219 +
  2.2220 +/* Get the ethtool Wake-on-LAN settings.  Assumes that wol points to
  2.2221 +   kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
  2.2222 +   other threads or interrupts aren't messing with the 8139.  */
  2.2223 +static void netdev_get_wol (struct net_device *dev, struct ethtool_wolinfo *wol)
  2.2224 +{
  2.2225 +	struct rtl8139_private *np = dev->priv;
  2.2226 +	void *ioaddr = np->mmio_addr;
  2.2227 +
  2.2228 +	if (rtl_chip_info[np->chipset].flags & HasLWake) {
  2.2229 +		u8 cfg3 = RTL_R8 (Config3);
  2.2230 +		u8 cfg5 = RTL_R8 (Config5);
  2.2231 +
  2.2232 +		wol->supported = WAKE_PHY | WAKE_MAGIC
  2.2233 +			| WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
  2.2234 +
  2.2235 +		wol->wolopts = 0;
  2.2236 +		if (cfg3 & Cfg3_LinkUp)
  2.2237 +			wol->wolopts |= WAKE_PHY;
  2.2238 +		if (cfg3 & Cfg3_Magic)
  2.2239 +			wol->wolopts |= WAKE_MAGIC;
  2.2240 +		/* (KON)FIXME: See how netdev_set_wol() handles the
  2.2241 +		   following constants.  */
  2.2242 +		if (cfg5 & Cfg5_UWF)
  2.2243 +			wol->wolopts |= WAKE_UCAST;
  2.2244 +		if (cfg5 & Cfg5_MWF)
  2.2245 +			wol->wolopts |= WAKE_MCAST;
  2.2246 +		if (cfg5 & Cfg5_BWF)
  2.2247 +			wol->wolopts |= WAKE_BCAST;
  2.2248 +	}
  2.2249 +}
  2.2250 +
  2.2251 +
  2.2252 +/* Set the ethtool Wake-on-LAN settings.  Return 0 or -errno.  Assumes
  2.2253 +   that wol points to kernel memory and other threads or interrupts
  2.2254 +   aren't messing with the 8139.  */
  2.2255 +static int netdev_set_wol (struct net_device *dev,
  2.2256 +			   const struct ethtool_wolinfo *wol)
  2.2257 +{
  2.2258 +	struct rtl8139_private *np = dev->priv;
  2.2259 +	void *ioaddr = np->mmio_addr;
  2.2260 +	u32 support;
  2.2261 +	u8 cfg3, cfg5;
  2.2262 +
  2.2263 +	support = ((rtl_chip_info[np->chipset].flags & HasLWake)
  2.2264 +		   ? (WAKE_PHY | WAKE_MAGIC
  2.2265 +		      | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
  2.2266 +		   : 0);
  2.2267 +	if (wol->wolopts & ~support)
  2.2268 +		return -EINVAL;
  2.2269 +
  2.2270 +	cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
  2.2271 +	if (wol->wolopts & WAKE_PHY)
  2.2272 +		cfg3 |= Cfg3_LinkUp;
  2.2273 +	if (wol->wolopts & WAKE_MAGIC)
  2.2274 +		cfg3 |= Cfg3_Magic;
  2.2275 +	RTL_W8 (Cfg9346, Cfg9346_Unlock);
  2.2276 +	RTL_W8 (Config3, cfg3);
  2.2277 +	RTL_W8 (Cfg9346, Cfg9346_Lock);
  2.2278 +
  2.2279 +	cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
  2.2280 +	/* (KON)FIXME: These are untested.  We may have to set the
  2.2281 +	   CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
  2.2282 +	   documentation.  */
  2.2283 +	if (wol->wolopts & WAKE_UCAST)
  2.2284 +		cfg5 |= Cfg5_UWF;
  2.2285 +	if (wol->wolopts & WAKE_MCAST)
  2.2286 +		cfg5 |= Cfg5_MWF;
  2.2287 +	if (wol->wolopts & WAKE_BCAST)
  2.2288 +		cfg5 |= Cfg5_BWF;
  2.2289 +	RTL_W8 (Config5, cfg5);	/* need not unlock via Cfg9346 */
  2.2290 +
  2.2291 +	return 0;
  2.2292 +}
  2.2293 +
  2.2294 +#if 0
  2.2295 +static int netdev_ethtool_ioctl (struct net_device *dev, void *useraddr)
  2.2296 +{
  2.2297 +	struct rtl8139_private *np = dev->priv;
  2.2298 +	u32 ethcmd;
  2.2299 +
  2.2300 +	/* dev_ioctl() in ../../net/core/dev.c has already checked
  2.2301 +	   capable(CAP_NET_ADMIN), so don't bother with that here.  */
  2.2302 +
  2.2303 +	if (get_user(ethcmd, (u32 *)useraddr))
  2.2304 +		return -EFAULT;
  2.2305 +
  2.2306 +	switch (ethcmd) {
  2.2307 +
  2.2308 +	case ETHTOOL_GDRVINFO: {
  2.2309 +		struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
  2.2310 +		strcpy (info.driver, DRV_NAME);
  2.2311 +		strcpy (info.version, DRV_VERSION);
  2.2312 +		strcpy (info.bus_info, np->pci_dev->slot_name);
  2.2313 +		info.regdump_len = np->regs_len;
  2.2314 +		if (copy_to_user (useraddr, &info, sizeof (info)))
  2.2315 +			return -EFAULT;
  2.2316 +		return 0;
  2.2317 +	}
  2.2318 +
  2.2319 +	/* get settings */
  2.2320 +	case ETHTOOL_GSET: {
  2.2321 +		struct ethtool_cmd ecmd = { ETHTOOL_GSET };
  2.2322 +		spin_lock_irq(&np->lock);
  2.2323 +		mii_ethtool_gset(&np->mii, &ecmd);
  2.2324 +		spin_unlock_irq(&np->lock);
  2.2325 +		if (copy_to_user(useraddr, &ecmd, sizeof(ecmd)))
  2.2326 +			return -EFAULT;
  2.2327 +		return 0;
  2.2328 +	}
  2.2329 +	/* set settings */
  2.2330 +	case ETHTOOL_SSET: {
  2.2331 +		int r;
  2.2332 +		struct ethtool_cmd ecmd;
  2.2333 +		if (copy_from_user(&ecmd, useraddr, sizeof(ecmd)))
  2.2334 +			return -EFAULT;
  2.2335 +		spin_lock_irq(&np->lock);
  2.2336 +		r = mii_ethtool_sset(&np->mii, &ecmd);
  2.2337 +		spin_unlock_irq(&np->lock);
  2.2338 +		return r;
  2.2339 +	}
  2.2340 +	/* restart autonegotiation */
  2.2341 +	case ETHTOOL_NWAY_RST: {
  2.2342 +		return mii_nway_restart(&np->mii);
  2.2343 +	}
  2.2344 +	/* get link status */
  2.2345 +	case ETHTOOL_GLINK: {
  2.2346 +		struct ethtool_value edata = {ETHTOOL_GLINK};
  2.2347 +		edata.data = mii_link_ok(&np->mii);
  2.2348 +		if (copy_to_user(useraddr, &edata, sizeof(edata)))
  2.2349 +			return -EFAULT;
  2.2350 +		return 0;
  2.2351 +	}
  2.2352 +
  2.2353 +	/* get message-level */
  2.2354 +	case ETHTOOL_GMSGLVL: {
  2.2355 +		struct ethtool_value edata = {ETHTOOL_GMSGLVL};
  2.2356 +		edata.data = debug;
  2.2357 +		if (copy_to_user(useraddr, &edata, sizeof(edata)))
  2.2358 +			return -EFAULT;
  2.2359 +		return 0;
  2.2360 +	}
  2.2361 +	/* set message-level */
  2.2362 +	case ETHTOOL_SMSGLVL: {
  2.2363 +		struct ethtool_value edata;
  2.2364 +		if (copy_from_user(&edata, useraddr, sizeof(edata)))
  2.2365 +			return -EFAULT;
  2.2366 +		debug = edata.data;
  2.2367 +		return 0;
  2.2368 +	}
  2.2369 +
  2.2370 +	case ETHTOOL_GWOL:
  2.2371 +		{
  2.2372 +			struct ethtool_wolinfo wol = { ETHTOOL_GWOL };
  2.2373 +			spin_lock_irq (&np->lock);
  2.2374 +			netdev_get_wol (dev, &wol);
  2.2375 +			spin_unlock_irq (&np->lock);
  2.2376 +			if (copy_to_user (useraddr, &wol, sizeof (wol)))
  2.2377 +				return -EFAULT;
  2.2378 +			return 0;
  2.2379 +		}
  2.2380 +
  2.2381 +	case ETHTOOL_SWOL:
  2.2382 +		{
  2.2383 +			struct ethtool_wolinfo wol;
  2.2384 +			int rc;
  2.2385 +			if (copy_from_user (&wol, useraddr, sizeof (wol)))
  2.2386 +				return -EFAULT;
  2.2387 +			spin_lock_irq (&np->lock);
  2.2388 +			rc = netdev_set_wol (dev, &wol);
  2.2389 +			spin_unlock_irq (&np->lock);
  2.2390 +			return rc;
  2.2391 +		}
  2.2392 +
  2.2393 +/* TODO: we are too slack to do reg dumping for pio, for now */
  2.2394 +#ifndef CONFIG_8139TOO_PIO
  2.2395 +	/* NIC register dump */
  2.2396 +	case ETHTOOL_GREGS: {
  2.2397 +                struct ethtool_regs regs;
  2.2398 +		unsigned int regs_len = np->regs_len;
  2.2399 +                u8 *regbuf = kmalloc(regs_len, GFP_KERNEL);
  2.2400 +                int rc;
  2.2401 +
  2.2402 +		if (!regbuf)
  2.2403 +			return -ENOMEM;
  2.2404 +		memset(regbuf, 0, regs_len);
  2.2405 +
  2.2406 +                rc = copy_from_user(&regs, useraddr, sizeof(regs));
  2.2407 +		if (rc) {
  2.2408 +			rc = -EFAULT;
  2.2409 +			goto err_out_gregs;
  2.2410 +		}
  2.2411 +                
  2.2412 +                if (regs.len > regs_len)
  2.2413 +                        regs.len = regs_len;
  2.2414 +                if (regs.len < regs_len) {
  2.2415 +			rc = -EINVAL;
  2.2416 +			goto err_out_gregs;
  2.2417 +		}
  2.2418 +
  2.2419 +                regs.version = RTL_REGS_VER;
  2.2420 +                rc = copy_to_user(useraddr, &regs, sizeof(regs));
  2.2421 +		if (rc) {
  2.2422 +			rc = -EFAULT;
  2.2423 +			goto err_out_gregs;
  2.2424 +		}
  2.2425 +
  2.2426 +                useraddr += offsetof(struct ethtool_regs, data);
  2.2427 +
  2.2428 +                spin_lock_irq(&np->lock);
  2.2429 +                memcpy_fromio(regbuf, np->mmio_addr, regs_len);
  2.2430 +                spin_unlock_irq(&np->lock);
  2.2431 +
  2.2432 +                if (copy_to_user(useraddr, regbuf, regs_len))
  2.2433 +                        rc = -EFAULT;
  2.2434 +
  2.2435 +err_out_gregs:
  2.2436 +		kfree(regbuf);
  2.2437 +		return rc;
  2.2438 +	}
  2.2439 +#endif /* CONFIG_8139TOO_PIO */
  2.2440 +
  2.2441 +	/* get string list(s) */
  2.2442 +	case ETHTOOL_GSTRINGS: {
  2.2443 +		struct ethtool_gstrings estr = { ETHTOOL_GSTRINGS };
  2.2444 +
  2.2445 +		if (copy_from_user(&estr, useraddr, sizeof(estr)))
  2.2446 +			return -EFAULT;
  2.2447 +		if (estr.string_set != ETH_SS_STATS)
  2.2448 +			return -EINVAL;
  2.2449 +
  2.2450 +		estr.len = RTL_NUM_STATS;
  2.2451 +		if (copy_to_user(useraddr, &estr, sizeof(estr)))
  2.2452 +			return -EFAULT;
  2.2453 +		if (copy_to_user(useraddr + sizeof(estr),
  2.2454 +				 &ethtool_stats_keys,
  2.2455 +				 sizeof(ethtool_stats_keys)))
  2.2456 +			return -EFAULT;
  2.2457 +		return 0;
  2.2458 +	}
  2.2459 +
  2.2460 +	/* get NIC-specific statistics */
  2.2461 +	case ETHTOOL_GSTATS: {
  2.2462 +		struct ethtool_stats estats = { ETHTOOL_GSTATS };
  2.2463 +		u64 *tmp_stats;
  2.2464 +		const unsigned int sz = sizeof(u64) * RTL_NUM_STATS;
  2.2465 +		int i;
  2.2466 +
  2.2467 +		estats.n_stats = RTL_NUM_STATS;
  2.2468 +		if (copy_to_user(useraddr, &estats, sizeof(estats)))
  2.2469 +			return -EFAULT;
  2.2470 +
  2.2471 +		tmp_stats = kmalloc(sz, GFP_KERNEL);
  2.2472 +		if (!tmp_stats)
  2.2473 +			return -ENOMEM;
  2.2474 +		memset(tmp_stats, 0, sz);
  2.2475 +
  2.2476 +		i = 0;
  2.2477 +		tmp_stats[i++] = np->xstats.early_rx;
  2.2478 +		tmp_stats[i++] = np->xstats.tx_buf_mapped;
  2.2479 +		tmp_stats[i++] = np->xstats.tx_timeouts;
  2.2480 +		tmp_stats[i++] = np->xstats.rx_lost_in_ring;
  2.2481 +		if (i != RTL_NUM_STATS)
  2.2482 +			BUG();
  2.2483 +
  2.2484 +		i = copy_to_user(useraddr + sizeof(estats), tmp_stats, sz);
  2.2485 +		kfree(tmp_stats);
  2.2486 +
  2.2487 +		if (i)
  2.2488 +			return -EFAULT;
  2.2489 +		return 0;
  2.2490 +	}
  2.2491 +	default:
  2.2492 +		break;
  2.2493 +	}
  2.2494 +
  2.2495 +	return -EOPNOTSUPP;
  2.2496 +}
  2.2497 +
  2.2498 +
  2.2499 +static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
  2.2500 +{
  2.2501 +	struct rtl8139_private *np = dev->priv;
  2.2502 +	struct mii_ioctl_data *data = (struct mii_ioctl_data *) & rq->ifr_data;
  2.2503 +	int rc;
  2.2504 +
  2.2505 +	if (!netif_running(dev))
  2.2506 +		return -EINVAL;
  2.2507 +
  2.2508 +	if (cmd == SIOCETHTOOL)
  2.2509 +		rc = netdev_ethtool_ioctl(dev, (void *) rq->ifr_data);
  2.2510 +
  2.2511 +	else {
  2.2512 +		spin_lock_irq(&np->lock);
  2.2513 +		rc = generic_mii_ioctl(&np->mii, data, cmd, NULL);
  2.2514 +		spin_unlock_irq(&np->lock);
  2.2515 +	}
  2.2516 +
  2.2517 +	return rc;
  2.2518 +}
  2.2519 +#endif
  2.2520 +
  2.2521 +
  2.2522 +static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
  2.2523 +{
  2.2524 +	struct rtl8139_private *tp = dev->priv;
  2.2525 +	void *ioaddr = tp->mmio_addr;
  2.2526 +	unsigned long flags;
  2.2527 +
  2.2528 +	if (netif_running(dev)) {
  2.2529 +		spin_lock_irqsave (&tp->lock, flags);
  2.2530 +		tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
  2.2531 +		RTL_W32 (RxMissed, 0);
  2.2532 +		spin_unlock_irqrestore (&tp->lock, flags);
  2.2533 +	}
  2.2534 +
  2.2535 +	return &tp->stats;
  2.2536 +}
  2.2537 +
  2.2538 +/* Set or clear the multicast filter for this adaptor.
  2.2539 +   This routine is not state sensitive and need not be SMP locked. */
  2.2540 +
  2.2541 +static void __set_rx_mode (struct net_device *dev)
  2.2542 +{
  2.2543 +	struct rtl8139_private *tp = dev->priv;
  2.2544 +	void *ioaddr = tp->mmio_addr;
  2.2545 +	u32 mc_filter[2];	/* Multicast hash filter */
  2.2546 +	int i, rx_mode;
  2.2547 +	u32 tmp;
  2.2548 +
  2.2549 +	DPRINTK ("%s:   rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
  2.2550 +			dev->name, dev->flags, RTL_R32 (RxConfig));
  2.2551 +
  2.2552 +	/* Note: do not reorder, GCC is clever about common statements. */
  2.2553 +	if (dev->flags & IFF_PROMISC) {
  2.2554 +		/* Unconditionally log net taps. */
  2.2555 +		printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
  2.2556 +			dev->name);
  2.2557 +		rx_mode =
  2.2558 +		    AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
  2.2559 +		    AcceptAllPhys;
  2.2560 +		mc_filter[1] = mc_filter[0] = 0xffffffff;
  2.2561 +	} else if ((dev->mc_count > multicast_filter_limit)
  2.2562 +		   || (dev->flags & IFF_ALLMULTI)) {
  2.2563 +		/* Too many to filter perfectly -- accept all multicasts. */
  2.2564 +		rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
  2.2565 +		mc_filter[1] = mc_filter[0] = 0xffffffff;
  2.2566 +	} else {
  2.2567 +		struct dev_mc_list *mclist;
  2.2568 +		rx_mode = AcceptBroadcast | AcceptMyPhys;
  2.2569 +		mc_filter[1] = mc_filter[0] = 0;
  2.2570 +		for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
  2.2571 +		     i++, mclist = mclist->next) {
  2.2572 +			int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
  2.2573 +
  2.2574 +			mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
  2.2575 +			rx_mode |= AcceptMulticast;
  2.2576 +		}
  2.2577 +	}
  2.2578 +
  2.2579 +	/* We can safely update without stopping the chip. */
  2.2580 +	tmp = rtl8139_rx_config | rx_mode;
  2.2581 +	if (tp->rx_config != tmp) {
  2.2582 +		RTL_W32_F (RxConfig, tmp);
  2.2583 +		tp->rx_config = tmp;
  2.2584 +	}
  2.2585 +	RTL_W32_F (MAR0 + 0, mc_filter[0]);
  2.2586 +	RTL_W32_F (MAR0 + 4, mc_filter[1]);
  2.2587 +}
  2.2588 +
  2.2589 +static void rtl8139_set_rx_mode (struct net_device *dev)
  2.2590 +{
  2.2591 +	unsigned long flags;
  2.2592 +	struct rtl8139_private *tp = dev->priv;
  2.2593 +
  2.2594 +	spin_lock_irqsave (&tp->lock, flags);
  2.2595 +	__set_rx_mode(dev);
  2.2596 +	spin_unlock_irqrestore (&tp->lock, flags);
  2.2597 +}
  2.2598 +
  2.2599 +#ifdef CONFIG_PM
  2.2600 +
  2.2601 +static int rtl8139_suspend (struct pci_dev *pdev, u32 state)
  2.2602 +{
  2.2603 +	struct net_device *dev = pci_get_drvdata (pdev);
  2.2604 +	struct rtl8139_private *tp = dev->priv;
  2.2605 +	void *ioaddr = tp->mmio_addr;
  2.2606 +	unsigned long flags;
  2.2607 +
  2.2608 +	if (!netif_running (dev))
  2.2609 +		return 0;
  2.2610 +
  2.2611 +	netif_device_detach (dev);
  2.2612 +
  2.2613 +	spin_lock_irqsave (&tp->lock, flags);
  2.2614 +
  2.2615 +	/* Disable interrupts, stop Tx and Rx. */
  2.2616 +	RTL_W16 (IntrMask, 0);
  2.2617 +	RTL_W8 (ChipCmd, 0);
  2.2618 +
  2.2619 +	/* Update the error counts. */
  2.2620 +	tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
  2.2621 +	RTL_W32 (RxMissed, 0);
  2.2622 +
  2.2623 +	spin_unlock_irqrestore (&tp->lock, flags);
  2.2624 +	return 0;
  2.2625 +}
  2.2626 +
  2.2627 +
  2.2628 +static int rtl8139_resume (struct pci_dev *pdev)
  2.2629 +{
  2.2630 +	struct net_device *dev = pci_get_drvdata (pdev);
  2.2631 +
  2.2632 +	if (!netif_running (dev))
  2.2633 +		return 0;
  2.2634 +	netif_device_attach (dev);
  2.2635 +	rtl8139_hw_start (dev);
  2.2636 +	return 0;
  2.2637 +}
  2.2638 +
  2.2639 +#endif /* CONFIG_PM */
  2.2640 +
  2.2641 +
  2.2642 +static struct pci_driver rtl8139_pci_driver = {
  2.2643 +	.name		= DRV_NAME,
  2.2644 +	.id_table	= rtl8139_pci_tbl,
  2.2645 +	.probe		= rtl8139_init_one,
  2.2646 +	.remove		= __devexit_p(rtl8139_remove_one),
  2.2647 +#ifdef CONFIG_PM
  2.2648 +	.suspend	= rtl8139_suspend,
  2.2649 +	.resume		= rtl8139_resume,
  2.2650 +#endif /* CONFIG_PM */
  2.2651 +};
  2.2652 +
  2.2653 +
  2.2654 +static int __init rtl8139_init_module (void)
  2.2655 +{
  2.2656 +	/* when we're a module, we always print a version message,
  2.2657 +	 * even if no 8139 board is found.
  2.2658 +	 */
  2.2659 +#ifdef MODULE
  2.2660 +	printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
  2.2661 +#endif
  2.2662 +
  2.2663 +	return pci_module_init (&rtl8139_pci_driver);
  2.2664 +}
  2.2665 +
  2.2666 +
  2.2667 +static void __exit rtl8139_cleanup_module (void)
  2.2668 +{
  2.2669 +	pci_unregister_driver (&rtl8139_pci_driver);
  2.2670 +}
  2.2671 +
  2.2672 +
  2.2673 +module_init(rtl8139_init_module);
  2.2674 +module_exit(rtl8139_cleanup_module);
     3.1 --- a/xen/drivers/net/Makefile	Thu Jul 10 08:45:03 2003 +0000
     3.2 +++ b/xen/drivers/net/Makefile	Thu Jul 10 08:57:37 2003 +0000
     3.3 @@ -2,12 +2,14 @@
     3.4  include $(BASEDIR)/Rules.mk
     3.5  
     3.6  default: $(OBJS)
     3.7 -	$(MAKE) -C ne
     3.8 +	$(MAKE) -C tulip
     3.9 +	$(MAKE) -C e100
    3.10  	$(MAKE) -C e1000
    3.11 -	$(LD) -r -o driver.o e1000/e1000.o $(OBJS) ne/ne_drv.o
    3.12 +	$(LD) -r -o driver.o e100/e100.o e1000/e1000.o $(OBJS) tulip/tulip.o
    3.13  
    3.14  clean:
    3.15 -	$(MAKE) -C ne clean
    3.16 +	$(MAKE) -C tulip clean
    3.17 +	$(MAKE) -C e100 clean
    3.18  	$(MAKE) -C e1000 clean
    3.19  	rm -f *.o *~ core
    3.20  
     4.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     4.2 +++ b/xen/drivers/net/SUPPORTED_CARDS	Thu Jul 10 08:57:37 2003 +0000
     4.3 @@ -0,0 +1,14 @@
     4.4 +
     4.5 +Recommended (cards tested and working at full efficiency):
     4.6 + 3com 3c905   (3c59x.c Linux driver)
     4.7 + Broadcom tg3 (tg3.c Linux driver)
     4.8 + Intel e1000  (e1000 Linux driver)
     4.9 + Intel e100   (e100 Linux driver) [*]
    4.10 +
    4.11 +Driver ported, but may not be tested, and won't work at full 
    4.12 +efficiency (extra copies are incurred within Xen):
    4.13 + ne2k, pcnet32/lance, rtl8139, tulip, via-rhine, 
    4.14 +
    4.15 +*: Note that certain revisions of e100 do not support
    4.16 +   scatter/gather DMA. These cards will incur an extra 
    4.17 +   copy within Xen for every transmitted packet.
    4.18 \ No newline at end of file
     5.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     5.2 +++ b/xen/drivers/net/e100/LICENSE	Thu Jul 10 08:57:37 2003 +0000
     5.3 @@ -0,0 +1,339 @@
     5.4 +
     5.5 +"This software program is licensed subject to the GNU General Public License 
     5.6 +(GPL). Version 2, June 1991, available at 
     5.7 +<http://www.fsf.org/copyleft/gpl.html>"
     5.8 +
     5.9 +GNU General Public License 
    5.10 +
    5.11 +Version 2, June 1991
    5.12 +
    5.13 +Copyright (C) 1989, 1991 Free Software Foundation, Inc.  
    5.14 +59 Temple Place - Suite 330, Boston, MA  02111-1307, USA
    5.15 +
    5.16 +Everyone is permitted to copy and distribute verbatim copies of this license
    5.17 +document, but changing it is not allowed.
    5.18 +
    5.19 +Preamble
    5.20 +
    5.21 +The licenses for most software are designed to take away your freedom to 
    5.22 +share and change it. By contrast, the GNU General Public License is intended
    5.23 +to guarantee your freedom to share and change free software--to make sure 
    5.24 +the software is free for all its users. This General Public License applies 
    5.25 +to most of the Free Software Foundation's software and to any other program 
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   5.278 +    (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED 
   5.279 +    INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF 
   5.280 +    THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR 
   5.281 +    OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 
   5.282 +
   5.283 +END OF TERMS AND CONDITIONS
   5.284 +
   5.285 +How to Apply These Terms to Your New Programs
   5.286 +
   5.287 +If you develop a new program, and you want it to be of the greatest 
   5.288 +possible use to the public, the best way to achieve this is to make it free 
   5.289 +software which everyone can redistribute and change under these terms. 
   5.290 +
   5.291 +To do so, attach the following notices to the program. It is safest to 
   5.292 +attach them to the start of each source file to most effectively convey the
   5.293 +exclusion of warranty; and each file should have at least the "copyright" 
   5.294 +line and a pointer to where the full notice is found. 
   5.295 +
   5.296 +one line to give the program's name and an idea of what it does.
   5.297 +Copyright (C) yyyy  name of author
   5.298 +
   5.299 +This program is free software; you can redistribute it and/or modify it 
   5.300 +under the terms of the GNU General Public License as published by the Free 
   5.301 +Software Foundation; either version 2 of the License, or (at your option) 
   5.302 +any later version.
   5.303 +
   5.304 +This program is distributed in the hope that it will be useful, but WITHOUT 
   5.305 +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
   5.306 +FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
   5.307 +more details.
   5.308 +
   5.309 +You should have received a copy of the GNU General Public License along with
   5.310 +this program; if not, write to the Free Software Foundation, Inc., 59 
   5.311 +Temple Place - Suite 330, Boston, MA  02111-1307, USA.
   5.312 +
   5.313 +Also add information on how to contact you by electronic and paper mail. 
   5.314 +
   5.315 +If the program is interactive, make it output a short notice like this when 
   5.316 +it starts in an interactive mode: 
   5.317 +
   5.318 +Gnomovision version 69, Copyright (C) year name of author Gnomovision comes 
   5.319 +with ABSOLUTELY NO WARRANTY; for details type 'show w'.  This is free 
   5.320 +software, and you are welcome to redistribute it under certain conditions; 
   5.321 +type 'show c' for details.
   5.322 +
   5.323 +The hypothetical commands 'show w' and 'show c' should show the appropriate 
   5.324 +parts of the General Public License. Of course, the commands you use may be 
   5.325 +called something other than 'show w' and 'show c'; they could even be 
   5.326 +mouse-clicks or menu items--whatever suits your program. 
   5.327 +
   5.328 +You should also get your employer (if you work as a programmer) or your 
   5.329 +school, if any, to sign a "copyright disclaimer" for the program, if 
   5.330 +necessary. Here is a sample; alter the names: 
   5.331 +
   5.332 +Yoyodyne, Inc., hereby disclaims all copyright interest in the program 
   5.333 +'Gnomovision' (which makes passes at compilers) written by James Hacker.
   5.334 +
   5.335 +signature of Ty Coon, 1 April 1989
   5.336 +Ty Coon, President of Vice
   5.337 +
   5.338 +This General Public License does not permit incorporating your program into 
   5.339 +proprietary programs. If your program is a subroutine library, you may 
   5.340 +consider it more useful to permit linking proprietary applications with the 
   5.341 +library. If this is what you want to do, use the GNU Library General Public 
   5.342 +License instead of this License.
     6.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     6.2 +++ b/xen/drivers/net/e100/Makefile	Thu Jul 10 08:57:37 2003 +0000
     6.3 @@ -0,0 +1,8 @@
     6.4 +
     6.5 +include $(BASEDIR)/Rules.mk
     6.6 +
     6.7 +default: $(OBJS)
     6.8 +	$(LD) -r -o e100.o $(OBJS)
     6.9 +
    6.10 +clean:
    6.11 +	rm -f *.o *~ core
     7.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     7.2 +++ b/xen/drivers/net/e100/e100.h	Thu Jul 10 08:57:37 2003 +0000
     7.3 @@ -0,0 +1,996 @@
     7.4 +/*******************************************************************************
     7.5 +
     7.6 +  
     7.7 +  Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
     7.8 +  
     7.9 +  This program is free software; you can redistribute it and/or modify it 
    7.10 +  under the terms of the GNU General Public License as published by the Free 
    7.11 +  Software Foundation; either version 2 of the License, or (at your option) 
    7.12 +  any later version.
    7.13 +  
    7.14 +  This program is distributed in the hope that it will be useful, but WITHOUT 
    7.15 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
    7.16 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
    7.17 +  more details.
    7.18 +  
    7.19 +  You should have received a copy of the GNU General Public License along with
    7.20 +  this program; if not, write to the Free Software Foundation, Inc., 59 
    7.21 +  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
    7.22 +  
    7.23 +  The full GNU General Public License is included in this distribution in the
    7.24 +  file called LICENSE.
    7.25 +  
    7.26 +  Contact Information:
    7.27 +  Linux NICS <linux.nics@intel.com>
    7.28 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
    7.29 +*******************************************************************************/
    7.30 +
    7.31 +#ifndef _E100_INC_
    7.32 +#define _E100_INC_
    7.33 +
    7.34 +#include <linux/module.h>
    7.35 +#include <linux/types.h>
    7.36 +#include <linux/init.h>
    7.37 +#include <linux/mm.h>
    7.38 +#include <linux/errno.h>
    7.39 +#include <linux/ioport.h>
    7.40 +#include <linux/pci.h>
    7.41 +#include <linux/kernel.h>
    7.42 +#include <linux/netdevice.h>
    7.43 +#include <linux/etherdevice.h>
    7.44 +#include <linux/skbuff.h>
    7.45 +#include <linux/delay.h>
    7.46 +#include <linux/timer.h>
    7.47 +#include <linux/slab.h>
    7.48 +#include <linux/interrupt.h>
    7.49 +#include <linux/version.h>
    7.50 +#include <linux/string.h>
    7.51 +/*#include <linux/wait.h>*/
    7.52 +#include <linux/reboot.h>
    7.53 +#include <asm/io.h>
    7.54 +#include <asm/unaligned.h>
    7.55 +#include <asm/processor.h>
    7.56 +#include <linux/ethtool.h>
    7.57 +/*#include <linux/inetdevice.h>*/
    7.58 +#include <asm/bitops.h>
    7.59 +
    7.60 +#include <linux/if.h>
    7.61 +#include <asm/uaccess.h>
    7.62 +/*#include <linux/ip.h>*/
    7.63 +#include <linux/if_vlan.h>
    7.64 +#include <linux/mii.h>
    7.65 +
    7.66 +#define yield() ((void)0)
    7.67 +
    7.68 +#define E100_REGS_LEN 1
    7.69 +/*
    7.70 + *  Configure parameters for buffers per controller.
    7.71 + *  If the machine this is being used on is a faster machine (i.e. > 150MHz)
    7.72 + *  and running on a 10MBS network then more queueing of data occurs. This
    7.73 + *  may indicate the some of the numbers below should be adjusted.  Here are
    7.74 + *  some typical numbers:
    7.75 + *                             MAX_TCB 64
    7.76 + *                             MAX_RFD 64
    7.77 + *  The default numbers give work well on most systems tests so no real
    7.78 + *  adjustments really need to take place.  Also, if the machine is connected
    7.79 + *  to a 100MBS network the numbers described above can be lowered from the
    7.80 + *  defaults as considerably less data will be queued.
    7.81 + */
    7.82 +
    7.83 +#define TX_FRAME_CNT   8	/* consecutive transmit frames per interrupt */
    7.84 +/* TX_FRAME_CNT must be less than MAX_TCB    */
    7.85 +
    7.86 +#define E100_DEFAULT_TCB   64
    7.87 +#define E100_MIN_TCB       2*TX_FRAME_CNT + 3	/* make room for at least 2 interrupts */
    7.88 +#define E100_MAX_TCB       1024
    7.89 +
    7.90 +#define E100_DEFAULT_RFD   64
    7.91 +#define E100_MIN_RFD       8
    7.92 +#define E100_MAX_RFD       1024
    7.93 +
    7.94 +#define E100_DEFAULT_XSUM         true
    7.95 +#define E100_DEFAULT_BER          ZLOCK_MAX_ERRORS
    7.96 +#define E100_DEFAULT_SPEED_DUPLEX 0
    7.97 +#define E100_DEFAULT_FC           0
    7.98 +#define E100_DEFAULT_IFS          true
    7.99 +#define E100_DEFAULT_UCODE        true
   7.100 +
   7.101 +#define TX_THRSHLD     8
   7.102 +
   7.103 +/* IFS parameters */
   7.104 +#define MIN_NUMBER_OF_TRANSMITS_100 1000
   7.105 +#define MIN_NUMBER_OF_TRANSMITS_10  100
   7.106 +
   7.107 +#define E100_MAX_NIC 16
   7.108 +
   7.109 +#define E100_MAX_SCB_WAIT	100	/* Max udelays in wait_scb */
   7.110 +#define E100_MAX_CU_IDLE_WAIT	50	/* Max udelays in wait_cus_idle */
   7.111 +
   7.112 +/* HWI feature related constant */
   7.113 +#define HWI_MAX_LOOP                    100
   7.114 +#define MAX_SAME_RESULTS		3
   7.115 +#define HWI_REGISTER_GRANULARITY        80	/* register granularity = 80 Cm */
   7.116 +#define HWI_NEAR_END_BOUNDARY           1000	/* Near end is defined as < 10 meters */
   7.117 +
   7.118 +/* CPUSAVER_BUNDLE_MAX: Sets the maximum number of frames that will be bundled.
   7.119 + * In some situations, such as the TCP windowing algorithm, it may be
   7.120 + * better to limit the growth of the bundle size than let it go as
   7.121 + * high as it can, because that could cause too much added latency.
   7.122 + * The default is six, because this is the number of packets in the
   7.123 + * default TCP window size.  A value of 1 would make CPUSaver indicate
   7.124 + * an interrupt for every frame received.  If you do not want to put
   7.125 + * a limit on the bundle size, set this value to xFFFF.
   7.126 + */
   7.127 +#define E100_DEFAULT_CPUSAVER_BUNDLE_MAX	6
   7.128 +#define E100_DEFAULT_CPUSAVER_INTERRUPT_DELAY	0x600
   7.129 +#define E100_DEFAULT_BUNDLE_SMALL_FR		false
   7.130 +
   7.131 +/* end of configurables */
   7.132 +
   7.133 +/* ====================================================================== */
   7.134 +/*                                hw                                      */
   7.135 +/* ====================================================================== */
   7.136 +
   7.137 +/* timeout for command completion */
   7.138 +#define E100_CMD_WAIT   100	/* iterations */
   7.139 +
   7.140 +struct driver_stats {
   7.141 +	struct net_device_stats net_stats;
   7.142 +
   7.143 +	unsigned long tx_late_col;
   7.144 +	unsigned long tx_ok_defrd;
   7.145 +	unsigned long tx_one_retry;
   7.146 +	unsigned long tx_mt_one_retry;
   7.147 +	unsigned long rcv_cdt_frames;
   7.148 +	unsigned long xmt_fc_pkts;
   7.149 +	unsigned long rcv_fc_pkts;
   7.150 +	unsigned long rcv_fc_unsupported;
   7.151 +	unsigned long xmt_tco_pkts;
   7.152 +	unsigned long rcv_tco_pkts;
   7.153 +	unsigned long rx_intr_pkts;
   7.154 +};
   7.155 +
   7.156 +/* TODO: kill me when we can do C99 */
   7.157 +#define false		(0)
   7.158 +#define true		(1)
   7.159 +
   7.160 +/* Changed for 82558 and 82559 enhancements */
   7.161 +/* defines for 82558/9 flow control CSR values */
   7.162 +#define DFLT_FC_THLD       0x00	/* Rx FIFO threshold of 0.5KB free  */
   7.163 +#define DFLT_FC_CMD        0x00	/* FC Command in CSR */
   7.164 +
   7.165 +/* ====================================================================== */
   7.166 +/*                              equates                                   */
   7.167 +/* ====================================================================== */
   7.168 +
   7.169 +/*
   7.170 + * These are general purpose defines 
   7.171 + */
   7.172 +
   7.173 +/* Bit Mask definitions */
   7.174 +#define BIT_0       0x0001
   7.175 +#define BIT_1       0x0002
   7.176 +#define BIT_2       0x0004
   7.177 +#define BIT_3       0x0008
   7.178 +#define BIT_4       0x0010
   7.179 +#define BIT_5       0x0020
   7.180 +#define BIT_6       0x0040
   7.181 +#define BIT_7       0x0080
   7.182 +#define BIT_8       0x0100
   7.183 +#define BIT_9       0x0200
   7.184 +#define BIT_10      0x0400
   7.185 +#define BIT_11      0x0800
   7.186 +#define BIT_12      0x1000
   7.187 +#define BIT_13      0x2000
   7.188 +#define BIT_14      0x4000
   7.189 +#define BIT_15      0x8000
   7.190 +#define BIT_28      0x10000000
   7.191 +
   7.192 +#define BIT_0_2     0x0007
   7.193 +#define BIT_0_3     0x000F
   7.194 +#define BIT_0_4     0x001F
   7.195 +#define BIT_0_5     0x003F
   7.196 +#define BIT_0_6     0x007F
   7.197 +#define BIT_0_7     0x00FF
   7.198 +#define BIT_0_8     0x01FF
   7.199 +#define BIT_0_13    0x3FFF
   7.200 +#define BIT_0_15    0xFFFF
   7.201 +#define BIT_1_2     0x0006
   7.202 +#define BIT_1_3     0x000E
   7.203 +#define BIT_2_5     0x003C
   7.204 +#define BIT_3_4     0x0018
   7.205 +#define BIT_4_5     0x0030
   7.206 +#define BIT_4_6     0x0070
   7.207 +#define BIT_4_7     0x00F0
   7.208 +#define BIT_5_7     0x00E0
   7.209 +#define BIT_5_12    0x1FE0
   7.210 +#define BIT_5_15    0xFFE0
   7.211 +#define BIT_6_7     0x00c0
   7.212 +#define BIT_7_11    0x0F80
   7.213 +#define BIT_8_10    0x0700
   7.214 +#define BIT_9_13    0x3E00
   7.215 +#define BIT_12_15   0xF000
   7.216 +#define BIT_8_15    0xFF00
   7.217 +
   7.218 +#define BIT_16_20   0x001F0000
   7.219 +#define BIT_21_25   0x03E00000
   7.220 +#define BIT_26_27   0x0C000000
   7.221 +
   7.222 +/* Transmit Threshold related constants */
   7.223 +#define DEFAULT_TX_PER_UNDERRUN         20000
   7.224 +
   7.225 +#define MAX_MULTICAST_ADDRS             64
   7.226 +#define MAX_FILTER                      16
   7.227 +
   7.228 +#define FULL_DUPLEX      2
   7.229 +#define HALF_DUPLEX      1
   7.230 +
   7.231 +/*
   7.232 + * These defines are specific to the 82557 
   7.233 + */
   7.234 +
   7.235 +/* E100 PORT functions -- lower 4 bits */
   7.236 +#define PORT_SOFTWARE_RESET         0
   7.237 +#define PORT_SELFTEST               1
   7.238 +#define PORT_SELECTIVE_RESET        2
   7.239 +#define PORT_DUMP                   3
   7.240 +
   7.241 +/* SCB Status Word bit definitions */
   7.242 +/* Interrupt status/ack fields */
   7.243 +/* ER and FCP interrupts for 82558 masks  */
   7.244 +#define SCB_STATUS_ACK_MASK        BIT_8_15	/* Status Mask */
   7.245 +#define SCB_STATUS_ACK_CX          BIT_15	/* CU Completed Action Cmd */
   7.246 +#define SCB_STATUS_ACK_FR          BIT_14	/* RU Received A Frame */
   7.247 +#define SCB_STATUS_ACK_CNA         BIT_13	/* CU Became Inactive (IDLE) */
   7.248 +#define SCB_STATUS_ACK_RNR         BIT_12	/* RU Became Not Ready */
   7.249 +#define SCB_STATUS_ACK_MDI         BIT_11	/* MDI read or write done */
   7.250 +#define SCB_STATUS_ACK_SWI         BIT_10	/* S/W generated interrupt */
   7.251 +#define SCB_STATUS_ACK_ER          BIT_9	/* Early Receive */
   7.252 +#define SCB_STATUS_ACK_FCP         BIT_8	/* Flow Control Pause */
   7.253 +
   7.254 +/*- CUS Fields */
   7.255 +#define SCB_CUS_MASK            (BIT_6 | BIT_7)	/* CUS 2-bit Mask */
   7.256 +#define SCB_CUS_IDLE            0	/* CU Idle */
   7.257 +#define SCB_CUS_SUSPEND         BIT_6	/* CU Suspended */
   7.258 +#define SCB_CUS_ACTIVE          BIT_7	/* CU Active */
   7.259 +
   7.260 +/*- RUS Fields */
   7.261 +#define SCB_RUS_IDLE            0	/* RU Idle */
   7.262 +#define SCB_RUS_MASK            BIT_2_5	/* RUS 3-bit Mask */
   7.263 +#define SCB_RUS_SUSPEND         BIT_2	/* RU Suspended */
   7.264 +#define SCB_RUS_NO_RESOURCES    BIT_3	/* RU Out Of Resources */
   7.265 +#define SCB_RUS_READY           BIT_4	/* RU Ready */
   7.266 +#define SCB_RUS_SUSP_NO_RBDS    (BIT_2 | BIT_5)	/* RU No More RBDs */
   7.267 +#define SCB_RUS_NO_RBDS         (BIT_3 | BIT_5)	/* RU No More RBDs */
   7.268 +#define SCB_RUS_READY_NO_RBDS   (BIT_4 | BIT_5)	/* RU Ready, No RBDs */
   7.269 +
   7.270 +/* SCB Command Word bit definitions */
   7.271 +/*- CUC fields */
   7.272 +/* Changing mask to 4 bits */
   7.273 +#define SCB_CUC_MASK            BIT_4_7	/* CUC 4-bit Mask */
   7.274 +#define SCB_CUC_NOOP            0
   7.275 +#define SCB_CUC_START           BIT_4	/* CU Start */
   7.276 +#define SCB_CUC_RESUME          BIT_5	/* CU Resume */
   7.277 +#define SCB_CUC_UNKNOWN         BIT_7	/* CU unknown command */
   7.278 +/* Changed for 82558 enhancements */
   7.279 +#define SCB_CUC_STATIC_RESUME   (BIT_5 | BIT_7)	/* 82558/9 Static Resume */
   7.280 +#define SCB_CUC_DUMP_ADDR       BIT_6	/* CU Dump Counters Address */
   7.281 +#define SCB_CUC_DUMP_STAT       (BIT_4 | BIT_6)	/* CU Dump stat. counters */
   7.282 +#define SCB_CUC_LOAD_BASE       (BIT_5 | BIT_6)	/* Load the CU base */
   7.283 +/* Below was defined as BIT_4_7 */
   7.284 +#define SCB_CUC_DUMP_RST_STAT   BIT_4_6	/* CU Dump & reset statistics cntrs */
   7.285 +
   7.286 +/*- RUC fields */
   7.287 +#define SCB_RUC_MASK            BIT_0_2	/* RUC 3-bit Mask */
   7.288 +#define SCB_RUC_START           BIT_0	/* RU Start */
   7.289 +#define SCB_RUC_RESUME          BIT_1	/* RU Resume */
   7.290 +#define SCB_RUC_ABORT           BIT_2	/* RU Abort */
   7.291 +#define SCB_RUC_LOAD_HDS        (BIT_0 | BIT_2)	/* Load RFD Header Data Size */
   7.292 +#define SCB_RUC_LOAD_BASE       (BIT_1 | BIT_2)	/* Load the RU base */
   7.293 +#define SCB_RUC_RBD_RESUME      BIT_0_2	/* RBD resume */
   7.294 +
   7.295 +/* Interrupt fields (assuming byte addressing) */
   7.296 +#define SCB_INT_MASK            BIT_0	/* Mask interrupts */
   7.297 +#define SCB_SOFT_INT            BIT_1	/* Generate a S/W interrupt */
   7.298 +/*  Specific Interrupt Mask Bits (upper byte of SCB Command word) */
   7.299 +#define SCB_FCP_INT_MASK        BIT_2	/* Flow Control Pause */
   7.300 +#define SCB_ER_INT_MASK         BIT_3	/* Early Receive */
   7.301 +#define SCB_RNR_INT_MASK        BIT_4	/* RU Not Ready */
   7.302 +#define SCB_CNA_INT_MASK        BIT_5	/* CU Not Active */
   7.303 +#define SCB_FR_INT_MASK         BIT_6	/* Frame Received */
   7.304 +#define SCB_CX_INT_MASK         BIT_7	/* CU eXecution w/ I-bit done */
   7.305 +#define SCB_BACHELOR_INT_MASK   BIT_2_7	/* 82558 interrupt mask bits */
   7.306 +
   7.307 +#define SCB_GCR2_EEPROM_ACCESS_SEMAPHORE BIT_7
   7.308 +
   7.309 +/* EEPROM bit definitions */
   7.310 +/*- EEPROM control register bits */
   7.311 +#define EEPROM_FLAG_ASF  0x8000
   7.312 +#define EEPROM_FLAG_GCL  0x4000
   7.313 +
   7.314 +#define EN_TRNF          0x10	/* Enable turnoff */
   7.315 +#define EEDO             0x08	/* EEPROM data out */
   7.316 +#define EEDI             0x04	/* EEPROM data in (set for writing data) */
   7.317 +#define EECS             0x02	/* EEPROM chip select (1=hi, 0=lo) */
   7.318 +#define EESK             0x01	/* EEPROM shift clock (1=hi, 0=lo) */
   7.319 +
   7.320 +/*- EEPROM opcodes */
   7.321 +#define EEPROM_READ_OPCODE          06
   7.322 +#define EEPROM_WRITE_OPCODE         05
   7.323 +#define EEPROM_ERASE_OPCODE         07
   7.324 +#define EEPROM_EWEN_OPCODE          19	/* Erase/write enable */
   7.325 +#define EEPROM_EWDS_OPCODE          16	/* Erase/write disable */
   7.326 +
   7.327 +/*- EEPROM data locations */
   7.328 +#define EEPROM_NODE_ADDRESS_BYTE_0      0
   7.329 +#define EEPROM_COMPATIBILITY_WORD       3
   7.330 +#define EEPROM_PWA_NO                   8
   7.331 +#define EEPROM_ID_WORD			0x0A
   7.332 +#define EEPROM_CONFIG_ASF		0x0D
   7.333 +#define EEPROM_SMBUS_ADDR		0x90
   7.334 +
   7.335 +#define EEPROM_SUM                      0xbaba
   7.336 +
   7.337 +// Zero Locking Algorithm definitions:
   7.338 +#define ZLOCK_ZERO_MASK		0x00F0
   7.339 +#define ZLOCK_MAX_READS		50	
   7.340 +#define ZLOCK_SET_ZERO		0x2010
   7.341 +#define ZLOCK_MAX_SLEEP		300 * HZ	
   7.342 +#define ZLOCK_MAX_ERRORS	300
   7.343 +
   7.344 +/* E100 Action Commands */
   7.345 +#define CB_IA_ADDRESS           1
   7.346 +#define CB_CONFIGURE            2
   7.347 +#define CB_MULTICAST            3
   7.348 +#define CB_TRANSMIT             4
   7.349 +#define CB_LOAD_MICROCODE       5
   7.350 +#define CB_LOAD_FILTER		8
   7.351 +#define CB_MAX_NONTX_CMD        9
   7.352 +#define CB_IPCB_TRANSMIT        9
   7.353 +
   7.354 +/* Pre-defined Filter Bits */
   7.355 +#define CB_FILTER_EL            0x80000000
   7.356 +#define CB_FILTER_FIX           0x40000000
   7.357 +#define CB_FILTER_ARP           0x08000000
   7.358 +#define CB_FILTER_IA_MATCH      0x02000000
   7.359 +
   7.360 +/* Command Block (CB) Field Definitions */
   7.361 +/*- CB Command Word */
   7.362 +#define CB_EL_BIT           BIT_15	/* CB EL Bit */
   7.363 +#define CB_S_BIT            BIT_14	/* CB Suspend Bit */
   7.364 +#define CB_I_BIT            BIT_13	/* CB Interrupt Bit */
   7.365 +#define CB_TX_SF_BIT        BIT_3	/* TX CB Flexible Mode */
   7.366 +#define CB_CMD_MASK         BIT_0_3	/* CB 4-bit CMD Mask */
   7.367 +#define CB_CID_DEFAULT      (0x1f << 8)	/* CB 5-bit CID (max value) */
   7.368 +
   7.369 +/*- CB Status Word */
   7.370 +#define CB_STATUS_MASK          BIT_12_15	/* CB Status Mask (4-bits) */
   7.371 +#define CB_STATUS_COMPLETE      BIT_15	/* CB Complete Bit */
   7.372 +#define CB_STATUS_OK            BIT_13	/* CB OK Bit */
   7.373 +#define CB_STATUS_VLAN          BIT_12 /* CB Valn detected Bit */
   7.374 +#define CB_STATUS_FAIL          BIT_11	/* CB Fail (F) Bit */
   7.375 +
   7.376 +/*misc command bits */
   7.377 +#define CB_TX_EOF_BIT           BIT_15	/* TX CB/TBD EOF Bit */
   7.378 +
   7.379 +/* Config params */
   7.380 +#define CB_CFIG_BYTE_COUNT          22	/* 22 config bytes */
   7.381 +#define CB_CFIG_D102_BYTE_COUNT    10
   7.382 +
   7.383 +/* Receive Frame Descriptor Fields */
   7.384 +
   7.385 +/*- RFD Status Bits */
   7.386 +#define RFD_RECEIVE_COLLISION   BIT_0	/* Collision detected on Receive */
   7.387 +#define RFD_IA_MATCH            BIT_1	/* Indv Address Match Bit */
   7.388 +#define RFD_RX_ERR              BIT_4	/* RX_ERR pin on Phy was set */
   7.389 +#define RFD_FRAME_TOO_SHORT     BIT_7	/* Receive Frame Short */
   7.390 +#define RFD_DMA_OVERRUN         BIT_8	/* Receive DMA Overrun */
   7.391 +#define RFD_NO_RESOURCES        BIT_9	/* No Buffer Space */
   7.392 +#define RFD_ALIGNMENT_ERROR     BIT_10	/* Alignment Error */
   7.393 +#define RFD_CRC_ERROR           BIT_11	/* CRC Error */
   7.394 +#define RFD_STATUS_OK           BIT_13	/* RFD OK Bit */
   7.395 +#define RFD_STATUS_COMPLETE     BIT_15	/* RFD Complete Bit */
   7.396 +
   7.397 +/*- RFD Command Bits*/
   7.398 +#define RFD_EL_BIT      BIT_15	/* RFD EL Bit */
   7.399 +#define RFD_S_BIT       BIT_14	/* RFD Suspend Bit */
   7.400 +#define RFD_H_BIT       BIT_4	/* Header RFD Bit */
   7.401 +#define RFD_SF_BIT      BIT_3	/* RFD Flexible Mode */
   7.402 +
   7.403 +/*- RFD misc bits*/
   7.404 +#define RFD_EOF_BIT         BIT_15	/* RFD End-Of-Frame Bit */
   7.405 +#define RFD_F_BIT           BIT_14	/* RFD Buffer Fetch Bit */
   7.406 +#define RFD_ACT_COUNT_MASK  BIT_0_13	/* RFD Actual Count Mask */
   7.407 +
   7.408 +/* Receive Buffer Descriptor Fields*/
   7.409 +#define RBD_EOF_BIT             BIT_15	/* RBD End-Of-Frame Bit */
   7.410 +#define RBD_F_BIT               BIT_14	/* RBD Buffer Fetch Bit */
   7.411 +#define RBD_ACT_COUNT_MASK      BIT_0_13	/* RBD Actual Count Mask */
   7.412 +
   7.413 +#define SIZE_FIELD_MASK     BIT_0_13	/* Size of the associated buffer */
   7.414 +#define RBD_EL_BIT          BIT_15	/* RBD EL Bit */
   7.415 +
   7.416 +/* Self Test Results*/
   7.417 +#define CB_SELFTEST_FAIL_BIT        BIT_12
   7.418 +#define CB_SELFTEST_DIAG_BIT        BIT_5
   7.419 +#define CB_SELFTEST_REGISTER_BIT    BIT_3
   7.420 +#define CB_SELFTEST_ROM_BIT         BIT_2
   7.421 +
   7.422 +#define CB_SELFTEST_ERROR_MASK ( \
   7.423 +                CB_SELFTEST_FAIL_BIT | CB_SELFTEST_DIAG_BIT | \
   7.424 +                CB_SELFTEST_REGISTER_BIT | CB_SELFTEST_ROM_BIT)
   7.425 +
   7.426 +/* adapter vendor & device ids */
   7.427 +#define PCI_OHIO_BOARD   0x10f0	/* subdevice ID, Ohio dual port nic */
   7.428 +
   7.429 +/* Values for PCI_REV_ID_REGISTER values */
   7.430 +#define D101A4_REV_ID      4	/* 82558 A4 stepping */
   7.431 +#define D101B0_REV_ID      5	/* 82558 B0 stepping */
   7.432 +#define D101MA_REV_ID      8	/* 82559 A0 stepping */
   7.433 +#define D101S_REV_ID      9	/* 82559S A-step */
   7.434 +#define D102_REV_ID      12
   7.435 +#define D102C_REV_ID     13	/* 82550 step C */
   7.436 +#define D102E_REV_ID     15
   7.437 +
   7.438 +/* ############Start of 82555 specific defines################## */
   7.439 +
   7.440 +#define PHY_82555_LED_SWITCH_CONTROL    	0x1b	/* 82555 led switch control register */
   7.441 +
   7.442 +/* 82555 led switch control reg. opcodes */
   7.443 +#define PHY_82555_LED_NORMAL_CONTROL    0	// control back to the 8255X
   7.444 +#define PHY_82555_LED_DRIVER_CONTROL    BIT_2	// the driver is in control
   7.445 +#define PHY_82555_LED_OFF               BIT_2	// activity LED is off
   7.446 +#define PHY_82555_LED_ON_559           (BIT_0 | BIT_2)	// activity LED is on for 559 and later
   7.447 +#define PHY_82555_LED_ON_PRE_559       (BIT_0 | BIT_1 | BIT_2)	// activity LED is on for 558 and before
   7.448 +
   7.449 +// Describe the state of the phy led.
   7.450 +// needed for the function : 'e100_blink_timer'
   7.451 +enum led_state_e {
   7.452 +	LED_OFF = 0,
   7.453 +	LED_ON,
   7.454 +};
   7.455 +
   7.456 +/* ############End of 82555 specific defines##################### */
   7.457 +
   7.458 +#define RFD_PARSE_BIT			BIT_3
   7.459 +#define RFD_TCP_PACKET			0x00
   7.460 +#define RFD_UDP_PACKET			0x01
   7.461 +#define TCPUDP_CHECKSUM_BIT_VALID	BIT_4
   7.462 +#define TCPUDP_CHECKSUM_VALID		BIT_5
   7.463 +#define CHECKSUM_PROTOCOL_MASK		0x03
   7.464 +
   7.465 +#define VLAN_SIZE   4
   7.466 +#define CHKSUM_SIZE 2
   7.467 +#define RFD_DATA_SIZE (ETH_FRAME_LEN + CHKSUM_SIZE + VLAN_SIZE)
   7.468 +
   7.469 +/* Bits for bdp->flags */
   7.470 +#define DF_LINK_FC_CAP     0x00000001	/* Link is flow control capable */
   7.471 +#define DF_CSUM_OFFLOAD    0x00000002
   7.472 +#define DF_UCODE_LOADED    0x00000004
   7.473 +#define USE_IPCB           0x00000008	/* set if using ipcb for transmits */
   7.474 +#define IS_BACHELOR        0x00000010	/* set if 82558 or newer board */
   7.475 +#define IS_ICH             0x00000020
   7.476 +#define DF_SPEED_FORCED    0x00000040	/* set if speed is forced */
   7.477 +#define LED_IS_ON	   0x00000080	/* LED is turned ON by the driver */
   7.478 +#define DF_LINK_FC_TX_ONLY 0x00000100	/* Received PAUSE frames are honored*/
   7.479 +
   7.480 +typedef struct net_device_stats net_dev_stats_t;
   7.481 +
   7.482 +/* needed macros */
   7.483 +/* These macros use the bdp pointer. If you use them it better be defined */
   7.484 +#define PREV_TCB_USED(X)  ((X).tail ? (X).tail - 1 : bdp->params.TxDescriptors - 1)
   7.485 +#define NEXT_TCB_TOUSE(X) ((((X) + 1) >= bdp->params.TxDescriptors) ? 0 : (X) + 1)
   7.486 +#define TCB_TO_USE(X)     ((X).tail)
   7.487 +#define TCBS_AVAIL(X)     (NEXT_TCB_TOUSE( NEXT_TCB_TOUSE((X).tail)) != (X).head)
   7.488 +
   7.489 +#define RFD_POINTER(skb,bdp)      ((rfd_t *) (((unsigned char *)((skb)->data))-((bdp)->rfd_size)))
   7.490 +#define SKB_RFD_STATUS(skb,bdp)   ((RFD_POINTER((skb),(bdp)))->rfd_header.cb_status)
   7.491 +
   7.492 +/* ====================================================================== */
   7.493 +/*                              82557                                     */
   7.494 +/* ====================================================================== */
   7.495 +
   7.496 +/* Changed for 82558 enhancement */
   7.497 +typedef struct _d101_scb_ext_t {
   7.498 +	u32 scb_rx_dma_cnt;	/* Rx DMA byte count */
   7.499 +	u8 scb_early_rx_int;	/* Early Rx DMA byte count */
   7.500 +	u8 scb_fc_thld;	/* Flow Control threshold */
   7.501 +	u8 scb_fc_xon_xoff;	/* Flow Control XON/XOFF values */
   7.502 +	u8 scb_pmdr;	/* Power Mgmt. Driver Reg */
   7.503 +} d101_scb_ext __attribute__ ((__packed__));
   7.504 +
   7.505 +/* Changed for 82559 enhancement */
   7.506 +typedef struct _d101m_scb_ext_t {
   7.507 +	u32 scb_rx_dma_cnt;	/* Rx DMA byte count */
   7.508 +	u8 scb_early_rx_int;	/* Early Rx DMA byte count */
   7.509 +	u8 scb_fc_thld;	/* Flow Control threshold */
   7.510 +	u8 scb_fc_xon_xoff;	/* Flow Control XON/XOFF values */
   7.511 +	u8 scb_pmdr;	/* Power Mgmt. Driver Reg */
   7.512 +	u8 scb_gen_ctrl;	/* General Control */
   7.513 +	u8 scb_gen_stat;	/* General Status */
   7.514 +	u16 scb_reserved;	/* Reserved */
   7.515 +	u32 scb_function_event;	/* Cardbus Function Event */
   7.516 +	u32 scb_function_event_mask;	/* Cardbus Function Mask */
   7.517 +	u32 scb_function_present_state;	/* Cardbus Function state */
   7.518 +	u32 scb_force_event;	/* Cardbus Force Event */
   7.519 +} d101m_scb_ext __attribute__ ((__packed__));
   7.520 +
   7.521 +/* Changed for 82550 enhancement */
   7.522 +typedef struct _d102_scb_ext_t {
   7.523 +	u32 scb_rx_dma_cnt;	/* Rx DMA byte count */
   7.524 +	u8 scb_early_rx_int;	/* Early Rx DMA byte count */
   7.525 +	u8 scb_fc_thld;	/* Flow Control threshold */
   7.526 +	u8 scb_fc_xon_xoff;	/* Flow Control XON/XOFF values */
   7.527 +	u8 scb_pmdr;	/* Power Mgmt. Driver Reg */
   7.528 +	u8 scb_gen_ctrl;	/* General Control */
   7.529 +	u8 scb_gen_stat;	/* General Status */
   7.530 +	u8 scb_gen_ctrl2;
   7.531 +	u8 scb_reserved;	/* Reserved */
   7.532 +	u32 scb_scheduling_reg;
   7.533 +	u32 scb_reserved2;
   7.534 +	u32 scb_function_event;	/* Cardbus Function Event */
   7.535 +	u32 scb_function_event_mask;	/* Cardbus Function Mask */
   7.536 +	u32 scb_function_present_state;	/* Cardbus Function state */
   7.537 +	u32 scb_force_event;	/* Cardbus Force Event */
   7.538 +} d102_scb_ext __attribute__ ((__packed__));
   7.539 +
   7.540 +/*
   7.541 + * 82557 status control block. this will be memory mapped & will hang of the
   7.542 + * the bdp, which hangs of the bdp. This is the brain of it.
   7.543 + */
   7.544 +typedef struct _scb_t {
   7.545 +	u16 scb_status;	/* SCB Status register */
   7.546 +	u8 scb_cmd_low;	/* SCB Command register (low byte) */
   7.547 +	u8 scb_cmd_hi;	/* SCB Command register (high byte) */
   7.548 +	u32 scb_gen_ptr;	/* SCB General pointer */
   7.549 +	u32 scb_port;	/* PORT register */
   7.550 +	u16 scb_flsh_cntrl;	/* Flash Control register */
   7.551 +	u16 scb_eprm_cntrl;	/* EEPROM control register */
   7.552 +	u32 scb_mdi_cntrl;	/* MDI Control Register */
   7.553 +	/* Changed for 82558 enhancement */
   7.554 +	union {
   7.555 +		u32 scb_rx_dma_cnt;	/* Rx DMA byte count */
   7.556 +		d101_scb_ext d101_scb;	/* 82558/9 specific fields */
   7.557 +		d101m_scb_ext d101m_scb;	/* 82559 specific fields */
   7.558 +		d102_scb_ext d102_scb;
   7.559 +	} scb_ext;
   7.560 +} scb_t __attribute__ ((__packed__));
   7.561 +
   7.562 +/* Self test
   7.563 + * This is used to dump results of the self test 
   7.564 + */
   7.565 +typedef struct _self_test_t {
   7.566 +	u32 st_sign;	/* Self Test Signature */
   7.567 +	u32 st_result;	/* Self Test Results */
   7.568 +} self_test_t __attribute__ ((__packed__));
   7.569 +
   7.570 +/* 
   7.571 + *  Statistical Counters 
   7.572 + */
   7.573 +/* 82557 counters */
   7.574 +typedef struct _basic_cntr_t {
   7.575 +	u32 xmt_gd_frames;	/* Good frames transmitted */
   7.576 +	u32 xmt_max_coll;	/* Fatal frames -- had max collisions */
   7.577 +	u32 xmt_late_coll;	/* Fatal frames -- had a late coll. */
   7.578 +	u32 xmt_uruns;	/* Xmit underruns (fatal or re-transmit) */
   7.579 +	u32 xmt_lost_crs;	/* Frames transmitted without CRS */
   7.580 +	u32 xmt_deferred;	/* Deferred transmits */
   7.581 +	u32 xmt_sngl_coll;	/* Transmits that had 1 and only 1 coll. */
   7.582 +	u32 xmt_mlt_coll;	/* Transmits that had multiple coll. */
   7.583 +	u32 xmt_ttl_coll;	/* Transmits that had 1+ collisions. */
   7.584 +	u32 rcv_gd_frames;	/* Good frames received */
   7.585 +	u32 rcv_crc_errs;	/* Aligned frames that had a CRC error */
   7.586 +	u32 rcv_algn_errs;	/* Receives that had alignment errors */
   7.587 +	u32 rcv_rsrc_err;	/* Good frame dropped cuz no resources */
   7.588 +	u32 rcv_oruns;	/* Overrun errors - bus was busy */
   7.589 +	u32 rcv_err_coll;	/* Received frms. that encountered coll. */
   7.590 +	u32 rcv_shrt_frames;	/* Received frames that were to short */
   7.591 +} basic_cntr_t;
   7.592 +
   7.593 +/* 82558 extended statistic counters */
   7.594 +typedef struct _ext_cntr_t {
   7.595 +	u32 xmt_fc_frames;
   7.596 +	u32 rcv_fc_frames;
   7.597 +	u32 rcv_fc_unsupported;
   7.598 +} ext_cntr_t;
   7.599 +
   7.600 +/* 82559 TCO statistic counters */
   7.601 +typedef struct _tco_cntr_t {
   7.602 +	u16 xmt_tco_frames;
   7.603 +	u16 rcv_tco_frames;
   7.604 +} tco_cntr_t;
   7.605 +
   7.606 +/* Structures to access thet physical dump area */
   7.607 +/* Use one of these types, according to the statisitcal counters mode,
   7.608 +   to cast the pointer to the physical dump area and access the cmd_complete
   7.609 +   DWORD. */
   7.610 +
   7.611 +/* 557-mode : only basic counters + cmd_complete */
   7.612 +typedef struct _err_cntr_557_t {
   7.613 +	basic_cntr_t basic_stats;
   7.614 +	u32 cmd_complete;
   7.615 +} err_cntr_557_t;
   7.616 +
   7.617 +/* 558-mode : basic + extended counters + cmd_complete */
   7.618 +typedef struct _err_cntr_558_t {
   7.619 +	basic_cntr_t basic_stats;
   7.620 +	ext_cntr_t extended_stats;
   7.621 +	u32 cmd_complete;
   7.622 +} err_cntr_558_t;
   7.623 +
   7.624 +/* 559-mode : basic + extended + TCO counters + cmd_complete */
   7.625 +typedef struct _err_cntr_559_t {
   7.626 +	basic_cntr_t basic_stats;
   7.627 +	ext_cntr_t extended_stats;
   7.628 +	tco_cntr_t tco_stats;
   7.629 +	u32 cmd_complete;
   7.630 +} err_cntr_559_t;
   7.631 +
   7.632 +/* This typedef defines the struct needed to hold the largest number of counters */
   7.633 +typedef err_cntr_559_t max_counters_t;
   7.634 +
   7.635 +/* Different statistical-counters mode the controller may be in */
   7.636 +typedef enum _stat_mode_t {
   7.637 +	E100_BASIC_STATS = 0,	/* 82557 stats : 16 counters / 16 dw */
   7.638 +	E100_EXTENDED_STATS,	/* 82558 stats : 19 counters / 19 dw */
   7.639 +	E100_TCO_STATS		/* 82559 stats : 21 counters / 20 dw */
   7.640 +} stat_mode_t;
   7.641 +
   7.642 +/* dump statistical counters complete codes */
   7.643 +#define DUMP_STAT_COMPLETED	0xA005
   7.644 +#define DUMP_RST_STAT_COMPLETED	0xA007
   7.645 +
   7.646 +/* Command Block (CB) Generic Header Structure*/
   7.647 +typedef struct _cb_header_t {
   7.648 +	u16 cb_status;	/* Command Block Status */
   7.649 +	u16 cb_cmd;	/* Command Block Command */
   7.650 +	u32 cb_lnk_ptr;	/* Link To Next CB */
   7.651 +} cb_header_t __attribute__ ((__packed__));
   7.652 +
   7.653 +//* Individual Address Command Block (IA_CB)*/
   7.654 +typedef struct _ia_cb_t {
   7.655 +	cb_header_t ia_cb_hdr;
   7.656 +	u8 ia_addr[ETH_ALEN];
   7.657 +} ia_cb_t __attribute__ ((__packed__));
   7.658 +
   7.659 +/* Configure Command Block (CONFIG_CB)*/
   7.660 +typedef struct _config_cb_t {
   7.661 +	cb_header_t cfg_cbhdr;
   7.662 +	u8 cfg_byte[CB_CFIG_BYTE_COUNT + CB_CFIG_D102_BYTE_COUNT];
   7.663 +} config_cb_t __attribute__ ((__packed__));
   7.664 +
   7.665 +/* MultiCast Command Block (MULTICAST_CB)*/
   7.666 +typedef struct _multicast_cb_t {
   7.667 +	cb_header_t mc_cbhdr;
   7.668 +	u16 mc_count;	/* Number of multicast addresses */
   7.669 +	u8 mc_addr[(ETH_ALEN * MAX_MULTICAST_ADDRS)];
   7.670 +} mltcst_cb_t __attribute__ ((__packed__));
   7.671 +
   7.672 +#define UCODE_MAX_DWORDS	134
   7.673 +/* Load Microcode Command Block (LOAD_UCODE_CB)*/
   7.674 +typedef struct _load_ucode_cb_t {
   7.675 +	cb_header_t load_ucode_cbhdr;
   7.676 +	u32 ucode_dword[UCODE_MAX_DWORDS];
   7.677 +} load_ucode_cb_t __attribute__ ((__packed__));
   7.678 +
   7.679 +/* Load Programmable Filter Data*/
   7.680 +typedef struct _filter_cb_t {
   7.681 +	cb_header_t filter_cb_hdr;
   7.682 +	u32 filter_data[MAX_FILTER];
   7.683 +} filter_cb_t __attribute__ ((__packed__));
   7.684 +
   7.685 +/* NON_TRANSMIT_CB -- Generic Non-Transmit Command Block 
   7.686 + */
   7.687 +typedef struct _nxmit_cb_t {
   7.688 +	union {
   7.689 +		config_cb_t config;
   7.690 +		ia_cb_t setup;
   7.691 +		load_ucode_cb_t load_ucode;
   7.692 +		mltcst_cb_t multicast;
   7.693 +		filter_cb_t filter;
   7.694 +	} ntcb;
   7.695 +} nxmit_cb_t __attribute__ ((__packed__));
   7.696 +
   7.697 +/*Block for queuing for postponed execution of the non-transmit commands*/
   7.698 +typedef struct _nxmit_cb_entry_t {
   7.699 +	struct list_head list_elem;
   7.700 +	nxmit_cb_t *non_tx_cmd;
   7.701 +	dma_addr_t dma_addr;
   7.702 +	unsigned long expiration_time;
   7.703 +} nxmit_cb_entry_t;
   7.704 +
   7.705 +/* States for postponed non tx commands execution */
   7.706 +typedef enum _non_tx_cmd_state_t {
   7.707 +	E100_NON_TX_IDLE = 0,	/* No queued NON-TX commands */
   7.708 +	E100_WAIT_TX_FINISH,	/* Wait for completion of the TX activities */
   7.709 +	E100_WAIT_NON_TX_FINISH	/* Wait for completion of the non TX command */
   7.710 +} non_tx_cmd_state_t;
   7.711 +
   7.712 +/* some defines for the ipcb */
   7.713 +#define IPCB_IP_CHECKSUM_ENABLE 	BIT_4
   7.714 +#define IPCB_TCPUDP_CHECKSUM_ENABLE	BIT_5
   7.715 +#define IPCB_TCP_PACKET 		BIT_6
   7.716 +#define IPCB_LARGESEND_ENABLE 		BIT_7
   7.717 +#define IPCB_HARDWAREPARSING_ENABLE	BIT_0
   7.718 +#define IPCB_INSERTVLAN_ENABLE 		BIT_1
   7.719 +#define IPCB_IP_ACTIVATION_DEFAULT      IPCB_HARDWAREPARSING_ENABLE
   7.720 +
   7.721 +/* Transmit Buffer Descriptor (TBD)*/
   7.722 +typedef struct _tbd_t {
   7.723 +	u32 tbd_buf_addr;	/* Physical Transmit Buffer Address */
   7.724 +	u16 tbd_buf_cnt;	/* Actual Count Of Bytes */
   7.725 +	u16 padd;
   7.726 +} tbd_t __attribute__ ((__packed__));
   7.727 +
   7.728 +/* d102 specific fields */
   7.729 +typedef struct _tcb_ipcb_t {
   7.730 +	u16 schedule_low;
   7.731 +	u8 ip_schedule;
   7.732 +	u8 ip_activation_high;
   7.733 +	u16 vlan;
   7.734 +	u8 ip_header_offset;
   7.735 +	u8 tcp_header_offset;
   7.736 +	union {
   7.737 +		u32 sec_rec_phys_addr;
   7.738 +		u32 tbd_zero_address;
   7.739 +	} tbd_sec_addr;
   7.740 +	union {
   7.741 +		u16 sec_rec_size;
   7.742 +		u16 tbd_zero_size;
   7.743 +	} tbd_sec_size;
   7.744 +	u16 total_tcp_payload;
   7.745 +} tcb_ipcb_t __attribute__ ((__packed__));
   7.746 +
   7.747 +#define E100_TBD_ARRAY_SIZE (2+MAX_SKB_FRAGS)
   7.748 +
   7.749 +/* Transmit Command Block (TCB)*/
   7.750 +struct _tcb_t {
   7.751 +	cb_header_t tcb_hdr;
   7.752 +	u32 tcb_tbd_ptr;	/* TBD address */
   7.753 +	u16 tcb_cnt;	/* Data Bytes In TCB past header */
   7.754 +	u8 tcb_thrshld;	/* TX Threshold for FIFO Extender */
   7.755 +	u8 tcb_tbd_num;
   7.756 +
   7.757 +	union {
   7.758 +		tcb_ipcb_t ipcb;	/* d102 ipcb fields */
   7.759 +		tbd_t tbd_array[E100_TBD_ARRAY_SIZE];
   7.760 +	} tcbu;
   7.761 +
   7.762 +	/* From here onward we can dump anything we want as long as the
   7.763 +	 * size of the total structure is a multiple of a paragraph
   7.764 +	 * boundary ( i.e. -16 bit aligned ).
   7.765 +	 */
   7.766 +	tbd_t *tbd_ptr;
   7.767 +
   7.768 +	u32 tcb_tbd_dflt_ptr;	/* TBD address for non-segmented packet */
   7.769 +	u32 tcb_tbd_expand_ptr;	/* TBD address for segmented packet */
   7.770 +
   7.771 +	struct sk_buff *tcb_skb;	/* the associated socket buffer */
   7.772 +	dma_addr_t tcb_phys;	/* phys addr of the TCB */
   7.773 +} __attribute__ ((__packed__));
   7.774 +
   7.775 +#define _TCB_T_
   7.776 +typedef struct _tcb_t tcb_t;
   7.777 +
   7.778 +/* Receive Frame Descriptor (RFD) - will be using the simple model*/
   7.779 +struct _rfd_t {
   7.780 +	/* 8255x */
   7.781 +	cb_header_t rfd_header;
   7.782 +	u32 rfd_rbd_ptr;	/* Receive Buffer Descriptor Addr */
   7.783 +	u16 rfd_act_cnt;	/* Number Of Bytes Received */
   7.784 +	u16 rfd_sz;	/* Number Of Bytes In RFD */
   7.785 +	/* D102 aka Gamla */
   7.786 +	u16 vlanid;
   7.787 +	u8 rcvparserstatus;
   7.788 +	u8 reserved;
   7.789 +	u16 securitystatus;
   7.790 +	u8 checksumstatus;
   7.791 +	u8 zerocopystatus;
   7.792 +	u8 pad[8];	/* data should be 16 byte aligned */
   7.793 +	u8 data[RFD_DATA_SIZE];
   7.794 +
   7.795 +} __attribute__ ((__packed__));
   7.796 +
   7.797 +#define _RFD_T_
   7.798 +typedef struct _rfd_t rfd_t;
   7.799 +
   7.800 +/* Receive Buffer Descriptor (RBD)*/
   7.801 +typedef struct _rbd_t {
   7.802 +	u16 rbd_act_cnt;	/* Number Of Bytes Received */
   7.803 +	u16 rbd_filler;
   7.804 +	u32 rbd_lnk_addr;	/* Link To Next RBD */
   7.805 +	u32 rbd_rcb_addr;	/* Receive Buffer Address */
   7.806 +	u16 rbd_sz;	/* Receive Buffer Size */
   7.807 +	u16 rbd_filler1;
   7.808 +} rbd_t __attribute__ ((__packed__));
   7.809 +
   7.810 +/*
   7.811 + * This structure is used to maintain a FIFO access to a resource that is 
   7.812 + * maintained as a circular queue. The resource to be maintained is pointed
   7.813 + * to by the "data" field in the structure below. In this driver the TCBs', 
   7.814 + * TBDs' & RFDs' are maintained  as a circular queue & are managed thru this
   7.815 + * structure.
   7.816 + */
   7.817 +typedef struct _buf_pool_t {
   7.818 +	unsigned int head;	/* index to first used resource */
   7.819 +	unsigned int tail;	/* index to last used resource */
   7.820 +	void *data;		/* points to resource pool */
   7.821 +} buf_pool_t;
   7.822 +
   7.823 +/*Rx skb holding structure*/
   7.824 +struct rx_list_elem {
   7.825 +	struct list_head list_elem;
   7.826 +	dma_addr_t dma_addr;
   7.827 +	struct sk_buff *skb;
   7.828 +};
   7.829 +
   7.830 +enum next_cu_cmd_e { RESUME_NO_WAIT = 0, RESUME_WAIT, START_WAIT };
   7.831 +enum zlock_state_e { ZLOCK_INITIAL, ZLOCK_READING, ZLOCK_SLEEPING };
   7.832 +enum tx_queue_stop_type { LONG_STOP = 0, SHORT_STOP };
   7.833 +
   7.834 +/* 64 bit aligned size */
   7.835 +#define E100_SIZE_64A(X) ((sizeof(X) + 7) & ~0x7)
   7.836 +
   7.837 +typedef struct _bd_dma_able_t {
   7.838 +	char selftest[E100_SIZE_64A(self_test_t)];
   7.839 +	char stats_counters[E100_SIZE_64A(max_counters_t)];
   7.840 +} bd_dma_able_t;
   7.841 +
   7.842 +/* bit masks for bool parameters */
   7.843 +#define PRM_XSUMRX       0x00000001
   7.844 +#define PRM_UCODE        0x00000002
   7.845 +#define PRM_FC           0x00000004
   7.846 +#define PRM_IFS          0x00000008
   7.847 +#define PRM_BUNDLE_SMALL 0x00000010
   7.848 +
   7.849 +struct cfg_params {
   7.850 +	int e100_speed_duplex;
   7.851 +	int RxDescriptors;
   7.852 +	int TxDescriptors;
   7.853 +	int IntDelay;
   7.854 +	int BundleMax;
   7.855 +	int ber;
   7.856 +	u32 b_params;
   7.857 +};
   7.858 +struct ethtool_lpbk_data{
   7.859 +        dma_addr_t dma_handle;
   7.860 +        tcb_t *tcb;
   7.861 +        rfd_t *rfd;
   7.862 +
   7.863 +};
   7.864 +
   7.865 +struct e100_private {
   7.866 +	struct vlan_group *vlgrp;
   7.867 +	u32 flags;		/* board management flags */
   7.868 +	u32 tx_per_underrun;	/* number of good tx frames per underrun */
   7.869 +	unsigned int tx_count;	/* count of tx frames, so we can request an interrupt */
   7.870 +	u8 tx_thld;		/* stores transmit threshold */
   7.871 +	u16 eeprom_size;
   7.872 +	u32 pwa_no;		/* PWA: xxxxxx-0xx */
   7.873 +	u8 perm_node_address[ETH_ALEN];
   7.874 +	struct list_head active_rx_list;	/* list of rx buffers */
   7.875 +	struct list_head rx_struct_pool;	/* pool of rx buffer struct headers */
   7.876 +	u16 rfd_size;			/* size of the adapter's RFD struct */
   7.877 +	int skb_req;			/* number of skbs neede by the adapter */
   7.878 +	u8 intr_mask;			/* mask for interrupt status */
   7.879 +
   7.880 +	void *dma_able;			/* dma allocated structs */
   7.881 +	dma_addr_t dma_able_phys;
   7.882 +	self_test_t *selftest;		/* pointer to self test area */
   7.883 +	dma_addr_t selftest_phys;	/* phys addr of selftest */
   7.884 +	max_counters_t *stats_counters;	/* pointer to stats table */
   7.885 +	dma_addr_t stat_cnt_phys;	/* phys addr of stat counter area */
   7.886 +
   7.887 +	stat_mode_t stat_mode;	/* statistics mode: extended, TCO, basic */
   7.888 +	scb_t *scb;		/* memory mapped ptr to 82557 scb */
   7.889 +
   7.890 +	tcb_t *last_tcb;	/* pointer to last tcb sent */
   7.891 +	buf_pool_t tcb_pool;	/* adapter's TCB array */
   7.892 +	dma_addr_t tcb_phys;	/* phys addr of start of TCBs */
   7.893 +
   7.894 +	u16 cur_line_speed;
   7.895 +	u16 cur_dplx_mode;
   7.896 +
   7.897 +	struct net_device *device;
   7.898 +	struct pci_dev *pdev;
   7.899 +	struct driver_stats drv_stats;
   7.900 +
   7.901 +	u8 rev_id;		/* adapter PCI revision ID */
   7.902 +
   7.903 +	unsigned int phy_addr;	/* address of PHY component */
   7.904 +	unsigned int PhyId;	/* ID of PHY component */
   7.905 +	unsigned int PhyState;	/* state for the fix squelch algorithm */
   7.906 +	unsigned int PhyDelay;	/* delay for the fix squelch algorithm */
   7.907 +
   7.908 +	/* Lock defintions for the driver */
   7.909 +	spinlock_t bd_lock;		/* board lock */
   7.910 +	spinlock_t bd_non_tx_lock;	/* Non transmit command lock  */
   7.911 +	spinlock_t config_lock;		/* config block lock */
   7.912 +	spinlock_t mdi_access_lock;	/* mdi lock */
   7.913 +
   7.914 +	struct timer_list watchdog_timer;	/* watchdog timer id */
   7.915 +
   7.916 +	/* non-tx commands parameters */
   7.917 +	struct timer_list nontx_timer_id;	/* non-tx timer id */
   7.918 +	struct list_head non_tx_cmd_list;
   7.919 +	non_tx_cmd_state_t non_tx_command_state;
   7.920 +	nxmit_cb_entry_t *same_cmd_entry[CB_MAX_NONTX_CMD];
   7.921 +
   7.922 +	enum next_cu_cmd_e next_cu_cmd;
   7.923 +
   7.924 +	/* Zero Locking Algorithm data members */
   7.925 +	enum zlock_state_e zlock_state;
   7.926 +	u8 zlock_read_data[16];	/* number of times each value 0-15 was read */
   7.927 +	u16 zlock_read_cnt;	/* counts number of reads */
   7.928 +	ulong zlock_sleep_cnt;	/* keeps track of "sleep" time */
   7.929 +
   7.930 +	u8 config[CB_CFIG_BYTE_COUNT + CB_CFIG_D102_BYTE_COUNT];
   7.931 +
   7.932 +	/* IFS params */
   7.933 +	u8 ifs_state;
   7.934 +	u8 ifs_value;
   7.935 +
   7.936 +	struct cfg_params params;	/* adapter's command line parameters */
   7.937 +
   7.938 +	u32 speed_duplex_caps;	/* adapter's speed/duplex capabilities */
   7.939 +
   7.940 +	/* WOL params for ethtool */
   7.941 +	u32 wolsupported;
   7.942 +	u32 wolopts;
   7.943 +	u16 ip_lbytes;
   7.944 +	struct ethtool_lpbk_data loopback;
   7.945 +	struct timer_list blink_timer;	/* led blink timer id */
   7.946 +
   7.947 +#ifdef CONFIG_PM
   7.948 +	u32 pci_state[16];
   7.949 +#endif
   7.950 +	char ifname[IFNAMSIZ];
   7.951 +#ifdef E100_CU_DEBUG	
   7.952 +	u8 last_cmd;
   7.953 +	u8 last_sub_cmd;
   7.954 +#endif	
   7.955 +};
   7.956 +
   7.957 +#define E100_AUTONEG        0
   7.958 +#define E100_SPEED_10_HALF  1
   7.959 +#define E100_SPEED_10_FULL  2
   7.960 +#define E100_SPEED_100_HALF 3
   7.961 +#define E100_SPEED_100_FULL 4
   7.962 +
   7.963 +/********* function prototypes *************/
   7.964 +extern void e100_isolate_driver(struct e100_private *bdp);
   7.965 +extern void e100_sw_reset(struct e100_private *bdp, u32 reset_cmd);
   7.966 +extern u8 e100_start_cu(struct e100_private *bdp, tcb_t *tcb);
   7.967 +extern void e100_free_non_tx_cmd(struct e100_private *bdp,
   7.968 +				 nxmit_cb_entry_t *non_tx_cmd);
   7.969 +extern nxmit_cb_entry_t *e100_alloc_non_tx_cmd(struct e100_private *bdp);
   7.970 +extern unsigned char e100_exec_non_cu_cmd(struct e100_private *bdp,
   7.971 +					  nxmit_cb_entry_t *cmd);
   7.972 +extern unsigned char e100_selftest(struct e100_private *bdp, u32 *st_timeout,
   7.973 +				   u32 *st_result);
   7.974 +extern unsigned char e100_get_link_state(struct e100_private *bdp);
   7.975 +extern unsigned char e100_wait_scb(struct e100_private *bdp);
   7.976 +
   7.977 +extern void e100_deisolate_driver(struct e100_private *bdp, u8 full_reset);
   7.978 +extern unsigned char e100_configure_device(struct e100_private *bdp);
   7.979 +#ifdef E100_CU_DEBUG
   7.980 +extern unsigned char e100_cu_unknown_state(struct e100_private *bdp);
   7.981 +#endif
   7.982 +
   7.983 +#define ROM_TEST_FAIL		0x01
   7.984 +#define REGISTER_TEST_FAIL	0x02
   7.985 +#define SELF_TEST_FAIL		0x04
   7.986 +#define TEST_TIMEOUT		0x08
   7.987 +
   7.988 +enum test_offsets {
   7.989 +	E100_EEPROM_TEST_FAIL = 0,
   7.990 +	E100_CHIP_TIMEOUT,
   7.991 +	E100_ROM_TEST_FAIL,
   7.992 +	E100_REG_TEST_FAIL,
   7.993 +	E100_MAC_TEST_FAIL,
   7.994 +	E100_LPBK_MAC_FAIL,
   7.995 +	E100_LPBK_PHY_FAIL,
   7.996 +	E100_MAX_TEST_RES
   7.997 +};
   7.998 +
   7.999 +#endif
     8.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     8.2 +++ b/xen/drivers/net/e100/e100_config.c	Thu Jul 10 08:57:37 2003 +0000
     8.3 @@ -0,0 +1,639 @@
     8.4 +/*******************************************************************************
     8.5 +
     8.6 +  
     8.7 +  Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
     8.8 +  
     8.9 +  This program is free software; you can redistribute it and/or modify it 
    8.10 +  under the terms of the GNU General Public License as published by the Free 
    8.11 +  Software Foundation; either version 2 of the License, or (at your option) 
    8.12 +  any later version.
    8.13 +  
    8.14 +  This program is distributed in the hope that it will be useful, but WITHOUT 
    8.15 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
    8.16 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
    8.17 +  more details.
    8.18 +  
    8.19 +  You should have received a copy of the GNU General Public License along with
    8.20 +  this program; if not, write to the Free Software Foundation, Inc., 59 
    8.21 +  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
    8.22 +  
    8.23 +  The full GNU General Public License is included in this distribution in the
    8.24 +  file called LICENSE.
    8.25 +  
    8.26 +  Contact Information:
    8.27 +  Linux NICS <linux.nics@intel.com>
    8.28 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
    8.29 +*******************************************************************************/
    8.30 +
    8.31 +/**********************************************************************
    8.32 +*                                                                     *
    8.33 +* INTEL CORPORATION                                                   *
    8.34 +*                                                                     *
    8.35 +* This software is supplied under the terms of the license included   *
    8.36 +* above.  All use of this driver must be in accordance with the terms *
    8.37 +* of that license.                                                    *
    8.38 +*                                                                     *
    8.39 +* Module Name:  e100_config.c                                         *
    8.40 +*                                                                     *
    8.41 +* Abstract:     Functions for configuring the network adapter.        *
    8.42 +*                                                                     *
    8.43 +* Environment:  This file is intended to be specific to the Linux     *
    8.44 +*               operating system.                                     *
    8.45 +*                                                                     *
    8.46 +**********************************************************************/
    8.47 +#include "e100_config.h"
    8.48 +
    8.49 +static void e100_config_long_rx(struct e100_private *bdp, unsigned char enable);
    8.50 +
    8.51 +static const u8 def_config[] = {
    8.52 +	CB_CFIG_BYTE_COUNT,
    8.53 +	0x08, 0x00, 0x00, 0x00, 0x00, 0x32, 0x07, 0x01,
    8.54 +	0x00, 0x2e, 0x00, 0x60, 0x00, 0xf2, 0xc8, 0x00,
    8.55 +	0x40, 0xf2, 0x80, 0x3f, 0x05
    8.56 +};
    8.57 +
    8.58 +/**
    8.59 + * e100_config_init_82557 - config the 82557 adapter
    8.60 + * @bdp: atapter's private data struct
    8.61 + *
    8.62 + * This routine will initialize the 82557 configure block.
    8.63 + * All other init functions will only set values that are
    8.64 + * different from the 82557 default.
    8.65 + */
    8.66 +static void __devinit
    8.67 +e100_config_init_82557(struct e100_private *bdp)
    8.68 +{
    8.69 +	/* initialize config block */
    8.70 +	memcpy(bdp->config, def_config, sizeof (def_config));
    8.71 +	bdp->config[0] = CB_CFIG_BYTE_COUNT;	/* just in case */
    8.72 +
    8.73 +	e100_config_ifs(bdp);
    8.74 +
    8.75 +	/*
    8.76 +	 * Enable extended statistical counters (82558 and up) and TCO counters
    8.77 +	 * (82559 and up) and set the statistical counters' mode in bdp 
    8.78 +	 *  
    8.79 +	 *  stat. mode      |    TCO stat. bit (2)  |  Extended stat. bit (5)
    8.80 +	 * ------------------------------------------------------------------
    8.81 +	 *  Basic (557)     |       0               |         1
    8.82 +	 * ------------------------------------------------------------------
    8.83 +	 *  Extended (558)  |       0               |         0
    8.84 +	 * ------------------------------------------------------------------
    8.85 +	 *  TCO (559)       |       1               |         1
    8.86 +	 * ------------------------------------------------------------------
    8.87 +	 *  Reserved        |       1               |         0
    8.88 +	 * ------------------------------------------------------------------
    8.89 +	 */
    8.90 +	bdp->config[6] &= ~CB_CFIG_TCO_STAT;
    8.91 +	bdp->config[6] |= CB_CFIG_EXT_STAT_DIS;
    8.92 +	bdp->stat_mode = E100_BASIC_STATS;
    8.93 +
    8.94 +	/* Setup for MII or 503 operation.  The CRS+CDT bit should only be set */
    8.95 +	/* when operating in 503 mode. */
    8.96 +	if (bdp->phy_addr == 32) {
    8.97 +		bdp->config[8] &= ~CB_CFIG_503_MII;
    8.98 +		bdp->config[15] |= CB_CFIG_CRS_OR_CDT;
    8.99 +	} else {
   8.100 +		bdp->config[8] |= CB_CFIG_503_MII;
   8.101 +		bdp->config[15] &= ~CB_CFIG_CRS_OR_CDT;
   8.102 +	}
   8.103 +
   8.104 +	e100_config_fc(bdp);
   8.105 +	e100_config_force_dplx(bdp);
   8.106 +	e100_config_promisc(bdp, false);
   8.107 +	e100_config_mulcast_enbl(bdp, false);
   8.108 +}
   8.109 +
   8.110 +static void __devinit
   8.111 +e100_config_init_82558(struct e100_private *bdp)
   8.112 +{
   8.113 +	/* MWI enable. This should be turned on only if the adapter is a 82558/9
   8.114 +	 * and if the PCI command reg. has enabled the MWI bit. */
   8.115 +	bdp->config[3] |= CB_CFIG_MWI_EN;
   8.116 +
   8.117 +	bdp->config[6] &= ~CB_CFIG_EXT_TCB_DIS;
   8.118 +
   8.119 +	if (bdp->rev_id >= D101MA_REV_ID) {
   8.120 +		/* this is 82559 and up - enable TCO counters */
   8.121 +		bdp->config[6] |= CB_CFIG_TCO_STAT;
   8.122 +		bdp->config[6] |= CB_CFIG_EXT_STAT_DIS;
   8.123 +		bdp->stat_mode = E100_TCO_STATS;
   8.124 +
   8.125 +		if ((bdp->rev_id < D102_REV_ID) &&
   8.126 +		    (bdp->params.b_params & PRM_XSUMRX) &&
   8.127 +		    (bdp->pdev->device != 0x1209)) {
   8.128 +
   8.129 +			bdp->flags |= DF_CSUM_OFFLOAD;
   8.130 +			bdp->config[9] |= 1;
   8.131 +		}
   8.132 +	} else {
   8.133 +		/* this is 82558 */
   8.134 +		bdp->config[6] &= ~CB_CFIG_TCO_STAT;
   8.135 +		bdp->config[6] &= ~CB_CFIG_EXT_STAT_DIS;
   8.136 +		bdp->stat_mode = E100_EXTENDED_STATS;
   8.137 +	}
   8.138 +
   8.139 +	e100_config_long_rx(bdp, true);
   8.140 +}
   8.141 +
   8.142 +static void __devinit
   8.143 +e100_config_init_82550(struct e100_private *bdp)
   8.144 +{
   8.145 +	/* The D102 chip allows for 32 config bytes.  This value is
   8.146 +	 * supposed to be in Byte 0.  Just add the extra bytes to
   8.147 +	 * what was already setup in the block. */
   8.148 +	bdp->config[0] += CB_CFIG_D102_BYTE_COUNT;
   8.149 +
   8.150 +	/* now we need to enable the extended RFD.  When this is
   8.151 +	 * enabled, the immediated receive data buffer starts at offset
   8.152 +	 * 32 from the RFD base address, instead of at offset 16. */
   8.153 +	bdp->config[7] |= CB_CFIG_EXTENDED_RFD;
   8.154 +
   8.155 +	/* put the chip into D102 receive mode.  This is necessary
   8.156 +	 * for any parsing and offloading features. */
   8.157 +	bdp->config[22] = CB_CFIG_RECEIVE_GAMLA_MODE;
   8.158 +
   8.159 +	/* set the flag if checksum offloading was enabled */
   8.160 +	if (bdp->params.b_params & PRM_XSUMRX) {
   8.161 +		bdp->flags |= DF_CSUM_OFFLOAD;
   8.162 +	}
   8.163 +}
   8.164 +
   8.165 +/* Initialize the adapter's configure block */
   8.166 +void __devinit
   8.167 +e100_config_init(struct e100_private *bdp)
   8.168 +{
   8.169 +	e100_config_init_82557(bdp);
   8.170 +
   8.171 +	if (bdp->flags & IS_BACHELOR)
   8.172 +		e100_config_init_82558(bdp);
   8.173 +
   8.174 +	if (bdp->rev_id >= D102_REV_ID)
   8.175 +		e100_config_init_82550(bdp);
   8.176 +}
   8.177 +
   8.178 +/**
   8.179 + * e100_force_config - force a configure command
   8.180 + * @bdp: atapter's private data struct
   8.181 + *
   8.182 + * This routine will force a configure command to the adapter.
   8.183 + * The command will be executed in polled mode as interrupts
   8.184 + * are _disabled_ at this time.
   8.185 + *
   8.186 + * Returns:
   8.187 + *      true: if the configure command was successfully issued and completed
   8.188 + *      false: otherwise
   8.189 + */
   8.190 +unsigned char
   8.191 +e100_force_config(struct e100_private *bdp)
   8.192 +{
   8.193 +	spin_lock_bh(&(bdp->config_lock));
   8.194 +
   8.195 +	bdp->config[0] = CB_CFIG_BYTE_COUNT;
   8.196 +	if (bdp->rev_id >= D102_REV_ID) {
   8.197 +		/* The D102 chip allows for 32 config bytes.  This value is
   8.198 +		   supposed to be in Byte 0.  Just add the extra bytes to
   8.199 +		   what was already setup in the block. */
   8.200 +		bdp->config[0] += CB_CFIG_D102_BYTE_COUNT;
   8.201 +	}
   8.202 +
   8.203 +	spin_unlock_bh(&(bdp->config_lock));
   8.204 +
   8.205 +	// although we call config outside the lock, there is no
   8.206 +	// race condition because config byte count has maximum value
   8.207 +	return e100_config(bdp);
   8.208 +}
   8.209 +
   8.210 +/**
   8.211 + * e100_config - issue a configure command
   8.212 + * @bdp: atapter's private data struct
   8.213 + *
   8.214 + * This routine will issue a configure command to the 82557.
   8.215 + * This command will be executed in polled mode as interrupts
   8.216 + * are _disabled_ at this time.
   8.217 + *
   8.218 + * Returns:
   8.219 + *      true: if the configure command was successfully issued and completed
   8.220 + *      false: otherwise
   8.221 + */
   8.222 +unsigned char
   8.223 +e100_config(struct e100_private *bdp)
   8.224 +{
   8.225 +	cb_header_t *pntcb_hdr;
   8.226 +	unsigned char res = true;
   8.227 +	nxmit_cb_entry_t *cmd;
   8.228 +
   8.229 +	if (bdp->config[0] == 0) {
   8.230 +		goto exit;
   8.231 +	}
   8.232 +
   8.233 +	if ((cmd = e100_alloc_non_tx_cmd(bdp)) == NULL) {
   8.234 +		res = false;
   8.235 +		goto exit;
   8.236 +	}
   8.237 +
   8.238 +	pntcb_hdr = (cb_header_t *) cmd->non_tx_cmd;
   8.239 +	pntcb_hdr->cb_cmd = __constant_cpu_to_le16(CB_CONFIGURE);
   8.240 +
   8.241 +	spin_lock_bh(&bdp->config_lock);
   8.242 +
   8.243 +	if (bdp->config[0] < CB_CFIG_MIN_PARAMS) {
   8.244 +		bdp->config[0] = CB_CFIG_MIN_PARAMS;
   8.245 +	}
   8.246 +
   8.247 +	/* Copy the device's config block to the device's memory */
   8.248 +	memcpy(cmd->non_tx_cmd->ntcb.config.cfg_byte, bdp->config,
   8.249 +	       bdp->config[0]);
   8.250 +	/* reset number of bytes to config next time */
   8.251 +	bdp->config[0] = 0;
   8.252 +
   8.253 +	spin_unlock_bh(&bdp->config_lock);
   8.254 +
   8.255 +	res = e100_exec_non_cu_cmd(bdp, cmd);
   8.256 +
   8.257 +exit:
   8.258 +	if (netif_running(bdp->device))
   8.259 +		netif_wake_queue(bdp->device);
   8.260 +	return res;
   8.261 +}
   8.262 +
   8.263 +/**
   8.264 + * e100_config_fc - config flow-control state
   8.265 + * @bdp: adapter's private data struct
   8.266 + *
   8.267 + * This routine will enable or disable flow control support in the adapter's
   8.268 + * config block. Flow control will be enable only if requested using the command
   8.269 + * line option, and if the link is flow-contorl capable (both us and the link
   8.270 + * partner). But, if link partner is capable of autoneg, but not capable of
   8.271 + * flow control, received PAUSE	frames are still honored.
   8.272 + */
   8.273 +void
   8.274 +e100_config_fc(struct e100_private *bdp)
   8.275 +{
   8.276 +	unsigned char enable = false;
   8.277 +	/* 82557 doesn't support fc. Don't touch this option */
   8.278 +	if (!(bdp->flags & IS_BACHELOR))
   8.279 +		return;
   8.280 +
   8.281 +	/* Enable fc if requested and if the link supports it */
   8.282 +	if ((bdp->params.b_params & PRM_FC) && (bdp->flags & 
   8.283 +		(DF_LINK_FC_CAP | DF_LINK_FC_TX_ONLY))) {
   8.284 +		enable = true;
   8.285 +	}
   8.286 +
   8.287 +	spin_lock_bh(&(bdp->config_lock));
   8.288 +
   8.289 +	if (enable) {
   8.290 +		if (bdp->flags & DF_LINK_FC_TX_ONLY) {
   8.291 +			/* If link partner is capable of autoneg, but  */
   8.292 +			/* not capable of flow control, Received PAUSE */
   8.293 +			/* frames are still honored, i.e.,             */
   8.294 +			/* transmitted frames would be paused by       */
   8.295 +			/* incoming PAUSE frames                       */
   8.296 +			bdp->config[16] = DFLT_NO_FC_DELAY_LSB;
   8.297 +			bdp->config[17] = DFLT_NO_FC_DELAY_MSB;
   8.298 +			bdp->config[19] &= ~(CB_CFIG_FC_RESTOP | CB_CFIG_FC_RESTART);
   8.299 +			bdp->config[19] |= CB_CFIG_FC_REJECT;
   8.300 +			bdp->config[19] &= ~CB_CFIG_TX_FC_DIS;
   8.301 +		} else {
   8.302 +			bdp->config[16] = DFLT_FC_DELAY_LSB;
   8.303 +			bdp->config[17] = DFLT_FC_DELAY_MSB;
   8.304 +			bdp->config[19] |= CB_CFIG_FC_OPTS;
   8.305 +			bdp->config[19] &= ~CB_CFIG_TX_FC_DIS;
   8.306 +		}
   8.307 +	} else {
   8.308 +		bdp->config[16] = DFLT_NO_FC_DELAY_LSB;
   8.309 +		bdp->config[17] = DFLT_NO_FC_DELAY_MSB;
   8.310 +		bdp->config[19] &= ~CB_CFIG_FC_OPTS;
   8.311 +		bdp->config[19] |= CB_CFIG_TX_FC_DIS;
   8.312 +	}
   8.313 +	E100_CONFIG(bdp, 19);
   8.314 +	spin_unlock_bh(&(bdp->config_lock));
   8.315 +
   8.316 +	return;
   8.317 +}
   8.318 +
   8.319 +/**
   8.320 + * e100_config_promisc - configure promiscuous mode
   8.321 + * @bdp: atapter's private data struct
   8.322 + * @enable: should we enable this option or not
   8.323 + *
   8.324 + * This routine will enable or disable promiscuous mode
   8.325 + * in the adapter's config block.
   8.326 + */
   8.327 +void
   8.328 +e100_config_promisc(struct e100_private *bdp, unsigned char enable)
   8.329 +{
   8.330 +	spin_lock_bh(&(bdp->config_lock));
   8.331 +
   8.332 +	/* if in promiscuous mode, save bad frames */
   8.333 +	if (enable) {
   8.334 +
   8.335 +		if (!(bdp->config[6] & CB_CFIG_SAVE_BAD_FRAMES)) {
   8.336 +			bdp->config[6] |= CB_CFIG_SAVE_BAD_FRAMES;
   8.337 +			E100_CONFIG(bdp, 6);
   8.338 +		}
   8.339 +
   8.340 +		if (bdp->config[7] & (u8) BIT_0) {
   8.341 +			bdp->config[7] &= (u8) (~BIT_0);
   8.342 +			E100_CONFIG(bdp, 7);
   8.343 +		}
   8.344 +
   8.345 +		if (!(bdp->config[15] & CB_CFIG_PROMISCUOUS)) {
   8.346 +			bdp->config[15] |= CB_CFIG_PROMISCUOUS;
   8.347 +			E100_CONFIG(bdp, 15);
   8.348 +		}
   8.349 +
   8.350 +	} else {		/* not in promiscuous mode */
   8.351 +
   8.352 +		if (bdp->config[6] & CB_CFIG_SAVE_BAD_FRAMES) {
   8.353 +			bdp->config[6] &= ~CB_CFIG_SAVE_BAD_FRAMES;
   8.354 +			E100_CONFIG(bdp, 6);
   8.355 +		}
   8.356 +
   8.357 +		if (!(bdp->config[7] & (u8) BIT_0)) {
   8.358 +			bdp->config[7] |= (u8) (BIT_0);
   8.359 +			E100_CONFIG(bdp, 7);
   8.360 +		}
   8.361 +
   8.362 +		if (bdp->config[15] & CB_CFIG_PROMISCUOUS) {
   8.363 +			bdp->config[15] &= ~CB_CFIG_PROMISCUOUS;
   8.364 +			E100_CONFIG(bdp, 15);
   8.365 +		}
   8.366 +	}
   8.367 +
   8.368 +	spin_unlock_bh(&(bdp->config_lock));
   8.369 +}
   8.370 +
   8.371 +/**
   8.372 + * e100_config_mulcast_enbl - configure allmulti mode
   8.373 + * @bdp: atapter's private data struct
   8.374 + * @enable: should we enable this option or not
   8.375 + *
   8.376 + * This routine will enable or disable reception of all multicast packets
   8.377 + * in the adapter's config block.
   8.378 + */
   8.379 +void
   8.380 +e100_config_mulcast_enbl(struct e100_private *bdp, unsigned char enable)
   8.381 +{
   8.382 +	spin_lock_bh(&(bdp->config_lock));
   8.383 +
   8.384 +	/* this flag is used to enable receiving all multicast packet */
   8.385 +	if (enable) {
   8.386 +		if (!(bdp->config[21] & CB_CFIG_MULTICAST_ALL)) {
   8.387 +			bdp->config[21] |= CB_CFIG_MULTICAST_ALL;
   8.388 +			E100_CONFIG(bdp, 21);
   8.389 +		}
   8.390 +
   8.391 +	} else {
   8.392 +		if (bdp->config[21] & CB_CFIG_MULTICAST_ALL) {
   8.393 +			bdp->config[21] &= ~CB_CFIG_MULTICAST_ALL;
   8.394 +			E100_CONFIG(bdp, 21);
   8.395 +		}
   8.396 +	}
   8.397 +
   8.398 +	spin_unlock_bh(&(bdp->config_lock));
   8.399 +}
   8.400 +
   8.401 +/**
   8.402 + * e100_config_ifs - configure the IFS parameter
   8.403 + * @bdp: atapter's private data struct
   8.404 + *
   8.405 + * This routine will configure the adaptive IFS value
   8.406 + * in the adapter's config block. IFS values are only
   8.407 + * relevant in half duplex, so set to 0 in full duplex.
   8.408 + */
   8.409 +void
   8.410 +e100_config_ifs(struct e100_private *bdp)
   8.411 +{
   8.412 +	u8 value = 0;
   8.413 +
   8.414 +	spin_lock_bh(&(bdp->config_lock));
   8.415 +
   8.416 +	/* IFS value is only needed to be specified at half-duplex mode */
   8.417 +	if (bdp->cur_dplx_mode == HALF_DUPLEX) {
   8.418 +		value = (u8) bdp->ifs_value;
   8.419 +	}
   8.420 +
   8.421 +	if (bdp->config[2] != value) {
   8.422 +		bdp->config[2] = value;
   8.423 +		E100_CONFIG(bdp, 2);
   8.424 +	}
   8.425 +
   8.426 +	spin_unlock_bh(&(bdp->config_lock));
   8.427 +}
   8.428 +
   8.429 +/**
   8.430 + * e100_config_force_dplx - configure the forced full duplex mode
   8.431 + * @bdp: atapter's private data struct
   8.432 + *
   8.433 + * This routine will enable or disable force full duplex
   8.434 + * in the adapter's config block. If the PHY is 503, and
   8.435 + * the duplex is full, consider the adapter forced.
   8.436 + */
   8.437 +void
   8.438 +e100_config_force_dplx(struct e100_private *bdp)
   8.439 +{
   8.440 +	spin_lock_bh(&(bdp->config_lock));
   8.441 +
   8.442 +	/* We must force full duplex on if we are using PHY 0, and we are */
   8.443 +	/* supposed to run in FDX mode. We do this because the e100 has only */
   8.444 +	/* one FDX# input pin, and that pin will be connected to PHY 1. */
   8.445 +	/* Changed the 'if' condition below to fix performance problem * at 10
   8.446 +	 * full. The Phy was getting forced to full duplex while the MAC * was
   8.447 +	 * not, because the cur_dplx_mode was not being set to 2 by SetupPhy. *
   8.448 +	 * This is how the condition was, initially. * This has been changed so
   8.449 +	 * that the MAC gets forced to full duplex * simply if the user has
   8.450 +	 * forced full duplex. * * if (( bdp->phy_addr == 0 ) && (
   8.451 +	 * bdp->cur_dplx_mode == 2 )) */
   8.452 +	/* The rest of the fix is in the PhyDetect code. */
   8.453 +	if ((bdp->params.e100_speed_duplex == E100_SPEED_10_FULL) ||
   8.454 +	    (bdp->params.e100_speed_duplex == E100_SPEED_100_FULL) ||
   8.455 +	    ((bdp->phy_addr == 32) && (bdp->cur_dplx_mode == FULL_DUPLEX))) {
   8.456 +		if (!(bdp->config[19] & (u8) CB_CFIG_FORCE_FDX)) {
   8.457 +			bdp->config[19] |= (u8) CB_CFIG_FORCE_FDX;
   8.458 +			E100_CONFIG(bdp, 19);
   8.459 +		}
   8.460 +
   8.461 +	} else {
   8.462 +		if (bdp->config[19] & (u8) CB_CFIG_FORCE_FDX) {
   8.463 +			bdp->config[19] &= (u8) (~CB_CFIG_FORCE_FDX);
   8.464 +			E100_CONFIG(bdp, 19);
   8.465 +		}
   8.466 +	}
   8.467 +
   8.468 +	spin_unlock_bh(&(bdp->config_lock));
   8.469 +}
   8.470 +
   8.471 +/**
   8.472 + * e100_config_long_rx
   8.473 + * @bdp: atapter's private data struct
   8.474 + * @enable: should we enable this option or not
   8.475 + *
   8.476 + * This routine will enable or disable reception of larger packets.
   8.477 + * This is needed by VLAN implementations.
   8.478 + */
   8.479 +static void
   8.480 +e100_config_long_rx(struct e100_private *bdp, unsigned char enable)
   8.481 +{
   8.482 +	if (enable) {
   8.483 +		if (!(bdp->config[18] & CB_CFIG_LONG_RX_OK)) {
   8.484 +			bdp->config[18] |= CB_CFIG_LONG_RX_OK;
   8.485 +			E100_CONFIG(bdp, 18);
   8.486 +		}
   8.487 +
   8.488 +	} else {
   8.489 +		if ((bdp->config[18] & CB_CFIG_LONG_RX_OK)) {
   8.490 +			bdp->config[18] &= ~CB_CFIG_LONG_RX_OK;
   8.491 +			E100_CONFIG(bdp, 18);
   8.492 +		}
   8.493 +	}
   8.494 +}
   8.495 +
   8.496 +/**
   8.497 + * e100_config_wol
   8.498 + * @bdp: atapter's private data struct
   8.499 + *
   8.500 + * This sets configuration options for PHY and Magic Packet WoL 
   8.501 + */
   8.502 +void
   8.503 +e100_config_wol(struct e100_private *bdp)
   8.504 +{
   8.505 +	spin_lock_bh(&(bdp->config_lock));
   8.506 +
   8.507 +	if (bdp->wolopts & WAKE_PHY) {
   8.508 +		bdp->config[9] |= CB_LINK_STATUS_WOL;
   8.509 +	}
   8.510 +	else {
   8.511 +		/* Disable PHY WoL */
   8.512 +		bdp->config[9] &= ~CB_LINK_STATUS_WOL;
   8.513 +	}
   8.514 +
   8.515 +	if (bdp->wolopts & WAKE_MAGIC) {
   8.516 +		bdp->config[19] &= ~CB_DISABLE_MAGPAK_WAKE;
   8.517 +	}
   8.518 +	else {
   8.519 +		/* Disable Magic Packet WoL */
   8.520 +		bdp->config[19] |= CB_DISABLE_MAGPAK_WAKE;
   8.521 +	}
   8.522 +
   8.523 +	E100_CONFIG(bdp, 19);
   8.524 +	spin_unlock_bh(&(bdp->config_lock));
   8.525 +}
   8.526 +
   8.527 +void
   8.528 +e100_config_vlan_drop(struct e100_private *bdp, unsigned char enable)
   8.529 +{
   8.530 +	spin_lock_bh(&(bdp->config_lock));
   8.531 +	if (enable) {
   8.532 +		if (!(bdp->config[22] & CB_CFIG_VLAN_DROP_ENABLE)) {
   8.533 +			bdp->config[22] |= CB_CFIG_VLAN_DROP_ENABLE;
   8.534 +			E100_CONFIG(bdp, 22);
   8.535 +		}
   8.536 +
   8.537 +	} else {
   8.538 +		if ((bdp->config[22] & CB_CFIG_VLAN_DROP_ENABLE)) {
   8.539 +			bdp->config[22] &= ~CB_CFIG_VLAN_DROP_ENABLE;
   8.540 +			E100_CONFIG(bdp, 22);
   8.541 +		}
   8.542 +	}
   8.543 +	spin_unlock_bh(&(bdp->config_lock));
   8.544 +}
   8.545 +
   8.546 +/**
   8.547 + * e100_config_loopback_mode
   8.548 + * @bdp: atapter's private data struct
   8.549 + * @mode: loopback mode(phy/mac/none)
   8.550 + *
   8.551 + */
   8.552 +unsigned char
   8.553 +e100_config_loopback_mode(struct e100_private *bdp, u8 mode)
   8.554 +{
   8.555 +	unsigned char bc_changed = false;
   8.556 +	u8 config_byte;
   8.557 +
   8.558 +	spin_lock_bh(&(bdp->config_lock));
   8.559 +
   8.560 +	switch (mode) {
   8.561 +	case NO_LOOPBACK:
   8.562 +		config_byte = CB_CFIG_LOOPBACK_NORMAL;
   8.563 +		break;
   8.564 +	case MAC_LOOPBACK:
   8.565 +		config_byte = CB_CFIG_LOOPBACK_INTERNAL;
   8.566 +		break;
   8.567 +	case PHY_LOOPBACK:
   8.568 +		config_byte = CB_CFIG_LOOPBACK_EXTERNAL;
   8.569 +		break;
   8.570 +	default:
   8.571 +		printk(KERN_NOTICE "e100: e100_config_loopback_mode: "
   8.572 +		       "Invalid argument 'mode': %d\n", mode);
   8.573 +		goto exit;
   8.574 +	}
   8.575 +
   8.576 +	if ((bdp->config[10] & CB_CFIG_LOOPBACK_MODE) != config_byte) {
   8.577 +
   8.578 +		bdp->config[10] &= (~CB_CFIG_LOOPBACK_MODE);
   8.579 +		bdp->config[10] |= config_byte;
   8.580 +		E100_CONFIG(bdp, 10);
   8.581 +		bc_changed = true;
   8.582 +	}
   8.583 +
   8.584 +exit:
   8.585 +	spin_unlock_bh(&(bdp->config_lock));
   8.586 +	return bc_changed;
   8.587 +}
   8.588 +unsigned char
   8.589 +e100_config_tcb_ext_enable(struct e100_private *bdp, unsigned char enable)
   8.590 +{
   8.591 +        unsigned char bc_changed = false;
   8.592 + 
   8.593 +        spin_lock_bh(&(bdp->config_lock));
   8.594 + 
   8.595 +        if (enable) {
   8.596 +                if (bdp->config[6] & CB_CFIG_EXT_TCB_DIS) {
   8.597 + 
   8.598 +                        bdp->config[6] &= (~CB_CFIG_EXT_TCB_DIS);
   8.599 +                        E100_CONFIG(bdp, 6);
   8.600 +                        bc_changed = true;
   8.601 +                }
   8.602 + 
   8.603 +        } else {
   8.604 +                if (!(bdp->config[6] & CB_CFIG_EXT_TCB_DIS)) {
   8.605 + 
   8.606 +                        bdp->config[6] |= CB_CFIG_EXT_TCB_DIS;
   8.607 +                        E100_CONFIG(bdp, 6);
   8.608 +                        bc_changed = true;
   8.609 +                }
   8.610 +        }
   8.611 +        spin_unlock_bh(&(bdp->config_lock));
   8.612 + 
   8.613 +        return bc_changed;
   8.614 +}
   8.615 +unsigned char
   8.616 +e100_config_dynamic_tbd(struct e100_private *bdp, unsigned char enable)
   8.617 +{
   8.618 +        unsigned char bc_changed = false;
   8.619 + 
   8.620 +        spin_lock_bh(&(bdp->config_lock));
   8.621 + 
   8.622 +        if (enable) {
   8.623 +                if (!(bdp->config[7] & CB_CFIG_DYNTBD_EN)) {
   8.624 + 
   8.625 +                        bdp->config[7] |= CB_CFIG_DYNTBD_EN;
   8.626 +                        E100_CONFIG(bdp, 7);
   8.627 +                        bc_changed = true;
   8.628 +                }
   8.629 + 
   8.630 +        } else {
   8.631 +                if (bdp->config[7] & CB_CFIG_DYNTBD_EN) {
   8.632 + 
   8.633 +                        bdp->config[7] &= (~CB_CFIG_DYNTBD_EN);
   8.634 +                        E100_CONFIG(bdp, 7);
   8.635 +                        bc_changed = true;
   8.636 +                }
   8.637 +        }
   8.638 +        spin_unlock_bh(&(bdp->config_lock));
   8.639 + 
   8.640 +        return bc_changed;
   8.641 +}
   8.642 +
     9.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     9.2 +++ b/xen/drivers/net/e100/e100_config.h	Thu Jul 10 08:57:37 2003 +0000
     9.3 @@ -0,0 +1,167 @@
     9.4 +/*******************************************************************************
     9.5 +
     9.6 +  
     9.7 +  Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
     9.8 +  
     9.9 +  This program is free software; you can redistribute it and/or modify it 
    9.10 +  under the terms of the GNU General Public License as published by the Free 
    9.11 +  Software Foundation; either version 2 of the License, or (at your option) 
    9.12 +  any later version.
    9.13 +  
    9.14 +  This program is distributed in the hope that it will be useful, but WITHOUT 
    9.15 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
    9.16 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
    9.17 +  more details.
    9.18 +  
    9.19 +  You should have received a copy of the GNU General Public License along with
    9.20 +  this program; if not, write to the Free Software Foundation, Inc., 59 
    9.21 +  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
    9.22 +  
    9.23 +  The full GNU General Public License is included in this distribution in the
    9.24 +  file called LICENSE.
    9.25 +  
    9.26 +  Contact Information:
    9.27 +  Linux NICS <linux.nics@intel.com>
    9.28 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
    9.29 +*******************************************************************************/
    9.30 +
    9.31 +#ifndef _E100_CONFIG_INC_
    9.32 +#define _E100_CONFIG_INC_
    9.33 +
    9.34 +#include "e100.h"
    9.35 +
    9.36 +#define E100_CONFIG(bdp, X) ((bdp)->config[0] = max_t(u8, (bdp)->config[0], (X)+1))
    9.37 +
    9.38 +#define CB_CFIG_MIN_PARAMS         8
    9.39 +
    9.40 +/* byte 0 bit definitions*/
    9.41 +#define CB_CFIG_BYTE_COUNT_MASK     BIT_0_5	/* Byte count occupies bit 5-0 */
    9.42 +
    9.43 +/* byte 1 bit definitions*/
    9.44 +#define CB_CFIG_RXFIFO_LIMIT_MASK   BIT_0_4	/* RxFifo limit mask */
    9.45 +#define CB_CFIG_TXFIFO_LIMIT_MASK   BIT_4_7	/* TxFifo limit mask */
    9.46 +
    9.47 +/* byte 2 bit definitions -- ADAPTIVE_IFS*/
    9.48 +
    9.49 +/* word 3 bit definitions -- RESERVED*/
    9.50 +/* Changed for 82558 enhancements */
    9.51 +/* byte 3 bit definitions */
    9.52 +#define CB_CFIG_MWI_EN      BIT_0	/* Enable MWI on PCI bus */
    9.53 +#define CB_CFIG_TYPE_EN     BIT_1	/* Type Enable */
    9.54 +#define CB_CFIG_READAL_EN   BIT_2	/* Enable Read Align */
    9.55 +#define CB_CFIG_TERMCL_EN   BIT_3	/* Cache line write  */
    9.56 +
    9.57 +/* byte 4 bit definitions*/
    9.58 +#define CB_CFIG_RX_MIN_DMA_MASK     BIT_0_6	/* Rx minimum DMA count mask */
    9.59 +
    9.60 +/* byte 5 bit definitions*/
    9.61 +#define CB_CFIG_TX_MIN_DMA_MASK BIT_0_6	/* Tx minimum DMA count mask */
    9.62 +#define CB_CFIG_DMBC_EN         BIT_7	/* Enable Tx/Rx min. DMA counts */
    9.63 +
    9.64 +/* Changed for 82558 enhancements */
    9.65 +/* byte 6 bit definitions*/
    9.66 +#define CB_CFIG_LATE_SCB           BIT_0	/* Update SCB After New Tx Start */
    9.67 +#define CB_CFIG_DIRECT_DMA_DIS     BIT_1	/* Direct DMA mode */
    9.68 +#define CB_CFIG_TNO_INT            BIT_2	/* Tx Not OK Interrupt */
    9.69 +#define CB_CFIG_TCO_STAT           BIT_2	/* TCO statistics in 559 and above */
    9.70 +#define CB_CFIG_CI_INT             BIT_3	/* Command Complete Interrupt */
    9.71 +#define CB_CFIG_EXT_TCB_DIS        BIT_4	/* Extended TCB */
    9.72 +#define CB_CFIG_EXT_STAT_DIS       BIT_5	/* Extended Stats */
    9.73 +#define CB_CFIG_SAVE_BAD_FRAMES    BIT_7	/* Save Bad Frames Enabled */
    9.74 +
    9.75 +/* byte 7 bit definitions*/
    9.76 +#define CB_CFIG_DISC_SHORT_FRAMES   BIT_0	/* Discard Short Frames */
    9.77 +#define CB_CFIG_DYNTBD_EN           BIT_7	/* Enable dynamic TBD */
    9.78 +/* Enable extended RFD's on D102 */
    9.79 +#define CB_CFIG_EXTENDED_RFD        BIT_5
    9.80 +
    9.81 +/* byte 8 bit definitions*/
    9.82 +#define CB_CFIG_503_MII             BIT_0	/* 503 vs. MII mode */
    9.83 +
    9.84 +/* byte 9 bit definitions -- pre-defined all zeros*/
    9.85 +#define CB_LINK_STATUS_WOL	BIT_5
    9.86 +
    9.87 +/* byte 10 bit definitions*/
    9.88 +#define CB_CFIG_NO_SRCADR       BIT_3	/* No Source Address Insertion */
    9.89 +#define CB_CFIG_PREAMBLE_LEN    BIT_4_5	/* Preamble Length */
    9.90 +#define CB_CFIG_LOOPBACK_MODE   BIT_6_7	/* Loopback Mode */
    9.91 +#define CB_CFIG_LOOPBACK_NORMAL 0
    9.92 +#define CB_CFIG_LOOPBACK_INTERNAL BIT_6
    9.93 +#define CB_CFIG_LOOPBACK_EXTERNAL BIT_6_7
    9.94 +
    9.95 +/* byte 11 bit definitions*/
    9.96 +#define CB_CFIG_LINEAR_PRIORITY     BIT_0_2	/* Linear Priority */
    9.97 +
    9.98 +/* byte 12 bit definitions*/
    9.99 +#define CB_CFIG_LINEAR_PRI_MODE     BIT_0	/* Linear Priority mode */
   9.100 +#define CB_CFIG_IFS_MASK            BIT_4_7	/* Interframe Spacing mask */
   9.101 +
   9.102 +/* byte 13 bit definitions -- pre-defined all zeros*/
   9.103 +
   9.104 +/* byte 14 bit definitions -- pre-defined 0xf2*/
   9.105 +
   9.106 +/* byte 15 bit definitions*/
   9.107 +#define CB_CFIG_PROMISCUOUS         BIT_0	/* Promiscuous Mode Enable */
   9.108 +#define CB_CFIG_BROADCAST_DIS       BIT_1	/* Broadcast Mode Disable */
   9.109 +#define CB_CFIG_CRS_OR_CDT          BIT_7	/* CRS Or CDT */
   9.110 +
   9.111 +/* byte 16 bit definitions -- pre-defined all zeros*/
   9.112 +#define DFLT_FC_DELAY_LSB  0x1f	/* Delay for outgoing Pause frames */
   9.113 +#define DFLT_NO_FC_DELAY_LSB  0x00	/* no flow control default value */
   9.114 +
   9.115 +/* byte 17 bit definitions -- pre-defined 0x40*/
   9.116 +#define DFLT_FC_DELAY_MSB  0x01	/* Delay for outgoing Pause frames */
   9.117 +#define DFLT_NO_FC_DELAY_MSB  0x40	/* no flow control default value */
   9.118 +
   9.119 +/* byte 18 bit definitions*/
   9.120 +#define CB_CFIG_STRIPPING           BIT_0	/* Padding Disabled */
   9.121 +#define CB_CFIG_PADDING             BIT_1	/* Padding Disabled */
   9.122 +#define CB_CFIG_CRC_IN_MEM          BIT_2	/* Transfer CRC To Memory */
   9.123 +
   9.124 +/* byte 19 bit definitions*/
   9.125 +#define CB_CFIG_TX_ADDR_WAKE        BIT_0	/* Address Wakeup */
   9.126 +#define CB_DISABLE_MAGPAK_WAKE      BIT_1	/* Magic Packet Wakeup disable */
   9.127 +/* Changed TX_FC_EN to TX_FC_DIS because 0 enables, 1 disables. Jul 8, 1999 */
   9.128 +#define CB_CFIG_TX_FC_DIS           BIT_2	/* Tx Flow Control Disable */
   9.129 +#define CB_CFIG_FC_RESTOP           BIT_3	/* Rx Flow Control Restop */
   9.130 +#define CB_CFIG_FC_RESTART          BIT_4	/* Rx Flow Control Restart */
   9.131 +#define CB_CFIG_FC_REJECT           BIT_5	/* Rx Flow Control Restart */
   9.132 +#define CB_CFIG_FC_OPTS (CB_CFIG_FC_RESTOP | CB_CFIG_FC_RESTART | CB_CFIG_FC_REJECT)
   9.133 +
   9.134 +/* end 82558/9 specifics */
   9.135 +
   9.136 +#define CB_CFIG_FORCE_FDX           BIT_6	/* Force Full Duplex */
   9.137 +#define CB_CFIG_FDX_ENABLE          BIT_7	/* Full Duplex Enabled */
   9.138 +
   9.139 +/* byte 20 bit definitions*/
   9.140 +#define CB_CFIG_MULTI_IA            BIT_6	/* Multiple IA Addr */
   9.141 +
   9.142 +/* byte 21 bit definitions*/
   9.143 +#define CB_CFIG_MULTICAST_ALL       BIT_3	/* Multicast All */
   9.144 +
   9.145 +/* byte 22 bit defines */
   9.146 +#define CB_CFIG_RECEIVE_GAMLA_MODE  BIT_0	/* D102 receive mode */
   9.147 +#define CB_CFIG_VLAN_DROP_ENABLE    BIT_1	/* vlan stripping */
   9.148 +
   9.149 +#define CB_CFIG_LONG_RX_OK	    BIT_3
   9.150 +
   9.151 +#define NO_LOOPBACK	0	
   9.152 +#define MAC_LOOPBACK	0x01
   9.153 +#define PHY_LOOPBACK	0x02
   9.154 +
   9.155 +/* function prototypes */
   9.156 +extern void e100_config_init(struct e100_private *bdp);
   9.157 +extern unsigned char e100_force_config(struct e100_private *bdp);
   9.158 +extern unsigned char e100_config(struct e100_private *bdp);
   9.159 +extern void e100_config_fc(struct e100_private *bdp);
   9.160 +extern void e100_config_promisc(struct e100_private *bdp, unsigned char enable);
   9.161 +extern void e100_config_brdcast_dsbl(struct e100_private *bdp);
   9.162 +extern void e100_config_mulcast_enbl(struct e100_private *bdp,
   9.163 +				     unsigned char enable);
   9.164 +extern void e100_config_ifs(struct e100_private *bdp);
   9.165 +extern void e100_config_force_dplx(struct e100_private *bdp);
   9.166 +extern u8 e100_config_loopback_mode(struct e100_private *bdp, u8 mode);
   9.167 +extern u8 e100_config_dynamic_tbd(struct e100_private *bdp, u8 enable);
   9.168 +extern u8 e100_config_tcb_ext_enable(struct e100_private *bdp, u8 enable);
   9.169 +extern void e100_config_vlan_drop(struct e100_private *bdp, unsigned char enable);
   9.170 +#endif /* _E100_CONFIG_INC_ */
    10.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    10.2 +++ b/xen/drivers/net/e100/e100_eeprom.c	Thu Jul 10 08:57:37 2003 +0000
    10.3 @@ -0,0 +1,565 @@
    10.4 +/*******************************************************************************
    10.5 +
    10.6 +  
    10.7 +  Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
    10.8 +  
    10.9 +  This program is free software; you can redistribute it and/or modify it 
   10.10 +  under the terms of the GNU General Public License as published by the Free 
   10.11 +  Software Foundation; either version 2 of the License, or (at your option) 
   10.12 +  any later version.
   10.13 +  
   10.14 +  This program is distributed in the hope that it will be useful, but WITHOUT 
   10.15 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
   10.16 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
   10.17 +  more details.
   10.18 +  
   10.19 +  You should have received a copy of the GNU General Public License along with
   10.20 +  this program; if not, write to the Free Software Foundation, Inc., 59 
   10.21 +  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
   10.22 +  
   10.23 +  The full GNU General Public License is included in this distribution in the
   10.24 +  file called LICENSE.
   10.25 +  
   10.26 +  Contact Information:
   10.27 +  Linux NICS <linux.nics@intel.com>
   10.28 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
   10.29 +*******************************************************************************/
   10.30 +
   10.31 +/**********************************************************************
   10.32 +*                                                                     *
   10.33 +* INTEL CORPORATION                                                   *
   10.34 +*                                                                     *
   10.35 +* This software is supplied under the terms of the license included   *
   10.36 +* above.  All use of this driver must be in accordance with the terms *
   10.37 +* of that license.                                                    *
   10.38 +*                                                                     *
   10.39 +* Module Name:  e100_eeprom.c                                         *
   10.40 +*                                                                     *
   10.41 +* Abstract:     This module contains routines to read and write to a  *
   10.42 +*               serial EEPROM                                         *
   10.43 +*                                                                     *
   10.44 +* Environment:  This file is intended to be specific to the Linux     *
   10.45 +*               operating system.                                     *
   10.46 +*                                                                     *
   10.47 +**********************************************************************/
   10.48 +#include "e100.h"
   10.49 +
   10.50 +#define CSR_EEPROM_CONTROL_FIELD(bdp) ((bdp)->scb->scb_eprm_cntrl)
   10.51 +
   10.52 +#define CSR_GENERAL_CONTROL2_FIELD(bdp) \
   10.53 +	           ((bdp)->scb->scb_ext.d102_scb.scb_gen_ctrl2)
   10.54 +
   10.55 +#define EEPROM_STALL_TIME	4
   10.56 +#define EEPROM_CHECKSUM		((u16) 0xBABA)
   10.57 +#define EEPROM_MAX_WORD_SIZE	256
   10.58 +
   10.59 +void e100_eeprom_cleanup(struct e100_private *adapter);
   10.60 +u16 e100_eeprom_calculate_chksum(struct e100_private *adapter);
   10.61 +static void e100_eeprom_write_word(struct e100_private *adapter, u16 reg,
   10.62 +				   u16 data);
   10.63 +void e100_eeprom_write_block(struct e100_private *adapter, u16 start, u16 *data,
   10.64 +			     u16 size);
   10.65 +u16 e100_eeprom_size(struct e100_private *adapter);
   10.66 +u16 e100_eeprom_read(struct e100_private *adapter, u16 reg);
   10.67 +
   10.68 +static void shift_out_bits(struct e100_private *adapter, u16 data, u16 count);
   10.69 +static u16 shift_in_bits(struct e100_private *adapter);
   10.70 +static void raise_clock(struct e100_private *adapter, u16 *x);
   10.71 +static void lower_clock(struct e100_private *adapter, u16 *x);
   10.72 +static u16 eeprom_wait_cmd_done(struct e100_private *adapter);
   10.73 +static void eeprom_stand_by(struct e100_private *adapter);
   10.74 +
   10.75 +//----------------------------------------------------------------------------------------
   10.76 +// Procedure:   eeprom_set_semaphore
   10.77 +//
   10.78 +// Description: This function set (write 1) Gamla EEPROM semaphore bit (bit 23 word 0x1C in the CSR).
   10.79 +//
   10.80 +// Arguments:
   10.81 +//      Adapter                 - Adapter context
   10.82 +//
   10.83 +// Returns:  true if success
   10.84 +//           else return false 
   10.85 +//
   10.86 +//----------------------------------------------------------------------------------------
   10.87 +
   10.88 +inline u8
   10.89 +eeprom_set_semaphore(struct e100_private *adapter)
   10.90 +{
   10.91 +	u16 data = 0;
   10.92 +	unsigned long expiration_time = jiffies + HZ / 100 + 1;
   10.93 +
   10.94 +	do {
   10.95 +		// Get current value of General Control 2
   10.96 +		data = readb(&CSR_GENERAL_CONTROL2_FIELD(adapter));
   10.97 +
   10.98 +		// Set bit 23 word 0x1C in the CSR.
   10.99 +		data |= SCB_GCR2_EEPROM_ACCESS_SEMAPHORE;
  10.100 +		writeb(data, &CSR_GENERAL_CONTROL2_FIELD(adapter));
  10.101 +
  10.102 +		// Check to see if this bit set or not.
  10.103 +		data = readb(&CSR_GENERAL_CONTROL2_FIELD(adapter));
  10.104 +
  10.105 +		if (data & SCB_GCR2_EEPROM_ACCESS_SEMAPHORE) {
  10.106 +			return true;
  10.107 +		}
  10.108 +
  10.109 +		if (time_before(jiffies, expiration_time))
  10.110 +			yield();
  10.111 +		else
  10.112 +			return false;
  10.113 +
  10.114 +	} while (true);
  10.115 +}
  10.116 +
  10.117 +//----------------------------------------------------------------------------------------
  10.118 +// Procedure:   eeprom_reset_semaphore
  10.119 +//
  10.120 +// Description: This function reset (write 0) Gamla EEPROM semaphore bit 
  10.121 +//              (bit 23 word 0x1C in the CSR).
  10.122 +//
  10.123 +// Arguments:  struct e100_private * adapter - Adapter context
  10.124 +//----------------------------------------------------------------------------------------
  10.125 +
  10.126 +inline void
  10.127 +eeprom_reset_semaphore(struct e100_private *adapter)
  10.128 +{
  10.129 +	u16 data = 0;
  10.130 +
  10.131 +	data = readb(&CSR_GENERAL_CONTROL2_FIELD(adapter));
  10.132 +	data &= ~(SCB_GCR2_EEPROM_ACCESS_SEMAPHORE);
  10.133 +	writeb(data, &CSR_GENERAL_CONTROL2_FIELD(adapter));
  10.134 +}
  10.135 +
  10.136 +//----------------------------------------------------------------------------------------
  10.137 +// Procedure:   e100_eeprom_size
  10.138 +//
  10.139 +// Description: This routine determines the size of the EEPROM.  This value should be
  10.140 +//              checked for validity - ie. is it too big or too small.  The size returned
  10.141 +//              is then passed to the read/write functions.
  10.142 +//
  10.143 +// Returns:
  10.144 +//      Size of the eeprom, or zero if an error occurred
  10.145 +//----------------------------------------------------------------------------------------
  10.146 +u16
  10.147 +e100_eeprom_size(struct e100_private *adapter)
  10.148 +{
  10.149 +	u16 x, size = 1;	// must be one to accumulate a product
  10.150 +
  10.151 +	// if we've already stored this data, read from memory
  10.152 +	if (adapter->eeprom_size) {
  10.153 +		return adapter->eeprom_size;
  10.154 +	}
  10.155 +	// otherwise, read from the eeprom
  10.156 +	// Set EEPROM semaphore.
  10.157 +	if (adapter->rev_id >= D102_REV_ID) {
  10.158 +		if (!eeprom_set_semaphore(adapter))
  10.159 +			return 0;
  10.160 +	}
  10.161 +	// enable the eeprom by setting EECS.
  10.162 +	x = readw(&CSR_EEPROM_CONTROL_FIELD(adapter));
  10.163 +	x &= ~(EEDI | EEDO | EESK);
  10.164 +	x |= EECS;
  10.165 +	writew(x, &CSR_EEPROM_CONTROL_FIELD(adapter));
  10.166 +
  10.167 +	// write the read opcode
  10.168 +	shift_out_bits(adapter, EEPROM_READ_OPCODE, 3);
  10.169 +
  10.170 +	// experiment to discover the size of the eeprom.  request register zero
  10.171 +	// and wait for the eeprom to tell us it has accepted the entire address.
  10.172 +	x = readw(&CSR_EEPROM_CONTROL_FIELD(adapter));
  10.173 +	do {
  10.174 +		size *= 2;	// each bit of address doubles eeprom size
  10.175 +		x |= EEDO;	// set bit to detect "dummy zero"
  10.176 +		x &= ~EEDI;	// address consists of all zeros
  10.177 +
  10.178 +		writew(x, &CSR_EEPROM_CONTROL_FIELD(adapter));
  10.179 +		readw(&(adapter->scb->scb_status));
  10.180 +		udelay(EEPROM_STALL_TIME);
  10.181 +		raise_clock(adapter, &x);
  10.182 +		lower_clock(adapter, &x);
  10.183 +
  10.184 +		// check for "dummy zero"
  10.185 +		x = readw(&CSR_EEPROM_CONTROL_FIELD(adapter));
  10.186 +		if (size > EEPROM_MAX_WORD_SIZE) {
  10.187 +			size = 0;
  10.188 +			break;
  10.189 +		}
  10.190 +	} while (x & EEDO);
  10.191 +
  10.192 +	// read in the value requested
  10.193 +	(void) shift_in_bits(adapter);
  10.194 +	e100_eeprom_cleanup(adapter);
  10.195 +
  10.196 +	// Clear EEPROM Semaphore.
  10.197 +	if (adapter->rev_id >= D102_REV_ID) {
  10.198 +		eeprom_reset_semaphore(adapter);
  10.199 +	}
  10.200 +
  10.201 +	return size;
  10.202 +}
  10.203 +
  10.204 +//----------------------------------------------------------------------------------------
  10.205 +// Procedure:   eeprom_address_size
  10.206 +//
  10.207 +// Description: determines the number of bits in an address for the eeprom acceptable
  10.208 +//              values are 64, 128, and 256
  10.209 +// Arguments: size of the eeprom
  10.210 +// Returns: bits in an address for that size eeprom
  10.211 +//----------------------------------------------------------------------------------------
  10.212 +
  10.213 +static inline int
  10.214 +eeprom_address_size(u16 size)
  10.215 +{
  10.216 +	int isize = size;
  10.217 +	
  10.218 +	return (ffs(isize) - 1);
  10.219 +}
  10.220 +
  10.221 +//----------------------------------------------------------------------------------------
  10.222 +// Procedure:   e100_eeprom_read
  10.223 +//
  10.224 +// Description: This routine serially reads one word out of the EEPROM.
  10.225 +//
  10.226 +// Arguments:
  10.227 +//      adapter - our adapter context
  10.228 +//      reg - EEPROM word to read.
  10.229 +//
  10.230 +// Returns:
  10.231 +//      Contents of EEPROM word (reg).
  10.232 +//----------------------------------------------------------------------------------------
  10.233 +
  10.234 +u16
  10.235 +e100_eeprom_read(struct e100_private *adapter, u16 reg)
  10.236 +{
  10.237 +	u16 x, data, bits;
  10.238 +
  10.239 +	// Set EEPROM semaphore.
  10.240 +	if (adapter->rev_id >= D102_REV_ID) {
  10.241 +		if (!eeprom_set_semaphore(adapter))
  10.242 +			return 0;
  10.243 +	}
  10.244 +	// eeprom size is initialized to zero
  10.245 +	if (!adapter->eeprom_size)
  10.246 +		adapter->eeprom_size = e100_eeprom_size(adapter);
  10.247 +
  10.248 +	bits = eeprom_address_size(adapter->eeprom_size);
  10.249 +
  10.250 +	// select EEPROM, reset bits, set EECS
  10.251 +	x = readw(&CSR_EEPROM_CONTROL_FIELD(adapter));
  10.252 +
  10.253 +	x &= ~(EEDI | EEDO | EESK);
  10.254 +	x |= EECS;
  10.255 +	writew(x, &CSR_EEPROM_CONTROL_FIELD(adapter));
  10.256 +
  10.257 +	// write the read opcode and register number in that order
  10.258 +	// The opcode is 3bits in length, reg is 'bits' bits long
  10.259 +	shift_out_bits(adapter, EEPROM_READ_OPCODE, 3);
  10.260 +	shift_out_bits(adapter, reg, bits);
  10.261 +
  10.262 +	// Now read the data (16 bits) in from the selected EEPROM word
  10.263 +	data = shift_in_bits(adapter);
  10.264 +
  10.265 +	e100_eeprom_cleanup(adapter);
  10.266 +
  10.267 +	// Clear EEPROM Semaphore.
  10.268 +	if (adapter->rev_id >= D102_REV_ID) {
  10.269 +		eeprom_reset_semaphore(adapter);
  10.270 +	}
  10.271 +
  10.272 +	return data;
  10.273 +}
  10.274 +
  10.275 +//----------------------------------------------------------------------------------------
  10.276 +// Procedure:   shift_out_bits
  10.277 +//
  10.278 +// Description: This routine shifts data bits out to the EEPROM.
  10.279 +//
  10.280 +// Arguments:
  10.281 +//      data - data to send to the EEPROM.
  10.282 +//      count - number of data bits to shift out.
  10.283 +//
  10.284 +// Returns: (none)
  10.285 +//----------------------------------------------------------------------------------------
  10.286 +
  10.287 +static void
  10.288 +shift_out_bits(struct e100_private *adapter, u16 data, u16 count)
  10.289 +{
  10.290 +	u16 x, mask;
  10.291 +
  10.292 +	mask = 1 << (count - 1);
  10.293 +	x = readw(&CSR_EEPROM_CONTROL_FIELD(adapter));
  10.294 +	x &= ~(EEDO | EEDI);
  10.295 +
  10.296 +	do {
  10.297 +		x &= ~EEDI;
  10.298 +		if (data & mask)
  10.299 +			x |= EEDI;
  10.300 +
  10.301 +		writew(x, &CSR_EEPROM_CONTROL_FIELD(adapter));
  10.302 +		readw(&(adapter->scb->scb_status)); /* flush command to card */
  10.303 +		udelay(EEPROM_STALL_TIME);
  10.304 +		raise_clock(adapter, &x);
  10.305 +		lower_clock(adapter, &x);
  10.306 +		mask = mask >> 1;
  10.307 +	} while (mask);
  10.308 +
  10.309 +	x &= ~EEDI;
  10.310 +	writew(x, &CSR_EEPROM_CONTROL_FIELD(adapter));
  10.311 +}
  10.312 +
  10.313 +//----------------------------------------------------------------------------------------
  10.314 +// Procedure:   raise_clock
  10.315 +//
  10.316 +// Description: This routine raises the EEPROM's clock input (EESK)
  10.317 +//
  10.318 +// Arguments:
  10.319 +//      x - Ptr to the EEPROM control register's current value
  10.320 +//
  10.321 +// Returns: (none)
  10.322 +//----------------------------------------------------------------------------------------
  10.323 +
  10.324 +void
  10.325 +raise_clock(struct e100_private *adapter, u16 *x)
  10.326 +{
  10.327 +	*x = *x | EESK;
  10.328 +	writew(*x, &CSR_EEPROM_CONTROL_FIELD(adapter));
  10.329 +	readw(&(adapter->scb->scb_status)); /* flush command to card */
  10.330 +	udelay(EEPROM_STALL_TIME);
  10.331 +}
  10.332 +
  10.333 +//----------------------------------------------------------------------------------------
  10.334 +// Procedure:   lower_clock
  10.335 +//
  10.336 +// Description: This routine lower's the EEPROM's clock input (EESK)
  10.337 +//
  10.338 +// Arguments:
  10.339 +//      x - Ptr to the EEPROM control register's current value
  10.340 +//
  10.341 +// Returns: (none)
  10.342 +//----------------------------------------------------------------------------------------
  10.343 +
  10.344 +void
  10.345 +lower_clock(struct e100_private *adapter, u16 *x)
  10.346 +{
  10.347 +	*x = *x & ~EESK;
  10.348 +	writew(*x, &CSR_EEPROM_CONTROL_FIELD(adapter));
  10.349 +	readw(&(adapter->scb->scb_status)); /* flush command to card */
  10.350 +	udelay(EEPROM_STALL_TIME);
  10.351 +}
  10.352 +
  10.353 +//----------------------------------------------------------------------------------------
  10.354 +// Procedure:   shift_in_bits
  10.355 +//
  10.356 +// Description: This routine shifts data bits in from the EEPROM.
  10.357 +//
  10.358 +// Arguments:
  10.359 +//
  10.360 +// Returns:
  10.361 +//      The contents of that particular EEPROM word
  10.362 +//----------------------------------------------------------------------------------------
  10.363 +
  10.364 +static u16
  10.365 +shift_in_bits(struct e100_private *adapter)
  10.366 +{
  10.367 +	u16 x, d, i;
  10.368 +
  10.369 +	x = readw(&CSR_EEPROM_CONTROL_FIELD(adapter));
  10.370 +	x &= ~(EEDO | EEDI);
  10.371 +	d = 0;
  10.372 +
  10.373 +	for (i = 0; i < 16; i++) {
  10.374 +		d <<= 1;
  10.375 +		raise_clock(adapter, &x);
  10.376 +
  10.377 +		x = readw(&CSR_EEPROM_CONTROL_FIELD(adapter));
  10.378 +
  10.379 +		x &= ~EEDI;
  10.380 +		if (x & EEDO)
  10.381 +			d |= 1;
  10.382 +
  10.383 +		lower_clock(adapter, &x);
  10.384 +	}
  10.385 +
  10.386 +	return d;
  10.387 +}
  10.388 +
  10.389 +//----------------------------------------------------------------------------------------
  10.390 +// Procedure:   e100_eeprom_cleanup
  10.391 +//
  10.392 +// Description: This routine returns the EEPROM to an idle state
  10.393 +//----------------------------------------------------------------------------------------
  10.394 +
  10.395 +void
  10.396 +e100_eeprom_cleanup(struct e100_private *adapter)
  10.397 +{
  10.398 +	u16 x;
  10.399 +
  10.400 +	x = readw(&CSR_EEPROM_CONTROL_FIELD(adapter));
  10.401 +
  10.402 +	x &= ~(EECS | EEDI);
  10.403 +	writew(x, &CSR_EEPROM_CONTROL_FIELD(adapter));
  10.404 +
  10.405 +	raise_clock(adapter, &x);
  10.406 +	lower_clock(adapter, &x);
  10.407 +}
  10.408 +
  10.409 +//**********************************************************************************
  10.410 +// Procedure:   e100_eeprom_update_chksum
  10.411 +//
  10.412 +// Description: Calculates the checksum and writes it to the EEProm. 
  10.413 +//              It calculates the checksum accroding to the formula: 
  10.414 +//                              Checksum = 0xBABA - (sum of first 63 words).
  10.415 +//
  10.416 +//-----------------------------------------------------------------------------------
  10.417 +u16
  10.418 +e100_eeprom_calculate_chksum(struct e100_private *adapter)
  10.419 +{
  10.420 +	u16 idx, xsum_index, checksum = 0;
  10.421 +
  10.422 +	// eeprom size is initialized to zero
  10.423 +	if (!adapter->eeprom_size)
  10.424 +		adapter->eeprom_size = e100_eeprom_size(adapter);
  10.425 +
  10.426 +	xsum_index = adapter->eeprom_size - 1;
  10.427 +	for (idx = 0; idx < xsum_index; idx++)
  10.428 +		checksum += e100_eeprom_read(adapter, idx);
  10.429 +
  10.430 +	checksum = EEPROM_CHECKSUM - checksum;
  10.431 +	return checksum;
  10.432 +}
  10.433 +
  10.434 +//----------------------------------------------------------------------------------------
  10.435 +// Procedure:   e100_eeprom_write_word
  10.436 +//
  10.437 +// Description: This routine writes a word to a specific EEPROM location without.
  10.438 +//              taking EEPROM semaphore and updating checksum. 
  10.439 +//              Use e100_eeprom_write_block for the EEPROM update
  10.440 +// Arguments: reg - The EEPROM word that we are going to write to.
  10.441 +//            data - The data (word) that we are going to write to the EEPROM.
  10.442 +//----------------------------------------------------------------------------------------
  10.443 +static void
  10.444 +e100_eeprom_write_word(struct e100_private *adapter, u16 reg, u16 data)
  10.445 +{
  10.446 +	u16 x;
  10.447 +	u16 bits;
  10.448 +
  10.449 +	bits = eeprom_address_size(adapter->eeprom_size);
  10.450 +
  10.451 +	/* select EEPROM, mask off ASIC and reset bits, set EECS */
  10.452 +	x = readw(&CSR_EEPROM_CONTROL_FIELD(adapter));
  10.453 +	x &= ~(EEDI | EEDO | EESK);
  10.454 +	writew(x, &CSR_EEPROM_CONTROL_FIELD(adapter));
  10.455 +	readw(&(adapter->scb->scb_status)); /* flush command to card */
  10.456 +	udelay(EEPROM_STALL_TIME);
  10.457 +	x |= EECS;
  10.458 +	writew(x, &CSR_EEPROM_CONTROL_FIELD(adapter));
  10.459 +
  10.460 +	shift_out_bits(adapter, EEPROM_EWEN_OPCODE, 5);
  10.461 +	shift_out_bits(adapter, reg, (u16) (bits - 2));
  10.462 +	if (!eeprom_wait_cmd_done(adapter))
  10.463 +		return;
  10.464 +
  10.465 +	/* write the new word to the EEPROM & send the write opcode the EEPORM */
  10.466 +	shift_out_bits(adapter, EEPROM_WRITE_OPCODE, 3);
  10.467 +
  10.468 +	/* select which word in the EEPROM that we are writing to */
  10.469 +	shift_out_bits(adapter, reg, bits);
  10.470 +
  10.471 +	/* write the data to the selected EEPROM word */
  10.472 +	shift_out_bits(adapter, data, 16);
  10.473 +	if (!eeprom_wait_cmd_done(adapter))
  10.474 +		return;
  10.475 +
  10.476 +	shift_out_bits(adapter, EEPROM_EWDS_OPCODE, 5);
  10.477 +	shift_out_bits(adapter, reg, (u16) (bits - 2));
  10.478 +	if (!eeprom_wait_cmd_done(adapter))
  10.479 +		return;
  10.480 +
  10.481 +	e100_eeprom_cleanup(adapter);
  10.482 +}
  10.483 +
  10.484 +//----------------------------------------------------------------------------------------
  10.485 +// Procedure:   e100_eeprom_write_block
  10.486 +//
  10.487 +// Description: This routine writes a block of words starting from specified EEPROM 
  10.488 +//              location and updates checksum
  10.489 +// Arguments: reg - The EEPROM word that we are going to write to.
  10.490 +//            data - The data (word) that we are going to write to the EEPROM.
  10.491 +//----------------------------------------------------------------------------------------
  10.492 +void
  10.493 +e100_eeprom_write_block(struct e100_private *adapter, u16 start, u16 *data,
  10.494 +			u16 size)
  10.495 +{
  10.496 +	u16 checksum;
  10.497 +	u16 i;
  10.498 +
  10.499 +	if (!adapter->eeprom_size)
  10.500 +		adapter->eeprom_size = e100_eeprom_size(adapter);
  10.501 +
  10.502 +	// Set EEPROM semaphore.
  10.503 +	if (adapter->rev_id >= D102_REV_ID) {
  10.504 +		if (!eeprom_set_semaphore(adapter))
  10.505 +			return;
  10.506 +	}
  10.507 +
  10.508 +	for (i = 0; i < size; i++) {
  10.509 +		e100_eeprom_write_word(adapter, start + i, data[i]);
  10.510 +	}
  10.511 +	//Update checksum
  10.512 +	checksum = e100_eeprom_calculate_chksum(adapter);
  10.513 +	e100_eeprom_write_word(adapter, (adapter->eeprom_size - 1), checksum);
  10.514 +
  10.515 +	// Clear EEPROM Semaphore.
  10.516 +	if (adapter->rev_id >= D102_REV_ID) {
  10.517 +		eeprom_reset_semaphore(adapter);
  10.518 +	}
  10.519 +}
  10.520 +
  10.521 +//----------------------------------------------------------------------------------------
  10.522 +// Procedure:   eeprom_wait_cmd_done
  10.523 +//
  10.524 +// Description: This routine waits for the the EEPROM to finish its command.  
  10.525 +//                              Specifically, it waits for EEDO (data out) to go high.
  10.526 +// Returns:     true - If the command finished
  10.527 +//              false - If the command never finished (EEDO stayed low)
  10.528 +//----------------------------------------------------------------------------------------
  10.529 +static u16
  10.530 +eeprom_wait_cmd_done(struct e100_private *adapter)
  10.531 +{
  10.532 +	u16 x;
  10.533 +	unsigned long expiration_time = jiffies + HZ / 100 + 1;
  10.534 +
  10.535 +	eeprom_stand_by(adapter);
  10.536 +
  10.537 +	do {
  10.538 +		rmb();
  10.539 +		x = readw(&CSR_EEPROM_CONTROL_FIELD(adapter));
  10.540 +		if (x & EEDO)
  10.541 +			return true;
  10.542 +		if (time_before(jiffies, expiration_time))
  10.543 +			yield();
  10.544 +		else
  10.545 +			return false;
  10.546 +	} while (true);
  10.547 +}
  10.548 +
  10.549 +//----------------------------------------------------------------------------------------
  10.550 +// Procedure:   eeprom_stand_by
  10.551 +//
  10.552 +// Description: This routine lowers the EEPROM chip select (EECS) for a few microseconds.
  10.553 +//----------------------------------------------------------------------------------------
  10.554 +static void
  10.555 +eeprom_stand_by(struct e100_private *adapter)
  10.556 +{
  10.557 +	u16 x;
  10.558 +
  10.559 +	x = readw(&CSR_EEPROM_CONTROL_FIELD(adapter));
  10.560 +	x &= ~(EECS | EESK);
  10.561 +	writew(x, &CSR_EEPROM_CONTROL_FIELD(adapter));
  10.562 +	readw(&(adapter->scb->scb_status)); /* flush command to card */
  10.563 +	udelay(EEPROM_STALL_TIME);
  10.564 +	x |= EECS;
  10.565 +	writew(x, &CSR_EEPROM_CONTROL_FIELD(adapter));
  10.566 +	readw(&(adapter->scb->scb_status)); /* flush command to card */
  10.567 +	udelay(EEPROM_STALL_TIME);
  10.568 +}
    11.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    11.2 +++ b/xen/drivers/net/e100/e100_main.c	Thu Jul 10 08:57:37 2003 +0000
    11.3 @@ -0,0 +1,4236 @@
    11.4 +/*******************************************************************************
    11.5 +
    11.6 +  
    11.7 +  Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
    11.8 +  
    11.9 +  This program is free software; you can redistribute it and/or modify it 
   11.10 +  under the terms of the GNU General Public License as published by the Free 
   11.11 +  Software Foundation; either version 2 of the License, or (at your option) 
   11.12 +  any later version.
   11.13 +  
   11.14 +  This program is distributed in the hope that it will be useful, but WITHOUT 
   11.15 +  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
   11.16 +  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
   11.17 +  more details.
   11.18 +  
   11.19 +  You should have received a copy of the GNU General Public License along with
   11.20 +  this program; if not, write to the Free Software Foundation, Inc., 59 
   11.21 +  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
   11.22 +  
   11.23 +  The full GNU General Public License is included in this distribution in the
   11.24 +  file called LICENSE.
   11.25 +  
   11.26 +  Contact Information:
   11.27 +  Linux NICS <linux.nics@intel.com>
   11.28 +  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
   11.29 +*******************************************************************************/
   11.30 +
   11.31 +/**********************************************************************
   11.32 +*                                                                     *
   11.33 +* INTEL CORPORATION                                                   *
   11.34 +*                                                                     *
   11.35 +* This software is supplied under the terms of the license included   *
   11.36 +* above.  All use of this driver must be in accordance with the terms *
   11.37 +* of that license.                                                    *
   11.38 +*                                                                     *
   11.39 +* Module Name:  e100_main.c                                           *
   11.40 +*                                                                     *
   11.41 +* Abstract:     Functions for the driver entry points like load,      *
   11.42 +*               unload, open and close. All board specific calls made *
   11.43 +*               by the network interface section of the driver.       *
   11.44 +*                                                                     *
   11.45 +* Environment:  This file is intended to be specific to the Linux     *
   11.46 +*               operating system.                                     *
   11.47 +*                                                                     *
   11.48 +**********************************************************************/
   11.49 +
   11.50 +/* Change Log
   11.51 + * 
   11.52 + * 2.2.21	02/11/03
   11.53 + * o Removed marketing brand strings. Instead, Using generic string 
   11.54 + *   "Intel(R) PRO/100 Network Connection" for all adapters.
   11.55 + * o Implemented ethtool -S option
   11.56 + * o Strip /proc/net/PRO_LAN_Adapters files for kernel driver
   11.57 + * o Bug fix: Read wrong byte in EEPROM when offset is odd number
   11.58 + * o Bug fix: PHY loopback test fails on ICH devices
   11.59 + * o Bug fix: System panic on e100_close when repeating Hot Remove and 
   11.60 + *   Add in a team
   11.61 + * o Bug fix: Linux Bonding driver claims adapter's link loss because of
   11.62 + *   not updating last_rx field
   11.63 + * o Bug fix: e100 does not check validity of MAC address
   11.64 + * o New feature: added ICH5 support
   11.65 + * 
   11.66 + * 2.1.27	11/20/02
   11.67 + *   o Bug fix: Device command timeout due to SMBus processing during init
   11.68 + *   o Bug fix: Not setting/clearing I (Interrupt) bit in tcb correctly
   11.69 + *   o Bug fix: Not using EEPROM WoL setting as default in ethtool
   11.70 + *   o Bug fix: Not able to set autoneg on using ethtool when interface down
   11.71 + *   o Bug fix: Not able to change speed/duplex using ethtool/mii
   11.72 + *     when interface up
   11.73 + *   o Bug fix: Ethtool shows autoneg on when forced to 100/Full
   11.74 + *   o Bug fix: Compiler error when CONFIG_PROC_FS not defined
   11.75 + *   o Bug fix: 2.5.44 e100 doesn't load with preemptive kernel enabled
   11.76 + *     (sleep while holding spinlock)
   11.77 + *   o Bug fix: 2.1.24-k1 doesn't display complete statistics
   11.78 + *   o Bug fix: System panic due to NULL watchdog timer dereference during
   11.79 + *     ifconfig down, rmmod and insmod
   11.80 + *
   11.81 + * 2.1.24       10/7/02
   11.82 + */
   11.83 + 
   11.84 +#include <linux/config.h>
   11.85 +/*#include <net/checksum.h>*/
   11.86 +/*#include <linux/tcp.h>*/
   11.87 +/*#include <linux/udp.h>*/
   11.88 +#include "e100.h"
   11.89 +#include "e100_ucode.h"
   11.90 +#include "e100_config.h"
   11.91 +#include "e100_phy.h"
   11.92 +
   11.93 +extern void e100_force_speed_duplex_to_phy(struct e100_private *bdp);
   11.94 +
   11.95 +#if 0
   11.96 +static char e100_gstrings_stats[][ETH_GSTRING_LEN] = {
   11.97 +	"rx_packets", "tx_packets", "rx_bytes", "tx_bytes", "rx_errors",
   11.98 +	"tx_errors", "rx_dropped", "tx_dropped", "multicast", "collisions",
   11.99 +	"rx_length_errors", "rx_over_errors", "rx_crc_errors",
  11.100 +	"rx_frame_errors", "rx_fifo_errors", "rx_missed_errors",
  11.101 +	"tx_aborted_errors", "tx_carrier_errors", "tx_fifo_errors",
  11.102 +	"tx_heartbeat_errors", "tx_window_errors",
  11.103 +};
  11.104 +#define E100_STATS_LEN	sizeof(e100_gstrings_stats) / ETH_GSTRING_LEN
  11.105 +#endif
  11.106 +
  11.107 +#if 0
  11.108 +static int e100_do_ethtool_ioctl(struct net_device *, struct ifreq *);
  11.109 +#endif
  11.110 +static void e100_get_speed_duplex_caps(struct e100_private *);
  11.111 +#if 0
  11.112 +static int e100_ethtool_get_settings(struct net_device *, struct ifreq *);
  11.113 +static int e100_ethtool_set_settings(struct net_device *, struct ifreq *);
  11.114 +
  11.115 +static int e100_ethtool_get_drvinfo(struct net_device *, struct ifreq *);
  11.116 +static int e100_ethtool_eeprom(struct net_device *, struct ifreq *);
  11.117 +#endif
  11.118 +
  11.119 +#define E100_EEPROM_MAGIC 0x1234
  11.120 +#if 0
  11.121 +static int e100_ethtool_glink(struct net_device *, struct ifreq *);
  11.122 +static int e100_ethtool_gregs(struct net_device *, struct ifreq *);
  11.123 +static int e100_ethtool_nway_rst(struct net_device *, struct ifreq *);
  11.124 +static int e100_ethtool_wol(struct net_device *, struct ifreq *);
  11.125 +#endif
  11.126 +#ifdef CONFIG_PM
  11.127 +static unsigned char e100_setup_filter(struct e100_private *bdp);
  11.128 +static void e100_do_wol(struct pci_dev *pcid, struct e100_private *bdp);
  11.129 +#endif
  11.130 +#if 0
  11.131 +static u16 e100_get_ip_lbytes(struct net_device *dev);
  11.132 +#endif
  11.133 +extern void e100_config_wol(struct e100_private *bdp);
  11.134 +extern u32 e100_run_diag(struct net_device *dev, u64 *test_info, u32 flags);
  11.135 +#if 0
  11.136 +static int e100_ethtool_test(struct net_device *, struct ifreq *);
  11.137 +static int e100_ethtool_gstrings(struct net_device *, struct ifreq *);
  11.138 +static char *test_strings[] = {
  11.139 +	"E100_EEPROM_TEST_FAIL",
  11.140 +	"E100_CHIP_TIMEOUT",
  11.141 +	"E100_ROM_TEST_FAIL",
  11.142 +	"E100_REG_TEST_FAIL",
  11.143 +	"E100_MAC_TEST_FAIL",
  11.144 +	"E100_LPBK_MAC_FAIL",
  11.145 +	"E100_LPBK_PHY_FAIL"
  11.146 +};
  11.147 +#endif
  11.148 +
  11.149 +static int e100_ethtool_led_blink(struct net_device *, struct ifreq *);
  11.150 +
  11.151 +#if 0
  11.152 +static int e100_mii_ioctl(struct net_device *, struct ifreq *, int);
  11.153 +#endif
  11.154 +
  11.155 +static unsigned char e100_delayed_exec_non_cu_cmd(struct e100_private *,
  11.156 +						  nxmit_cb_entry_t *);
  11.157 +static void e100_free_nontx_list(struct e100_private *);
  11.158 +static void e100_non_tx_background(unsigned long);
  11.159 +
  11.160 +/* Global Data structures and variables */
  11.161 +char e100_copyright[] __devinitdata = "Copyright (c) 2003 Intel Corporation";
  11.162 +char e100_driver_version[]="2.2.21-k1";
  11.163 +const char *e100_full_driver_name = "Intel(R) PRO/100 Network Driver";
  11.164 +char e100_short_driver_name[] = "e100";
  11.165 +static int e100nics = 0;
  11.166 +static void e100_vlan_rx_register(struct net_device *netdev, struct vlan_group
  11.167 +		*grp);
  11.168 +static void e100_vlan_rx_add_vid(struct net_device *netdev, u16 vid);
  11.169 +static void e100_vlan_rx_kill_vid(struct net_device *netdev, u16 vid);
  11.170 +
  11.171 +#ifdef CONFIG_PM
  11.172 +static int e100_notify_reboot(struct notifier_block *, unsigned long event, void *ptr);
  11.173 +static int e100_suspend(struct pci_dev *pcid, u32 state);
  11.174 +static int e100_resume(struct pci_dev *pcid);
  11.175 +struct notifier_block e100_notifier_reboot = {
  11.176 +        .notifier_call  = e100_notify_reboot,
  11.177 +        .next           = NULL,
  11.178 +        .priority       = 0
  11.179 +};
  11.180 +#endif
  11.181 +
  11.182 +/*********************************************************************/
  11.183 +/*! This is a GCC extension to ANSI C.
  11.184 + *  See the item "Labeled Elements in Initializers" in the section
  11.185 + *  "Extensions to the C Language Family" of the GCC documentation.
  11.186 + *********************************************************************/
  11.187 +#define E100_PARAM_INIT { [0 ... E100_MAX_NIC] = -1 }
  11.188 +
  11.189 +/* All parameters are treated the same, as an integer array of values.
  11.190 + * This macro just reduces the need to repeat the same declaration code
  11.191 + * over and over (plus this helps to avoid typo bugs).
  11.192 + */
  11.193 +#define E100_PARAM(X, S)                                        \
  11.194 +        static const int X[E100_MAX_NIC + 1] = E100_PARAM_INIT; \
  11.195 +        MODULE_PARM(X, "1-" __MODULE_STRING(E100_MAX_NIC) "i"); \
  11.196 +        MODULE_PARM_DESC(X, S);
  11.197 +
  11.198 +/* ====================================================================== */
  11.199 +static u8 e100_D101M_checksum(struct e100_private *, struct sk_buff *);
  11.200 +static u8 e100_D102_check_checksum(rfd_t *);
  11.201 +#if 0
  11.202 +static int e100_ioctl(struct net_device *, struct ifreq *, int);
  11.203 +#endif
  11.204 +static int e100_open(struct net_device *);
  11.205 +static int e100_close(struct net_device *);
  11.206 +static int e100_change_mtu(struct net_device *, int);
  11.207 +static int e100_xmit_frame(struct sk_buff *, struct net_device *);
  11.208 +static unsigned char e100_init(struct e100_private *);
  11.209 +static int e100_set_mac(struct net_device *, void *);
  11.210 +struct net_device_stats *e100_get_stats(struct net_device *);
  11.211 +
  11.212 +static void e100intr(int, void *, struct pt_regs *);
  11.213 +static void e100_print_brd_conf(struct e100_private *);
  11.214 +static void e100_set_multi(struct net_device *);
  11.215 +void e100_set_speed_duplex(struct e100_private *);
  11.216 +
  11.217 +static u8 e100_pci_setup(struct pci_dev *, struct e100_private *);
  11.218 +static u8 e100_sw_init(struct e100_private *);
  11.219 +static void e100_tco_workaround(struct e100_private *);
  11.220 +static unsigned char e100_alloc_space(struct e100_private *);
  11.221 +static void e100_dealloc_space(struct e100_private *);
  11.222 +static int e100_alloc_tcb_pool(struct e100_private *);
  11.223 +static void e100_setup_tcb_pool(tcb_t *, unsigned int, struct e100_private *);
  11.224 +static void e100_free_tcb_pool(struct e100_private *);
  11.225 +static int e100_alloc_rfd_pool(struct e100_private *);
  11.226 +static void e100_free_rfd_pool(struct e100_private *);
  11.227 +
  11.228 +static void e100_rd_eaddr(struct e100_private *);
  11.229 +static void e100_rd_pwa_no(struct e100_private *);
  11.230 +extern u16 e100_eeprom_read(struct e100_private *, u16);
  11.231 +extern void e100_eeprom_write_block(struct e100_private *, u16, u16 *, u16);
  11.232 +extern u16 e100_eeprom_size(struct e100_private *);
  11.233 +u16 e100_eeprom_calculate_chksum(struct e100_private *adapter);
  11.234 +
  11.235 +static unsigned char e100_clr_cntrs(struct e100_private *);
  11.236 +static unsigned char e100_load_microcode(struct e100_private *);
  11.237 +static unsigned char e100_hw_init(struct e100_private *);
  11.238 +static unsigned char e100_setup_iaaddr(struct e100_private *, u8 *);
  11.239 +static unsigned char e100_update_stats(struct e100_private *bdp);
  11.240 +
  11.241 +static void e100_start_ru(struct e100_private *);
  11.242 +static void e100_dump_stats_cntrs(struct e100_private *);
  11.243 +
  11.244 +static void e100_check_options(int board, struct e100_private *bdp);
  11.245 +static void e100_set_int_option(int *, int, int, int, int, char *);
  11.246 +static void e100_set_bool_option(struct e100_private *bdp, int, u32, int,
  11.247 +				 char *);
  11.248 +unsigned char e100_wait_exec_cmplx(struct e100_private *, u32, u8, u8);
  11.249 +void e100_exec_cmplx(struct e100_private *, u32, u8);
  11.250 +static unsigned char e100_asf_enabled(struct e100_private *bdp);
  11.251 +
  11.252 +/**
  11.253 + * e100_get_rx_struct - retrieve cell to hold skb buff from the pool
  11.254 + * @bdp: atapter's private data struct
  11.255 + *
  11.256 + * Returns the new cell to hold sk_buff or %NULL.
  11.257 + */
  11.258 +static inline struct rx_list_elem *
  11.259 +e100_get_rx_struct(struct e100_private *bdp)
  11.260 +{
  11.261 +	struct rx_list_elem *rx_struct = NULL;
  11.262 +
  11.263 +	if (!list_empty(&(bdp->rx_struct_pool))) {
  11.264 +		rx_struct = list_entry(bdp->rx_struct_pool.next,
  11.265 +				       struct rx_list_elem, list_elem);
  11.266 +		list_del(&(rx_struct->list_elem));
  11.267 +	}
  11.268 +
  11.269 +	return rx_struct;
  11.270 +}
  11.271 +
  11.272 +/**
  11.273 + * e100_alloc_skb - allocate an skb for the adapter
  11.274 + * @bdp: atapter's private data struct
  11.275 + *
  11.276 + * Allocates skb with enough room for rfd, and data, and reserve non-data space.
  11.277 + * Returns the new cell with sk_buff or %NULL.
  11.278 + */
  11.279 +static inline struct rx_list_elem *
  11.280 +e100_alloc_skb(struct e100_private *bdp)
  11.281 +{
  11.282 +	struct sk_buff *new_skb;
  11.283 +	u32 skb_size = sizeof (rfd_t);
  11.284 +	struct rx_list_elem *rx_struct;
  11.285 +
  11.286 +	new_skb = (struct sk_buff *) dev_alloc_skb(skb_size);
  11.287 +	if (new_skb) {
  11.288 +		/* The IP data should be 
  11.289 +		   DWORD aligned. since the ethernet header is 14 bytes long, 
  11.290 +		   we need to reserve 2 extra bytes so that the TCP/IP headers
  11.291 +		   will be DWORD aligned. */
  11.292 +		skb_reserve(new_skb, 2);
  11.293 +		if ((rx_struct = e100_get_rx_struct(bdp)) == NULL)
  11.294 +			goto err;
  11.295 +		rx_struct->skb = new_skb;
  11.296 +		rx_struct->dma_addr = pci_map_single(bdp->pdev, new_skb->data,
  11.297 +						     sizeof (rfd_t),
  11.298 +						     PCI_DMA_FROMDEVICE);
  11.299 +		if (!rx_struct->dma_addr)
  11.300 +			goto err;
  11.301 +		skb_reserve(new_skb, bdp->rfd_size);
  11.302 +		return rx_struct;
  11.303 +	} else {
  11.304 +		return NULL;
  11.305 +	}
  11.306 +
  11.307 +err:
  11.308 +	dev_kfree_skb_irq(new_skb);
  11.309 +	return NULL;
  11.310 +}
  11.311 +
  11.312 +/**
  11.313 + * e100_add_skb_to_end - add an skb to the end of our rfd list
  11.314 + * @bdp: atapter's private data struct
  11.315 + * @rx_struct: rx_list_elem with the new skb
  11.316 + *
  11.317 + * Adds a newly allocated skb to the end of our rfd list.
  11.318 + */
  11.319 +inline void
  11.320 +e100_add_skb_to_end(struct e100_private *bdp, struct rx_list_elem *rx_struct)
  11.321 +{
  11.322 +	rfd_t *rfdn;		/* The new rfd */
  11.323 +	rfd_t *rfd;		/* The old rfd */
  11.324 +	struct rx_list_elem *rx_struct_last;
  11.325 +
  11.326 +	(rx_struct->skb)->dev = bdp->device;
  11.327 +	rfdn = RFD_POINTER(rx_struct->skb, bdp);
  11.328 +	rfdn->rfd_header.cb_status = 0;
  11.329 +	rfdn->rfd_header.cb_cmd = __constant_cpu_to_le16(RFD_EL_BIT);
  11.330 +	rfdn->rfd_act_cnt = 0;
  11.331 +	rfdn->rfd_sz = __constant_cpu_to_le16(RFD_DATA_SIZE);
  11.332 +
  11.333 +	pci_dma_sync_single(bdp->pdev, rx_struct->dma_addr, bdp->rfd_size,
  11.334 +			    PCI_DMA_TODEVICE);
  11.335 +
  11.336 +	if (!list_empty(&(bdp->active_rx_list))) {
  11.337 +		rx_struct_last = list_entry(bdp->active_rx_list.prev,
  11.338 +					    struct rx_list_elem, list_elem);
  11.339 +		rfd = RFD_POINTER(rx_struct_last->skb, bdp);
  11.340 +		pci_dma_sync_single(bdp->pdev, rx_struct_last->dma_addr,
  11.341 +				    4, PCI_DMA_FROMDEVICE);
  11.342 +		put_unaligned(cpu_to_le32(rx_struct->dma_addr),
  11.343 +			      ((u32 *) (&(rfd->rfd_header.cb_lnk_ptr))));
  11.344 +
  11.345 +		pci_dma_sync_single(bdp->pdev, rx_struct_last->dma_addr,
  11.346 +				    8, PCI_DMA_TODEVICE);
  11.347 +		rfd->rfd_header.cb_cmd &=
  11.348 +			__constant_cpu_to_le16((u16) ~RFD_EL_BIT);
  11.349 +
  11.350 +		pci_dma_sync_single(bdp->pdev, rx_struct_last->dma_addr,
  11.351 +				    4, PCI_DMA_TODEVICE);
  11.352 +	}
  11.353 +
  11.354 +	list_add_tail(&(rx_struct->list_elem), &(bdp->active_rx_list));
  11.355 +}
  11.356 +
  11.357 +static inline void
  11.358 +e100_alloc_skbs(struct e100_private *bdp)
  11.359 +{
  11.360 +	for (; bdp->skb_req > 0; bdp->skb_req--) {
  11.361 +		struct rx_list_elem *rx_struct;
  11.362 +
  11.363 +		if ((rx_struct = e100_alloc_skb(bdp)) == NULL)
  11.364 +			return;
  11.365 +
  11.366 +		e100_add_skb_to_end(bdp, rx_struct);
  11.367 +	}
  11.368 +}
  11.369 +
  11.370 +void e100_tx_srv(struct e100_private *);
  11.371 +u32 e100_rx_srv(struct e100_private *);
  11.372 +
  11.373 +void e100_watchdog(struct net_device *);
  11.374 +void e100_refresh_txthld(struct e100_private *);
  11.375 +void e100_manage_adaptive_ifs(struct e100_private *);
  11.376 +void e100_clear_pools(struct e100_private *);
  11.377 +static void e100_clear_structs(struct net_device *);
  11.378 +static inline tcb_t *e100_prepare_xmit_buff(struct e100_private *,
  11.379 +					    struct sk_buff *);
  11.380 +static void e100_set_multi_exec(struct net_device *dev);
  11.381 +
  11.382 +MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
  11.383 +MODULE_DESCRIPTION("Intel(R) PRO/100 Network Driver");
  11.384 +MODULE_LICENSE("GPL");
  11.385 +
  11.386 +E100_PARAM(TxDescriptors, "Number of transmit descriptors");
  11.387 +E100_PARAM(RxDescriptors, "Number of receive descriptors");
  11.388 +E100_PARAM(XsumRX, "Disable or enable Receive Checksum offload");
  11.389 +E100_PARAM(e100_speed_duplex, "Speed and Duplex settings");
  11.390 +E100_PARAM(ucode, "Disable or enable microcode loading");
  11.391 +E100_PARAM(ber, "Value for the BER correction algorithm");
  11.392 +E100_PARAM(flow_control, "Disable or enable Ethernet PAUSE frames processing");
  11.393 +E100_PARAM(IntDelay, "Value for CPU saver's interrupt delay");
  11.394 +E100_PARAM(BundleSmallFr, "Disable or enable interrupt bundling of small frames");
  11.395 +E100_PARAM(BundleMax, "Maximum number for CPU saver's packet bundling");
  11.396 +E100_PARAM(IFS, "Disable or enable the adaptive IFS algorithm");
  11.397 +
  11.398 +/**
  11.399 + * e100_exec_cmd - issue a comand
  11.400 + * @bdp: atapter's private data struct
  11.401 + * @scb_cmd_low: the command that is to be issued
  11.402 + *
  11.403 + * This general routine will issue a command to the e100.
  11.404 + */
  11.405 +static inline void
  11.406 +e100_exec_cmd(struct e100_private *bdp, u8 cmd_low)
  11.407 +{
  11.408 +	writeb(cmd_low, &(bdp->scb->scb_cmd_low));
  11.409 +	readw(&(bdp->scb->scb_status));	/* flushes last write, read-safe */
  11.410 +}
  11.411 +
  11.412 +/**
  11.413 + * e100_wait_scb - wait for SCB to clear
  11.414 + * @bdp: atapter's private data struct
  11.415 + *
  11.416 + * This routine checks to see if the e100 has accepted a command.
  11.417 + * It does so by checking the command field in the SCB, which will
  11.418 + * be zeroed by the e100 upon accepting a command.  The loop waits
  11.419 + * for up to 1 millisecond for command acceptance.
  11.420 + *
  11.421 + * Returns:
  11.422 + *      true if the SCB cleared within 1 millisecond.
  11.423 + *      false if it didn't clear within 1 millisecond
  11.424 + */
  11.425 +unsigned char
  11.426 +e100_wait_scb(struct e100_private *bdp)
  11.427 +{
  11.428 +	int i;
  11.429 +
  11.430 +	/* loop on the scb for a few times */
  11.431 +	for (i = 0; i < 100; i++) {
  11.432 +		if (!readb(&bdp->scb->scb_cmd_low))
  11.433 +			return true;
  11.434 +		cpu_relax();
  11.435 +	}
  11.436 +
  11.437 +	/* it didn't work. do it the slow way using udelay()s */
  11.438 +	for (i = 0; i < E100_MAX_SCB_WAIT; i++) {
  11.439 +		if (!readb(&bdp->scb->scb_cmd_low))
  11.440 +			return true;
  11.441 +		cpu_relax();
  11.442 +		udelay(1);
  11.443 +	}
  11.444 +
  11.445 +	return false;
  11.446 +}
  11.447 +
  11.448 +/**
  11.449 + * e100_wait_exec_simple - issue a command
  11.450 + * @bdp: atapter's private data struct
  11.451 + * @scb_cmd_low: the command that is to be issued
  11.452 + *
  11.453 + * This general routine will issue a command to the e100 after waiting for
  11.454 + * the previous command to finish.
  11.455 + *
  11.456 + * Returns:
  11.457 + *      true if the command was issued to the chip successfully
  11.458 + *      false if the command was not issued to the chip
  11.459 + */
  11.460 +inline unsigned char
  11.461 +e100_wait_exec_simple(struct e100_private *bdp, u8 scb_cmd_low)
  11.462 +{
  11.463 +	if (!e100_wait_scb(bdp)) {
  11.464 +		printk(KERN_DEBUG "e100: %s: e100_wait_exec_simple: failed\n",
  11.465 +		       bdp->device->name);
  11.466 +#ifdef E100_CU_DEBUG		
  11.467 +		printk(KERN_ERR "e100: %s: Last command (%x/%x) "
  11.468 +			"timeout\n", bdp->device->name, 
  11.469 +			bdp->last_cmd, bdp->last_sub_cmd);
  11.470 +		printk(KERN_ERR "e100: %s: Current simple command (%x) "
  11.471 +			"can't be executed\n", 
  11.472 +			bdp->device->name, scb_cmd_low);
  11.473 +#endif		
  11.474 +		return false;
  11.475 +	}
  11.476 +	e100_exec_cmd(bdp, scb_cmd_low);
  11.477 +#ifdef E100_CU_DEBUG	
  11.478 +	bdp->last_cmd = scb_cmd_low;
  11.479 +	bdp->last_sub_cmd = 0;
  11.480 +#endif	
  11.481 +	return true;
  11.482 +}
  11.483 +
  11.484 +void
  11.485 +e100_exec_cmplx(struct e100_private *bdp, u32 phys_addr, u8 cmd)
  11.486 +{
  11.487 +	writel(phys_addr, &(bdp->scb->scb_gen_ptr));
  11.488 +	readw(&(bdp->scb->scb_status));	/* flushes last write, read-safe */
  11.489 +	e100_exec_cmd(bdp, cmd);
  11.490 +}
  11.491 +
  11.492 +unsigned char
  11.493 +e100_wait_exec_cmplx(struct e100_private *bdp, u32 phys_addr, u8 cmd, u8 sub_cmd)
  11.494 +{
  11.495 +	if (!e100_wait_scb(bdp)) {
  11.496 +#ifdef E100_CU_DEBUG		
  11.497 +		printk(KERN_ERR "e100: %s: Last command (%x/%x) "
  11.498 +			"timeout\n", bdp->device->name, 
  11.499 +			bdp->last_cmd, bdp->last_sub_cmd);
  11.500 +		printk(KERN_ERR "e100: %s: Current complex command "
  11.501 +			"(%x/%x) can't be executed\n", 
  11.502 +			bdp->device->name, cmd, sub_cmd);
  11.503 +#endif		
  11.504 +		return false;
  11.505 +	}
  11.506 +	e100_exec_cmplx(bdp, phys_addr, cmd);
  11.507 +#ifdef E100_CU_DEBUG	
  11.508 +	bdp->last_cmd = cmd;
  11.509 +	bdp->last_sub_cmd = sub_cmd;
  11.510 +#endif	
  11.511 +	return true;
  11.512 +}
  11.513 +
  11.514 +inline u8
  11.515 +e100_wait_cus_idle(struct e100_private *bdp)
  11.516 +{
  11.517 +	int i;
  11.518 +
  11.519 +	/* loop on the scb for a few times */
  11.520 +	for (i = 0; i < 100; i++) {
  11.521 +		if (((readw(&(bdp->scb->scb_status)) & SCB_CUS_MASK) !=
  11.522 +		     SCB_CUS_ACTIVE)) {
  11.523 +			return true;
  11.524 +		}
  11.525 +		cpu_relax();
  11.526 +	}
  11.527 +
  11.528 +	for (i = 0; i < E100_MAX_CU_IDLE_WAIT; i++) {
  11.529 +		if (((readw(&(bdp->scb->scb_status)) & SCB_CUS_MASK) !=
  11.530 +		     SCB_CUS_ACTIVE)) {
  11.531 +			return true;
  11.532 +		}
  11.533 +		cpu_relax();
  11.534 +		udelay(1);
  11.535 +	}
  11.536 +
  11.537 +	return false;
  11.538 +}
  11.539 +
  11.540 +/**
  11.541 + * e100_disable_clear_intr - disable and clear/ack interrupts
  11.542 + * @bdp: atapter's private data struct
  11.543 + *
  11.544 + * This routine disables interrupts at the hardware, by setting
  11.545 + * the M (mask) bit in the adapter's CSR SCB command word.
  11.546 + * It also clear/ack interrupts.
  11.547 + */
  11.548 +static inline void
  11.549 +e100_disable_clear_intr(struct e100_private *bdp)
  11.550 +{
  11.551 +	u16 intr_status;
  11.552 +	/* Disable interrupts on our PCI board by setting the mask bit */
  11.553 +	writeb(SCB_INT_MASK, &bdp->scb->scb_cmd_hi);
  11.554 +	intr_status = readw(&bdp->scb->scb_status);
  11.555 +	/* ack and clear intrs */
  11.556 +	writew(intr_status, &bdp->scb->scb_status);
  11.557 +	readw(&bdp->scb->scb_status);
  11.558 +}
  11.559 +
  11.560 +/**
  11.561 + * e100_set_intr_mask - set interrupts
  11.562 + * @bdp: atapter's private data struct
  11.563 + *
  11.564 + * This routine sets interrupts at the hardware, by resetting
  11.565 + * the M (mask) bit in the adapter's CSR SCB command word
  11.566 + */
  11.567 +static inline void
  11.568 +e100_set_intr_mask(struct e100_private *bdp)
  11.569 +{
  11.570 +	writeb(bdp->intr_mask, &bdp->scb->scb_cmd_hi);
  11.571 +	readw(&(bdp->scb->scb_status)); /* flushes last write, read-safe */
  11.572 +}
  11.573 +
  11.574 +static inline void
  11.575 +e100_trigger_SWI(struct e100_private *bdp)
  11.576 +{
  11.577 +	/* Trigger interrupt on our PCI board by asserting SWI bit */
  11.578 +	writeb(SCB_SOFT_INT, &bdp->scb->scb_cmd_hi);
  11.579 +	readw(&(bdp->scb->scb_status));	/* flushes last write, read-safe */
  11.580 +}
  11.581 +
  11.582 +static int __devinit
  11.583 +e100_found1(struct pci_dev *pcid, const struct pci_device_id *ent)
  11.584 +{
  11.585 +	static int first_time = true;
  11.586 +	struct net_device *dev = NULL;
  11.587 +	struct e100_private *bdp = NULL;
  11.588 +	int rc = 0;
  11.589 +	u16 cal_checksum, read_checksum;
  11.590 +
  11.591 +	dev = alloc_etherdev(sizeof (struct e100_private));
  11.592 +	if (dev == NULL) {
  11.593 +		printk(KERN_ERR "e100: Not able to alloc etherdev struct\n");
  11.594 +		rc = -ENODEV;
  11.595 +		goto out;
  11.596 +	}
  11.597 +
  11.598 +	SET_MODULE_OWNER(dev);
  11.599 +
  11.600 +	if (first_time) {
  11.601 +		first_time = false;
  11.602 +        	printk(KERN_NOTICE "%s - version %s\n",
  11.603 +	               e100_full_driver_name, e100_driver_version);
  11.604 +		printk(KERN_NOTICE "%s\n", e100_copyright);
  11.605 +		printk(KERN_NOTICE "\n");
  11.606 +	}
  11.607 +
  11.608 +	bdp = dev->priv;
  11.609 +	bdp->pdev = pcid;
  11.610 +	bdp->device = dev;
  11.611 +
  11.612 +	pci_set_drvdata(pcid, dev);
  11.613 +
  11.614 +	if ((rc = e100_alloc_space(bdp)) != 0) {
  11.615 +		goto err_dev;
  11.616 +	}
  11.617 +
  11.618 +	bdp->flags = 0;
  11.619 +	bdp->ifs_state = 0;
  11.620 +	bdp->ifs_value = 0;
  11.621 +	bdp->scb = 0;
  11.622 +
  11.623 +	init_timer(&bdp->nontx_timer_id);
  11.624 +	bdp->nontx_timer_id.data = (unsigned long) bdp;
  11.625 +	bdp->nontx_timer_id.function = (void *) &e100_non_tx_background;
  11.626 +	INIT_LIST_HEAD(&(bdp->non_tx_cmd_list));
  11.627 +	bdp->non_tx_command_state = E100_NON_TX_IDLE;
  11.628 +
  11.629 +	init_timer(&bdp->watchdog_timer);
  11.630 +	bdp->watchdog_timer.data = (unsigned long) dev;
  11.631 +	bdp->watchdog_timer.function = (void *) &e100_watchdog;
  11.632 +
  11.633 +	if ((rc = e100_pci_setup(pcid, bdp)) != 0) {
  11.634 +		goto err_dealloc;
  11.635 +	}
  11.636 +
  11.637 +	if (((bdp->pdev->device > 0x1030)
  11.638 +	       && (bdp->pdev->device < 0x103F))
  11.639 +	    || ((bdp->pdev->device >= 0x1050)
  11.640 +	       && (bdp->pdev->device <= 0x1057))
  11.641 +	    || (bdp->pdev->device == 0x2449)
  11.642 +	    || (bdp->pdev->device == 0x2459)
  11.643 +	    || (bdp->pdev->device == 0x245D)) {
  11.644 +		bdp->rev_id = D101MA_REV_ID;	/* workaround for ICH3 */
  11.645 +		bdp->flags |= IS_ICH;
  11.646 +	}
  11.647 +
  11.648 +	if (bdp->rev_id == 0xff)
  11.649 +		bdp->rev_id = 1;
  11.650 +
  11.651 +	if ((u8) bdp->rev_id >= D101A4_REV_ID)
  11.652 +		bdp->flags |= IS_BACHELOR;
  11.653 +
  11.654 +	if ((u8) bdp->rev_id >= D102_REV_ID) {
  11.655 +		bdp->flags |= USE_IPCB;
  11.656 +		bdp->rfd_size = 32;
  11.657 +	} else {
  11.658 +		bdp->rfd_size = 16;
  11.659 +	}
  11.660 +	e100_check_options(e100nics, bdp);
  11.661 +
  11.662 +	if (!e100_init(bdp)) {
  11.663 +		printk(KERN_ERR "e100: Failed to initialize, instance #%d\n",
  11.664 +		       e100nics);
  11.665 +		rc = -ENODEV;
  11.666 +		goto err_pci;
  11.667 +	}
  11.668 +
  11.669 +	/* Check if checksum is valid */
  11.670 +	cal_checksum = e100_eeprom_calculate_chksum(bdp);
  11.671 +	read_checksum = e100_eeprom_read(bdp, (bdp->eeprom_size - 1));
  11.672 +	if (cal_checksum != read_checksum) {
  11.673 +                printk(KERN_ERR "e100: Corrupted EEPROM on instance #%d\n",
  11.674 +		       e100nics);
  11.675 +                rc = -ENODEV;
  11.676 +                goto err_pci;
  11.677 +	}
  11.678 +	
  11.679 +	dev->vlan_rx_register = e100_vlan_rx_register;
  11.680 +	dev->vlan_rx_add_vid = e100_vlan_rx_add_vid;
  11.681 +	dev->vlan_rx_kill_vid = e100_vlan_rx_kill_vid;
  11.682 +	dev->irq = pcid->irq;
  11.683 +	dev->open = &e100_open;
  11.684 +	dev->hard_start_xmit = &e100_xmit_frame;
  11.685 +	dev->stop = &e100_close;
  11.686 +	dev->change_mtu = &e100_change_mtu;
  11.687 +	dev->get_stats = &e100_get_stats;
  11.688 +	dev->set_multicast_list = &e100_set_multi;
  11.689 +	dev->set_mac_address = &e100_set_mac;
  11.690 +#if 0
  11.691 +	dev->do_ioctl = &e100_ioctl;
  11.692 +#endif
  11.693 +
  11.694 +	if (bdp->flags & USE_IPCB)
  11.695 +	dev->features = NETIF_F_SG | NETIF_F_HW_CSUM |
  11.696 +			NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
  11.697 +		
  11.698 +	e100nics++;
  11.699 +
  11.700 +	e100_get_speed_duplex_caps(bdp);
  11.701 +
  11.702 +	if ((rc = register_netdev(dev)) != 0) {
  11.703 +		goto err_pci;
  11.704 +	}
  11.705 +        memcpy(bdp->ifname, dev->name, IFNAMSIZ);
  11.706 +        bdp->ifname[IFNAMSIZ-1] = 0;	
  11.707 +
  11.708 +	printk(KERN_NOTICE
  11.709 +	       "e100: %s: %s\n", 
  11.710 +	       bdp->device->name, "Intel(R) PRO/100 Network Connection");
  11.711 +	e100_print_brd_conf(bdp);
  11.712 +
  11.713 +	bdp->wolsupported = 0;
  11.714 +	bdp->wolopts = 0;
  11.715 +	
  11.716 +	/* Check if WoL is enabled on EEPROM */
  11.717 +	if (e100_eeprom_read(bdp, EEPROM_ID_WORD) & BIT_5) {
  11.718 +		/* Magic Packet WoL is enabled on device by default */
  11.719 +		/* if EEPROM WoL bit is TRUE                        */
  11.720 +		bdp->wolsupported = WAKE_MAGIC;
  11.721 +		bdp->wolopts = WAKE_MAGIC;
  11.722 +		if (bdp->rev_id >= D101A4_REV_ID)
  11.723 +			bdp->wolsupported = WAKE_PHY | WAKE_MAGIC;
  11.724 +		if (bdp->rev_id >= D101MA_REV_ID)
  11.725 +			bdp->wolsupported |= WAKE_UCAST | WAKE_ARP;
  11.726 +	}
  11.727 +
  11.728 +	printk(KERN_NOTICE "\n");
  11.729 +
  11.730 +	if ( !(dev->features & NETIF_F_SG) )
  11.731 +		alert_slow_netdevice(dev, (char *)e100_full_driver_name);
  11.732 +
  11.733 +	goto out;
  11.734 +
  11.735 +err_pci:
  11.736 +	iounmap(bdp->scb);
  11.737 +	pci_release_regions(pcid);
  11.738 +	pci_disable_device(pcid);
  11.739 +err_dealloc:
  11.740 +	e100_dealloc_space(bdp);
  11.741 +err_dev:
  11.742 +	pci_set_drvdata(pcid, NULL);
  11.743 +	kfree(dev);
  11.744 +out:
  11.745 +	return rc;
  11.746 +}
  11.747 +
  11.748 +/**
  11.749 + * e100_clear_structs - free resources
  11.750 + * @dev: adapter's net_device struct
  11.751 + *
  11.752 + * Free all device specific structs, unmap i/o address, etc.
  11.753 + */
  11.754 +static void __devexit
  11.755 +e100_clear_structs(struct net_device *dev)
  11.756 +{
  11.757 +	struct e100_private *bdp = dev->priv;
  11.758 +
  11.759 +	iounmap(bdp->scb);
  11.760 +	pci_release_regions(bdp->pdev);
  11.761 +	pci_disable_device(bdp->pdev);
  11.762 +
  11.763 +	e100_dealloc_space(bdp);
  11.764 +	pci_set_drvdata(bdp->pdev, NULL);
  11.765 +	kfree(dev);
  11.766 +}
  11.767 +
  11.768 +static void __devexit
  11.769 +e100_remove1(struct pci_dev *pcid)
  11.770 +{
  11.771 +	struct net_device *dev;
  11.772 +	struct e100_private *bdp;
  11.773 +
  11.774 +	if (!(dev = (struct net_device *) pci_get_drvdata(pcid)))
  11.775 +		return;
  11.776 +
  11.777 +	bdp = dev->priv;
  11.778 +
  11.779 +	unregister_netdev(dev);
  11.780 +
  11.781 +	e100_sw_reset(bdp, PORT_SELECTIVE_RESET);
  11.782 +
  11.783 +	if (bdp->non_tx_command_state != E100_NON_TX_IDLE) {
  11.784 +		del_timer_sync(&bdp->nontx_timer_id);
  11.785 +		e100_free_nontx_list(bdp);
  11.786 +		bdp->non_tx_command_state = E100_NON_TX_IDLE;
  11.787 +	}
  11.788 +
  11.789 +	e100_clear_structs(dev);
  11.790 +
  11.791 +	--e100nics;
  11.792 +}
  11.793 +
  11.794 +static struct pci_device_id e100_id_table[] __devinitdata = {
  11.795 +	{0x8086, 0x1229, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
  11.796 +	{0x8086, 0x2449, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
  11.797 +	{0x8086, 0x1059, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
  11.798 +	{0x8086, 0x1209, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
  11.799 +  	{0x8086, 0x1029, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
  11.800 +	{0x8086, 0x1030, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },	
  11.801 +	{0x8086, 0x1031, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, 
  11.802 +	{0x8086, 0x1032, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
  11.803 +	{0x8086, 0x1033, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, 
  11.804 +	{0x8086, 0x1034, PCI_ANY_ID, PCI_ANY_ID, 0, 0, }, 
  11.805 +	{0x8086, 0x1038, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
  11.806 +	{0x8086, 0x1039, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
  11.807 +	{0x8086, 0x103A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
  11.808 +	{0x8086, 0x103B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
  11.809 +	{0x8086, 0x103C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
  11.810 +	{0x8086, 0x103D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
  11.811 +	{0x8086, 0x103E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
  11.812 +	{0x8086, 0x1050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
  11.813 +	{0x8086, 0x1051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
  11.814 +	{0x8086, 0x1052, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
  11.815 +	{0x8086, 0x1053, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
  11.816 +	{0x8086, 0x1054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
  11.817 +	{0x8086, 0x1055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
  11.818 +	{0x8086, 0x2459, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
  11.819 +	{0x8086, 0x245D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
  11.820 +	{0,} /* This has to be the last entry*/
  11.821 +};
  11.822 +MODULE_DEVICE_TABLE(pci, e100_id_table);
  11.823 +
  11.824 +static struct pci_driver e100_driver = {
  11.825 +	.name         = "e100",
  11.826 +	.id_table     = e100_id_table,
  11.827 +	.probe        = e100_found1,
  11.828 +	.remove       = __devexit_p(e100_remove1),
  11.829 +#ifdef CONFIG_PM
  11.830 +	.suspend      = e100_suspend,
  11.831 +	.resume       = e100_resume,
  11.832 +#endif
  11.833 +};
  11.834 +
  11.835 +static int __init
  11.836 +e100_init_module(void)
  11.837 +{
  11.838 +	int ret;
  11.839 +        ret = pci_module_init(&e100_driver);
  11.840 +
  11.841 +	if(ret >= 0) {
  11.842 +#ifdef CONFIG_PM
  11.843 +		register_reboot_notifier(&e100_notifier_reboot);
  11.844 +#endif 
  11.845 +	}
  11.846 +
  11.847 +	return ret;
  11.848 +}
  11.849 +
  11.850 +static void __exit
  11.851 +e100_cleanup_module(void)
  11.852 +{
  11.853 +#ifdef CONFIG_PM	
  11.854 +	unregister_reboot_notifier(&e100_notifier_reboot);
  11.855 +#endif 
  11.856 +
  11.857 +	pci_unregister_driver(&e100_driver);
  11.858 +}
  11.859 +
  11.860 +module_init(e100_init_module);
  11.861 +module_exit(e100_cleanup_module);
  11.862 +
  11.863 +/**
  11.864 + * e100_check_options - check command line options
  11.865 + * @board: board number
  11.866 + * @bdp: atapter's private data struct
  11.867 + *
  11.868 + * This routine does range checking on command-line options
  11.869 + */
  11.870 +void __devinit
  11.871 +e100_check_options(int board, struct e100_private *bdp)
  11.872 +{
  11.873 +	if (board >= E100_MAX_NIC) {
  11.874 +		printk(KERN_NOTICE 
  11.875 +		       "e100: No configuration available for board #%d\n",
  11.876 +		       board);
  11.877 +		printk(KERN_NOTICE "e100: Using defaults for all values\n");
  11.878 +		board = E100_MAX_NIC;
  11.879 +	}
  11.880 +
  11.881 +	e100_set_int_option(&(bdp->params.TxDescriptors), TxDescriptors[board],
  11.882 +			    E100_MIN_TCB, E100_MAX_TCB, E100_DEFAULT_TCB,
  11.883 +			    "TxDescriptor count");
  11.884 +
  11.885 +	e100_set_int_option(&(bdp->params.RxDescriptors), RxDescriptors[board],
  11.886 +			    E100_MIN_RFD, E100_MAX_RFD, E100_DEFAULT_RFD,
  11.887 +			    "RxDescriptor count");
  11.888 +
  11.889 +	e100_set_int_option(&(bdp->params.e100_speed_duplex),
  11.890 +			    e100_speed_duplex[board], 0, 4,
  11.891 +			    E100_DEFAULT_SPEED_DUPLEX, "speed/duplex mode");
  11.892 +
  11.893 +	e100_set_int_option(&(bdp->params.ber), ber[board], 0, ZLOCK_MAX_ERRORS,
  11.894 +			    E100_DEFAULT_BER, "Bit Error Rate count");
  11.895 +
  11.896 +	e100_set_bool_option(bdp, XsumRX[board], PRM_XSUMRX, E100_DEFAULT_XSUM,
  11.897 +			     "XsumRX value");
  11.898 +
  11.899 +	/* Default ucode value depended on controller revision */
  11.900 +	if (bdp->rev_id >= D101MA_REV_ID) {
  11.901 +		e100_set_bool_option(bdp, ucode[board], PRM_UCODE,
  11.902 +				     E100_DEFAULT_UCODE, "ucode value");
  11.903 +	} else {
  11.904 +		e100_set_bool_option(bdp, ucode[board], PRM_UCODE, false,
  11.905 +				     "ucode value");
  11.906 +	}
  11.907 +
  11.908 +	e100_set_bool_option(bdp, flow_control[board], PRM_FC, E100_DEFAULT_FC,
  11.909 +			     "flow control value");
  11.910 +
  11.911 +	e100_set_bool_option(bdp, IFS[board], PRM_IFS, E100_DEFAULT_IFS,
  11.912 +			     "IFS value");
  11.913 +
  11.914 +	e100_set_bool_option(bdp, BundleSmallFr[board], PRM_BUNDLE_SMALL,
  11.915 +			     E100_DEFAULT_BUNDLE_SMALL_FR,
  11.916 +			     "CPU saver bundle small frames value");
  11.917 +
  11.918 +	e100_set_int_option(&(bdp->params.IntDelay), IntDelay[board], 0x0,
  11.919 +			    0xFFFF, E100_DEFAULT_CPUSAVER_INTERRUPT_DELAY,
  11.920 +			    "CPU saver interrupt delay value");
  11.921 +
  11.922 +	e100_set_int_option(&(bdp->params.BundleMax), BundleMax[board], 0x1,
  11.923 +			    0xFFFF, E100_DEFAULT_CPUSAVER_BUNDLE_MAX,
  11.924 +			    "CPU saver bundle max value");
  11.925 +
  11.926 +}
  11.927 +
  11.928 +/**
  11.929 + * e100_set_int_option - check and set an integer option
  11.930 + * @option: a pointer to the relevant option field
  11.931 + * @val: the value specified
  11.932 + * @min: the minimum valid value
  11.933 + * @max: the maximum valid value
  11.934 + * @default_val: the default value
  11.935 + * @name: the name of the option
  11.936 + *
  11.937 + * This routine does range checking on a command-line option.
  11.938 + * If the option's value is '-1' use the specified default.
  11.939 + * Otherwise, if the value is invalid, change it to the default.
  11.940 + */
  11.941 +void __devinit
  11.942 +e100_set_int_option(int *option, int val, int min, int max, int default_val,
  11.943 +		    char *name)
  11.944 +{
  11.945 +	if (val == -1) {	/* no value specified. use default */
  11.946 +		*option = default_val;
  11.947 +
  11.948 +	} else if ((val < min) || (val > max)) {
  11.949 +		printk(KERN_NOTICE
  11.950 +		       "e100: Invalid %s specified (%i). "
  11.951 +		       "Valid range is %i-%i\n",
  11.952 +		       name, val, min, max);
  11.953 +		printk(KERN_NOTICE "e100: Using default %s of %i\n", name,
  11.954 +		       default_val);
  11.955 +		*option = default_val;
  11.956 +	} else {
  11.957 +		printk(KERN_INFO "e100: Using specified %s of %i\n", name, val);
  11.958 +		*option = val;
  11.959 +	}
  11.960 +}
  11.961 +
  11.962 +/**
  11.963 + * e100_set_bool_option - check and set a boolean option
  11.964 + * @bdp: atapter's private data struct
  11.965 + * @val: the value specified
  11.966 + * @mask: the mask for the relevant option
  11.967 + * @default_val: the default value
  11.968 + * @name: the name of the option
  11.969 + *
  11.970 + * This routine checks a boolean command-line option.
  11.971 + * If the option's value is '-1' use the specified default.
  11.972 + * Otherwise, if the value is invalid (not 0 or 1), 
  11.973 + * change it to the default.
  11.974 + */
  11.975 +void __devinit
  11.976 +e100_set_bool_option(struct e100_private *bdp, int val, u32 mask,
  11.977 +		     int default_val, char *name)
  11.978 +{
  11.979 +	if (val == -1) {
  11.980 +		if (default_val)
  11.981 +			bdp->params.b_params |= mask;
  11.982 +
  11.983 +	} else if ((val != true) && (val != false)) {
  11.984 +		printk(KERN_NOTICE
  11.985 +		       "e100: Invalid %s specified (%i). "
  11.986 +		       "Valid values are %i/%i\n",
  11.987 +		       name, val, false, true);
  11.988 +		printk(KERN_NOTICE "e100: Using default %s of %i\n", name,
  11.989 +		       default_val);
  11.990 +
  11.991 +		if (default_val)
  11.992 +			bdp->params.b_params |= mask;
  11.993 +	} else {
  11.994 +		printk(KERN_INFO "e100: Using specified %s of %i\n", name, val);
  11.995 +		if (val)
  11.996 +			bdp->params.b_params |= mask;
  11.997 +	}
  11.998 +}
  11.999 +
 11.1000 +static int
 11.1001 +e100_open(struct net_device *dev)
 11.1002 +{
 11.1003 +	struct e100_private *bdp;
 11.1004 +	int rc = 0;
 11.1005 +
 11.1006 +	bdp = dev->priv;
 11.1007 +
 11.1008 +	/* setup the tcb pool */
 11.1009 +	if (!e100_alloc_tcb_pool(bdp)) {
 11.1010 +		rc = -ENOMEM;
 11.1011 +		goto err_exit;
 11.1012 +	}
 11.1013 +	bdp->last_tcb = NULL;
 11.1014 +
 11.1015 +	bdp->tcb_pool.head = 0;
 11.1016 +	bdp->tcb_pool.tail = 1;	
 11.1017 +
 11.1018 +	e100_setup_tcb_pool((tcb_t *) bdp->tcb_pool.data,
 11.1019 +			    bdp->params.TxDescriptors, bdp);
 11.1020 +
 11.1021 +	if (!e100_alloc_rfd_pool(bdp)) {
 11.1022 +		rc = -ENOMEM;
 11.1023 +		goto err_exit;
 11.1024 +	}
 11.1025 +
 11.1026 +	if (!e100_wait_exec_cmplx(bdp, 0, SCB_CUC_LOAD_BASE, 0)) {
 11.1027 +		rc = -EAGAIN;
 11.1028 +		goto err_exit;
 11.1029 +	}
 11.1030 +
 11.1031 +	if (!e100_wait_exec_cmplx(bdp, 0, SCB_RUC_LOAD_BASE, 0)) {
 11.1032 +		rc = -EAGAIN;
 11.1033 +		goto err_exit;
 11.1034 +	}
 11.1035 +
 11.1036 +	mod_timer(&(bdp->watchdog_timer), jiffies + (2 * HZ));
 11.1037 +
 11.1038 +	netif_start_queue(dev);
 11.1039 +
 11.1040 +	e100_start_ru(bdp);
 11.1041 +	if ((rc = request_irq(dev->irq, &e100intr, SA_SHIRQ,
 11.1042 +			      dev->name, dev)) != 0) {
 11.1043 +		del_timer_sync(&bdp->watchdog_timer);
 11.1044 +		goto err_exit;
 11.1045 +	}
 11.1046 +	bdp->intr_mask = 0;
 11.1047 +	e100_set_intr_mask(bdp);
 11.1048 +
 11.1049 +	e100_force_config(bdp);
 11.1050 +
 11.1051 +	goto exit;
 11.1052 +
 11.1053 +err_exit:
 11.1054 +	e100_clear_pools(bdp);
 11.1055 +exit:
 11.1056 +	return rc;
 11.1057 +}
 11.1058 +
 11.1059 +static int
 11.1060 +e100_close(struct net_device *dev)
 11.1061 +{
 11.1062 +	struct e100_private *bdp = dev->priv;
 11.1063 +
 11.1064 +	e100_disable_clear_intr(bdp);
 11.1065 +	free_irq(dev->irq, dev);
 11.1066 +	bdp->intr_mask = SCB_INT_MASK;
 11.1067 +	e100_isolate_driver(bdp);
 11.1068 +
 11.1069 +	netif_carrier_off(bdp->device);
 11.1070 +	bdp->cur_line_speed = 0;
 11.1071 +	bdp->cur_dplx_mode = 0;
 11.1072 +	e100_clear_pools(bdp);
 11.1073 +
 11.1074 +	return 0;
 11.1075 +}
 11.1076 +
 11.1077 +static int
 11.1078 +e100_change_mtu(struct net_device *dev, int new_mtu)
 11.1079 +{
 11.1080 +	if ((new_mtu < 68) || (new_mtu > (ETH_DATA_LEN + VLAN_SIZE)))
 11.1081 +		return -EINVAL;
 11.1082 +
 11.1083 +	dev->mtu = new_mtu;
 11.1084 +	return 0;
 11.1085 +}
 11.1086 +
 11.1087 +static int
 11.1088 +e100_xmit_frame(struct sk_buff *skb, struct net_device *dev)
 11.1089 +{
 11.1090 +	int rc = 0;
 11.1091 +	int notify_stop = false;
 11.1092 +	struct e100_private *bdp = dev->priv;
 11.1093 +
 11.1094 +	if (!spin_trylock(&bdp->bd_non_tx_lock)) {
 11.1095 +		notify_stop = true;
 11.1096 +		rc = 1;
 11.1097 +		goto exit2;
 11.1098 +	}
 11.1099 +
 11.1100 +	if (!TCBS_AVAIL(bdp->tcb_pool) ||
 11.1101 +	    (bdp->non_tx_command_state != E100_NON_TX_IDLE)) {
 11.1102 +		notify_stop = true;
 11.1103 +		rc = 1;
 11.1104 +		goto exit1;
 11.1105 +	}
 11.1106 +
 11.1107 +	e100_prepare_xmit_buff(bdp, skb);
 11.1108 +
 11.1109 +	bdp->drv_stats.net_stats.tx_bytes += skb->len;
 11.1110 +
 11.1111 +	dev->trans_start = jiffies;
 11.1112 +
 11.1113 +exit1:
 11.1114 +	spin_unlock(&bdp->bd_non_tx_lock);
 11.1115 +exit2:
 11.1116 +	if (notify_stop) {
 11.1117 +		netif_stop_queue(dev);
 11.1118 +	}
 11.1119 +
 11.1120 +	return rc;
 11.1121 +}
 11.1122 +
 11.1123 +/**
 11.1124 + * e100_get_stats - get driver statistics
 11.1125 + * @dev: adapter's net_device struct
 11.1126 + *
 11.1127 + * This routine is called when the OS wants the adapter's stats returned.
 11.1128 + * It returns the address of the net_device_stats stucture for the device.
 11.1129 + * If the statistics are currently being updated, then they might be incorrect
 11.1130 + * for a short while. However, since this cannot actually cause damage, no
 11.1131 + * locking is used.
 11.1132 + */
 11.1133 +struct net_device_stats *
 11.1134 +e100_get_stats(struct net_device *dev)
 11.1135 +{
 11.1136 +	struct e100_private *bdp = dev->priv;
 11.1137 +
 11.1138 +	bdp->drv_stats.net_stats.tx_errors =
 11.1139 +		bdp->drv_stats.net_stats.tx_carrier_errors +
 11.1140 +		bdp->drv_stats.net_stats.tx_aborted_errors;
 11.1141 +
 11.1142 +	bdp->drv_stats.net_stats.rx_errors =
 11.1143 +		bdp->drv_stats.net_stats.rx_crc_errors +
 11.1144 +		bdp->drv_stats.net_stats.rx_frame_errors +
 11.1145 +		bdp->drv_stats.net_stats.rx_length_errors +
 11.1146 +		bdp->drv_stats.rcv_cdt_frames;
 11.1147 +
 11.1148 +	return &(bdp->drv_stats.net_stats);
 11.1149 +}
 11.1150 +
 11.1151 +/**
 11.1152 + * e100_set_mac - set the MAC address
 11.1153 + * @dev: adapter's net_device struct
 11.1154 + * @addr: the new address
 11.1155 + *
 11.1156 + * This routine sets the ethernet address of the board
 11.1157 + * Returns:
 11.1158 + * 0  - if successful
 11.1159 + * -1 - otherwise
 11.1160 + */
 11.1161 +static int
 11.1162 +e100_set_mac(struct net_device *dev, void *addr)
 11.1163 +{
 11.1164 +	struct e100_private *bdp;
 11.1165 +	int rc = -1;
 11.1166 +	struct sockaddr *p_sockaddr = (struct sockaddr *) addr;
 11.1167 +
 11.1168 +	if (!is_valid_ether_addr(p_sockaddr->sa_data))
 11.1169 +		return -EADDRNOTAVAIL;
 11.1170 +	bdp = dev->priv;
 11.1171 +
 11.1172 +	if (e100_setup_iaaddr(bdp, (u8 *) (p_sockaddr->sa_data))) {
 11.1173 +		memcpy(&(dev->dev_addr[0]), p_sockaddr->sa_data, ETH_ALEN);
 11.1174 +		rc = 0;
 11.1175 +	}
 11.1176 +
 11.1177 +	return rc;
 11.1178 +}
 11.1179 +
 11.1180 +static void
 11.1181 +e100_set_multi_exec(struct net_device *dev)
 11.1182 +{
 11.1183 +	struct e100_private *bdp = dev->priv;
 11.1184 +	mltcst_cb_t *mcast_buff;
 11.1185 +	cb_header_t *cb_hdr;
 11.1186 +	struct dev_mc_list *mc_list;
 11.1187 +	unsigned int i;
 11.1188 +	nxmit_cb_entry_t *cmd = e100_alloc_non_tx_cmd(bdp);
 11.1189 +
 11.1190 +	if (cmd != NULL) {
 11.1191 +		mcast_buff = &((cmd->non_tx_cmd)->ntcb.multicast);
 11.1192 +		cb_hdr = &((cmd->non_tx_cmd)->ntcb.multicast.mc_cbhdr);
 11.1193 +	} else {
 11.1194 +		return;
 11.1195 +	}
 11.1196 +
 11.1197 +	/* initialize the multi cast command */
 11.1198 +	cb_hdr->cb_cmd = __constant_cpu_to_le16(CB_MULTICAST);
 11.1199 +
 11.1200 +	/* now fill in the rest of the multicast command */
 11.1201 +	*(u16 *) (&(mcast_buff->mc_count)) = cpu_to_le16(dev->mc_count * 6);
 11.1202 +	for (i = 0, mc_list = dev->mc_list;
 11.1203 +	     (i < dev->mc_count) && (i < MAX_MULTICAST_ADDRS);
 11.1204 +	     i++, mc_list = mc_list->next) {
 11.1205 +		/* copy into the command */
 11.1206 +		memcpy(&(mcast_buff->mc_addr[i * ETH_ALEN]),
 11.1207 +		       (u8 *) &(mc_list->dmi_addr), ETH_ALEN);
 11.1208 +	}
 11.1209 +
 11.1210 +	if (!e100_exec_non_cu_cmd(bdp, cmd)) {
 11.1211 +		printk(KERN_WARNING "e100: %s: Multicast setup failed\n", 
 11.1212 +		       dev->name);
 11.1213 +	}
 11.1214 +}
 11.1215 +
 11.1216 +/**
 11.1217 + * e100_set_multi - set multicast status
 11.1218 + * @dev: adapter's net_device struct
 11.1219 + *
 11.1220 + * This routine is called to add or remove multicast addresses, and/or to
 11.1221 + * change the adapter's promiscuous state.
 11.1222 + */
 11.1223 +static void
 11.1224 +e100_set_multi(struct net_device *dev)
 11.1225 +{
 11.1226 +	struct e100_private *bdp = dev->priv;
 11.1227 +	unsigned char promisc_enbl;
 11.1228 +	unsigned char mulcast_enbl;
 11.1229 +
 11.1230 +	promisc_enbl = ((dev->flags & IFF_PROMISC) == IFF_PROMISC);
 11.1231 +	mulcast_enbl = ((dev->flags & IFF_ALLMULTI) ||
 11.1232 +			(dev->mc_count > MAX_MULTICAST_ADDRS));
 11.1233 +
 11.1234 +	e100_config_promisc(bdp, promisc_enbl);
 11.1235 +	e100_config_mulcast_enbl(bdp, mulcast_enbl);
 11.1236 +
 11.1237 +	/* reconfigure the chip if something has changed in its config space */
 11.1238 +	e100_config(bdp);
 11.1239 +
 11.1240 +	if (promisc_enbl || mulcast_enbl) {
 11.1241 +		return;	/* no need for Multicast Cmd */
 11.1242 +	}
 11.1243 +
 11.1244 +	/* get the multicast CB */
 11.1245 +	e100_set_multi_exec(dev);
 11.1246 +}
 11.1247 +
 11.1248 +#if 0
 11.1249 +static int
 11.1250 +e100_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 11.1251 +{
 11.1252 +
 11.1253 +	switch (cmd) {
 11.1254 +
 11.1255 +	case SIOCETHTOOL:
 11.1256 +		return e100_do_ethtool_ioctl(dev, ifr);
 11.1257 +		break;
 11.1258 +
 11.1259 +	case SIOCGMIIPHY:	/* Get address of MII PHY in use. */
 11.1260 +	case SIOCGMIIREG:	/* Read MII PHY register. */
 11.1261 +	case SIOCSMIIREG:	/* Write to MII PHY register. */
 11.1262 +		return e100_mii_ioctl(dev, ifr, cmd);
 11.1263 +		break;
 11.1264 +
 11.1265 +	default:
 11.1266 +		return -EOPNOTSUPP;
 11.1267 +	}
 11.1268 +	return 0;
 11.1269 +
 11.1270 +}
 11.1271 +#endif
 11.1272 +
 11.1273 +/**
 11.1274 + * e100init - initialize the adapter
 11.1275 + * @bdp: atapter's private data struct
 11.1276 + *
 11.1277 + * This routine is called when this driver is loaded. This is the initialization
 11.1278 + * routine which allocates memory, configures the adapter and determines the
 11.1279 + * system resources.
 11.1280 + *
 11.1281 + * Returns:
 11.1282 + *      true: if successful
 11.1283 + *      false: otherwise
 11.1284 + */
 11.1285 +static unsigned char __devinit
 11.1286 +e100_init(struct e100_private *bdp)
 11.1287 +{
 11.1288 +	u32 st_timeout = 0;
 11.1289 +	u32 st_result = 0;
 11.1290 +	e100_sw_init(bdp);
 11.1291 +
 11.1292 +	if (!e100_selftest(bdp, &st_timeout, &st_result)) {
 11.1293 +        	if (st_timeout) {
 11.1294 +			printk(KERN_ERR "e100: selftest timeout\n");
 11.1295 +		} else {
 11.1296 +			printk(KERN_ERR "e100: selftest failed. Results: %x\n",
 11.1297 +					st_result);
 11.1298 +		}
 11.1299 +		return false;
 11.1300 +	}
 11.1301 +	else
 11.1302 +		printk(KERN_DEBUG "e100: selftest OK.\n");
 11.1303 +
 11.1304 +	/* read the MAC address from the eprom */
 11.1305 +	e100_rd_eaddr(bdp);
 11.1306 +	if (!is_valid_ether_addr(bdp->device->dev_addr)) {
 11.1307 +		printk(KERN_ERR "e100: Invalid Ethernet address\n");
 11.1308 +		return false;
 11.1309 +	}
 11.1310 +	/* read NIC's part number */
 11.1311 +	e100_rd_pwa_no(bdp);
 11.1312 +
 11.1313 +	if (!e100_hw_init(bdp)) {
 11.1314 +		printk(KERN_ERR "e100: hw init failed\n");
 11.1315 +		return false;
 11.1316 +	}
 11.1317 +	/* Interrupts are enabled after device reset */
 11.1318 +	e100_disable_clear_intr(bdp);
 11.1319 +
 11.1320 +	return true;
 11.1321 +}
 11.1322 +
 11.1323 +/**
 11.1324 + * e100_sw_init - initialize software structs
 11.1325 + * @bdp: atapter's private data struct
 11.1326 + * 
 11.1327 + * This routine initializes all software structures. Sets up the
 11.1328 + * circular structures for the RFD's & TCB's. Allocates the per board
 11.1329 + * structure for storing adapter information. The CSR is also memory 
 11.1330 + * mapped in this routine.
 11.1331 + *
 11.1332 + * Returns :
 11.1333 + *      true: if S/W was successfully initialized
 11.1334 + *      false: otherwise
 11.1335 + */
 11.1336 +static unsigned char __devinit
 11.1337 +e100_sw_init(struct e100_private *bdp)
 11.1338 +{
 11.1339 +	bdp->next_cu_cmd = START_WAIT;	// init the next cu state
 11.1340 +
 11.1341 +	/* 
 11.1342 +	 * Set the value for # of good xmits per underrun. the value assigned
 11.1343 +	 * here is an intelligent  suggested default. Nothing magical about it.
 11.1344 +	 */
 11.1345 +	bdp->tx_per_underrun = DEFAULT_TX_PER_UNDERRUN;
 11.1346 +
 11.1347 +	/* get the default transmit threshold value */
 11.1348 +	bdp->tx_thld = TX_THRSHLD;
 11.1349 +
 11.1350 +	/* get the EPROM size */
 11.1351 +	bdp->eeprom_size = e100_eeprom_size(bdp);
 11.1352 +
 11.1353 +	/* Initialize our spinlocks */
 11.1354 +	spin_lock_init(&(bdp->bd_lock));
 11.1355 +	spin_lock_init(&(bdp->bd_non_tx_lock));
 11.1356 +	spin_lock_init(&(bdp->config_lock));
 11.1357 +	spin_lock_init(&(bdp->mdi_access_lock));
 11.1358 +
 11.1359 +	return 1;
 11.1360 +}
 11.1361 +
 11.1362 +static void __devinit
 11.1363 +e100_tco_workaround(struct e100_private *bdp)
 11.1364 +{
 11.1365 +	int i;
 11.1366 +
 11.1367 +	/* Do software reset */
 11.1368 +	e100_sw_reset(bdp, PORT_SOFTWARE_RESET);
 11.1369 +
 11.1370 +	/* Do a dummy LOAD CU BASE command. */
 11.1371 +	/* This gets us out of pre-driver to post-driver. */
 11.1372 +	e100_exec_cmplx(bdp, 0, SCB_CUC_LOAD_BASE);
 11.1373 +
 11.1374 +	/* Wait 20 msec for reset to take effect */
 11.1375 +	set_current_state(TASK_UNINTERRUPTIBLE);
 11.1376 +	schedule_timeout(HZ / 50 + 1);
 11.1377 +
 11.1378 +	/* disable interrupts since they are enabled */
 11.1379 +	/* after device reset                        */
 11.1380 +	e100_disable_clear_intr(bdp);
 11.1381 +
 11.1382 +	/* Wait for command to be cleared up to 1 sec */
 11.1383 +	for (i=0; i<100; i++) {
 11.1384 +		if (!readb(&bdp->scb->scb_cmd_low))
 11.1385 +			break;
 11.1386 +		set_current_state(TASK_UNINTERRUPTIBLE);
 11.1387 +		schedule_timeout(HZ / 100 + 1);
 11.1388 +	}
 11.1389 +
 11.1390 +	/* Wait for TCO request bit in PMDR register to be clear */
 11.1391 +	for (i=0; i<50; i++) {
 11.1392 +		if (!(readb(&bdp->scb->scb_ext.d101m_scb.scb_pmdr) & BIT_1))
 11.1393 +			break;
 11.1394 +		set_current_state(TASK_UNINTERRUPTIBLE);
 11.1395 +		schedule_timeout(HZ / 100 + 1);
 11.1396 +	}
 11.1397 +}
 11.1398 +
 11.1399 +/**
 11.1400 + * e100_hw_init - initialized tthe hardware
 11.1401 + * @bdp: atapter's private data struct
 11.1402 + *
 11.1403 + * This routine performs a reset on the adapter, and configures the adapter.
 11.1404 + * This includes configuring the 82557 LAN controller, validating and setting
 11.1405 + * the node address, detecting and configuring the Phy chip on the adapter,
 11.1406 + * and initializing all of the on chip counters.
 11.1407 + *
 11.1408 + * Returns:
 11.1409 + *      true - If the adapter was initialized
 11.1410 + *      false - If the adapter failed initialization
 11.1411 + */
 11.1412 +unsigned char __devinit
 11.1413 +e100_hw_init(struct e100_private *bdp)
 11.1414 +{
 11.1415 +	if (!e100_phy_init(bdp))
 11.1416 +		return false;
 11.1417 +
 11.1418 +	e100_sw_reset(bdp, PORT_SELECTIVE_RESET);
 11.1419 +
 11.1420 +	/* Only 82559 or above needs TCO workaround */
 11.1421 +	if (bdp->rev_id >= D101MA_REV_ID)
 11.1422 +		e100_tco_workaround(bdp);
 11.1423 +
 11.1424 +	/* Load the CU BASE (set to 0, because we use linear mode) */
 11.1425 +	if (!e100_wait_exec_cmplx(bdp, 0, SCB_CUC_LOAD_BASE, 0))
 11.1426 +		return false;
 11.1427 +
 11.1428 +	if (!e100_wait_exec_cmplx(bdp, 0, SCB_RUC_LOAD_BASE, 0))
 11.1429 +		return false;
 11.1430 +
 11.1431 +	/* Load interrupt microcode  */
 11.1432 +	if (e100_load_microcode(bdp)) {
 11.1433 +		bdp->flags |= DF_UCODE_LOADED;
 11.1434 +	}
 11.1435 +
 11.1436 +	e100_config_init(bdp);
 11.1437 +	if (!e100_config(bdp)) {
 11.1438 +		return false;
 11.1439 +	}
 11.1440 +
 11.1441 +	if (!e100_setup_iaaddr(bdp, bdp->device->dev_addr))
 11.1442 +		return false;
 11.1443 +
 11.1444 +	/* Clear the internal counters */
 11.1445 +	if (!e100_clr_cntrs(bdp))
 11.1446 +		return false;
 11.1447 +
 11.1448 +	/* Change for 82558 enhancement */
 11.1449 +	/* If 82558/9 and if the user has enabled flow control, set up the
 11.1450 +	 * Flow Control Reg. in the CSR */
 11.1451 +	if ((bdp->flags & IS_BACHELOR)
 11.1452 +	    && (bdp->params.b_params & PRM_FC)) {
 11.1453 +		writeb(DFLT_FC_THLD, &bdp->scb->scb_ext.d101_scb.scb_fc_thld);
 11.1454 +		writeb(DFLT_FC_CMD,
 11.1455 +		       &bdp->scb->scb_ext.d101_scb.scb_fc_xon_xoff);
 11.1456 +	}
 11.1457 +
 11.1458 +	return true;
 11.1459 +}
 11.1460 +
 11.1461 +/**
 11.1462 + * e100_setup_tcb_pool - setup TCB circular list
 11.1463 + * @head: Pointer to head of the allocated TCBs
 11.1464 + * @qlen: Number of elements in the queue
 11.1465 + * @bdp: atapter's private data struct
 11.1466 + * 
 11.1467 + * This routine arranges the contigiously allocated TCB's in a circular list.
 11.1468 + * Also does the one time initialization of the TCBs.
 11.1469 + */
 11.1470 +static void
 11.1471 +e100_setup_tcb_pool(tcb_t *head, unsigned int qlen, struct e100_private *bdp)
 11.1472 +{
 11.1473 +	int ele_no;
 11.1474 +	tcb_t *pcurr_tcb;	/* point to current tcb */
 11.1475 +	u32 next_phys;		/* the next phys addr */
 11.1476 +	u16 txcommand = CB_S_BIT | CB_TX_SF_BIT;
 11.1477 +
 11.1478 +	bdp->tx_count = 0;
 11.1479 +	if (bdp->flags & USE_IPCB) {
 11.1480 +		txcommand |= CB_IPCB_TRANSMIT | CB_CID_DEFAULT;
 11.1481 +	} else if (bdp->flags & IS_BACHELOR) {
 11.1482 +		txcommand |= CB_TRANSMIT | CB_CID_DEFAULT;
 11.1483 +	} else {
 11.1484 +		txcommand |= CB_TRANSMIT;
 11.1485 +	}
 11.1486 +
 11.1487 +	for (ele_no = 0, next_phys = bdp->tcb_phys, pcurr_tcb = head;
 11.1488 +	     ele_no < qlen; ele_no++, pcurr_tcb++) {
 11.1489 +
 11.1490 +		/* set the phys addr for this TCB, next_phys has not incr. yet */
 11.1491 +		pcurr_tcb->tcb_phys = next_phys;
 11.1492 +		next_phys += sizeof (tcb_t);
 11.1493 +
 11.1494 +		/* set the link to next tcb */
 11.1495 +		if (ele_no == (qlen - 1))
 11.1496 +			pcurr_tcb->tcb_hdr.cb_lnk_ptr =
 11.1497 +				cpu_to_le32(bdp->tcb_phys);
 11.1498 +		else
 11.1499 +			pcurr_tcb->tcb_hdr.cb_lnk_ptr = cpu_to_le32(next_phys);
 11.1500 +
 11.1501 +		pcurr_tcb->tcb_hdr.cb_status = 0;
 11.1502 +		pcurr_tcb->tcb_hdr.cb_cmd = cpu_to_le16(txcommand);
 11.1503 +		pcurr_tcb->tcb_cnt = 0;	
 11.1504 +		pcurr_tcb->tcb_thrshld = bdp->tx_thld;	
 11.1505 +		if (ele_no < 2) {
 11.1506 +			pcurr_tcb->tcb_hdr.cb_status =
 11.1507 +				cpu_to_le16(CB_STATUS_COMPLETE);
 11.1508 +		}
 11.1509 +		pcurr_tcb->tcb_tbd_num = 1;
 11.1510 +
 11.1511 +		if (bdp->flags & IS_BACHELOR) {
 11.1512 +			pcurr_tcb->tcb_tbd_ptr =
 11.1513 +				__constant_cpu_to_le32(0xFFFFFFFF);
 11.1514 +		} else {
 11.1515 +			pcurr_tcb->tcb_tbd_ptr =
 11.1516 +				cpu_to_le32(pcurr_tcb->tcb_phys + 0x10);
 11.1517 +		}
 11.1518 +
 11.1519 +		if (bdp->flags & IS_BACHELOR) {
 11.1520 +			pcurr_tcb->tcb_tbd_expand_ptr =
 11.1521 +				cpu_to_le32(pcurr_tcb->tcb_phys + 0x20);
 11.1522 +		} else {
 11.1523 +			pcurr_tcb->tcb_tbd_expand_ptr =
 11.1524 +				cpu_to_le32(pcurr_tcb->tcb_phys + 0x10);
 11.1525 +		}
 11.1526 +		pcurr_tcb->tcb_tbd_dflt_ptr = pcurr_tcb->tcb_tbd_ptr;
 11.1527 +
 11.1528 +		if (bdp->flags & USE_IPCB) {
 11.1529 +			pcurr_tcb->tbd_ptr = &(pcurr_tcb->tcbu.tbd_array[1]);
 11.1530 +			pcurr_tcb->tcbu.ipcb.ip_activation_high =
 11.1531 +				IPCB_IP_ACTIVATION_DEFAULT;
 11.1532 +			pcurr_tcb->tcbu.ipcb.vlan = 0;
 11.1533 +		} else {
 11.1534 +			pcurr_tcb->tbd_ptr = &(pcurr_tcb->tcbu.tbd_array[0]);
 11.1535 +		}
 11.1536 +
 11.1537 +		pcurr_tcb->tcb_skb = NULL;
 11.1538 +	}
 11.1539 +
 11.1540 +	wmb();
 11.1541 +}
 11.1542 +
 11.1543 +/***************************************************************************/
 11.1544 +/***************************************************************************/
 11.1545 +/*       Memory Management Routines                                        */
 11.1546 +/***************************************************************************/
 11.1547 +
 11.1548 +/**
 11.1549 + * e100_alloc_space - allocate private driver data
 11.1550 + * @bdp: atapter's private data struct
 11.1551 + *
 11.1552 + * This routine allocates memory for the driver. Memory allocated is for the
 11.1553 + * selftest and statistics structures.
 11.1554 + *
 11.1555 + * Returns:
 11.1556 + *      0: if the operation was successful
 11.1557 + *      %-ENOMEM: if memory allocation failed
 11.1558 + */
 11.1559 +unsigned char __devinit
 11.1560 +e100_alloc_space(struct e100_private *bdp)
 11.1561 +{
 11.1562 +	unsigned long off;
 11.1563 +
 11.1564 +	/* allocate all the dma-able structures in one call:
 11.1565 +	 * selftest results, adapter stats, and non-tx cb commands */
 11.1566 +	if (!(bdp->dma_able =
 11.1567 +	      pci_alloc_consistent(bdp->pdev, sizeof (bd_dma_able_t),
 11.1568 +				   &(bdp->dma_able_phys)))) {
 11.1569 +		goto err;
 11.1570 +	}
 11.1571 +
 11.1572 +	/* now assign the various pointers into the struct we've just allocated */
 11.1573 +	off = offsetof(bd_dma_able_t, selftest);
 11.1574 +
 11.1575 +	bdp->selftest = (self_test_t *) (bdp->dma_able + off);
 11.1576 +	bdp->selftest_phys = bdp->dma_able_phys + off;
 11.1577 +
 11.1578 +	off = offsetof(bd_dma_able_t, stats_counters);
 11.1579 +
 11.1580 +	bdp->stats_counters = (max_counters_t *) (bdp->dma_able + off);
 11.1581 +	bdp->stat_cnt_phys = bdp->dma_able_phys + off;
 11.1582 +
 11.1583 +	return 0;
 11.1584 +
 11.1585 +err:
 11.1586 +	printk(KERN_ERR
 11.1587 +	       "e100: Failed to allocate memory\n");
 11.1588 +	return -ENOMEM;
 11.1589 +}
 11.1590 +
 11.1591 +/**
 11.1592 + * e100_alloc_tcb_pool - allocate TCB circular list
 11.1593 + * @bdp: atapter's private data struct
 11.1594 + *
 11.1595 + * This routine allocates memory for the circular list of transmit descriptors.
 11.1596 + *
 11.1597 + * Returns:
 11.1598 + *       0: if allocation has failed.
 11.1599 + *       1: Otherwise. 
 11.1600 + */
 11.1601 +int
 11.1602 +e100_alloc_tcb_pool(struct e100_private *bdp)
 11.1603 +{
 11.1604 +	int stcb = sizeof (tcb_t) * bdp->params.TxDescriptors;
 11.1605 +
 11.1606 +	/* allocate space for the TCBs */
 11.1607 +	if (!(bdp->tcb_pool.data =
 11.1608 +	      pci_alloc_consistent(bdp->pdev, stcb, &bdp->tcb_phys)))
 11.1609 +		return 0;
 11.1610 +
 11.1611 +	memset(bdp->tcb_pool.data, 0x00, stcb);
 11.1612 +
 11.1613 +	return 1;
 11.1614 +}
 11.1615 +
 11.1616 +void
 11.1617 +e100_free_tcb_pool(struct e100_private *bdp)
 11.1618 +{
 11.1619 +	pci_free_consistent(bdp->pdev,
 11.1620 +			    sizeof (tcb_t) * bdp->params.TxDescriptors,
 11.1621 +			    bdp->tcb_pool.data, bdp->tcb_phys);
 11.1622 +	bdp->tcb_phys = 0;
 11.1623 +}
 11.1624 +
 11.1625 +static void
 11.1626 +e100_dealloc_space(struct e100_private *bdp)
 11.1627 +{
 11.1628 +	if (bdp->dma_able) {
 11.1629 +		pci_free_consistent(bdp->pdev, sizeof (bd_dma_able_t),
 11.1630 +				    bdp->dma_able, bdp->dma_able_phys);
 11.1631 +	}
 11.1632 +
 11.1633 +	bdp->selftest_phys = 0;
 11.1634 +	bdp->stat_cnt_phys = 0;
 11.1635 +	bdp->dma_able_phys = 0;
 11.1636 +	bdp->dma_able = 0;
 11.1637 +}
 11.1638 +
 11.1639 +static void
 11.1640 +e100_free_rfd_pool(struct e100_private *bdp)
 11.1641 +{
 11.1642 +	struct rx_list_elem *rx_struct;
 11.1643 +
 11.1644 +	while (!list_empty(&(bdp->active_rx_list))) {
 11.1645 +
 11.1646 +		rx_struct = list_entry(bdp->active_rx_list.next,
 11.1647 +				       struct rx_list_elem, list_elem);
 11.1648 +		list_del(&(rx_struct->list_elem));
 11.1649 +		pci_unmap_single(bdp->pdev, rx_struct->dma_addr,
 11.1650 +				 sizeof (rfd_t), PCI_DMA_TODEVICE);
 11.1651 +		dev_kfree_skb(rx_struct->skb);
 11.1652 +		kfree(rx_struct);
 11.1653 +	}
 11.1654 +
 11.1655 +	while (!list_empty(&(bdp->rx_struct_pool))) {
 11.1656 +		rx_struct = list_entry(bdp->rx_struct_pool.next,
 11.1657 +				       struct rx_list_elem, list_elem);
 11.1658 +		list_del(&(rx_struct->list_elem));
 11.1659 +		kfree(rx_struct);
 11.1660 +	}
 11.1661 +}
 11.1662 +
 11.1663 +/**
 11.1664 + * e100_alloc_rfd_pool - allocate RFDs
 11.1665 + * @bdp: atapter's private data struct
 11.1666 + *
 11.1667 + * Allocates initial pool of skb which holds both rfd and data,
 11.1668 + * and return a pointer to the head of the list
 11.1669 + */
 11.1670 +static int
 11.1671 +e100_alloc_rfd_pool(struct e100_private *bdp)
 11.1672 +{
 11.1673 +	struct rx_list_elem *rx_struct;
 11.1674 +	int i;
 11.1675 +
 11.1676 +	INIT_LIST_HEAD(&(bdp->active_rx_list));
 11.1677 +	INIT_LIST_HEAD(&(bdp->rx_struct_pool));
 11.1678 +	bdp->skb_req = bdp->params.RxDescriptors;
 11.1679 +	for (i = 0; i < bdp->skb_req; i++) {
 11.1680 +		rx_struct = kmalloc(sizeof (struct rx_list_elem), GFP_ATOMIC);
 11.1681 +		list_add(&(rx_struct->list_elem), &(bdp->rx_struct_pool));
 11.1682 +	}
 11.1683 +	e100_alloc_skbs(bdp);
 11.1684 +	return !list_empty(&(bdp->active_rx_list));
 11.1685 +
 11.1686 +}
 11.1687 +
 11.1688 +void
 11.1689 +e100_clear_pools(struct e100_private *bdp)
 11.1690 +{
 11.1691 +	bdp->last_tcb = NULL;
 11.1692 +	e100_free_rfd_pool(bdp);
 11.1693 +	e100_free_tcb_pool(bdp);
 11.1694 +}
 11.1695 +
 11.1696 +/*****************************************************************************/
 11.1697 +/*****************************************************************************/
 11.1698 +/*      Run Time Functions                                                   */
 11.1699 +/*****************************************************************************/
 11.1700 +
 11.1701 +/**
 11.1702 + * e100_watchdog
 11.1703 + * @dev: adapter's net_device struct
 11.1704 + *
 11.1705 + * This routine runs every 2 seconds and updates our statitics and link state,
 11.1706 + * and refreshs txthld value.
 11.1707 + */
 11.1708 +void
 11.1709 +e100_watchdog(struct net_device *dev)
 11.1710 +{
 11.1711 +	struct e100_private *bdp = dev->priv;
 11.1712 +
 11.1713 +#ifdef E100_CU_DEBUG
 11.1714 +	if (e100_cu_unknown_state(bdp)) {
 11.1715 +		printk(KERN_ERR "e100: %s: CU unknown state in e100_watchdog\n",
 11.1716 +			dev->name);
 11.1717 +	}
 11.1718 +#endif	
 11.1719 +	if (!netif_running(dev)) {
 11.1720 +		return;
 11.1721 +	}
 11.1722 +
 11.1723 +	/* check if link state has changed */
 11.1724 +	if (e100_phy_check(bdp)) {
 11.1725 +		if (netif_carrier_ok(dev)) {
 11.1726 +			printk(KERN_ERR
 11.1727 +			       "e100: %s NIC Link is Up %d Mbps %s duplex\n",
 11.1728 +			       bdp->device->name, bdp->cur_line_speed,
 11.1729 +			       (bdp->cur_dplx_mode == HALF_DUPLEX) ?
 11.1730 +			       "Half" : "Full");
 11.1731 +
 11.1732 +			e100_config_fc(bdp);
 11.1733 +			e100_config(bdp);  
 11.1734 +
 11.1735 +		} else {
 11.1736 +			printk(KERN_ERR "e100: %s NIC Link is Down\n",
 11.1737 +			       bdp->device->name);
 11.1738 +		}
 11.1739 +	}
 11.1740 +
 11.1741 +	// toggle the tx queue according to link status
 11.1742 +	// this also resolves a race condition between tx & non-cu cmd flows
 11.1743 +	if (netif_carrier_ok(dev)) {
 11.1744 +		if (netif_running(dev))
 11.1745 +			netif_wake_queue(dev);
 11.1746 +	} else {
 11.1747 +		if (netif_running(dev))
 11.1748 +			netif_stop_queue(dev);
 11.1749 +		/* When changing to non-autoneg, device may lose  */
 11.1750 +		/* link with some switches. e100 will try to      */
 11.1751 +		/* revover link by sending command to PHY layer   */
 11.1752 +		if (bdp->params.e100_speed_duplex != E100_AUTONEG)
 11.1753 +			e100_force_speed_duplex_to_phy(bdp);
 11.1754 +	}
 11.1755 +
 11.1756 +	rmb();
 11.1757 +
 11.1758 +	if (e100_update_stats(bdp)) {
 11.1759 +
 11.1760 +		/* Check if a change in the IFS parameter is needed,
 11.1761 +		   and configure the device accordingly */
 11.1762 +		if (bdp->params.b_params & PRM_IFS)
 11.1763 +			e100_manage_adaptive_ifs(bdp);
 11.1764 +
 11.1765 +		/* Now adjust our dynamic tx threshold value */
 11.1766 +		e100_refresh_txthld(bdp);
 11.1767 +
 11.1768 +		/* Now if we are on a 557 and we havn't received any frames then we
 11.1769 +		 * should issue a multicast command to reset the RU */
 11.1770 +		if (bdp->rev_id < D101A4_REV_ID) {
 11.1771 +			if (!(bdp->stats_counters->basic_stats.rcv_gd_frames)) {
 11.1772 +				e100_set_multi(dev);
 11.1773 +			}
 11.1774 +		}
 11.1775 +
 11.1776 +		/* Update the statistics needed by the upper interface */
 11.1777 +		/* This should be the last statistic related command
 11.1778 +		 * as it's async. now */
 11.1779 +		e100_dump_stats_cntrs(bdp);
 11.1780 +	}
 11.1781 +
 11.1782 +	wmb();
 11.1783 +
 11.1784 +	/* relaunch watchdog timer in 2 sec */
 11.1785 +	mod_timer(&(bdp->watchdog_timer), jiffies + (2 * HZ));
 11.1786 +
 11.1787 +	if (list_empty(&bdp->active_rx_list))
 11.1788 +		e100_trigger_SWI(bdp);
 11.1789 +}
 11.1790 +
 11.1791 +/**
 11.1792 + * e100_manage_adaptive_ifs
 11.1793 + * @bdp: atapter's private data struct
 11.1794 + *
 11.1795 + * This routine manages the adaptive Inter-Frame Spacing algorithm
 11.1796 + * using a state machine.
 11.1797 + */
 11.1798 +void
 11.1799 +e100_manage_adaptive_ifs(struct e100_private *bdp)
 11.1800 +{
 11.1801 +	static u16 state_table[9][4] = {	// rows are states
 11.1802 +		{2, 0, 0, 0},	// state0   // column0: next state if increasing
 11.1803 +		{2, 0, 5, 30},	// state1   // column1: next state if decreasing
 11.1804 +		{5, 1, 5, 30},	// state2   // column2: IFS value for 100 mbit
 11.1805 +		{5, 3, 0, 0},	// state3   // column3: IFS value for 10 mbit
 11.1806 +		{5, 3, 10, 60},	// state4
 11.1807 +		{8, 4, 10, 60},	// state5
 11.1808 +		{8, 6, 0, 0},	// state6
 11.1809 +		{8, 6, 20, 60},	// state7
 11.1810 +		{8, 7, 20, 60}	// state8
 11.1811 +	};
 11.1812 +
 11.1813 +	u32 transmits =
 11.1814 +		le32_to_cpu(bdp->stats_counters->basic_stats.xmt_gd_frames);
 11.1815 +	u32 collisions =
 11.1816 +		le32_to_cpu(bdp->stats_counters->basic_stats.xmt_ttl_coll);
 11.1817 +	u32 state = bdp->ifs_state;
 11.1818 +	u32 old_value = bdp->ifs_value;
 11.1819 +	int next_col;
 11.1820 +	u32 min_transmits;
 11.1821 +
 11.1822 +	if (bdp->cur_dplx_mode == FULL_DUPLEX) {
 11.1823 +		bdp->ifs_state = 0;
 11.1824 +		bdp->ifs_value = 0;
 11.1825 +
 11.1826 +	} else {		/* Half Duplex */
 11.1827 +		/* Set speed specific parameters */
 11.1828 +		if (bdp->cur_line_speed == 100) {
 11.1829 +			next_col = 2;
 11.1830 +			min_transmits = MIN_NUMBER_OF_TRANSMITS_100;
 11.1831 +
 11.1832 +		} else {	/* 10 Mbps */
 11.1833 +			next_col = 3;
 11.1834 +			min_transmits = MIN_NUMBER_OF_TRANSMITS_10;
 11.1835 +		}
 11.1836 +
 11.1837 +		if ((transmits / 32 < collisions)
 11.1838 +		    && (transmits > min_transmits)) {
 11.1839 +			state = state_table[state][0];	/* increment */
 11.1840 +
 11.1841 +		} else if (transmits < min_transmits) {
 11.1842 +			state = state_table[state][1];	/* decrement */
 11.1843 +		}
 11.1844 +
 11.1845 +		bdp->ifs_value = state_table[state][next_col];
 11.1846 +		bdp->ifs_state = state;
 11.1847 +	}
 11.1848 +
 11.1849 +	/* If the IFS value has changed, configure the device */
 11.1850 +	if (bdp->ifs_value != old_value) {
 11.1851 +		e100_config_ifs(bdp);
 11.1852 +		e100_config(bdp);
 11.1853 +	}
 11.1854 +}
 11.1855 +
 11.1856 +/**
 11.1857 + * e100intr - interrupt handler
 11.1858 + * @irq: the IRQ number
 11.1859 + * @dev_inst: the net_device struct
 11.1860 + * @regs: registers (unused)
 11.1861 + *
 11.1862 + * This routine is the ISR for the e100 board. It services
 11.1863 + * the RX & TX queues & starts the RU if it has stopped due
 11.1864 + * to no resources.
 11.1865 + */
 11.1866 +void
 11.1867 +e100intr(int irq, void *dev_inst, struct pt_regs *regs)
 11.1868 +{
 11.1869 +	struct net_device *dev;
 11.1870 +	struct e100_private *bdp;
 11.1871 +	u16 intr_status;
 11.1872 +
 11.1873 +	dev = dev_inst;
 11.1874 +	bdp = dev->priv;
 11.1875 +
 11.1876 +	intr_status = readw(&bdp->scb->scb_status);
 11.1877 +	/* If not my interrupt, just return */
 11.1878 +	if (!(intr_status & SCB_STATUS_ACK_MASK) || (intr_status == 0xffff)) {
 11.1879 +		return;
 11.1880 +	}
 11.1881 +
 11.1882 +	/* disable and ack intr */
 11.1883 +	e100_disable_clear_intr(bdp);
 11.1884 +
 11.1885 +	/* the device is closed, don't continue or else bad things may happen. */
 11.1886 +	if (!netif_running(dev)) {
 11.1887 +		e100_set_intr_mask(bdp);
 11.1888 +		return;
 11.1889 +	}
 11.1890 +
 11.1891 +	/* SWI intr (triggered by watchdog) is signal to allocate new skb buffers */
 11.1892 +	if (intr_status & SCB_STATUS_ACK_SWI) {
 11.1893 +		e100_alloc_skbs(bdp);
 11.1894 +	}
 11.1895 +
 11.1896 +	/* do recv work if any */
 11.1897 +	if (intr_status &
 11.1898 +	    (SCB_STATUS_ACK_FR | SCB_STATUS_ACK_RNR | SCB_STATUS_ACK_SWI)) 
 11.1899 +		bdp->drv_stats.rx_intr_pkts += e100_rx_srv(bdp);
 11.1900 +
 11.1901 +	/* clean up after tx'ed packets */
 11.1902 +	if (intr_status & (SCB_STATUS_ACK_CNA | SCB_STATUS_ACK_CX))
 11.1903 +		e100_tx_srv(bdp);
 11.1904 +
 11.1905 +	e100_set_intr_mask(bdp);
 11.1906 +}
 11.1907 +
 11.1908 +/**
 11.1909 + * e100_tx_skb_free - free TX skbs resources
 11.1910 + * @bdp: atapter's private data struct
 11.1911 + * @tcb: associated tcb of the freed skb
 11.1912 + *
 11.1913 + * This routine frees resources of TX skbs.
 11.1914 + */
 11.1915 +static inline void
 11.1916 +e100_tx_skb_free(struct e100_private *bdp, tcb_t *tcb)
 11.1917 +{
 11.1918 +	if (tcb->tcb_skb) {
 11.1919 +		int i;
 11.1920 +		tbd_t *tbd_arr = tcb->tbd_ptr;
 11.1921 +		int frags = skb_shinfo(tcb->tcb_skb)->nr_frags;
 11.1922 +
 11.1923 +		for (i = 0; i <= frags; i++, tbd_arr++) {
 11.1924 +			pci_unmap_single(bdp->pdev,
 11.1925 +					 le32_to_cpu(tbd_arr->tbd_buf_addr),
 11.1926 +					 le16_to_cpu(tbd_arr->tbd_buf_cnt),
 11.1927 +					 PCI_DMA_TODEVICE);
 11.1928 +		}
 11.1929 +		dev_kfree_skb_irq(tcb->tcb_skb);
 11.1930 +		tcb->tcb_skb = NULL;
 11.1931 +	}
 11.1932 +}
 11.1933 +
 11.1934 +/**
 11.1935 + * e100_tx_srv - service TX queues
 11.1936 + * @bdp: atapter's private data struct
 11.1937 + *
 11.1938 + * This routine services the TX queues. It reclaims the TCB's & TBD's & other
 11.1939 + * resources used during the transmit of this buffer. It is called from the ISR.
 11.1940 + * We don't need a tx_lock since we always access buffers which were already
 11.1941 + * prepared.
 11.1942 + */
 11.1943 +void
 11.1944 +e100_tx_srv(struct e100_private *bdp)
 11.1945 +{
 11.1946 +	tcb_t *tcb;
 11.1947 +	int i;
 11.1948 +
 11.1949 +	/* go over at most TxDescriptors buffers */
 11.1950 +	for (i = 0; i < bdp->params.TxDescriptors; i++) {
 11.1951 +		tcb = bdp->tcb_pool.data;
 11.1952 +		tcb += bdp->tcb_pool.head;
 11.1953 +
 11.1954 +		rmb();
 11.1955 +
 11.1956 +		/* if the buffer at 'head' is not complete, break */
 11.1957 +		if (!(tcb->tcb_hdr.cb_status &
 11.1958 +		      __constant_cpu_to_le16(CB_STATUS_COMPLETE)))
 11.1959 +			break;
 11.1960 +
 11.1961 +		/* service next buffer, clear the out of resource condition */
 11.1962 +		e100_tx_skb_free(bdp, tcb);
 11.1963 +
 11.1964 +		if (netif_running(bdp->device))
 11.1965 +			netif_wake_queue(bdp->device);
 11.1966 +
 11.1967 +		/* if we've caught up with 'tail', break */
 11.1968 +		if (NEXT_TCB_TOUSE(bdp->tcb_pool.head) == bdp->tcb_pool.tail) {
 11.1969 +			break;
 11.1970 +		}
 11.1971 +
 11.1972 +		bdp->tcb_pool.head = NEXT_TCB_TOUSE(bdp->tcb_pool.head);
 11.1973 +	}
 11.1974 +}
 11.1975 +
 11.1976 +/**
 11.1977 + * e100_rx_srv - service RX queue
 11.1978 + * @bdp: atapter's private data struct
 11.1979 + * @max_number_of_rfds: max number of RFDs to process
 11.1980 + * @rx_congestion: flag pointer, to inform the calling function of congestion.
 11.1981 + *
 11.1982 + * This routine processes the RX interrupt & services the RX queues.
 11.1983 + * For each successful RFD, it allocates a new msg block, links that
 11.1984 + * into the RFD list, and sends the old msg upstream.
 11.1985 + * The new RFD is then put at the end of the free list of RFD's.
 11.1986 + * It returns the number of serviced RFDs.
 11.1987 + */
 11.1988 +u32
 11.1989 +e100_rx_srv(struct e100_private *bdp)
 11.1990 +{
 11.1991 +	rfd_t *rfd;		/* new rfd, received rfd */
 11.1992 +	int i;
 11.1993 +	u16 rfd_status;
 11.1994 +	struct sk_buff *skb;
 11.1995 +	struct net_device *dev;
 11.1996 +	unsigned int data_sz;
 11.1997 +	struct rx_list_elem *rx_struct;
 11.1998 +	u32 rfd_cnt = 0;
 11.1999 +
 11.2000 +	dev = bdp->device;
 11.2001 +
 11.2002 +	/* current design of rx is as following:
 11.2003 +	 * 1. socket buffer (skb) used to pass network packet to upper layer
 11.2004 +	 * 2. all HW host memory structures (like RFDs, RBDs and data buffers)
 11.2005 +	 *    are placed in a skb's data room
 11.2006 +	 * 3. when rx process is complete, we change skb internal pointers to exclude
 11.2007 +	 *    from data area all unrelated things (RFD, RDB) and to leave
 11.2008 +	 *    just rx'ed packet netto
 11.2009 +	 * 4. for each skb passed to upper layer, new one is allocated instead.
 11.2010 +	 * 5. if no skb left, in 2 sec another atempt to allocate skbs will be made
 11.2011 +	 *    (watchdog trigger SWI intr and isr should allocate new skbs)
 11.2012 +	 */
 11.2013 +	for (i = 0; i < bdp->params.RxDescriptors; i++) {
 11.2014 +		if (list_empty(&(bdp->active_rx_list))) {
 11.2015 +			break;
 11.2016 +		}
 11.2017 +
 11.2018 +		rx_struct = list_entry(bdp->active_rx_list.next,
 11.2019 +				       struct rx_list_elem, list_elem);
 11.2020 +		skb = rx_struct->skb;
 11.2021 +
 11.2022 +		rfd = RFD_POINTER(skb, bdp);	/* locate RFD within skb */
 11.2023 +
 11.2024 +		// sync only the RFD header
 11.2025 +		pci_dma_sync_single(bdp->pdev, rx_struct->dma_addr,
 11.2026 +				    bdp->rfd_size, PCI_DMA_FROMDEVICE);
 11.2027 +		rfd_status = le16_to_cpu(rfd->rfd_header.cb_status);	/* get RFD's status */
 11.2028 +		if (!(rfd_status & RFD_STATUS_COMPLETE))	/* does not contains data yet - exit */
 11.2029 +			break;
 11.2030 +
 11.2031 +		/* to allow manipulation with current skb we need to unlink it */
 11.2032 +		list_del(&(rx_struct->list_elem));
 11.2033 +
 11.2034 +		/* do not free & unmap badly received packet.
 11.2035 +		 * move it to the end of skb list for reuse */
 11.2036 +		if (!(rfd_status & RFD_STATUS_OK)) {
 11.2037 +			e100_add_skb_to_end(bdp, rx_struct);
 11.2038 +			continue;
 11.2039 +		}
 11.2040 +
 11.2041 +		data_sz = min_t(u16, (le16_to_cpu(rfd->rfd_act_cnt) & 0x3fff),
 11.2042 +				(sizeof (rfd_t) - bdp->rfd_size));
 11.2043 +
 11.2044 +		/* now sync all the data */
 11.2045 +		pci_dma_sync_single(bdp->pdev, rx_struct->dma_addr,
 11.2046 +				    (data_sz + bdp->rfd_size),
 11.2047 +				    PCI_DMA_FROMDEVICE);
 11.2048 +
 11.2049 +		pci_unmap_single(bdp->pdev, rx_struct->dma_addr,
 11.2050 +				 sizeof (rfd_t), PCI_DMA_FROMDEVICE);
 11.2051 +
 11.2052 +		list_add(&(rx_struct->list_elem), &(bdp->rx_struct_pool));
 11.2053 +
 11.2054 +		/* end of dma access to rfd */
 11.2055 +		bdp->skb_req++;	/* incr number of requested skbs */
 11.2056 +		e100_alloc_skbs(bdp);	/* and get them */
 11.2057 +
 11.2058 +		/* set packet size, excluding checksum (2 last bytes) if it is present */
 11.2059 +		if ((bdp->flags & DF_CSUM_OFFLOAD)
 11.2060 +		    && (bdp->rev_id < D102_REV_ID))
 11.2061 +			skb_put(skb, (int) data_sz - 2);
 11.2062 +		else
 11.2063 +			skb_put(skb, (int) data_sz);
 11.2064 +
 11.2065 +		/* set the protocol */
 11.2066 +		skb->protocol = eth_type_trans(skb, dev);
 11.2067 +
 11.2068 +		/* set the checksum info */
 11.2069 +		if (bdp->flags & DF_CSUM_OFFLOAD) {
 11.2070 +			if (bdp->rev_id >= D102_REV_ID) {
 11.2071 +				skb->ip_summed = e100_D102_check_checksum(rfd);
 11.2072 +			} else {
 11.2073 +				skb->ip_summed = e100_D101M_checksum(bdp, skb);
 11.2074 +			}
 11.2075 +		} else {
 11.2076 +			skb->ip_summed = CHECKSUM_NONE;
 11.2077 +		}
 11.2078 +
 11.2079 +		if(bdp->vlgrp && (rfd_status & CB_STATUS_VLAN)) {
 11.2080 +			vlan_hwaccel_rx(skb, bdp->vlgrp, be16_to_cpu(rfd->vlanid));
 11.2081 +		} else {
 11.2082 +			netif_rx(skb);
 11.2083 +		}
 11.2084 +		dev->last_rx = jiffies;
 11.2085 +		bdp->drv_stats.net_stats.rx_bytes += skb->len;
 11.2086 +		
 11.2087 +		rfd_cnt++;
 11.2088 +	}			/* end of rfd loop */
 11.2089 +
 11.2090 +	/* restart the RU if it has stopped */
 11.2091 +	if ((readw(&bdp->scb->scb_status) & SCB_RUS_MASK) != SCB_RUS_READY) {
 11.2092 +		e100_start_ru(bdp);
 11.2093 +	}
 11.2094 +
 11.2095 +	return rfd_cnt;
 11.2096 +}
 11.2097 +
 11.2098 +void
 11.2099 +e100_refresh_txthld(struct e100_private *bdp)
 11.2100 +{
 11.2101 +	basic_cntr_t *pstat = &(bdp->stats_counters->basic_stats);
 11.2102 +
 11.2103 +	/* as long as tx_per_underrun is not 0, we can go about dynamically *
 11.2104 +	 * adjusting the xmit threshold. we stop doing that & resort to defaults
 11.2105 +	 * * once the adjustments become meaningless. the value is adjusted by *
 11.2106 +	 * dumping the error counters & checking the # of xmit underrun errors *
 11.2107 +	 * we've had. */
 11.2108 +	if (bdp->tx_per_underrun) {
 11.2109 +		/* We are going to last values dumped from the dump statistics
 11.2110 +		 * command */
 11.2111 +		if (le32_to_cpu(pstat->xmt_gd_frames)) {
 11.2112 +			if (le32_to_cpu(pstat->xmt_uruns)) {
 11.2113 +				/* 
 11.2114 +				 * if we have had more than one underrun per "DEFAULT #
 11.2115 +				 * OF XMITS ALLOWED PER UNDERRUN" good xmits, raise the
 11.2116 +				 * THRESHOLD.
 11.2117 +				 */
 11.2118 +				if ((le32_to_cpu(pstat->xmt_gd_frames) /
 11.2119 +				     le32_to_cpu(pstat->xmt_uruns)) <
 11.2120 +				    bdp->tx_per_underrun) {
 11.2121 +					bdp->tx_thld += 3;
 11.2122 +				}
 11.2123 +			}
 11.2124 +
 11.2125 +			/* 
 11.2126 +			 * if we've had less than one underrun per the DEFAULT number of
 11.2127 +			 * of good xmits allowed, lower the THOLD but not less than 0 
 11.2128 +			 */
 11.2129 +			if (le32_to_cpu(pstat->xmt_gd_frames) >
 11.2130 +			    bdp->tx_per_underrun) {
 11.2131 +				bdp->tx_thld--;
 11.2132 +
 11.2133 +				if (bdp->tx_thld < 6)
 11.2134 +					bdp->tx_thld = 6;
 11.2135 +
 11.2136 +			}
 11.2137 +		}
 11.2138 +
 11.2139 +		/* end good xmits */
 11.2140 +		/* 
 11.2141 +		 * * if our adjustments are becoming unresonable, stop adjusting &
 11.2142 +		 * resort * to defaults & pray. A THOLD value > 190 means that the
 11.2143 +		 * adapter will * wait for 190*8=1520 bytes in TX FIFO before it
 11.2144 +		 * starts xmit. Since * MTU is 1514, it doesn't make any sense for
 11.2145 +		 * further increase. */
 11.2146 +		if (bdp->tx_thld >= 190) {
 11.2147 +			bdp->tx_per_underrun = 0;
 11.2148 +			bdp->tx_thld = 189;
 11.2149 +		}
 11.2150 +	}			/* end underrun check */
 11.2151 +}
 11.2152 +
 11.2153 +/**
 11.2154 + * e100_prepare_xmit_buff - prepare a buffer for transmission
 11.2155 + * @bdp: atapter's private data struct
 11.2156 + * @skb: skb to send
 11.2157 + *
 11.2158 + * This routine prepare a buffer for transmission. It checks
 11.2159 + * the message length for the appropiate size. It picks up a
 11.2160 + * free tcb from the TCB pool and sets up the corresponding
 11.2161 + * TBD's. If the number of fragments are more than the number
 11.2162 + * of TBD/TCB it copies all the fragments in a coalesce buffer.
 11.2163 + * It returns a pointer to the prepared TCB.
 11.2164 + */
 11.2165 +static inline tcb_t *
 11.2166 +e100_prepare_xmit_buff(struct e100_private *bdp, struct sk_buff *skb)
 11.2167 +{
 11.2168 +	tcb_t *tcb, *prev_tcb;
 11.2169 +
 11.2170 +	tcb = bdp->tcb_pool.data;
 11.2171 +	tcb += TCB_TO_USE(bdp->tcb_pool);
 11.2172 +
 11.2173 +	if (bdp->flags & USE_IPCB) {
 11.2174 +		tcb->tcbu.ipcb.ip_activation_high = IPCB_IP_ACTIVATION_DEFAULT;
 11.2175 +		tcb->tcbu.ipcb.ip_schedule &= ~IPCB_TCP_PACKET;
 11.2176 +		tcb->tcbu.ipcb.ip_schedule &= ~IPCB_TCPUDP_CHECKSUM_ENABLE;
 11.2177 +	}
 11.2178 +
 11.2179 +	if(bdp->vlgrp && vlan_tx_tag_present(skb)) {
 11.2180 +		(tcb->tcbu).ipcb.ip_activation_high |= IPCB_INSERTVLAN_ENABLE;
 11.2181 +		(tcb->tcbu).ipcb.vlan = cpu_to_be16(vlan_tx_tag_get(skb));
 11.2182 +	}
 11.2183 +	
 11.2184 +	tcb->tcb_hdr.cb_status = 0;
 11.2185 +	tcb->tcb_thrshld = bdp->tx_thld;
 11.2186 +	tcb->tcb_hdr.cb_cmd |= __constant_cpu_to_le16(CB_S_BIT);
 11.2187 +
 11.2188 +	/* Set I (Interrupt) bit on every (TX_FRAME_CNT)th packet */
 11.2189 +	if (!(++bdp->tx_count % TX_FRAME_CNT))
 11.2190 +		tcb->tcb_hdr.cb_cmd |= __constant_cpu_to_le16(CB_I_BIT);
 11.2191 +	else
 11.2192 +		/* Clear I bit on other packets */
 11.2193 +		tcb->tcb_hdr.cb_cmd &= ~__constant_cpu_to_le16(CB_I_BIT);
 11.2194 +
 11.2195 +	tcb->tcb_skb = skb;
 11.2196 +
 11.2197 +#if 0
 11.2198 +	if (skb->ip_summed == CHECKSUM_HW) {
 11.2199 +		const struct iphdr *ip = skb->nh.iph;
 11.2200 +
 11.2201 +		if ((ip->protocol == IPPROTO_TCP) ||
 11.2202 +		    (ip->protocol == IPPROTO_UDP)) {
 11.2203 +
 11.2204 +			tcb->tcbu.ipcb.ip_activation_high |=
 11.2205 +				IPCB_HARDWAREPARSING_ENABLE;
 11.2206 +			tcb->tcbu.ipcb.ip_schedule |=
 11.2207 +				IPCB_TCPUDP_CHECKSUM_ENABLE;
 11.2208 +
 11.2209 +			if (ip->protocol == IPPROTO_TCP)
 11.2210 +				tcb->tcbu.ipcb.ip_schedule |= IPCB_TCP_PACKET;
 11.2211 +		}
 11.2212 +	}
 11.2213 +#endif
 11.2214 +
 11.2215 +	if (!skb_shinfo(skb)->nr_frags) {
 11.2216 +		(tcb->tbd_ptr)->tbd_buf_addr =
 11.2217 +			cpu_to_le32(pci_map_single(bdp->pdev, skb->data,
 11.2218 +						   skb->len, PCI_DMA_TODEVICE));
 11.2219 +		(tcb->tbd_ptr)->tbd_buf_cnt = cpu_to_le16(skb->len);
 11.2220 +		tcb->tcb_tbd_num = 1;
 11.2221 +		tcb->tcb_tbd_ptr = tcb->tcb_tbd_dflt_ptr;
 11.2222 +	} else {
 11.2223 +		int i;
 11.2224 +		void *addr;
 11.2225 +		tbd_t *tbd_arr_ptr = &(tcb->tbd_ptr[1]);
 11.2226 +		skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
 11.2227 +
 11.2228 +		(tcb->tbd_ptr)->tbd_buf_addr =
 11.2229 +			cpu_to_le32(pci_map_single(bdp->pdev, skb->data,
 11.2230 +						   (skb->len - skb->data_len),
 11.2231 +						   PCI_DMA_TODEVICE));
 11.2232 +		(tcb->tbd_ptr)->tbd_buf_cnt =
 11.2233 +			cpu_to_le16(skb->len - skb->data_len);
 11.2234 +
 11.2235 +		for (i = 0; i < skb_shinfo(skb)->nr_frags;
 11.2236 +		     i++, tbd_arr_ptr++, frag++) {
 11.2237 +
 11.2238 +			addr = ((void *) page_address(frag->page) +
 11.2239 +				frag->page_offset);
 11.2240 +
 11.2241 +			tbd_arr_ptr->tbd_buf_addr =
 11.2242 +				cpu_to_le32(pci_map_single(bdp->pdev,
 11.2243 +							   addr, frag->size,
 11.2244 +							   PCI_DMA_TODEVICE));
 11.2245 +			tbd_arr_ptr->tbd_buf_cnt = cpu_to_le16(frag->size);
 11.2246 +		}
 11.2247 +		tcb->tcb_tbd_num = skb_shinfo(skb)->nr_frags + 1;
 11.2248 +		tcb->tcb_tbd_ptr = tcb->tcb_tbd_expand_ptr;
 11.2249 +	}
 11.2250 +
 11.2251 +	/* clear the S-BIT on the previous tcb */
 11.2252 +	prev_tcb = bdp->tcb_pool.data;
 11.2253 +	prev_tcb += PREV_TCB_USED(bdp->tcb_pool);
 11.2254 +	prev_tcb->tcb_hdr.cb_cmd &= __constant_cpu_to_le16((u16) ~CB_S_BIT);
 11.2255 +
 11.2256 +	bdp->tcb_pool.tail = NEXT_TCB_TOUSE(bdp->tcb_pool.tail);
 11.2257 +
 11.2258 +	wmb();
 11.2259 +
 11.2260 +	e100_start_cu(bdp, tcb);
 11.2261 +
 11.2262 +	return tcb;
 11.2263 +}
 11.2264 +
 11.2265 +/* Changed for 82558 enhancement */
 11.2266 +/**
 11.2267 + * e100_start_cu - start the adapter's CU
 11.2268 + * @bdp: atapter's private data struct
 11.2269 + * @tcb: TCB to be transmitted
 11.2270 + *
 11.2271 + * This routine issues a CU Start or CU Resume command to the 82558/9.
 11.2272 + * This routine was added because the prepare_ext_xmit_buff takes advantage
 11.2273 + * of the 82558/9's Dynamic TBD chaining feature and has to start the CU as
 11.2274 + * soon as the first TBD is ready. 
 11.2275 + *
 11.2276 + * e100_start_cu must be called while holding the tx_lock ! 
 11.2277 + */
 11.2278 +u8
 11.2279 +e100_start_cu(struct e100_private *bdp, tcb_t *tcb)
 11.2280 +{
 11.2281 +	unsigned long lock_flag;
 11.2282 +	u8 ret = true;
 11.2283 +
 11.2284 +	spin_lock_irqsave(&(bdp->bd_lock), lock_flag);
 11.2285 +	switch (bdp->next_cu_cmd) {
 11.2286 +	case RESUME_NO_WAIT:
 11.2287 +		/*last cu command was a CU_RESMUE if this is a 558 or newer we don't need to
 11.2288 +		 * wait for command word to clear, we reach here only if we are bachlor
 11.2289 +		 */
 11.2290 +		e100_exec_cmd(bdp, SCB_CUC_RESUME);
 11.2291 +		break;
 11.2292 +
 11.2293 +	case RESUME_WAIT:
 11.2294 +		if ((bdp->flags & IS_ICH) &&
 11.2295 +		    (bdp->cur_line_speed == 10) &&
 11.2296 +		    (bdp->cur_dplx_mode == HALF_DUPLEX)) {
 11.2297 +			e100_wait_exec_simple(bdp, SCB_CUC_NOOP);
 11.2298 +			udelay(1);
 11.2299 +		}
 11.2300 +		if ((e100_wait_exec_simple(bdp, SCB_CUC_RESUME)) &&
 11.2301 +		    (bdp->flags & IS_BACHELOR) && (!(bdp->flags & IS_ICH))) {
 11.2302 +			bdp->next_cu_cmd = RESUME_NO_WAIT;
 11.2303 +		}
 11.2304 +		break;
 11.2305 +
 11.2306 +	case START_WAIT:
 11.2307 +		// The last command was a non_tx CU command
 11.2308 +		if (!e100_wait_cus_idle(bdp))
 11.2309 +			printk(KERN_DEBUG
 11.2310 +			       "e100: %s: cu_start: timeout waiting for cu\n",
 11.2311 +			       bdp->device->name);
 11.2312 +		if (!e100_wait_exec_cmplx(bdp, (u32) (tcb->tcb_phys),
 11.2313 +					  SCB_CUC_START, CB_TRANSMIT)) {
 11.2314 +			printk(KERN_DEBUG
 11.2315 +			       "e100: %s: cu_start: timeout waiting for scb\n",
 11.2316 +			       bdp->device->name);
 11.2317 +			e100_exec_cmplx(bdp, (u32) (tcb->tcb_phys),
 11.2318 +					SCB_CUC_START);
 11.2319 +			ret = false;
 11.2320 +		}
 11.2321 +
 11.2322 +		bdp->next_cu_cmd = RESUME_WAIT;
 11.2323 +
 11.2324 +		break;
 11.2325 +	}
 11.2326 +
 11.2327 +	/* save the last tcb */
 11.2328 +	bdp->last_tcb = tcb;
 11.2329 +
 11.2330 +	spin_unlock_irqrestore(&(bdp->bd_lock), lock_flag);
 11.2331 +	return ret;
 11.2332 +}
 11.2333 +
 11.2334 +/* ====================================================================== */
 11.2335 +/* hw                                                                     */
 11.2336 +/* ====================================================================== */
 11.2337 +
 11.2338 +/**
 11.2339 + * e100_selftest - perform H/W self test
 11.2340 + * @bdp: atapter's private data struct
 11.2341 + * @st_timeout: address to return timeout value, if fails
 11.2342 + * @st_result: address to return selftest result, if fails
 11.2343 + *
 11.2344 + * This routine will issue PORT Self-test command to test the e100.
 11.2345 + * The self-test will fail if the adapter's master-enable bit is not
 11.2346 + * set in the PCI Command Register, or if the adapter is not seated
 11.2347 + * in a PCI master-enabled slot. we also disable interrupts when the
 11.2348 + * command is completed.
 11.2349 + *
 11.2350 + * Returns:
 11.2351 + *      true: if adapter passes self_test
 11.2352 + *      false: otherwise
 11.2353 + */
 11.2354 +unsigned char
 11.2355 +e100_selftest(struct e100_private *bdp, u32 *st_timeout, u32 *st_result)
 11.2356 +{
 11.2357 +	u32 selftest_cmd;
 11.2358 +
 11.2359 +	/* initialize the nic state before running test */
 11.2360 +	e100_sw_reset(bdp, PORT_SOFTWARE_RESET);
 11.2361 +	/* Setup the address of the self_test area */
 11.2362 +	selftest_cmd = bdp->selftest_phys;
 11.2363 +
 11.2364 +	/* Setup SELF TEST Command Code in D3 - D0 */
 11.2365 +	selftest_cmd |= PORT_SELFTEST;
 11.2366 +
 11.2367 +	/* Initialize the self-test signature and results DWORDS */
 11.2368 +	bdp->selftest->st_sign = 0;
 11.2369 +	bdp->selftest->st_result = 0xffffffff;
 11.2370 +
 11.2371 +	/* Do the port command */
 11.2372 +	writel(selftest_cmd, &bdp->scb->scb_port);
 11.2373 +	readw(&(bdp->scb->scb_status));	/* flushes last write, read-safe */
 11.2374 +
 11.2375 +	/* Wait at least 10 milliseconds for the self-test to complete */
 11.2376 +	set_current_state(TASK_UNINTERRUPTIBLE);
 11.2377 +	schedule_timeout(HZ / 100 + 1);
 11.2378 +
 11.2379 +	/* disable interrupts since they are enabled */
 11.2380 +	/* after device reset during selftest        */
 11.2381 +	e100_disable_clear_intr(bdp);
 11.2382 +
 11.2383 +	/* if The First Self Test DWORD Still Zero, We've timed out. If the
 11.2384 +	 * second DWORD is not zero then we have an error. */
 11.2385 +	if ((bdp->selftest->st_sign == 0) || (bdp->selftest->st_result != 0)) {
 11.2386 +
 11.2387 +		if (st_timeout)
 11.2388 +			*st_timeout = !(le32_to_cpu(bdp->selftest->st_sign));
 11.2389 +
 11.2390 +		if (st_result)
 11.2391 +			*st_result = le32_to_cpu(bdp->selftest->st_result);
 11.2392 +
 11.2393 +		return false;
 11.2394 +	}
 11.2395 +
 11.2396 +	return true;
 11.2397 +}
 11.2398 +
 11.2399 +/**
 11.2400 + * e100_setup_iaaddr - issue IA setup sommand
 11.2401 + * @bdp: atapter's private data struct
 11.2402 + * @eaddr: new ethernet address
 11.2403 + *
 11.2404 + * This routine will issue the IA setup command. This command
 11.2405 + * will notify the 82557 (e100) of what its individual (node)
 11.2406 + * address is. This command will be executed in polled mode.
 11.2407 + *
 11.2408 + * Returns:
 11.2409 + *      true: if the IA setup command was successfully issued and completed
 11.2410 + *      false: otherwise
 11.2411 + */
 11.2412 +unsigned char
 11.2413 +e100_setup_iaaddr(struct e100_private *bdp, u8 *eaddr)
 11.2414 +{
 11.2415 +	unsigned int i;
 11.2416 +	cb_header_t *ntcb_hdr;
 11.2417 +	unsigned char res;
 11.2418 +	nxmit_cb_entry_t *cmd;
 11.2419 +
 11.2420 +	if ((cmd = e100_alloc_non_tx_cmd(bdp)) == NULL) {
 11.2421 +		res = false;
 11.2422 +		goto exit;
 11.2423 +	}
 11.2424 +
 11.2425 +	ntcb_hdr = (cb_header_t *) cmd->non_tx_cmd;
 11.2426 +	ntcb_hdr->cb_cmd = __constant_cpu_to_le16(CB_IA_ADDRESS);
 11.2427 +
 11.2428 +	for (i = 0; i < ETH_ALEN; i++) {
 11.2429 +		(cmd->non_tx_cmd)->ntcb.setup.ia_addr[i] = eaddr[i];
 11.2430 +	}
 11.2431 +
 11.2432 +	res = e100_exec_non_cu_cmd(bdp, cmd);
 11.2433 +	if (!res)
 11.2434 +		printk(KERN_WARNING "e100: %s: IA setup failed\n", 
 11.2435 +		       bdp->device->name);
 11.2436 +
 11.2437 +exit:
 11.2438 +	return res;
 11.2439 +}
 11.2440 +
 11.2441 +/**
 11.2442 + * e100_start_ru - start the RU if needed
 11.2443 + * @bdp: atapter's private data struct
 11.2444 + *
 11.2445 + * This routine checks the status of the 82557's receive unit(RU),
 11.2446 + * and starts the RU if it was not already active.  However,
 11.2447 + * before restarting the RU, the driver gives the RU the buffers
 11.2448 + * it freed up during the servicing of the ISR. If there are
 11.2449 + * no free buffers to give to the RU, (i.e. we have reached a
 11.2450 + * no resource condition) the RU will not be started till the
 11.2451 + * next ISR.
 11.2452 + */
 11.2453 +void
 11.2454 +e100_start_ru(struct e100_private *bdp)
 11.2455 +{
 11.2456 +	struct rx_list_elem *rx_struct = NULL;
 11.2457 +	int buffer_found = 0;
 11.2458 +	struct list_head *entry_ptr;
 11.2459 +
 11.2460 +	list_for_each(entry_ptr, &(bdp->active_rx_list)) {
 11.2461 +		rx_struct =
 11.2462 +			list_entry(entry_ptr, struct rx_list_elem, list_elem);
 11.2463 +		pci_dma_sync_single(bdp->pdev, rx_struct->dma_addr,
 11.2464 +				    bdp->rfd_size, PCI_DMA_FROMDEVICE);
 11.2465 +		if (!((SKB_RFD_STATUS(rx_struct->skb, bdp) &
 11.2466 +		       __constant_cpu_to_le16(RFD_STATUS_COMPLETE)))) {
 11.2467 +			buffer_found = 1;
 11.2468 +			break;
 11.2469 +		}
 11.2470 +	}
 11.2471 +
 11.2472 +	/* No available buffers */
 11.2473 +	if (!buffer_found) {
 11.2474 +		return;
 11.2475 +	}
 11.2476 +
 11.2477 +	spin_lock(&bdp->bd_lock);
 11.2478 +
 11.2479 +	if (!e100_wait_exec_cmplx(bdp, rx_struct->dma_addr, SCB_RUC_START, 0)) {
 11.2480 +		printk(KERN_DEBUG
 11.2481 +		       "e100: %s: start_ru: wait_scb failed\n", 
 11.2482 +		       bdp->device->name);
 11.2483 +		e100_exec_cmplx(bdp, rx_struct->dma_addr, SCB_RUC_START);
 11.2484 +	}
 11.2485 +	if (bdp->next_cu_cmd == RESUME_NO_WAIT) {
 11.2486 +		bdp->next_cu_cmd = RESUME_WAIT;
 11.2487 +	}
 11.2488 +	spin_unlock(&bdp->bd_lock);
 11.2489 +}
 11.2490 +
 11.2491 +/**
 11.2492 + * e100_cmd_complete_location
 11.2493 + * @bdp: atapter's private data struct
 11.2494 + *
 11.2495 + * This routine returns a pointer to the location of the command-complete
 11.2496 + * DWord in the dump statistical counters area, according to the statistical
 11.2497 + * counters mode (557 - basic, 558 - extended, or 559 - TCO mode).
 11.2498 + * See e100_config_init() for the setting of the statistical counters mode.
 11.2499 + */
 11.2500 +static u32 *
 11.2501 +e100_cmd_complete_location(struct e100_private *bdp)
 11.2502 +{
 11.2503 +	u32 *cmd_complete;
 11.2504 +	max_counters_t *stats = bdp->stats_counters;
 11.2505 +
 11.2506 +	switch (bdp->stat_mode) {
 11.2507 +	case E100_EXTENDED_STATS:
 11.2508 +		cmd_complete =
 11.2509 +			(u32 *) &(((err_cntr_558_t *) (stats))->cmd_complete);
 11.2510 +		break;
 11.2511 +
 11.2512 +	case E100_TCO_STATS:
 11.2513 +		cmd_complete =
 11.2514 +			(u32 *) &(((err_cntr_559_t *) (stats))->cmd_complete);
 11.2515 +		break;
 11.2516 +
 11.2517 +	case E100_BASIC_STATS:
 11.2518 +	default:		
 11.2519 +		cmd_complete =
 11.2520 +			(u32 *) &(((err_cntr_557_t *) (stats))->cmd_complete);
 11.2521 +		break;
 11.2522 +	}
 11.2523 +
 11.2524 +	return cmd_complete;
 11.2525 +}
 11.2526 +
 11.2527 +/**
 11.2528 + * e100_clr_cntrs - clear statistics counters
 11.2529 + * @bdp: atapter's private data struct
 11.2530 + *
 11.2531 + * This routine will clear the adapter error statistic counters.
 11.2532 + *
 11.2533 + * Returns:
 11.2534 + *      true: if successfully cleared stat counters
 11.2535 + *      false: otherwise
 11.2536 + */
 11.2537 +static unsigned char __devinit
 11.2538 +e100_clr_cntrs(struct e100_private *bdp)
 11.2539 +{
 11.2540 +	volatile u32 *pcmd_complete;
 11.2541 +
 11.2542 +	/* clear the dump counter complete word */
 11.2543 +	pcmd_complete = e100_cmd_complete_location(bdp);
 11.2544 +	*pcmd_complete = 0;
 11.2545 +	wmb();
 11.2546 +
 11.2547 +	if (!e100_wait_exec_cmplx(bdp, bdp->stat_cnt_phys, SCB_CUC_DUMP_ADDR, 0))
 11.2548 +		return false;
 11.2549 +
 11.2550 +	/* wait 10 microseconds for the command to complete */
 11.2551 +	udelay(10);
 11.2552 +
 11.2553 +	if (!e100_wait_exec_simple(bdp, SCB_CUC_DUMP_RST_STAT))
 11.2554 +		return false;
 11.2555 +
 11.2556 +	if (bdp->next_cu_cmd == RESUME_NO_WAIT) {
 11.2557 +		bdp->next_cu_cmd = RESUME_WAIT;
 11.2558 +	}
 11.2559 +
 11.2560 +	return true;
 11.2561 +}
 11.2562 +
 11.2563 +static unsigned char
 11.2564 +e100_update_stats(struct e100_private *bdp)
 11.2565 +{
 11.2566 +	u32 *pcmd_complete;
 11.2567 +	basic_cntr_t *pstat = &(bdp->stats_counters->basic_stats);
 11.2568 +
 11.2569 +	// check if last dump command completed
 11.2570 +	pcmd_complete = e100_cmd_complete_location(bdp);
 11.2571 +	if (*pcmd_complete != le32_to_cpu(DUMP_RST_STAT_COMPLETED) &&
 11.2572 +	    *pcmd_complete != le32_to_cpu(DUMP_STAT_COMPLETED)) {
 11.2573 +		return false;
 11.2574 +	}
 11.2575 +
 11.2576 +	/* increment the statistics */
 11.2577 +	bdp->drv_stats.net_stats.rx_packets +=
 11.2578 +		le32_to_cpu(pstat->rcv_gd_frames);
 11.2579 +	bdp->drv_stats.net_stats.tx_packets +=
 11.2580 +		le32_to_cpu(pstat->xmt_gd_frames);
 11.2581 +	bdp->drv_stats.net_stats.rx_dropped += le32_to_cpu(pstat->rcv_rsrc_err);
 11.2582 +	bdp->drv_stats.net_stats.collisions += le32_to_cpu(pstat->xmt_ttl_coll);
 11.2583 +	bdp->drv_stats.net_stats.rx_length_errors +=
 11.2584 +		le32_to_cpu(pstat->rcv_shrt_frames);
 11.2585 +	bdp->drv_stats.net_stats.rx_over_errors +=
 11.2586 +		le32_to_cpu(pstat->rcv_rsrc_err);
 11.2587 +	bdp->drv_stats.net_stats.rx_crc_errors +=
 11.2588 +		le32_to_cpu(pstat->rcv_crc_errs);
 11.2589 +	bdp->drv_stats.net_stats.rx_frame_errors +=
 11.2590 +		le32_to_cpu(pstat->rcv_algn_errs);
 11.2591 +	bdp->drv_stats.net_stats.rx_fifo_errors +=
 11.2592 +		le32_to_cpu(pstat->rcv_oruns);
 11.2593 +	bdp->drv_stats.net_stats.tx_aborted_errors +=
 11.2594 +		le32_to_cpu(pstat->xmt_max_coll);
 11.2595 +	bdp->drv_stats.net_stats.tx_carrier_errors +=
 11.2596 +		le32_to_cpu(pstat->xmt_lost_crs);
 11.2597 +	bdp->drv_stats.net_stats.tx_fifo_errors +=
 11.2598 +		le32_to_cpu(pstat->xmt_uruns);
 11.2599 +
 11.2600 +	bdp->drv_stats.tx_late_col += le32_to_cpu(pstat->xmt_late_coll);
 11.2601 +	bdp->drv_stats.tx_ok_defrd += le32_to_cpu(pstat->xmt_deferred);
 11.2602 +	bdp->drv_stats.tx_one_retry += le32_to_cpu(pstat->xmt_sngl_coll);
 11.2603 +	bdp->drv_stats.tx_mt_one_retry += le32_to_cpu(pstat->xmt_mlt_coll);
 11.2604 +	bdp->drv_stats.rcv_cdt_frames += le32_to_cpu(pstat->rcv_err_coll);
 11.2605 +
 11.2606 +	if (bdp->stat_mode != E100_BASIC_STATS) {
 11.2607 +		ext_cntr_t *pex_stat = &bdp->stats_counters->extended_stats;
 11.2608 +
 11.2609 +		bdp->drv_stats.xmt_fc_pkts +=
 11.2610 +			le32_to_cpu(pex_stat->xmt_fc_frames);
 11.2611 +		bdp->drv_stats.rcv_fc_pkts +=
 11.2612 +			le32_to_cpu(pex_stat->rcv_fc_frames);
 11.2613 +		bdp->drv_stats.rcv_fc_unsupported +=
 11.2614 +			le32_to_cpu(pex_stat->rcv_fc_unsupported);
 11.2615 +	}
 11.2616 +
 11.2617 +	if (bdp->stat_mode == E100_TCO_STATS) {
 11.2618 +		tco_cntr_t *ptco_stat = &bdp->stats_counters->tco_stats;
 11.2619 +
 11.2620 +		bdp->drv_stats.xmt_tco_pkts +=
 11.2621 +			le16_to_cpu(ptco_stat->xmt_tco_frames);
 11.2622 +		bdp->drv_stats.rcv_tco_pkts +=
 11.2623 +			le16_to_cpu(ptco_stat->rcv_tco_frames);
 11.2624 +	}
 11.2625 +
 11.2626 +	*pcmd_complete = 0;
 11.2627 +	return true;
 11.2628 +}
 11.2629 +
 11.2630 +/**
 11.2631 + * e100_dump_stat_cntrs
 11.2632 + * @bdp: atapter's private data struct
 11.2633 + *
 11.2634 + * This routine will dump the board statistical counters without waiting
 11.2635 + * for stat_dump to complete. Any access to this stats should verify the completion
 11.2636 + * of the command
 11.2637 + */
 11.2638 +void
 11.2639 +e100_dump_stats_cntrs(struct e100_private *bdp)
 11.2640 +{
 11.2641 +	unsigned long lock_flag_bd;
 11.2642 +
 11.2643 +	spin_lock_irqsave(&(bdp->bd_lock), lock_flag_bd);
 11.2644 +
 11.2645 +	/* dump h/w stats counters */
 11.2646 +	if (e100_wait_exec_simple(bdp, SCB_CUC_DUMP_RST_STAT)) {
 11.2647 +		if (bdp->next_cu_cmd == RESUME_NO_WAIT) {
 11.2648 +			bdp->next_cu_cmd = RESUME_WAIT;
 11.2649 +		}
 11.2650 +	}
 11.2651 +
 11.2652 +	spin_unlock_irqrestore(&(bdp->bd_lock), lock_flag_bd);
 11.2653 +}
 11.2654 +
 11.2655 +/**
 11.2656 + * e100_exec_non_cu_cmd
 11.2657 + * @bdp: atapter's private data struct
 11.2658 + * @command: the non-cu command to execute
 11.2659 + *
 11.2660 + * This routine will submit a command block to be executed,
 11.2661 + */
 11.2662 +unsigned char
 11.2663 +e100_exec_non_cu_cmd(struct e100_private *bdp, nxmit_cb_entry_t *command)
 11.2664 +{
 11.2665 +	cb_header_t *ntcb_hdr;
 11.2666 +	unsigned long lock_flag;
 11.2667 +	unsigned long expiration_time;
 11.2668 +	unsigned char rc = true;
 11.2669 +	u8 sub_cmd;
 11.2670 +
 11.2671 +	ntcb_hdr = (cb_header_t *) command->non_tx_cmd;	/* get hdr of non tcb cmd */
 11.2672 +	sub_cmd = cpu_to_le16(ntcb_hdr->cb_cmd);
 11.2673 +
 11.2674 +	/* Set the Command Block to be the last command block */
 11.2675 +	ntcb_hdr->cb_cmd |= __constant_cpu_to_le16(CB_EL_BIT);
 11.2676 +	ntcb_hdr->cb_status = 0;
 11.2677 +	ntcb_hdr->cb_lnk_ptr = 0;
 11.2678 +
 11.2679 +	wmb();
 11.2680 +	if (in_interrupt())
 11.2681 +		return e100_delayed_exec_non_cu_cmd(bdp, command);
 11.2682 +
 11.2683 +	if (netif_running(bdp->device) && netif_carrier_ok(bdp->device))
 11.2684 +		return e100_delayed_exec_non_cu_cmd(bdp, command);
 11.2685 +
 11.2686 +	spin_lock_bh(&(bdp->bd_non_tx_lock));
 11.2687 +
 11.2688 +	if (bdp->non_tx_command_state != E100_NON_TX_IDLE) {
 11.2689 +		goto delayed_exec;
 11.2690 +	}
 11.2691 +
 11.2692 +	if (bdp->last_tcb) {
 11.2693 +		rmb();
 11.2694 +		if ((bdp->last_tcb->tcb_hdr.cb_status &
 11.2695 +		     __constant_cpu_to_le16(CB_STATUS_COMPLETE)) == 0)
 11.2696 +			goto delayed_exec;
 11.2697 +	}
 11.2698 +
 11.2699 +	if ((readw(&bdp->scb->scb_status) & SCB_CUS_MASK) == SCB_CUS_ACTIVE) {
 11.2700 +		goto delayed_exec;
 11.2701 +	}
 11.2702 +
 11.2703 +	spin_lock_irqsave(&bdp->bd_lock, lock_flag);
 11.2704 +
 11.2705 +	if (!e100_wait_exec_cmplx(bdp, command->dma_addr, SCB_CUC_START, sub_cmd)) {
 11.2706 +		spin_unlock_irqrestore(&(bdp->bd_lock), lock_flag);
 11.2707 +		rc = false;
 11.2708 +		goto exit;
 11.2709 +	}
 11.2710 +
 11.2711 +	bdp->next_cu_cmd = START_WAIT;
 11.2712 +	spin_unlock_irqrestore(&(bdp->bd_lock), lock_flag);
 11.2713 +
 11.2714 +	/* now wait for completion of non-cu CB up to 20 msec */
 11.2715 +	expiration_time = jiffies + HZ / 50 + 1;
 11.2716 +	rmb();
 11.2717 +	while (!(ntcb_hdr->cb_status &
 11.2718 +		     __constant_cpu_to_le16(CB_STATUS_COMPLETE))) {
 11.2719 +
 11.2720 +		if (time_before(jiffies, expiration_time)) {
 11.2721 +			spin_unlock_bh(&(bdp->bd_non_tx_lock));
 11.2722 +			yield();
 11.2723 +			spin_lock_bh(&(bdp->bd_non_tx_lock));
 11.2724 +		} else {
 11.2725 +#ifdef E100_CU_DEBUG			
 11.2726 +			printk(KERN_ERR "e100: %s: non-TX command (%x) "
 11.2727 +				"timeout\n", bdp->device->name, sub_cmd);
 11.2728 +#endif			
 11.2729 +			rc = false;
 11.2730 +			goto exit;
 11.2731 +		}
 11.2732 +		rmb();
 11.2733 +	}
 11.2734 +
 11.2735 +exit:
 11.2736 +	e100_free_non_tx_cmd(bdp, command);
 11.2737 +
 11.2738 +	if (netif_running(bdp->device))
 11.2739 +		netif_wake_queue(bdp->device);
 11.2740 +
 11.2741 +	spin_unlock_bh(&(bdp->bd_non_tx_lock));
 11.2742 +	return rc;
 11.2743 +
 11.2744 +delayed_exec:
 11.2745 +	spin_unlock_bh(&(bdp->bd_non_tx_lock));
 11.2746 +	return e100_delayed_exec_non_cu_cmd(bdp, command);
 11.2747 +}
 11.2748 +
 11.2749 +/**
 11.2750 + * e100_sw_reset
 11.2751 + * @bdp: atapter's private data struct
 11.2752 + * @reset_cmd: s/w reset or selective reset
 11.2753 + *
 11.2754 + * This routine will issue a software reset to the adapter. It 
 11.2755 + * will also disable interrupts, as the are enabled after reset.
 11.2756 + */
 11.2757 +void
 11.2758 +e100_sw_reset(struct e100_private *bdp, u32 reset_cmd)
 11.2759 +{
 11.2760 +	/* Do  a selective reset first to avoid a potential PCI hang */
 11.2761 +	writel(PORT_SELECTIVE_RESET, &bdp->scb->scb_port);
 11.2762 +	readw(&(bdp->scb->scb_status));	/* flushes last write, read-safe */
 11.2763 +
 11.2764 +	/* wait for the reset to take effect */
 11.2765 +	udelay(20);
 11.2766 +	if (reset_cmd == PORT_SOFTWARE_RESET) {
 11.2767 +		writel(PORT_SOFTWARE_RESET, &bdp->scb->scb_port);
 11.2768 +
 11.2769 +		/* wait 20 micro seconds for the reset to take effect */
 11.2770 +		udelay(20);
 11.2771 +	}
 11.2772 +
 11.2773 +	/* Mask off our interrupt line -- it is unmasked after reset */
 11.2774 +	e100_disable_clear_intr(bdp);
 11.2775 +#ifdef E100_CU_DEBUG	
 11.2776 +	bdp->last_cmd = 0;
 11.2777 +	bdp->last_sub_cmd = 0;
 11.2778 +#endif	
 11.2779 +}
 11.2780 +
 11.2781 +/**
 11.2782 + * e100_load_microcode - Download microsocde to controller.
 11.2783 + * @bdp: atapter's private data struct
 11.2784 + *
 11.2785 + * This routine downloads microcode on to the controller. This
 11.2786 + * microcode is available for the 82558/9, 82550. Currently the
 11.2787 + * microcode handles interrupt bundling and TCO workaround.
 11.2788 + *
 11.2789 + * Returns:
 11.2790 + *      true: if successfull
 11.2791 + *      false: otherwise
 11.2792 + */
 11.2793 +static unsigned char
 11.2794 +e100_load_microcode(struct e100_private *bdp)
 11.2795 +{
 11.2796 +	static struct {
 11.2797 +		u8 rev_id;
 11.2798 +		u32 ucode[UCODE_MAX_DWORDS + 1];
 11.2799 +		int timer_dword;
 11.2800 +		int bundle_dword;
 11.2801 +		int min_size_dword;
 11.2802 +	} ucode_opts[] = {
 11.2803 +		{ D101A4_REV_ID,
 11.2804 +		  D101_A_RCVBUNDLE_UCODE,
 11.2805 +		  D101_CPUSAVER_TIMER_DWORD,
 11.2806 +		  D101_CPUSAVER_BUNDLE_DWORD,
 11.2807 +		  D101_CPUSAVER_MIN_SIZE_DWORD },
 11.2808 +		{ D101B0_REV_ID,
 11.2809 +		  D101_B0_RCVBUNDLE_UCODE,
 11.2810 +		  D101_CPUSAVER_TIMER_DWORD,
 11.2811 +		  D101_CPUSAVER_BUNDLE_DWORD,
 11.2812 +		  D101_CPUSAVER_MIN_SIZE_DWORD },
 11.2813 +		{ D101MA_REV_ID,
 11.2814 +		  D101M_B_RCVBUNDLE_UCODE,
 11.2815 +		  D101M_CPUSAVER_TIMER_DWORD,
 11.2816 +		  D101M_CPUSAVER_BUNDLE_DWORD,
 11.2817 +		  D101M_CPUSAVER_MIN_SIZE_DWORD },
 11.2818 +		{ D101S_REV_ID,
 11.2819 +		  D101S_RCVBUNDLE_UCODE,
 11.2820 +		  D101S_CPUSAVER_TIMER_DWORD,
 11.2821 +		  D101S_CPUSAVER_BUNDLE_DWORD,
 11.2822 +		  D101S_CPUSAVER_MIN_SIZE_DWORD },
 11.2823 +		{ D102_REV_ID,
 11.2824 +		  D102_B_RCVBUNDLE_UCODE,
 11.2825 +		  D102_B_CPUSAVER_TIMER_DWORD,
 11.2826 +		  D102_B_CPUSAVER_BUNDLE_DWORD,
 11.2827 +		  D102_B_CPUSAVER_MIN_SIZE_DWORD },
 11.2828 +		{ D102C_REV_ID,
 11.2829 +		  D102_C_RCVBUNDLE_UCODE,
 11.2830 +		  D102_C_CPUSAVER_TIMER_DWORD,
 11.2831 +		  D102_C_CPUSAVER_BUNDLE_DWORD,
 11.2832 +		  D102_C_CPUSAVER_MIN_SIZE_DWORD },
 11.2833 +		{ D102E_REV_ID,
 11.2834 +		  D102_E_RCVBUNDLE_UCODE,
 11.2835 +		  D102_E_CPUSAVER_TIMER_DWORD,
 11.2836 +		  D102_E_CPUSAVER_BUNDLE_DWORD,
 11.2837 +		  D102_E_CPUSAVER_MIN_SIZE_DWORD },
 11.2838 +		{ 0, {0}, 0, 0, 0}
 11.2839 +	}, *opts;
 11.2840 +
 11.2841 +	opts = ucode_opts;
 11.2842 +
 11.2843 +	/* User turned ucode loading off */
 11.2844 +	if (!(bdp->params.b_params & PRM_UCODE))
 11.2845 +		return false;
 11.2846 +
 11.2847 +	/* These controllers do not need ucode */
 11.2848 +	if (bdp->flags & IS_ICH)
 11.2849 +		return false;
 11.2850 +
 11.2851 +	/* Search for ucode match against h/w rev_id */
 11.2852 +	while (opts->rev_id) {
 11.2853 +		if (bdp->rev_id == opts->rev_id) {
 11.2854 +			int i;
 11.2855 +			u32 *ucode_dword;
 11.2856 +			load_ucode_cb_t *ucode_cmd_ptr;
 11.2857 +			nxmit_cb_entry_t *cmd = e100_alloc_non_tx_cmd(bdp);
 11.2858 +
 11.2859 +			if (cmd != NULL) {
 11.2860 +				ucode_cmd_ptr =
 11.2861 +					(load_ucode_cb_t *) cmd->non_tx_cmd;
 11.2862 +				ucode_dword = ucode_cmd_ptr->ucode_dword;
 11.2863 +			} else {
 11.2864 +				return false;
 11.2865 +			}
 11.2866 +
 11.2867 +			memcpy(ucode_dword, opts->ucode, sizeof (opts->ucode));
 11.2868 +
 11.2869 +			/* Insert user-tunable settings */
 11.2870 +			ucode_dword[opts->timer_dword] &= 0xFFFF0000;
 11.2871 +			ucode_dword[opts->timer_dword] |=
 11.2872 +				(u16) bdp->params.IntDelay;
 11.2873 +			ucode_dword[opts->bundle_dword] &= 0xFFFF0000;
 11.2874 +			ucode_dword[opts->bundle_dword] |=
 11.2875 +				(u16) bdp->params.BundleMax;
 11.2876 +			ucode_dword[opts->min_size_dword] &= 0xFFFF0000;
 11.2877 +			ucode_dword[opts->min_size_dword] |=
 11.2878 +				(bdp->params.b_params & PRM_BUNDLE_SMALL) ?
 11.2879 +				0xFFFF : 0xFF80;
 11.2880 +
 11.2881 +			for (i = 0; i < UCODE_MAX_DWORDS; i++)
 11.2882 +				cpu_to_le32s(&(ucode_dword[i]));
 11.2883 +
 11.2884 +			ucode_cmd_ptr->load_ucode_cbhdr.cb_cmd =
 11.2885 +				__constant_cpu_to_le16(CB_LOAD_MICROCODE);
 11.2886 +
 11.2887 +			return e100_exec_non_cu_cmd(bdp, cmd);
 11.2888 +		}
 11.2889 +		opts++;
 11.2890 +	}
 11.2891 +
 11.2892 +	return false;
 11.2893 +}
 11.2894 +
 11.2895 +/***************************************************************************/
 11.2896 +/***************************************************************************/
 11.2897 +/*       EEPROM  Functions                                                 */
 11.2898 +/***************************************************************************/
 11.2899 +
 11.2900 +/* Read PWA (printed wired assembly) number */
 11.2901 +void __devinit
 11.2902 +e100_rd_pwa_no(struct e100_private *bdp)
 11.2903 +{
 11.2904 +	bdp->pwa_no = e100_eeprom_read(bdp, EEPROM_PWA_NO);
 11.2905 +	bdp->pwa_no <<= 16;
 11.2906 +	bdp->pwa_no |= e100_eeprom_read(bdp, EEPROM_PWA_NO + 1);
 11.2907 +}
 11.2908 +
 11.2909 +/* Read the permanent ethernet address from the eprom. */
 11.2910 +void __devinit
 11.2911 +e100_rd_eaddr(struct e100_private *bdp)
 11.2912 +{
 11.2913 +	int i;
 11.2914 +	u16 eeprom_word;
 11.2915 +
 11.2916 +	for (i = 0; i < 6; i += 2) {
 11.2917 +		eeprom_word =
 11.2918 +			e100_eeprom_read(bdp,
 11.2919 +					 EEPROM_NODE_ADDRESS_BYTE_0 + (i / 2));
 11.2920 +
 11.2921 +		bdp->device->dev_addr[i] =
 11.2922 +			bdp->perm_node_address[i] = (u8) eeprom_word;
 11.2923 +		bdp->device->dev_addr[i + 1] =
 11.2924 +			bdp->perm_node_address[i + 1] = (u8) (eeprom_word >> 8);
 11.2925 +	}
 11.2926 +}
 11.2927 +
 11.2928 +/* Check the D102 RFD flags to see if the checksum passed */
 11.2929 +static unsigned char
 11.2930 +e100_D102_check_checksum(rfd_t *rfd)
 11.2931 +{
 11.2932 +	if (((le16_to_cpu(rfd->rfd_header.cb_status)) & RFD_PARSE_BIT)
 11.2933 +	    && (((rfd->rcvparserstatus & CHECKSUM_PROTOCOL_MASK) ==
 11.2934 +		 RFD_TCP_PACKET)
 11.2935 +		|| ((rfd->rcvparserstatus & CHECKSUM_PROTOCOL_MASK) ==
 11.2936 +		    RFD_UDP_PACKET))
 11.2937 +	    && (rfd->checksumstatus & TCPUDP_CHECKSUM_BIT_VALID)
 11.2938 +	    && (rfd->checksumstatus & TCPUDP_CHECKSUM_VALID)) {
 11.2939 +		return CHECKSUM_UNNECESSARY;
 11.2940 +	}
 11.2941 +	return CHECKSUM_NONE;
 11.2942 +}
 11.2943 +
 11.2944 +/**
 11.2945 + * e100_D101M_checksum
 11.2946 + * @bdp: atapter's private data struct
 11.2947 + * @skb: skb received
 11.2948 + *
 11.2949 + * Sets the skb->csum value from D101 csum found at the end of the Rx frame. The
 11.2950 + * D101M sums all words in frame excluding the ethernet II header (14 bytes) so
 11.2951 + * in case the packet is ethernet II and the protocol is IP, all is need is to
 11.2952 + * assign this value to skb->csum.
 11.2953 + */
 11.2954 +static unsigned char
 11.2955 +e100_D101M_checksum(struct e100_private *bdp, struct sk_buff *skb)
 11.2956 +{
 11.2957 +	unsigned short proto = (skb->protocol);
 11.2958 +
 11.2959 +	if (proto == __constant_htons(ETH_P_IP)) {
 11.2960 +
 11.2961 +		skb->csum = get_unaligned((u16 *) (skb->tail));
 11.2962 +		return CHECKSUM_HW;
 11.2963 +	}
 11.2964 +	return CHECKSUM_NONE;
 11.2965 +}
 11.2966 +
 11.2967 +/***************************************************************************/
 11.2968 +/***************************************************************************/
 11.2969 +/***************************************************************************/
 11.2970 +/***************************************************************************/
 11.2971 +/*       Auxilary Functions                                                */
 11.2972 +/***************************************************************************/
 11.2973 +
 11.2974 +/* Print the board's configuration */
 11.2975 +void __devinit
 11.2976 +e100_print_brd_conf(struct e100_private *bdp)
 11.2977 +{
 11.2978 +	/* Print the string if checksum Offloading was enabled */
 11.2979 +	if (bdp->flags & DF_CSUM_OFFLOAD)
 11.2980 +		printk(KERN_NOTICE "  Hardware receive checksums enabled\n");
 11.2981 +	else {
 11.2982 +		if (bdp->rev_id >= D101MA_REV_ID) 
 11.2983 +			printk(KERN_NOTICE "  Hardware receive checksums disabled\n");
 11.2984 +	}
 11.2985 +
 11.2986 +	if ((bdp->flags & DF_UCODE_LOADED))
 11.2987 +		printk(KERN_NOTICE "  cpu cycle saver enabled\n");
 11.2988 +}
 11.2989 +
 11.2990 +/**
 11.2991 + * e100_pci_setup - setup the adapter's PCI information
 11.2992 + * @pcid: adapter's pci_dev struct
 11.2993 + * @bdp: atapter's private data struct
 11.2994 + *
 11.2995 + * This routine sets up all PCI information for the adapter. It enables the bus
 11.2996 + * master bit (some BIOS don't do this), requests memory ans I/O regions, and
 11.2997 + * calls ioremap() on the adapter's memory region.
 11.2998 + *
 11.2999 + * Returns:
 11.3000 + *      true: if successfull
 11.3001 + *      false: otherwise
 11.3002 + */
 11.3003 +static unsigned char __devinit
 11.3004 +e100_pci_setup(struct pci_dev *pcid, struct e100_private *bdp)
 11.3005 +{
 11.3006 +	struct net_device *dev = bdp->device;
 11.3007 +	int rc = 0;
 11.3008 +
 11.3009 +	if ((rc = pci_enable_device(pcid)) != 0) {
 11.3010 +		goto err;
 11.3011 +	}
 11.3012 +
 11.3013 +	/* dev and ven ID have already been checked so it is our device */
 11.3014 +	pci_read_config_byte(pcid, PCI_REVISION_ID, (u8 *) &(bdp->rev_id));
 11.3015 +
 11.3016 +	/* address #0 is a memory region */
 11.3017 +	dev->mem_start = pci_resource_start(pcid, 0);
 11.3018 +	dev->mem_end = dev->mem_start + sizeof (scb_t);
 11.3019 +
 11.3020 +	/* address #1 is a IO region */
 11.3021 +	dev->base_addr = pci_resource_start(pcid, 1);
 11.3022 +
 11.3023 +	if ((rc = pci_request_regions(pcid, e100_short_driver_name)) != 0) {
 11.3024 +		goto err_disable;
 11.3025 +	}
 11.3026 +
 11.3027 +	pci_enable_wake(pcid, 0, 0);
 11.3028 +
 11.3029 +	/* if Bus Mastering is off, turn it on! */
 11.3030 +	pci_set_master(pcid);
 11.3031 +
 11.3032 +	/* address #0 is a memory mapping */
 11.3033 +	bdp->scb = (scb_t *) ioremap_nocache(dev->mem_start, sizeof (scb_t));
 11.3034 +
 11.3035 +	if (!bdp->scb) {
 11.3036 +		printk(KERN_ERR "e100: %s: Failed to map PCI address 0x%lX\n",
 11.3037 +		       dev->name, pci_resource_start(pcid, 0));
 11.3038 +		rc = -ENOMEM;
 11.3039 +		goto err_region;
 11.3040 +	}
 11.3041 +
 11.3042 +	return 0;
 11.3043 +
 11.3044 +err_region:
 11.3045 +	pci_release_regions(pcid);
 11.3046 +err_disable:
 11.3047 +	pci_disable_device(pcid);
 11.3048 +err:
 11.3049 +	return rc;
 11.3050 +}
 11.3051 +
 11.3052 +void
 11.3053 +e100_isolate_driver(struct e100_private *bdp)
 11.3054 +{
 11.3055 +
 11.3056 +	/* Check if interface is up                              */
 11.3057 +	/* NOTE: Can't use netif_running(bdp->device) because    */
 11.3058 +	/* dev_close clears __LINK_STATE_START before calling    */
 11.3059 +	/* e100_close (aka dev->stop)                            */
 11.3060 +	if (bdp->device->flags & IFF_UP) {
 11.3061 +		e100_disable_clear_intr(bdp);
 11.3062 +		del_timer_sync(&bdp->watchdog_timer);
 11.3063 +		netif_carrier_off(bdp->device);
 11.3064 +		netif_stop_queue(bdp->device); 
 11.3065 +		bdp->last_tcb = NULL;
 11.3066 +	} 
 11.3067 +	e100_sw_reset(bdp, PORT_SELECTIVE_RESET);
 11.3068 +}
 11.3069 +
 11.3070 +void
 11.3071 +e100_set_speed_duplex(struct e100_private *bdp)
 11.3072 +{
 11.3073 +	int carrier_ok;
 11.3074 +	/* Device may lose link with some siwtches when */
 11.3075 +	/* changing speed/duplex to non-autoneg. e100   */
 11.3076 +	/* needs to remember carrier state in order to  */
 11.3077 +	/* start watchdog timer for recovering link     */
 11.3078 +	if ((carrier_ok = netif_carrier_ok(bdp->device)))
 11.3079 +		e100_isolate_driver(bdp);
 11.3080 +	e100_phy_set_speed_duplex(bdp, true);
 11.3081 +	e100_config_fc(bdp);	/* re-config flow-control if necessary */
 11.3082 +	e100_config(bdp);	
 11.3083 +	if (carrier_ok)
 11.3084 +		e100_deisolate_driver(bdp, false);
 11.3085 +}
 11.3086 +
 11.3087 +static void
 11.3088 +e100_tcb_add_C_bit(struct e100_private *bdp)
 11.3089 +{
 11.3090 +	tcb_t *tcb = (tcb_t *) bdp->tcb_pool.data;
 11.3091 +	int i;
 11.3092 +
 11.3093 +	for (i = 0; i < bdp->params.TxDescriptors; i++, tcb++) {
 11.3094 +		tcb->tcb_hdr.cb_status |= cpu_to_le16(CB_STATUS_COMPLETE);
 11.3095 +	}
 11.3096 +}
 11.3097 +
 11.3098 +/* 
 11.3099 + * Procedure:   e100_configure_device
 11.3100 + *
 11.3101 + * Description: This routine will configure device
 11.3102 + *
 11.3103 + * Arguments:
 11.3104 + *      bdp - Ptr to this card's e100_bdconfig structure
 11.3105 + *
 11.3106 + * Returns:
 11.3107 + *        true upon success
 11.3108 + *        false upon failure
 11.3109 + */
 11.3110 +unsigned char
 11.3111 +e100_configure_device(struct e100_private *bdp)
 11.3112 +{
 11.3113 +	/*load CU & RU base */
 11.3114 +	if (!e100_wait_exec_cmplx(bdp, 0, SCB_CUC_LOAD_BASE, 0))
 11.3115 +		return false;
 11.3116 +
 11.3117 +	if (e100_load_microcode(bdp))
 11.3118 +		bdp->flags |= DF_UCODE_LOADED;
 11.3119 +
 11.3120 +	if (!e100_wait_exec_cmplx(bdp, 0, SCB_RUC_LOAD_BASE, 0))
 11.3121 +		return false;
 11.3122 +
 11.3123 +	/* Issue the load dump counters address command */
 11.3124 +	if (!e100_wait_exec_cmplx(bdp, bdp->stat_cnt_phys, SCB_CUC_DUMP_ADDR, 0))
 11.3125 +		return false;
 11.3126 +
 11.3127 +	if (!e100_setup_iaaddr(bdp, bdp->device->dev_addr)) {
 11.3128 +		printk(KERN_ERR "e100: e100_configure_device: "
 11.3129 +			"setup iaaddr failed\n");
 11.3130 +		return false;
 11.3131 +	}
 11.3132 +
 11.3133 +	e100_set_multi_exec(bdp->device);
 11.3134 +
 11.3135 +	/* Change for 82558 enhancement                                */
 11.3136 +	/* If 82558/9 and if the user has enabled flow control, set up */
 11.3137 +	/* flow Control Reg. in the CSR                                */
 11.3138 +	if ((bdp->flags & IS_BACHELOR)
 11.3139 +	    && (bdp->params.b_params & PRM_FC)) {
 11.3140 +		writeb(DFLT_FC_THLD,
 11.3141 +			&bdp->scb->scb_ext.d101_scb.scb_fc_thld);
 11.3142 +		writeb(DFLT_FC_CMD,
 11.3143 +			&bdp->scb->scb_ext.d101_scb.scb_fc_xon_xoff);
 11.3144 +	}
 11.3145 +
 11.3146 +	e100_force_config(bdp);
 11.3147 +
 11.3148 +	return true;
 11.3149 +}
 11.3150 +
 11.3151 +void
 11.3152 +e100_deisolate_driver(struct e100_private *bdp, u8 full_reset)
 11.3153 +{
 11.3154 +	u32 cmd = full_reset ? PORT_SOFTWARE_RESET : PORT_SELECTIVE_RESET;
 11.3155 +	e100_sw_reset(bdp, cmd);
 11.3156 +	if (cmd == PORT_SOFTWARE_RESET) {
 11.3157 +		if (!e100_configure_device(bdp))
 11.3158 +			printk(KERN_ERR "e100: e100_deisolate_driver:" 
 11.3159 +		       		" device configuration failed\n");
 11.3160 +	} 
 11.3161 +
 11.3162 +	if (netif_running(bdp->device)) {
 11.3163 +
 11.3164 +		bdp->next_cu_cmd = START_WAIT;
 11.3165 +		bdp->last_tcb = NULL;
 11.3166 +
 11.3167 +		e100_start_ru(bdp);
 11.3168 +
 11.3169 +		/* relaunch watchdog timer in 2 sec */
 11.3170 +		mod_timer(&(bdp->watchdog_timer), jiffies + (2 * HZ));
 11.3171 +
 11.3172 +		// we must clear tcbs since we may have lost Tx intrrupt
 11.3173 +		// or have unsent frames on the tcb chain
 11.3174 +		e100_tcb_add_C_bit(bdp);
 11.3175 +		e100_tx_srv(bdp);
 11.3176 +		netif_wake_queue(bdp->device);
 11.3177 +		e100_set_intr_mask(bdp);
 11.3178 +	}
 11.3179 +}
 11.3180 +
 11.3181 +#if 0
 11.3182 +static int
 11.3183 +e100_do_ethtool_ioctl(struct net_device *dev, struct ifreq *ifr)
 11.3184 +{
 11.3185 +	struct ethtool_cmd ecmd;
 11.3186 +	int rc = -EOPNOTSUPP;
 11.3187 +
 11.3188 +	if (copy_from_user(&ecmd, ifr->ifr_data, sizeof (ecmd.cmd)))
 11.3189 +		return -EFAULT;
 11.3190 +
 11.3191 +	switch (ecmd.cmd) {
 11.3192 +	case ETHTOOL_GSET:
 11.3193 +		rc = e100_ethtool_get_settings(dev, ifr);
 11.3194 +		break;
 11.3195 +	case ETHTOOL_SSET:
 11.3196 +		rc = e100_ethtool_set_settings(dev, ifr);
 11.3197 +		break;
 11.3198 +	case ETHTOOL_GDRVINFO:
 11.3199 +		rc = e100_ethtool_get_drvinfo(dev, ifr);
 11.3200 +		break;
 11.3201 +	case ETHTOOL_GREGS:
 11.3202 +		rc = e100_ethtool_gregs(dev, ifr);
 11.3203 +		break;
 11.3204 +	case ETHTOOL_NWAY_RST:
 11.3205 +		rc = e100_ethtool_nway_rst(dev, ifr);
 11.3206 +		break;
 11.3207 +	case ETHTOOL_GLINK:
 11.3208 +		rc = e100_ethtool_glink(dev, ifr);
 11.3209 +		break;
 11.3210 +	case ETHTOOL_GEEPROM:
 11.3211 +	case ETHTOOL_SEEPROM:
 11.3212 +		rc = e100_ethtool_eeprom(dev, ifr);
 11.3213 +		break;
 11.3214 +	case ETHTOOL_GSTATS: {
 11.3215 +		struct {
 11.3216 +			struct ethtool_stats cmd;
 11.3217 +			uint64_t data[E100_STATS_LEN];
 11.3218 +		} stats = { {ETHTOOL_GSTATS, E100_STATS_LEN} };
 11.3219 +		struct e100_private *bdp = dev->priv;
 11.3220 +		void *addr = ifr->ifr_data;
 11.3221 +		int i;
 11.3222 +
 11.3223 +		for(i = 0; i < E100_STATS_LEN; i++)
 11.3224 +			stats.data[i] =
 11.3225 +				((unsigned long *)&bdp->drv_stats.net_stats)[i];
 11.3226 +		if(copy_to_user(addr, &stats, sizeof(stats)))
 11.3227 +			return -EFAULT;
 11.3228 +		return 0;
 11.3229 +	}
 11.3230 +	case ETHTOOL_GWOL:
 11.3231 +	case ETHTOOL_SWOL:
 11.3232 +		rc = e100_ethtool_wol(dev, ifr);
 11.3233 +		break;
 11.3234 +	case ETHTOOL_TEST:
 11.3235 +		rc = e100_ethtool_test(dev, ifr);
 11.3236 +		break;
 11.3237 +	case ETHTOOL_GSTRINGS:
 11.3238 +		rc = e100_ethtool_gstrings(dev,ifr);
 11.3239 +		break;
 11.3240 +	case ETHTOOL_PHYS_ID:
 11.3241 +		rc = e100_ethtool_led_blink(dev,ifr);
 11.3242 +		break;
 11.3243 +	default:
 11.3244 +		break;
 11.3245 +	}			//switch
 11.3246 +	return rc;
 11.3247 +}
 11.3248 +
 11.3249 +static int
 11.3250 +e100_ethtool_get_settings(struct net_device *dev, struct ifreq *ifr)
 11.3251 +{
 11.3252 +	struct e100_private *bdp;
 11.3253 +	struct ethtool_cmd ecmd;
 11.3254 +	u16 advert = 0;
 11.3255 +
 11.3256 +	memset((void *) &ecmd, 0, sizeof (ecmd));
 11.3257 +
 11.3258 +	bdp = dev->priv;
 11.3259 +
 11.3260 +	ecmd.supported = bdp->speed_duplex_caps;
 11.3261 +
 11.3262 +	ecmd.port =
 11.3263 +		(bdp->speed_duplex_caps & SUPPORTED_TP) ? PORT_TP : PORT_FIBRE;
 11.3264 +	ecmd.transceiver = XCVR_INTERNAL;
 11.3265 +	ecmd.phy_address = bdp->phy_addr;
 11.3266 +
 11.3267 +	if (netif_carrier_ok(bdp->device)) {
 11.3268 +		ecmd.speed = bdp->cur_line_speed;
 11.3269 +		ecmd.duplex =
 11.3270 +			(bdp->cur_dplx_mode == HALF_DUPLEX) ? DUPLEX_HALF : DUPLEX_FULL;
 11.3271 +	}
 11.3272 +	else {
 11.3273 +		ecmd.speed = -1;
 11.3274 +		ecmd.duplex = -1;
 11.3275 +	}
 11.3276 +
 11.3277 +	ecmd.advertising = ADVERTISED_TP;
 11.3278 +
 11.3279 +	if (bdp->params.e100_speed_duplex == E100_AUTONEG) {
 11.3280 +		ecmd.autoneg = AUTONEG_ENABLE;
 11.3281 +		ecmd.advertising |= ADVERTISED_Autoneg;
 11.3282 +	} else {
 11.3283 +		ecmd.autoneg = AUTONEG_DISABLE;
 11.3284 +	}
 11.3285 +
 11.3286 +	if (bdp->speed_duplex_caps & SUPPORTED_MII) {
 11.3287 +		e100_mdi_read(bdp, MII_ADVERTISE, bdp->phy_addr, &advert);
 11.3288 +
 11.3289 +		if (advert & ADVERTISE_10HALF)
 11.3290 +			ecmd.advertising |= ADVERTISED_10baseT_Half;
 11.3291 +		if (advert & ADVERTISE_10FULL)
 11.3292 +			ecmd.advertising |= ADVERTISED_10baseT_Full;
 11.3293 +		if (advert & ADVERTISE_100HALF)
 11.3294 +			ecmd.advertising |= ADVERTISED_100baseT_Half;
 11.3295 +		if (advert & ADVERTISE_100FULL)
 11.3296 +			ecmd.advertising |= ADVERTISED_100baseT_Full;
 11.3297 +	} else {
 11.3298 +		ecmd.autoneg = AUTONEG_DISABLE;
 11.3299 +		ecmd.advertising &= ~ADVERTISED_Autoneg;
 11.3300 +	}
 11.3301 +
 11.3302 +	if (copy_to_user(ifr->ifr_data, &ecmd, sizeof (ecmd)))
 11.3303 +		return -EFAULT;
 11.3304 +
 11.3305 +	return 0;
 11.3306 +}
 11.3307 +
 11.3308 +static int
 11.3309 +e100_ethtool_set_settings(struct net_device *dev, struct ifreq *ifr)
 11.3310 +{
 11.3311 +	struct e100_private *bdp;
 11.3312 +	int e100_new_speed_duplex;
 11.3313 +	int ethtool_new_speed_duplex;
 11.3314 +	struct ethtool_cmd ecmd;
 11.3315 +
 11.3316 +	if (!capable(CAP_NET_ADMIN)) {
 11.3317 +		return -EPERM;
 11.3318 +	}
 11.3319 +
 11.3320 +	bdp = dev->priv;
 11.3321 +	if (copy_from_user(&ecmd, ifr->ifr_data, sizeof (ecmd))) {
 11.3322 +		return -EFAULT;
 11.3323 +	}
 11.3324 +
 11.3325 +	if ((ecmd.autoneg == AUTONEG_ENABLE)
 11.3326 +	    && (bdp->speed_duplex_caps & SUPPORTED_Autoneg)) {
 11.3327 +		bdp->params.e100_speed_duplex = E100_AUTONEG;
 11.3328 +		e100_set_speed_duplex(bdp);
 11.3329 +	} else {
 11.3330 +		if (ecmd.speed == SPEED_10) {
 11.3331 +			if (ecmd.duplex == DUPLEX_HALF) {
 11.3332 +				e100_new_speed_duplex =
 11.3333 +					E100_SPEED_10_HALF;
 11.3334 +				ethtool_new_speed_duplex =
 11.3335 +					SUPPORTED_10baseT_Half;
 11.3336 +			} else { 
 11.3337 +				e100_new_speed_duplex =
 11.3338 +					E100_SPEED_10_FULL;
 11.3339 +				ethtool_new_speed_duplex =
 11.3340 +					SUPPORTED_10baseT_Full;
 11.3341 +			} 
 11.3342 +		} else { 
 11.3343 +			if (ecmd.duplex == DUPLEX_HALF) {
 11.3344 +				e100_new_speed_duplex =
 11.3345 +					E100_SPEED_100_HALF;
 11.3346 +				ethtool_new_speed_duplex =
 11.3347 +					SUPPORTED_100baseT_Half;
 11.3348 +			} else { 
 11.3349 +				e100_new_speed_duplex =
 11.3350 +					E100_SPEED_100_FULL;
 11.3351 +				ethtool_new_speed_duplex =
 11.3352 +					SUPPORTED_100baseT_Full;
 11.3353 +			} 
 11.3354 +		}
 11.3355 +
 11.3356 +		if (bdp->speed_duplex_caps & ethtool_new_speed_duplex) {
 11.3357 +			bdp->params.e100_speed_duplex =
 11.3358 +				e100_new_speed_duplex;
 11.3359 +			e100_set_speed_duplex(bdp);
 11.3360 +		} else {
 11.3361 +			return -EOPNOTSUPP;
 11.3362 +		} 
 11.3363 +	}
 11.3364 +
 11.3365 +	return 0;
 11.3366 +}
 11.3367 +
 11.3368 +static int
 11.3369 +e100_ethtool_glink(struct net_device *dev, struct ifreq *ifr)
 11.3370 +{
 11.3371 +	struct e100_private *bdp;
 11.3372 +	struct ethtool_value info;
 11.3373 +
 11.3374 +	memset((void *) &info, 0, sizeof (info));
 11.3375 +
 11.3376 +	bdp = dev->priv;
 11.3377 +	info.cmd = ETHTOOL_GLINK;
 11.3378 +
 11.3379 +	/* Consider both PHY link and netif_running */
 11.3380 +	info.data = e100_update_link_state(bdp);
 11.3381 +
 11.3382 +	if (copy_to_user(ifr->ifr_data, &info, sizeof (info)))
 11.3383 +		return -EFAULT;
 11.3384 +
 11.3385 +	return 0;
 11.3386 +}
 11.3387 +
 11.3388 +static int
 11.3389 +e100_ethtool_test(struct net_device *dev, struct ifreq *ifr)
 11.3390 +{
 11.3391 +	struct ethtool_test *info;
 11.3392 +	int rc = -EFAULT;
 11.3393 +
 11.3394 +	info = kmalloc(sizeof(*info) + E100_MAX_TEST_RES * sizeof(u64),
 11.3395 +		       GFP_ATOMIC);
 11.3396 +
 11.3397 +	if (!info)
 11.3398 +		return -ENOMEM;
 11.3399 +
 11.3400 +	memset((void *) info, 0, sizeof(*info) +
 11.3401 +				 E100_MAX_TEST_RES * sizeof(u64));
 11.3402 +
 11.3403 +	if (copy_from_user(info, ifr->ifr_data, sizeof(*info)))
 11.3404 +		goto exit;
 11.3405 +
 11.3406 +	info->flags = e100_run_diag(dev, info->data, info->flags);
 11.3407 +
 11.3408 +	if (!copy_to_user(ifr->ifr_data, info,
 11.3409 +			 sizeof(*info) + E100_MAX_TEST_RES * sizeof(u64)))
 11.3410 +		rc = 0;
 11.3411 +exit:
 11.3412 +	kfree(info);
 11.3413 +	return rc;
 11.3414 +}
 11.3415 +
 11.3416 +static int
 11.3417 +e100_ethtool_gregs(struct net_device *dev, struct ifreq *ifr)
 11.3418 +{
 11.3419 +	struct e100_private *bdp;
 11.3420 +	u32 regs_buff[E100_REGS_LEN];
 11.3421 +	struct ethtool_regs regs = {ETHTOOL_GREGS};
 11.3422 +	void *addr = ifr->ifr_data;
 11.3423 +
 11.3424 +	if (!capable(CAP_NET_ADMIN))
 11.3425 +		return -EPERM;
 11.3426 +	bdp = dev->priv;
 11.3427 +
 11.3428 +	if(copy_from_user(&regs, addr, sizeof(regs)))
 11.3429 +		return -EFAULT;
 11.3430 +
 11.3431 +	regs.version = (1 << 24) | bdp->rev_id;
 11.3432 +	regs_buff[0] = readb(&(bdp->scb->scb_cmd_hi)) << 24 |
 11.3433 +		readb(&(bdp->scb->scb_cmd_low)) << 16 |
 11.3434 +		readw(&(bdp->scb->scb_status));
 11.3435 +
 11.3436 +	if(copy_to_user(addr, &regs, sizeof(regs)))
 11.3437 +		return -EFAULT;
 11.3438 +
 11.3439 +	addr += offsetof(struct ethtool_regs, data);
 11.3440 +	if(copy_to_user(addr, regs_buff, regs.len))
 11.3441 +		return -EFAULT;
 11.3442 +
 11.3443 +	return 0;
 11.3444 +}
 11.3445 +
 11.3446 +static int
 11.3447 +e100_ethtool_nway_rst(struct net_device *dev, struct ifreq *ifr)
 11.3448 +{
 11.3449 +	struct e100_private *bdp;
 11.3450 +
 11.3451 +	if (!capable(CAP_NET_ADMIN))
 11.3452 +		return -EPERM;
 11.3453 +
 11.3454 +	bdp = dev->priv;
 11.3455 +
 11.3456 +	if ((bdp->speed_duplex_caps & SUPPORTED_Autoneg) &&
 11.3457 +	    (bdp->params.e100_speed_duplex == E100_AUTONEG)) {
 11.3458 +		e100_set_speed_duplex(bdp);
 11.3459 +	} else {
 11.3460 +		return -EFAULT;
 11.3461 +	}
 11.3462 +	return 0;
 11.3463 +}
 11.3464 +
 11.3465 +static int
 11.3466 +e100_ethtool_get_drvinfo(struct net_device *dev, struct ifreq *ifr)
 11.3467 +{
 11.3468 +	struct e100_private *bdp;
 11.3469 +	struct ethtool_drvinfo info;
 11.3470 +
 11.3471 +	memset((void *) &info, 0, sizeof (info));
 11.3472 +
 11.3473 +	bdp = dev->priv;
 11.3474 +
 11.3475 +	strncpy(info.driver, e100_short_driver_name, sizeof (info.driver) - 1);
 11.3476 +	strncpy(info.version, e100_driver_version, sizeof (info.version) - 1);
 11.3477 +	strncpy(info.fw_version, "N/A",
 11.3478 +		sizeof (info.fw_version) - 1);
 11.3479 +	strncpy(info.bus_info, bdp->pdev->slot_name,
 11.3480 +		sizeof (info.bus_info) - 1);
 11.3481 +	info.n_stats = E100_STATS_LEN;
 11.3482 +	info.regdump_len  = E100_REGS_LEN * sizeof(u32);
 11.3483 +	info.eedump_len = (bdp->eeprom_size << 1);	
 11.3484 +	info.testinfo_len = E100_MAX_TEST_RES;
 11.3485 +	if (copy_to_user(ifr->ifr_data, &info, sizeof (info)))
 11.3486 +		return -EFAULT;
 11.3487 +
 11.3488 +	return 0;
 11.3489 +}
 11.3490 +
 11.3491 +static int
 11.3492 +e100_ethtool_eeprom(struct net_device *dev, struct ifreq *ifr)
 11.3493 +{
 11.3494 +	struct e100_private *bdp;
 11.3495 +	struct ethtool_eeprom ecmd;
 11.3496 +	u16 eeprom_data[256];
 11.3497 +	u16 *usr_eeprom_ptr;
 11.3498 +	u16 first_word, last_word;
 11.3499 +	int i, max_len;
 11.3500 +	void *ptr;
 11.3501 +	u8 *eeprom_data_bytes = (u8 *)eeprom_data;
 11.3502 +
 11.3503 +	if (!capable(CAP_NET_ADMIN))
 11.3504 +		return -EPERM;
 11.3505 +
 11.3506 +	bdp = dev->priv;
 11.3507 +
 11.3508 +	if (copy_from_user(&ecmd, ifr->ifr_data, sizeof (ecmd)))
 11.3509 +		return -EFAULT;
 11.3510 +
 11.3511 +	usr_eeprom_ptr =
 11.3512 +		(u16 *) (ifr->ifr_data + offsetof(struct ethtool_eeprom, data));
 11.3513 +
 11.3514 +        max_len = bdp->eeprom_size * 2;
 11.3515 +        
 11.3516 +        if (ecmd.offset > ecmd.offset + ecmd.len)
 11.3517 +        	return -EINVAL;
 11.3518 +        	
 11.3519 +	if ((ecmd.offset + ecmd.len) > max_len)
 11.3520 +		ecmd.len = (max_len - ecmd.offset);
 11.3521 +
 11.3522 +	first_word = ecmd.offset >> 1;
 11.3523 +	last_word = (ecmd.offset + ecmd.len - 1) >> 1;
 11.3524 +		
 11.3525 +	if (first_word >= bdp->eeprom_size)
 11.3526 +		return -EFAULT;
 11.3527 +
 11.3528 +	if (ecmd.cmd == ETHTOOL_GEEPROM) {
 11.3529 +        	for(i = 0; i <= (last_word - first_word); i++)
 11.3530 +			eeprom_data[i] = e100_eeprom_read(bdp, first_word + i);
 11.3531 +
 11.3532 +		ecmd.magic = E100_EEPROM_MAGIC;
 11.3533 +
 11.3534 +		if (copy_to_user(ifr->ifr_data, &ecmd, sizeof (ecmd)))
 11.3535 +			return -EFAULT;
 11.3536 +
 11.3537 +		if(ecmd.offset & 1)
 11.3538 +			eeprom_data_bytes++;
 11.3539 +		if (copy_to_user(usr_eeprom_ptr, eeprom_data_bytes, ecmd.len))
 11.3540 +			return -EFAULT;
 11.3541 +	} else {
 11.3542 +		if (ecmd.magic != E100_EEPROM_MAGIC)
 11.3543 +			return -EFAULT;
 11.3544 +
 11.3545 +		ptr = (void *)eeprom_data;
 11.3546 +        	if(ecmd.offset & 1) {
 11.3547 +                	/* need modification of first changed EEPROM word */
 11.3548 +                	/* only the second byte of the word is being modified */
 11.3549 +			eeprom_data[0] = e100_eeprom_read(bdp, first_word);
 11.3550 +                	ptr++;
 11.3551 +        	}
 11.3552 +        	if((ecmd.offset + ecmd.len) & 1) {
 11.3553 +	                /* need modification of last changed EEPROM word */
 11.3554 +	                /* only the first byte of the word is being modified */
 11.3555 +			eeprom_data[last_word - first_word] = 
 11.3556 +				e100_eeprom_read(bdp, last_word);
 11.3557 +		}
 11.3558 +        	if(copy_from_user(ptr, usr_eeprom_ptr, ecmd.len))
 11.3559 +	                return -EFAULT;
 11.3560 +
 11.3561 +		e100_eeprom_write_block(bdp, first_word, eeprom_data,
 11.3562 +					last_word - first_word + 1);
 11.3563 +
 11.3564 +		if (copy_to_user(ifr->ifr_data, &ecmd, sizeof (ecmd)))
 11.3565 +			return -EFAULT;
 11.3566 +	}
 11.3567 +	return 0;
 11.3568 +}
 11.3569 +#endif
 11.3570 +
 11.3571 +#define E100_BLINK_INTERVAL	(HZ/4)
 11.3572 +/**
 11.3573 + * e100_led_control
 11.3574 + * @bdp: atapter's private data struct
 11.3575 + * @led_mdi_op: led operation
 11.3576 + *
 11.3577 + * Software control over adapter's led. The possible operations are:
 11.3578 + * TURN LED OFF, TURN LED ON and RETURN LED CONTROL TO HARDWARE.
 11.3579 + */
 11.3580 +static void
 11.3581 +e100_led_control(struct e100_private *bdp, u16 led_mdi_op)
 11.3582 +{
 11.3583 +	e100_mdi_write(bdp, PHY_82555_LED_SWITCH_CONTROL,
 11.3584 +		       bdp->phy_addr, led_mdi_op);
 11.3585 +
 11.3586 +}
 11.3587 +/**
 11.3588 + * e100_led_blink_callback
 11.3589 + * @data: pointer to atapter's private data struct
 11.3590 + *
 11.3591 + * Blink timer callback function. Toggles ON/OFF led status bit and calls
 11.3592 + * led hardware access function. 
 11.3593 + */
 11.3594 +static void
 11.3595 +e100_led_blink_callback(unsigned long data)
 11.3596 +{
 11.3597 +	struct e100_private *bdp = (struct e100_private *) data;
 11.3598 +
 11.3599 +	if(bdp->flags & LED_IS_ON) {
 11.3600 +		bdp->flags &= ~LED_IS_ON;
 11.3601 +		e100_led_control(bdp, PHY_82555_LED_OFF);
 11.3602 +	} else {
 11.3603 +		bdp->flags |= LED_IS_ON;
 11.3604 +		if (bdp->rev_id >= D101MA_REV_ID)
 11.3605 +			e100_led_control(bdp, PHY_82555_LED_ON_559);
 11.3606 +		else
 11.3607 +			e100_led_control(bdp, PHY_82555_LED_ON_PRE_559);
 11.3608 +	}
 11.3609 +
 11.3610 +	mod_timer(&bdp->blink_timer, jiffies + E100_BLINK_INTERVAL);
 11.3611 +}
 11.3612 +/**
 11.3613 + * e100_ethtool_led_blink
 11.3614 + * @dev: pointer to atapter's net_device struct
 11.3615 + * @ifr: pointer to ioctl request structure
 11.3616 + *
 11.3617 + * Blink led ioctl handler. Initialtes blink timer and sleeps until
 11.3618 + * blink period expires. Than it kills timer and returns. The led control
 11.3619 + * is returned back to hardware when blink timer is killed.
 11.3620 + */
 11.3621 +static int
 11.3622 +e100_ethtool_led_blink(struct net_device *dev, struct ifreq *ifr)
 11.3623 +{
 11.3624 +	struct e100_private *bdp;
 11.3625 +	struct ethtool_value ecmd;
 11.3626 +
 11.3627 +	bdp = dev->priv;
 11.3628 +
 11.3629 +	if (copy_from_user(&ecmd, ifr->ifr_data, sizeof (ecmd)))
 11.3630 +		return -EFAULT;
 11.3631 +
 11.3632 +	if(!bdp->blink_timer.function) {
 11.3633 +		init_timer(&bdp->blink_timer);
 11.3634 +		bdp->blink_timer.function = e100_led_blink_callback;
 11.3635 +		bdp->blink_timer.data = (unsigned long) bdp;
 11.3636 +	}
 11.3637 +
 11.3638 +	mod_timer(&bdp->blink_timer, jiffies);
 11.3639 +
 11.3640 +	set_current_state(TASK_INTERRUPTIBLE);
 11.3641 +
 11.3642 +	if ((!ecmd.data) || (ecmd.data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ)))
 11.3643 +		ecmd.data = (u32)(MAX_SCHEDULE_TIMEOUT / HZ);
 11.3644 +
 11.3645 +	schedule_timeout(ecmd.data * HZ);
 11.3646 +
 11.3647 +	del_timer_sync(&bdp->blink_timer);
 11.3648 +
 11.3649 +	e100_led_control(bdp, PHY_82555_LED_NORMAL_CONTROL);
 11.3650 +
 11.3651 +	return 0;
 11.3652 +}
 11.3653 +
 11.3654 +static inline int __devinit
 11.3655 +e100_10BaseT_adapter(struct e100_private *bdp)
 11.3656 +{
 11.3657 +	return ((bdp->pdev->device == 0x1229) &&
 11.3658 +		(bdp->pdev->subsystem_vendor == 0x8086) &&
 11.3659 +		(bdp->pdev->subsystem_device == 0x0003));
 11.3660 +}
 11.3661 +
 11.3662 +static void __devinit
 11.3663 +e100_get_speed_duplex_caps(struct e100_private *bdp)
 11.3664 +{
 11.3665 +	u16 status;
 11.3666 +
 11.3667 +	e100_mdi_read(bdp, MII_BMSR, bdp->phy_addr, &status);
 11.3668 +
 11.3669 +	bdp->speed_duplex_caps = 0;
 11.3670 +
 11.3671 +	bdp->speed_duplex_caps |=
 11.3672 +		(status & BMSR_ANEGCAPABLE) ? SUPPORTED_Autoneg : 0;
 11.3673 +
 11.3674 +	bdp->speed_duplex_caps |=
 11.3675 +		(status & BMSR_10HALF) ? SUPPORTED_10baseT_Half : 0;
 11.3676 +
 11.3677 +	bdp->speed_duplex_caps |=
 11.3678 +		(status & BMSR_10FULL) ? SUPPORTED_10baseT_Full : 0;
 11.3679 +
 11.3680 +	bdp->speed_duplex_caps |=
 11.3681 +		(status & BMSR_100HALF) ? SUPPORTED_100baseT_Half : 0;
 11.3682 +
 11.3683 +	bdp->speed_duplex_caps |=
 11.3684 +		(status & BMSR_100FULL) ? SUPPORTED_100baseT_Full : 0;
 11.3685 +
 11.3686 +	if (IS_NC3133(bdp))
 11.3687 +		bdp->speed_duplex_caps =
 11.3688 +			(SUPPORTED_FIBRE | SUPPORTED_100baseT_Full);
 11.3689 +	else
 11.3690 +		bdp->speed_duplex_caps |= SUPPORTED_TP;
 11.3691 +
 11.3692 +	if ((status == 0xFFFF) && e100_10BaseT_adapter(bdp)) {
 11.3693 +		bdp->speed_duplex_caps =
 11.3694 +			(SUPPORTED_10baseT_Half | SUPPORTED_TP);
 11.3695 +	} else {
 11.3696 +		bdp->speed_duplex_caps |= SUPPORTED_MII;
 11.3697 +	}
 11.3698 +
 11.3699 +}
 11.3700 +
 11.3701 +#ifdef CONFIG_PM
 11.3702 +static unsigned char
 11.3703 +e100_setup_filter(struct e100_private *bdp)
 11.3704 +{
 11.3705 +	cb_header_t *ntcb_hdr;
 11.3706 +	unsigned char res = false;
 11.3707 +	nxmit_cb_entry_t *cmd;
 11.3708 +
 11.3709 +	if ((cmd = e100_alloc_non_tx_cmd(bdp)) == NULL) {
 11.3710 +		goto exit;
 11.3711 +	}
 11.3712 +
 11.3713 +	ntcb_hdr = (cb_header_t *) cmd->non_tx_cmd;
 11.3714 +	ntcb_hdr->cb_cmd = __constant_cpu_to_le16(CB_LOAD_FILTER);
 11.3715 +
 11.3716 +	/* Set EL and FIX bit */
 11.3717 +	(cmd->non_tx_cmd)->ntcb.filter.filter_data[0] =
 11.3718 +		__constant_cpu_to_le32(CB_FILTER_EL | CB_FILTER_FIX);
 11.3719 +
 11.3720 +	if (bdp->wolopts & WAKE_UCAST) {
 11.3721 +		(cmd->non_tx_cmd)->ntcb.filter.filter_data[0] |=
 11.3722 +			__constant_cpu_to_le32(CB_FILTER_IA_MATCH);
 11.3723 +	}
 11.3724 +
 11.3725 +	if (bdp->wolopts & WAKE_ARP) {
 11.3726 +		/* Setup ARP bit and lower IP parts */
 11.3727 +		/* bdp->ip_lbytes contains 2 lower bytes of IP address in network byte order */
 11.3728 +		(cmd->non_tx_cmd)->ntcb.filter.filter_data[0] |=
 11.3729 +			cpu_to_le32(CB_FILTER_ARP | bdp->ip_lbytes);
 11.3730 +	}
 11.3731 +
 11.3732 +	res = e100_exec_non_cu_cmd(bdp, cmd);
 11.3733 +	if (!res)
 11.3734 +		printk(KERN_WARNING "e100: %s: Filter setup failed\n",
 11.3735 +		       bdp->device->name);
 11.3736 +
 11.3737 +exit:
 11.3738 +	return res;
 11.3739 +
 11.3740 +}
 11.3741 +
 11.3742 +static void
 11.3743 +e100_do_wol(struct pci_dev *pcid, struct e100_private *bdp)
 11.3744 +{
 11.3745 +	e100_config_wol(bdp);
 11.3746 +
 11.3747 +	if (e100_config(bdp)) {
 11.3748 +		if (bdp->wolopts & (WAKE_UCAST | WAKE_ARP))
 11.3749 +			if (!e100_setup_filter(bdp))
 11.3750 +				printk(KERN_ERR
 11.3751 +				       "e100: WOL options failed\n");
 11.3752 +	} else {
 11.3753 +		printk(KERN_ERR "e100: config WOL failed\n");
 11.3754 +	}
 11.3755 +}
 11.3756 +#endif
 11.3757 +
 11.3758 +#if 0
 11.3759 +static u16
 11.3760 +e100_get_ip_lbytes(struct net_device *dev)
 11.3761 +{
 11.3762 +	struct in_ifaddr *ifa;
 11.3763 +	struct in_device *in_dev;
 11.3764 +	u32 res = 0;
 11.3765 +
 11.3766 +	in_dev = (struct in_device *) dev->ip_ptr;
 11.3767 +	/* Check if any in_device bound to interface */
 11.3768 +	if (in_dev) {
 11.3769 +		/* Check if any IP address is bound to interface */
 11.3770 +		if ((ifa = in_dev->ifa_list) != NULL) {
 11.3771 +			res = __constant_ntohl(ifa->ifa_address);
 11.3772 +			res = __constant_htons(res & 0x0000ffff);
 11.3773 +		}
 11.3774 +	}
 11.3775 +	return res;
 11.3776 +}
 11.3777 +
 11.3778 +static int
 11.3779 +e100_ethtool_wol(struct net_device *dev, struct ifreq *ifr)
 11.3780 +{
 11.3781 +	struct e100_private *bdp;
 11.3782 +	struct ethtool_wolinfo wolinfo;
 11.3783 +	int res = 0;
 11.3784 +
 11.3785 +	if (!capable(CAP_NET_ADMIN))
 11.3786 +		return -EPERM;
 11.3787 +
 11.3788 +	bdp = dev->priv;
 11.3789 +
 11.3790 +	if (copy_from_user(&wolinfo, ifr->ifr_data, sizeof (wolinfo))) {
 11.3791 +		return -EFAULT;
 11.3792 +	}
 11.3793 +
 11.3794 +	switch (wolinfo.cmd) {
 11.3795 +	case ETHTOOL_GWOL:
 11.3796 +		wolinfo.supported = bdp->wolsupported;
 11.3797 +		wolinfo.wolopts = bdp->wolopts;
 11.3798 +		if (copy_to_user(ifr->ifr_data, &wolinfo, sizeof (wolinfo)))
 11.3799 +			res = -EFAULT;
 11.3800 +		break;
 11.3801 +	case ETHTOOL_SWOL:
 11.3802 +		/* If ALL requests are supported or request is DISABLE wol */
 11.3803 +		if (((wolinfo.wolopts & bdp->wolsupported) == wolinfo.wolopts)
 11.3804 +		    || (wolinfo.wolopts == 0)) {
 11.3805 +			bdp->wolopts = wolinfo.wolopts;
 11.3806 +		} else {
 11.3807 +			res = -EOPNOTSUPP;
 11.3808 +		}
 11.3809 +		if (wolinfo.wolopts & WAKE_ARP)
 11.3810 +			bdp->ip_lbytes = e100_get_ip_lbytes(dev);
 11.3811 +		break;
 11.3812 +	default:
 11.3813 +		break;
 11.3814 +	}
 11.3815 +	return res;
 11.3816 +}
 11.3817 +
 11.3818 +static int e100_ethtool_gstrings(struct net_device *dev, struct ifreq *ifr)
 11.3819 +{
 11.3820 +	struct ethtool_gstrings info;
 11.3821 +	char *strings = NULL;
 11.3822 +	char *usr_strings;
 11.3823 +	int i;
 11.3824 +
 11.3825 +	memset((void *) &info, 0, sizeof(info));
 11.3826 +
 11.3827 +	usr_strings = (u8 *) (ifr->ifr_data + 
 11.3828 +			      offsetof(struct ethtool_gstrings, data));
 11.3829 +
 11.3830 +	if (copy_from_user(&info, ifr->ifr_data, sizeof (info)))
 11.3831 +		return -EFAULT;
 11.3832 +
 11.3833 +	switch (info.string_set) {
 11.3834 +	case ETH_SS_TEST: {
 11.3835 +		int ret = 0;
 11.3836 +		if (info.len > E100_MAX_TEST_RES)
 11.3837 +			info.len = E100_MAX_TEST_RES;
 11.3838 +		strings = kmalloc(info.len * ETH_GSTRING_LEN, GFP_ATOMIC);
 11.3839 +		if (!strings)
 11.3840 +			return -ENOMEM;
 11.3841 +		memset(strings, 0, info.len * ETH_GSTRING_LEN);
 11.3842 +
 11.3843 +		for (i = 0; i < info.len; i++) {
 11.3844 +			sprintf(strings + i * ETH_GSTRING_LEN, "%-31s",
 11.3845 +				test_strings[i]);
 11.3846 +		}
 11.3847 +		if (copy_to_user(ifr->ifr_data, &info, sizeof (info)))
 11.3848 +			ret = -EFAULT;
 11.3849 +		if (copy_to_user(usr_strings, strings, info.len * ETH_GSTRING_LEN))
 11.3850 +			ret = -EFAULT;
 11.3851 +		kfree(strings);
 11.3852 +		return ret;
 11.3853 +	}
 11.3854 +	case ETH_SS_STATS: {
 11.3855 +		char *strings = NULL;
 11.3856 +		void *addr = ifr->ifr_data;
 11.3857 +		info.len = E100_STATS_LEN;
 11.3858 +		strings = *e100_gstrings_stats;
 11.3859 +		if(copy_to_user(ifr->ifr_data, &info, sizeof(info)))
 11.3860 +			return -EFAULT;
 11.3861 +		addr += offsetof(struct ethtool_gstrings, data);
 11.3862 +		if(copy_to_user(addr, strings,
 11.3863 +		   info.len * ETH_GSTRING_LEN))
 11.3864 +			return -EFAULT;
 11.3865 +		return 0;
 11.3866 +	}
 11.3867 +	default:
 11.3868 +		return -EOPNOTSUPP;
 11.3869 +	}
 11.3870 +}
 11.3871 +
 11.3872 +static int
 11.3873 +e100_mii_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 11.3874 +{
 11.3875 +	struct e100_private *bdp;
 11.3876 +	struct mii_ioctl_data *data_ptr =
 11.3877 +		(struct mii_ioctl_data *) &(ifr->ifr_data);
 11.3878 +
 11.3879 +	bdp = dev->priv;
 11.3880 +
 11.3881 +	switch (cmd) {
 11.3882 +	case SIOCGMIIPHY:
 11.3883 +		data_ptr->phy_id = bdp->phy_addr & 0x1f;
 11.3884 +		break;
 11.3885 +
 11.3886 +	case SIOCGMIIREG:
 11.3887 +		if (!capable(CAP_NET_ADMIN))
 11.3888 +			return -EPERM;
 11.3889 +		e100_mdi_read(bdp, data_ptr->reg_num & 0x1f, bdp->phy_addr,
 11.3890 +			      &(data_ptr->val_out));
 11.3891 +		break;
 11.3892 +
 11.3893 +	case SIOCSMIIREG:
 11.3894 +		if (!capable(CAP_NET_ADMIN))
 11.3895 +			return -EPERM;
 11.3896 +		/* If reg = 0 && change speed/duplex */
 11.3897 +		if (data_ptr->reg_num == 0 && 
 11.3898 +			(data_ptr->val_in == (BMCR_ANENABLE | BMCR_ANRESTART) /* restart cmd */
 11.3899 +			|| data_ptr->val_in == (BMCR_RESET) /* reset cmd */ 
 11.3900 +			|| data_ptr->val_in & (BMCR_SPEED100 | BMCR_FULLDPLX) 
 11.3901 +			|| data_ptr->val_in == 0)) {
 11.3902 +				if (data_ptr->val_in == (BMCR_ANENABLE | BMCR_ANRESTART)
 11.3903 +					|| data_ptr->val_in == (BMCR_RESET))
 11.3904 +					bdp->params.e100_speed_duplex = E100_AUTONEG;
 11.3905 +				else if (data_ptr->val_in == (BMCR_SPEED100 | BMCR_FULLDPLX))
 11.3906 +					bdp->params.e100_speed_duplex = E100_SPEED_100_FULL;
 11.3907 +				else if (data_ptr->val_in == (BMCR_SPEED100))
 11.3908 +					bdp->params.e100_speed_duplex = E100_SPEED_100_HALF;
 11.3909 +				else if (data_ptr->val_in == (BMCR_FULLDPLX))
 11.3910 +					bdp->params.e100_speed_duplex = E100_SPEED_10_FULL;
 11.3911 +				else
 11.3912 +					bdp->params.e100_speed_duplex = E100_SPEED_10_HALF;
 11.3913 +				e100_set_speed_duplex(bdp);
 11.3914 +		}
 11.3915 +		else 
 11.3916 +			/* Only allows changing speed/duplex */
 11.3917 +			return -EINVAL;
 11.3918 +		
 11.3919 +		break;
 11.3920 +
 11.3921 +	default:
 11.3922 +		return -EOPNOTSUPP;
 11.3923 +	}
 11.3924 +	return 0;
 11.3925 +}
 11.3926 +#endif
 11.3927 +
 11.3928 +nxmit_cb_entry_t *
 11.3929 +e100_alloc_non_tx_cmd(struct e100_private *bdp)
 11.3930 +{
 11.3931 +	nxmit_cb_entry_t *non_tx_cmd_elem;
 11.3932 +
 11.3933 +	if (!(non_tx_cmd_elem = (nxmit_cb_entry_t *)
 11.3934 +	      kmalloc(sizeof (nxmit_cb_entry_t), GFP_ATOMIC))) {
 11.3935 +		return NULL;
 11.3936 +	}
 11.3937 +	non_tx_cmd_elem->non_tx_cmd =
 11.3938 +		pci_alloc_consistent(bdp->pdev, sizeof (nxmit_cb_t),
 11.3939 +				     &(non_tx_cmd_elem->dma_addr));
 11.3940 +	if (non_tx_cmd_elem->non_tx_cmd == NULL) {
 11.3941 +		kfree(non_tx_cmd_elem);
 11.3942 +		return NULL;
 11.3943 +	}
 11.3944 +	return non_tx_cmd_elem;
 11.3945 +}
 11.3946 +
 11.3947 +void
 11.3948 +e100_free_non_tx_cmd(struct e100_private *bdp,
 11.3949 +		     nxmit_cb_entry_t *non_tx_cmd_elem)
 11.3950 +{
 11.3951 +	pci_free_consistent(bdp->pdev, sizeof (nxmit_cb_t),
 11.3952 +			    non_tx_cmd_elem->non_tx_cmd,
 11.3953 +			    non_tx_cmd_elem->dma_addr);
 11.3954 +	kfree(non_tx_cmd_elem);
 11.3955 +}
 11.3956 +
 11.3957 +static void
 11.3958 +e100_free_nontx_list(struct e100_private *bdp)
 11.3959 +{
 11.3960 +	nxmit_cb_entry_t *command;
 11.3961 +	int i;
 11.3962 +
 11.3963 +	while (!list_empty(&bdp->non_tx_cmd_list)) {
 11.3964 +		command = list_entry(bdp->non_tx_cmd_list.next,
 11.3965 +				     nxmit_cb_entry_t, list_elem);
 11.3966 +		list_del(&(command->list_elem));
 11.3967 +		e100_free_non_tx_cmd(bdp, command);
 11.3968 +	}
 11.3969 +
 11.3970 +	for (i = 0; i < CB_MAX_NONTX_CMD; i++) {
 11.3971 +		bdp->same_cmd_entry[i] = NULL;
 11.3972 +	}
 11.3973 +}
 11.3974 +
 11.3975 +static unsigned char
 11.3976 +e100_delayed_exec_non_cu_cmd(struct e100_private *bdp,
 11.3977 +			     nxmit_cb_entry_t *command)
 11.3978 +{
 11.3979 +	nxmit_cb_entry_t *same_command;
 11.3980 +	cb_header_t *ntcb_hdr;
 11.3981 +	u16 cmd;
 11.3982 +
 11.3983 +	ntcb_hdr = (cb_header_t *) command->non_tx_cmd;
 11.3984 +
 11.3985 +	cmd = CB_CMD_MASK & le16_to_cpu(ntcb_hdr->cb_cmd);
 11.3986 +
 11.3987 +	spin_lock_bh(&(bdp->bd_non_tx_lock));
 11.3988 +
 11.3989 +	same_command = bdp->same_cmd_entry[cmd];
 11.3990 +
 11.3991 +	if (same_command != NULL) {
 11.3992 +		memcpy((void *) (same_command->non_tx_cmd),
 11.3993 +		       (void *) (command->non_tx_cmd), sizeof (nxmit_cb_t));
 11.3994 +		e100_free_non_tx_cmd(bdp, command);
 11.3995 +	} else {
 11.3996 +		list_add_tail(&(command->list_elem), &(bdp->non_tx_cmd_list));
 11.3997 +		bdp->same_cmd_entry[cmd] = command;
 11.3998 +	}
 11.3999 +
 11.4000 +	if (bdp->non_tx_command_state == E100_NON_TX_IDLE) {
 11.4001 +		bdp->non_tx_command_state = E100_WAIT_TX_FINISH;
 11.4002 +		mod_timer(&(bdp->nontx_timer_id), jiffies + 1);
 11.4003 +	}
 11.4004 +
 11.4005 +	spin_unlock_bh(&(bdp->bd_non_tx_lock));
 11.4006 +	return true;
 11.4007 +}
 11.4008 +
 11.4009 +static void
 11.4010 +e100_non_tx_background(unsigned long ptr)
 11.4011 +{
 11.4012 +	struct e100_private *bdp = (struct e100_private *) ptr;
 11.4013 +	nxmit_cb_entry_t *active_command;
 11.4014 +	int restart = true;
 11.4015 +	cb_header_t *non_tx_cmd;
 11.4016 +	u8 sub_cmd;
 11.4017 +
 11.4018 +	spin_lock_bh(&(bdp->bd_non_tx_lock));
 11.4019 +
 11.4020 +	switch (bdp->non_tx_command_state) {
 11.4021 +	case E100_WAIT_TX_FINISH:
 11.4022 +		if (bdp->last_tcb != NULL) {
 11.4023 +			rmb();
 11.4024 +			if ((bdp->last_tcb->tcb_hdr.cb_status &
 11.4025 +			     __constant_cpu_to_le16(CB_STATUS_COMPLETE)) == 0)
 11.4026 +				goto exit;
 11.4027 +		}
 11.4028 +		if ((readw(&bdp->scb->scb_status) & SCB_CUS_MASK) ==
 11.4029 +		    SCB_CUS_ACTIVE) {
 11.4030 +			goto exit;
 11.4031 +		}
 11.4032 +		break;
 11.4033 +
 11.4034 +	case E100_WAIT_NON_TX_FINISH:
 11.4035 +		active_command = list_entry(bdp->non_tx_cmd_list.next,
 11.4036 +					    nxmit_cb_entry_t, list_elem);
 11.4037 +		rmb();
 11.4038 +
 11.4039 +		if (((((cb_header_t *) (active_command->non_tx_cmd))->cb_status
 11.4040 +		      & __constant_cpu_to_le16(CB_STATUS_COMPLETE)) == 0)
 11.4041 +		    && time_before(jiffies, active_command->expiration_time)) {
 11.4042 +			goto exit;
 11.4043 +		} else {
 11.4044 +			non_tx_cmd = (cb_header_t *) active_command->non_tx_cmd;
 11.4045 +			sub_cmd = CB_CMD_MASK & le16_to_cpu(non_tx_cmd->cb_cmd);
 11.4046 +#ifdef E100_CU_DEBUG			
 11.4047 +			if (!(non_tx_cmd->cb_status 
 11.4048 +			    & __constant_cpu_to_le16(CB_STATUS_COMPLETE)))
 11.4049 +				printk(KERN_ERR "e100: %s: Queued "
 11.4050 +					"command (%x) timeout\n", 
 11.4051 +					bdp->device->name, sub_cmd);
 11.4052 +#endif			
 11.4053 +			list_del(&(active_command->list_elem));
 11.4054 +			e100_free_non_tx_cmd(bdp, active_command);
 11.4055 +		}
 11.4056 +		break;
 11.4057 +
 11.4058 +	default:
 11.4059 +		break;
 11.4060 +	}			//switch
 11.4061 +
 11.4062 +	if (list_empty(&bdp->non_tx_cmd_list)) {
 11.4063 +		bdp->non_tx_command_state = E100_NON_TX_IDLE;
 11.4064 +		spin_lock_irq(&(bdp->bd_lock));
 11.4065 +		bdp->next_cu_cmd = START_WAIT;
 11.4066 +		spin_unlock_irq(&(bdp->bd_lock));
 11.4067 +		restart = false;
 11.4068 +		goto exit;
 11.4069 +	} else {
 11.4070 +		u16 cmd_type;
 11.4071 +
 11.4072 +		bdp->non_tx_command_state = E100_WAIT_NON_TX_FINISH;
 11.4073 +		active_command = list_entry(bdp->non_tx_cmd_list.next,
 11.4074 +					    nxmit_cb_entry_t, list_elem);
 11.4075 +		sub_cmd = ((cb_header_t *) active_command->non_tx_cmd)->cb_cmd;
 11.4076 +		spin_lock_irq(&(bdp->bd_lock));
 11.4077 +		e100_wait_exec_cmplx(bdp, active_command->dma_addr,
 11.4078 +				     SCB_CUC_START, sub_cmd);
 11.4079 +		spin_unlock_irq(&(bdp->bd_lock));
 11.4080 +		active_command->expiration_time = jiffies + HZ;
 11.4081 +		cmd_type = CB_CMD_MASK &
 11.4082 +			le16_to_cpu(((cb_header_t *)
 11.4083 +				     (active_command->non_tx_cmd))->cb_cmd);
 11.4084 +		bdp->same_cmd_entry[cmd_type] = NULL;
 11.4085 +	}
 11.4086 +
 11.4087 +exit:
 11.4088 +	if (restart) {
 11.4089 +		mod_timer(&(bdp->nontx_timer_id), jiffies + 1);
 11.4090 +	} else {
 11.4091 +		if (netif_running(bdp->device))
 11.4092 +			netif_wake_queue(bdp->device);
 11.4093 +	}
 11.4094 +	spin_unlock_bh(&(bdp->bd_non_tx_lock));
 11.4095 +}
 11.4096 +
 11.4097 +static void
 11.4098 +e100_vlan_rx_register(struct net_device *netdev, struct vlan_group *grp)
 11.4099 +{
 11.4100 +	struct e100_private *bdp = netdev->priv;
 11.4101 +
 11.4102 +	e100_disable_clear_intr(bdp);
 11.4103 +	bdp->vlgrp = grp;
 11.4104 +
 11.4105 +	if(grp) {
 11.4106 +		/* enable VLAN tag insert/strip */
 11.4107 +		e100_config_vlan_drop(bdp, true);
 11.4108 +
 11.4109 +	} else {
 11.4110 +		/* disable VLAN tag insert/strip */
 11.4111 +		e100_config_vlan_drop(bdp, false);
 11.4112 +	}
 11.4113 +
 11.4114 +	e100_config(bdp);
 11.4115 +	e100_set_intr_mask(bdp);
 11.4116 +}
 11.4117 +
 11.4118 +static void
 11.4119 +e100_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
 11.4120 +{
 11.4121 +	/* We don't do Vlan filtering */
 11.4122 +	return;
 11.4123 +}
 11.4124 +
 11.4125 +static void
 11.4126 +e100_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
 11.4127 +{
 11.4128 +	struct e100_private *bdp = netdev->priv;
 11.4129 +
 11.4130 +	if(bdp->vlgrp)
 11.4131 +		bdp->vlgrp->vlan_devices[vid] = NULL;
 11.4132 +	/* We don't do Vlan filtering */
 11.4133 +	return;
 11.4134 +}
 11.4135 +
 11.4136 +#ifdef CONFIG_PM
 11.4137 +static int
 11.4138 +e100_notify_reboot(struct notifier_block *nb, unsigned long event, void *p)
 11.4139 +{
 11.4140 +        struct pci_dev *pdev;
 11.4141 +	
 11.4142 +        switch(event) {
 11.4143 +        case SYS_DOWN:
 11.4144 +        case SYS_HALT:
 11.4145 +        case SYS_POWER_OFF:
 11.4146 +                pci_for_each_dev(pdev) {
 11.4147 +                        if(pci_dev_driver(pdev) == &e100_driver) {
 11.4148 +				/* If net_device struct is allocated? */
 11.4149 +                                if (pci_get_drvdata(pdev))
 11.4150 +					e100_suspend(pdev, 3);
 11.4151 +
 11.4152 +			}
 11.4153 +		}
 11.4154 +        }
 11.4155 +        return NOTIFY_DONE;
 11.4156 +}
 11.4157 +
 11.4158 +static int
 11.4159 +e100_suspend(struct pci_dev *pcid, u32 state)
 11.4160 +{
 11.4161 +	struct net_device *netdev = pci_get_drvdata(pcid);
 11.4162 +	struct e100_private *bdp = netdev->priv;
 11.4163 +
 11.4164 +	e100_isolate_driver(bdp);
 11.4165 +	pci_save_state(pcid, bdp->pci_state);
 11.4166 +
 11.4167 +	/* Enable or disable WoL */
 11.4168 +	e100_do_wol(pcid, bdp);
 11.4169 +	
 11.4170 +	/* If wol is enabled */
 11.4171 +	if (bdp->wolopts || e100_asf_enabled(bdp)) {
 11.4172 +		pci_enable_wake(pcid, 3, 1);	/* Enable PME for power state D3 */
 11.4173 +		pci_set_power_state(pcid, 3);	/* Set power state to D3.        */
 11.4174 +	} else {
 11.4175 +		/* Disable bus mastering */
 11.4176 +		pci_disable_device(pcid);
 11.4177 +		pci_set_power_state(pcid, state);
 11.4178 +	}
 11.4179 +	return 0;
 11.4180 +}
 11.4181 +
 11.4182 +static int
 11.4183 +e100_resume(struct pci_dev *pcid)
 11.4184 +{
 11.4185 +	struct net_device *netdev = pci_get_drvdata(pcid);
 11.4186 +	struct e100_private *bdp = netdev->priv;
 11.4187 +
 11.4188 +	pci_set_power_state(pcid, 0);
 11.4189 +	pci_enable_wake(pcid, 0, 0);	/* Clear PME status and disable PME */
 11.4190 +	pci_restore_state(pcid, bdp->pci_state);
 11.4191 +
 11.4192 +	/* Also do device full reset because device was in D3 state */
 11.4193 +	e100_deisolate_driver(bdp, true);
 11.4194 +
 11.4195 +	return 0;
 11.4196 +}
 11.4197 +#endif /* CONFIG_PM */
 11.4198 +
 11.4199 +/**
 11.4200 + * e100_asf_enabled - checks if ASF is configured on the current adaper
 11.4201 + *                    by reading registers 0xD and 0x90 in the EEPROM 
 11.4202 + * @bdp: atapter's private data struct
 11.4203 + *
 11.4204 + * Returns: true if ASF is enabled
 11.4205 + */
 11.4206 +static unsigned char
 11.4207 +e100_asf_enabled(struct e100_private *bdp)
 11.4208 +{
 11.4209 +	u16 asf_reg;
 11.4210 +	u16 smbus_addr_reg;
 11.4211 +	if ((bdp->pdev->device >= 0x1050) && (bdp->pdev->device <= 0x1055)) {
 11.4212 +		asf_reg = e100_eeprom_read(bdp, EEPROM_CONFIG_ASF);
 11.4213 +		if ((asf_reg & EEPROM_FLAG_ASF)
 11.4214 +		    && !(asf_reg & EEPROM_FLAG_GCL)) {
 11.4215 +			smbus_addr_reg = 
 11.4216 +				e100_eeprom_read(bdp, EEPROM_SMBUS_ADDR);
 11.4217 +			if ((smbus_addr_reg & 0xFF) != 0xFE) 
 11.4218 +				return true;
 11.4219 +		}
 11.4220 +	}
 11.4221 +	return false;
 11.4222 +}
 11.4223 +
 11.4224 +#ifdef E100_CU_DEBUG
 11.4225 +unsigned char
 11.4226 +e100_cu_unknown_state(struct e100_private *bdp)
 11.4227 +{
 11.4228 +	u8 scb_cmd_low;
 11.4229 +	u16 scb_status;
 11.4230 +	scb_cmd_low = bdp->scb->scb_cmd_low;
 11.4231 +	scb_status = le16_to_cpu(bdp->scb->scb_status);
 11.4232 +	/* If CU is active and executing unknown cmd */
 11.4233 +	if (scb_status & SCB_CUS_ACTIVE && scb_cmd_low & SCB_CUC_UNKNOWN)
 11.4234 +		return true;
 11.4235 +	else
 11.4236 +		return false;
 11.4237 +}
 11.4238 +#endif
 11.4239 +
    12.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    12.2 +++ b/xen/drivers/net/e100/e100_phy.c	Thu Jul 10 08:57:37 2003 +0000
    12.3 @@ -0,0 +1,1160 @@
    12.4 +/*******************************************************************************
    12.5 +
    12.6 +  
    12.7 +  Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
    12.8 +  
    12.9 +  This program is free software; you can redistribute it and/or modify it