ia64/xen-unstable

changeset 5176:122c8adf6ca1

bitkeeper revision 1.1568 (42960d67jYin00CdEGWDPCLZ5h6Hnw)

Merge firebug.cl.cam.ac.uk:/local/scratch/kaf24/xen-unstable.bk
into firebug.cl.cam.ac.uk:/local/scratch/kaf24/xeno-unstable-ia64.bk
author kaf24@firebug.cl.cam.ac.uk
date Thu May 26 17:54:47 2005 +0000 (2005-05-26)
parents 3c8c7c46c4a8 44a4da6bfe52
children be52714e4727
files .rootkeys xen/arch/ia64/Makefile xen/arch/ia64/asm-offsets.c xen/arch/ia64/domain.c xen/arch/ia64/hypercall.c xen/arch/ia64/hyperprivop.S xen/arch/ia64/ivt.S xen/arch/ia64/patch/linux-2.6.11/entry.S xen/arch/ia64/patch/linux-2.6.11/kregs.h xen/arch/ia64/privop.c xen/arch/ia64/process.c xen/arch/ia64/tools/README.xenia64 xen/arch/ia64/tools/README.xenia64linux xen/arch/ia64/tools/mkbuildtree xen/arch/ia64/vcpu.c xen/arch/ia64/xenmisc.c xen/include/asm-ia64/xensystem.h xen/include/public/arch-ia64.h
line diff
     1.1 --- a/.rootkeys	Thu May 26 16:40:45 2005 +0000
     1.2 +++ b/.rootkeys	Thu May 26 17:54:47 2005 +0000
     1.3 @@ -1008,6 +1008,7 @@ 421098b2PHgzf_Gg4R65YRNi_QzMKQ xen/arch/
     1.4  421098b2O7jsNfzQXA1v3rbAc1QhpA xen/arch/ia64/dom_fw.c
     1.5  421098b2ZlaBcyiuuPr3WpzaSDwg6Q xen/arch/ia64/domain.c
     1.6  4239e98a_HX-FCIcXtVqY0BbrDqVug xen/arch/ia64/hypercall.c
     1.7 +4295e18f42gf1T-8W97A3KSlBaY1tA xen/arch/ia64/hyperprivop.S
     1.8  421098b3LYAS8xJkQiGP7tiTlyBt0Q xen/arch/ia64/idle0_task.c
     1.9  421098b3ys5GAr4z6_H1jD33oem82g xen/arch/ia64/irq.c
    1.10  4272a8e4lavI6DrTvqaIhXeR5RuKBw xen/arch/ia64/ivt.S
     2.1 --- a/xen/arch/ia64/Makefile	Thu May 26 16:40:45 2005 +0000
     2.2 +++ b/xen/arch/ia64/Makefile	Thu May 26 17:54:47 2005 +0000
     2.3 @@ -9,7 +9,7 @@ OBJS = xensetup.o setup.o time.o irq.o i
     2.4  	xenmem.o sal.o cmdline.o mm_init.o tlb.o smpboot.o \
     2.5  	extable.o linuxextable.o xenirq.o xentime.o \
     2.6  	regionreg.o entry.o unaligned.o privop.o vcpu.o \
     2.7 -	irq_ia64.o irq_lsapic.o vhpt.o xenasm.o dom_fw.o
     2.8 +	irq_ia64.o irq_lsapic.o vhpt.o xenasm.o hyperprivop.o dom_fw.o
     2.9  
    2.10  ifeq ($(CONFIG_VTI),y)
    2.11  OBJS += vmx_init.o vmx_virt.o vmx_vcpu.o vmx_process.o vmx_vsa.o vmx_ivt.o \
    2.12 @@ -29,6 +29,9 @@ default: $(OBJS) head.o ia64lib.o xen.ld
    2.13  	$(LD) $(LDFLAGS) -T $(BASEDIR)/arch/$(TARGET_ARCH)/xen.lds.s -N \
    2.14  		-Map map.out head.o $(ALL_OBJS) -o $(TARGET)-syms
    2.15  	$(OBJCOPY) -R .note -R .comment -S $(TARGET)-syms $(TARGET)
    2.16 +	$(NM) -n $(TARGET)-syms | grep -v '\( [aUw] \)\|\(__crc_\)\|\( \$[adt]\)'\
    2.17 +		 > $(BASEDIR)/System.map
    2.18 +
    2.19  
    2.20  asm-offsets.s: asm-offsets.c $(BASEDIR)/include/asm-ia64/.offsets.h.stamp
    2.21  	$(CC) $(CFLAGS) -S -o $@ $<
     3.1 --- a/xen/arch/ia64/asm-offsets.c	Thu May 26 16:40:45 2005 +0000
     3.2 +++ b/xen/arch/ia64/asm-offsets.c	Thu May 26 17:54:47 2005 +0000
     3.3 @@ -44,6 +44,13 @@ void foo(void)
     3.4  	DEFINE(XSI_PSR_IC_OFS, offsetof(vcpu_info_t, arch.interrupt_collection_enabled));
     3.5  	DEFINE(XSI_PSR_IC, (SHAREDINFO_ADDR+offsetof(vcpu_info_t, arch.interrupt_collection_enabled)));
     3.6  	DEFINE(XSI_PSR_I_OFS, offsetof(vcpu_info_t, arch.interrupt_delivery_enabled));
     3.7 +	DEFINE(XSI_IIP_OFS, offsetof(vcpu_info_t, arch.iip));
     3.8 +	DEFINE(XSI_IPSR_OFS, offsetof(vcpu_info_t, arch.ipsr));
     3.9 +	DEFINE(XSI_IFS_OFS, offsetof(vcpu_info_t, arch.ifs));
    3.10 +	DEFINE(XSI_BANKNUM_OFS, offsetof(vcpu_info_t, arch.banknum));
    3.11 +	DEFINE(XSI_METAPHYS_OFS, offsetof(vcpu_info_t, arch.metaphysical_mode));
    3.12 +	DEFINE(XSI_INCOMPL_REG_OFS, offsetof(vcpu_info_t, arch.incomplete_regframe));
    3.13 +	DEFINE(XSI_PEND_OFS, offsetof(vcpu_info_t, arch.pending_interruption));
    3.14  	//DEFINE(IA64_TASK_BLOCKED_OFFSET,offsetof (struct task_struct, blocked));
    3.15  	//DEFINE(IA64_TASK_CLEAR_CHILD_TID_OFFSET,offsetof (struct task_struct, clear_child_tid));
    3.16  	//DEFINE(IA64_TASK_GROUP_LEADER_OFFSET, offsetof (struct task_struct, group_leader));
     4.1 --- a/xen/arch/ia64/domain.c	Thu May 26 16:40:45 2005 +0000
     4.2 +++ b/xen/arch/ia64/domain.c	Thu May 26 17:54:47 2005 +0000
     4.3 @@ -116,6 +116,7 @@ void continue_cpu_idle_loop(void)
     4.4  #endif
     4.5  	    while ( !softirq_pending(cpu) )
     4.6  	        default_idle();
     4.7 +	    raise_softirq(SCHEDULE_SOFTIRQ);
     4.8  	    do_softirq();
     4.9  	}
    4.10  }
    4.11 @@ -132,7 +133,6 @@ void startup_cpu_idle_loop(void)
    4.12  	 * Therefore memory barrier to ensure state is visible.
    4.13  	 */
    4.14  	smp_mb();
    4.15 -	init_idle();
    4.16  #if 0
    4.17  //do we have to ensure the idle task has a shared page so that, for example,
    4.18  //region registers can be loaded from it.  Apparently not...
     5.1 --- a/xen/arch/ia64/hypercall.c	Thu May 26 16:40:45 2005 +0000
     5.2 +++ b/xen/arch/ia64/hypercall.c	Thu May 26 17:54:47 2005 +0000
     5.3 @@ -41,6 +41,10 @@ ia64_hypercall (struct pt_regs *regs)
     5.4  		ed->vcpu_info->arch.pending_interruption = 1;
     5.5  #endif
     5.6  		x = pal_emulator_static(regs->r28);
     5.7 +		if (regs->r28 == PAL_HALT_LIGHT) {
     5.8 +			do_sched_op(SCHEDOP_yield);
     5.9 +			//break;
    5.10 +		}
    5.11  		regs->r8 = x.status; regs->r9 = x.v0;
    5.12  		regs->r10 = x.v1; regs->r11 = x.v2;
    5.13  		break;
     6.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     6.2 +++ b/xen/arch/ia64/hyperprivop.S	Thu May 26 17:54:47 2005 +0000
     6.3 @@ -0,0 +1,103 @@
     6.4 +/*
     6.5 + * arch/ia64/kernel/hyperprivop.S
     6.6 + *
     6.7 + * Copyright (C) 2005 Hewlett-Packard Co
     6.8 + *	Dan Magenheimer <dan.magenheimer@hp.com>
     6.9 + */
    6.10 +
    6.11 +#include <linux/config.h>
    6.12 +
    6.13 +#include <asm/asmmacro.h>
    6.14 +#include <asm/kregs.h>
    6.15 +#include <asm/offsets.h>
    6.16 +#include <asm/processor.h>
    6.17 +#include <asm/system.h>
    6.18 +#include <public/arch-ia64.h>
    6.19 +
    6.20 +// Note: not hand-scheduled for now
    6.21 +//  Registers at entry
    6.22 +//	r16 == cr.isr
    6.23 +//	r17 == cr.iim
    6.24 +//	r18 == XSI_PSR_IC_OFS
    6.25 +//	r19 == vpsr.ic (low 32 bits) | vpsr.i (high 32 bits)
    6.26 +//	r31 == pr
    6.27 +GLOBAL_ENTRY(fast_hyperprivop)
    6.28 +	//cover;;
    6.29 +	// if domain interrupts pending, give up for now and do it the slow way
    6.30 +	adds r20=XSI_PEND_OFS-XSI_PSR_IC_OFS,r18 ;;
    6.31 +	ld8 r20=[r20] ;;
    6.32 +	cmp.ne p7,p0=r0,r20
    6.33 +(p7)	br.sptk.many dispatch_break_fault ;;
    6.34 +
    6.35 +	// HYPERPRIVOP_RFI?
    6.36 +	cmp.eq p7,p6=XEN_HYPER_RFI,r17
    6.37 +(p7)	br.sptk.many hyper_rfi;;
    6.38 +	// if not rfi, give up for now and do it the slow way
    6.39 +	br.sptk.many dispatch_break_fault ;;
    6.40 +
    6.41 +// ensure that, if giving up, registers at entry to fast_hyperprivop unchanged
    6.42 +ENTRY(hyper_rfi)
    6.43 +	adds r20=XSI_IPSR_OFS-XSI_PSR_IC_OFS,r18 ;;
    6.44 +	ld8 r21=[r20];;		// r21 = vcr.ipsr
    6.45 +	extr.u r22=r21,IA64_PSR_BE_BIT,1 ;;
    6.46 +	// if turning on psr.be, give up for now and do it the slow way
    6.47 +	cmp.ne p7,p0=r22,r0
    6.48 +(p7)	br.sptk.many dispatch_break_fault ;;
    6.49 +	// if (!(vpsr.dt && vpsr.rt && vpsr.it)), do it the slow way
    6.50 +	movl r20=(IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_IT);;
    6.51 +	and r22=r20,r21
    6.52 +	;;
    6.53 +	cmp.ne p7,p0=r22,r20
    6.54 +(p7)	br.sptk.many dispatch_break_fault ;;
    6.55 +	// if was in metaphys mode, do it the slow way (FIXME later?)
    6.56 +	adds r20=XSI_METAPHYS_OFS-XSI_PSR_IC_OFS,r18 ;;
    6.57 +	ld4 r20=[r20];;
    6.58 +	cmp.ne p7,p0=r20,r0
    6.59 +(p7)	br.sptk.many dispatch_break_fault ;;
    6.60 +	// if domain hasn't already done virtual bank switch
    6.61 +	//  do it the slow way (FIXME later?)
    6.62 +	adds r20=XSI_BANKNUM_OFS-XSI_PSR_IC_OFS,r18 ;;
    6.63 +	ld4 r20=[r20];;
    6.64 +	cmp.eq p7,p0=r20,r0
    6.65 +(p7)	br.sptk.many dispatch_break_fault ;;
    6.66 +	// validate vcr.iip, if in Xen range, do it the slow way
    6.67 +	adds r20=XSI_IIP_OFS-XSI_PSR_IC_OFS,r18 ;;
    6.68 +	ld8 r22=[r20];;
    6.69 +	movl r23=XEN_VIRT_SPACE_LOW
    6.70 +	movl r24=XEN_VIRT_SPACE_HIGH ;;
    6.71 +	cmp.ltu p0,p7=r22,r23 ;;	// if !(iip<low) &&
    6.72 +(p7)	cmp.geu p0,p7=r22,r24 ;;	//    !(iip>=high)
    6.73 +(p7)	br.sptk.many dispatch_break_fault ;;
    6.74 +
    6.75 +	// OK now, let's do an rfi.
    6.76 +	// r18=&vpsr.i|vpsr.ic, r21==vpsr, r20==&vcr.iip, r22=vcr.iip
    6.77 +	mov cr.iip=r22;;
    6.78 +	adds r20=XSI_INCOMPL_REG_OFS-XSI_PSR_IC_OFS,r18 ;;
    6.79 +	st4 [r20]=r0 ;;
    6.80 +	adds r20=XSI_IFS_OFS-XSI_PSR_IC_OFS,r18 ;;
    6.81 +	ld8 r20=[r20];;
    6.82 +	dep r20=0,r20,38,25;; // ensure ifs has no reserved bits set
    6.83 +	mov cr.ifs=r20 ;;
    6.84 +// TODO: increment a counter so we can count how many rfi's go the fast way
    6.85 +//    but where?  counter must be pinned
    6.86 +	// ipsr.cpl == (vcr.ipsr.cpl == 0) 2 : 3;
    6.87 +	dep r21=-1,r21,IA64_PSR_CPL1_BIT,1 ;;
    6.88 +	// vpsr.i = vcr.ipsr.i; vpsr.ic = vcr.ipsr.ic
    6.89 +	mov r19=r0 ;;
    6.90 +	extr.u r22=r21,IA64_PSR_I_BIT,1 ;;
    6.91 +	cmp.ne p7,p6=r22,r0 ;;
    6.92 +(p7)	dep r19=-1,r19,32,1
    6.93 +	extr.u r22=r21,IA64_PSR_IC_BIT,1 ;;
    6.94 +	cmp.ne p7,p6=r22,r0 ;;
    6.95 +(p7)	dep r19=-1,r19,0,1 ;;
    6.96 +	st8 [r18]=r19 ;;
    6.97 +	// force on psr.ic, i, dt, rt, it, bn
    6.98 +	movl r20=(IA64_PSR_I|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_IT|IA64_PSR_BN)
    6.99 +	;;
   6.100 +	or r21=r21,r20
   6.101 +	;;
   6.102 +	mov cr.ipsr=r21
   6.103 +	mov pr=r31,-1
   6.104 +	;;
   6.105 +	rfi
   6.106 +	;;
     7.1 --- a/xen/arch/ia64/ivt.S	Thu May 26 16:40:45 2005 +0000
     7.2 +++ b/xen/arch/ia64/ivt.S	Thu May 26 17:54:47 2005 +0000
     7.3 @@ -785,14 +785,19 @@ ENTRY(break_fault)
     7.4  	cmp.eq p7,p0=r0,r17			// is this a psuedo-cover?
     7.5  (p7)	br.sptk.many dispatch_privop_fault
     7.6  	;;
     7.7 -	cmp.ne p7,p0=r0,r19
     7.8 +	cmp4.ne p7,p0=r0,r19
     7.9  (p7)	br.sptk.many dispatch_break_fault
    7.10  	// If we get to here, we have a hyperprivop
    7.11  	// For now, hyperprivops are handled through the break mechanism
    7.12  	// Later, they will be fast hand-coded assembly with psr.ic off
    7.13  	// which means no calls, no use of r1-r15 and no memory accesses
    7.14  	// except to pinned addresses!
    7.15 +#define FAST_HYPERPRIVOPS
    7.16 +#ifdef FAST_HYPERPRIVOPS
    7.17 +	br.sptk.many fast_hyperprivop
    7.18 +#else
    7.19  	br.sptk.many dispatch_break_fault
    7.20 +#endif
    7.21  	;;
    7.22  #endif
    7.23  	mov r16=IA64_KR(CURRENT)		// r16 = current task; 12 cycle read lat.
    7.24 @@ -913,9 +918,10 @@ END(interrupt)
    7.25  	// fault ever gets "unreserved", simply moved the following code to a more
    7.26  	// suitable spot...
    7.27  
    7.28 -ENTRY(dispatch_break_fault)
    7.29 +GLOBAL_ENTRY(dispatch_break_fault)
    7.30  	SAVE_MIN_WITH_COVER
    7.31  	;;
    7.32 +dispatch_break_fault_post_save:
    7.33  	alloc r14=ar.pfs,0,0,4,0 // now it's safe (must be first in insn group!)
    7.34  	mov out0=cr.ifa
    7.35  	adds out1=16,sp
    7.36 @@ -1792,6 +1798,15 @@ ENTRY(dispatch_reflection)
    7.37  	mov rp=r14
    7.38  	br.sptk.many ia64_prepare_handle_reflection
    7.39  END(dispatch_reflection)
    7.40 +
    7.41 +#define SAVE_MIN_COVER_DONE	DO_SAVE_MIN(,mov r30=cr.ifs,)
    7.42 +
    7.43 +// same as dispatch_break_fault except cover has already been done
    7.44 +GLOBAL_ENTRY(dispatch_slow_hyperprivop)
    7.45 +	SAVE_MIN_COVER_DONE
    7.46 +	;;
    7.47 +	br.sptk.many dispatch_break_fault_post_save
    7.48 +END(dispatch_slow_hyperprivop)
    7.49  #endif
    7.50  
    7.51  #ifdef CONFIG_IA32_SUPPORT
     8.1 --- a/xen/arch/ia64/patch/linux-2.6.11/entry.S	Thu May 26 16:40:45 2005 +0000
     8.2 +++ b/xen/arch/ia64/patch/linux-2.6.11/entry.S	Thu May 26 17:54:47 2005 +0000
     8.3 @@ -1,5 +1,5 @@
     8.4 ---- /home/adsharma/disk2/xen-ia64/xeno-unstable-rebase.bk/xen/../../linux-2.6.11/arch/ia64/kernel/entry.S	2005-03-01 23:37:50.000000000 -0800
     8.5 -+++ /home/adsharma/disk2/xen-ia64/xeno-unstable-rebase.bk/xen/arch/ia64/entry.S	2005-05-18 12:40:51.000000000 -0700
     8.6 +--- ../../linux-2.6.11/arch/ia64/kernel/entry.S	2005-03-02 00:37:50.000000000 -0700
     8.7 ++++ arch/ia64/entry.S	2005-05-23 16:49:23.000000000 -0600
     8.8  @@ -46,6 +46,7 @@
     8.9   
    8.10   #include "minstate.h"
    8.11 @@ -97,11 +97,13 @@
    8.12   	;;					// added stop bits to prevent r8 dependency
    8.13   END(ia64_ret_from_clone)
    8.14   	// fall through
    8.15 -@@ -700,19 +732,25 @@
    8.16 +@@ -700,19 +732,27 @@
    8.17   .work_processed_syscall:
    8.18   	adds r2=PT(LOADRS)+16,r12
    8.19   	adds r3=PT(AR_BSPSTORE)+16,r12
    8.20 -+#ifndef XEN
    8.21 ++#ifdef XEN
    8.22 ++	;;
    8.23 ++#else
    8.24   	adds r18=TI_FLAGS+IA64_TASK_SIZE,r13
    8.25   	;;
    8.26   (p6)	ld4 r31=[r18]				// load current_thread_info()->flags
    8.27 @@ -123,7 +125,7 @@
    8.28   	;;
    8.29   	// start restoring the state saved on the kernel stack (struct pt_regs):
    8.30   	ld8 r9=[r2],PT(CR_IPSR)-PT(R9)
    8.31 -@@ -757,7 +795,11 @@
    8.32 +@@ -757,7 +797,11 @@
    8.33   	;;
    8.34   	ld8.fill r12=[r2]	// restore r12 (sp)
    8.35   	ld8.fill r15=[r3]	// restore r15
    8.36 @@ -135,7 +137,7 @@
    8.37   	;;
    8.38   (pUStk)	ld4 r3=[r3]		// r3 = cpu_data->phys_stacked_size_p8
    8.39   (pUStk) st1 [r14]=r17
    8.40 -@@ -814,9 +856,18 @@
    8.41 +@@ -814,9 +858,18 @@
    8.42   (pUStk)	cmp.eq.unc p6,p0=r0,r0		// p6 <- pUStk
    8.43   #endif
    8.44   .work_processed_kernel:
    8.45 @@ -154,7 +156,7 @@
    8.46   	adds r21=PT(PR)+16,r12
    8.47   	;;
    8.48   
    8.49 -@@ -828,17 +879,20 @@
    8.50 +@@ -828,17 +881,20 @@
    8.51   	ld8 r28=[r2],8		// load b6
    8.52   	adds r29=PT(R24)+16,r12
    8.53   
    8.54 @@ -176,7 +178,7 @@
    8.55   	;;
    8.56   	ld8 r31=[r2],16		// load ar.ssd
    8.57   	ld8.fill r8=[r3],16
    8.58 -@@ -934,7 +988,11 @@
    8.59 +@@ -934,7 +990,11 @@
    8.60   	shr.u r18=r19,16	// get byte size of existing "dirty" partition
    8.61   	;;
    8.62   	mov r16=ar.bsp		// get existing backing store pointer
    8.63 @@ -188,7 +190,7 @@
    8.64   	;;
    8.65   	ld4 r17=[r17]		// r17 = cpu_data->phys_stacked_size_p8
    8.66   (pKStk)	br.cond.dpnt skip_rbs_switch
    8.67 -@@ -1069,6 +1127,7 @@
    8.68 +@@ -1069,6 +1129,7 @@
    8.69   	mov pr=r31,-1		// I0
    8.70   	rfi			// B
    8.71   
    8.72 @@ -196,7 +198,7 @@
    8.73   	/*
    8.74   	 * On entry:
    8.75   	 *	r20 = &current->thread_info->pre_count (if CONFIG_PREEMPT)
    8.76 -@@ -1130,6 +1189,7 @@
    8.77 +@@ -1130,6 +1191,7 @@
    8.78   	ld8 r8=[r2]
    8.79   	ld8 r10=[r3]
    8.80   	br.cond.sptk.many .work_processed_syscall	// re-check
    8.81 @@ -204,7 +206,7 @@
    8.82   
    8.83   END(ia64_leave_kernel)
    8.84   
    8.85 -@@ -1166,6 +1226,7 @@
    8.86 +@@ -1166,6 +1228,7 @@
    8.87   	br.ret.sptk.many rp
    8.88   END(ia64_invoke_schedule_tail)
    8.89   
    8.90 @@ -212,7 +214,7 @@
    8.91   	/*
    8.92   	 * Setup stack and call do_notify_resume_user().  Note that pSys and pNonSys need to
    8.93   	 * be set up by the caller.  We declare 8 input registers so the system call
    8.94 -@@ -1264,6 +1325,7 @@
    8.95 +@@ -1264,6 +1327,7 @@
    8.96   	mov ar.unat=r9
    8.97   	br.many b7
    8.98   END(sys_rt_sigreturn)
    8.99 @@ -220,7 +222,7 @@
   8.100   
   8.101   GLOBAL_ENTRY(ia64_prepare_handle_unaligned)
   8.102   	.prologue
   8.103 -@@ -1278,6 +1340,7 @@
   8.104 +@@ -1278,6 +1342,7 @@
   8.105   	br.cond.sptk.many rp				// goes to ia64_leave_kernel
   8.106   END(ia64_prepare_handle_unaligned)
   8.107   
   8.108 @@ -228,7 +230,7 @@
   8.109   	//
   8.110   	// unw_init_running(void (*callback)(info, arg), void *arg)
   8.111   	//
   8.112 -@@ -1585,3 +1648,4 @@
   8.113 +@@ -1585,3 +1650,4 @@
   8.114   	data8 sys_ni_syscall
   8.115   
   8.116   	.org sys_call_table + 8*NR_syscalls	// guard against failures to increase NR_syscalls
     9.1 --- a/xen/arch/ia64/patch/linux-2.6.11/kregs.h	Thu May 26 16:40:45 2005 +0000
     9.2 +++ b/xen/arch/ia64/patch/linux-2.6.11/kregs.h	Thu May 26 17:54:47 2005 +0000
     9.3 @@ -45,7 +45,7 @@
     9.4   #define IA64_ISR_CODE_LFETCH	4
     9.5   #define IA64_ISR_CODE_PROBEF	5
     9.6   
     9.7 -+#ifdef CONFIG_VTI
     9.8 ++#ifdef XEN
     9.9  +/* Interruption Function State */
    9.10  +#define IA64_IFS_V_BIT		63
    9.11  +#define IA64_IFS_V	(__IA64_UL(1) << IA64_IFS_V_BIT)
    9.12 @@ -60,6 +60,6 @@
    9.13  +#define IA64_PTA_SIZE   (__IA64_UL(0x3f) << IA64_PTA_SIZE_BIT)
    9.14  +#define IA64_PTA_VF     (__IA64_UL(1) << IA64_PTA_VF_BIT)
    9.15  +#define IA64_PTA_BASE   (__IA64_UL(0) - ((__IA64_UL(1) << IA64_PTA_BASE_BIT)))
    9.16 -+#endif // CONFIG_VTI
    9.17 ++#endif
    9.18  +
    9.19   #endif /* _ASM_IA64_kREGS_H */
    10.1 --- a/xen/arch/ia64/privop.c	Thu May 26 16:40:45 2005 +0000
    10.2 +++ b/xen/arch/ia64/privop.c	Thu May 26 17:54:47 2005 +0000
    10.3 @@ -569,7 +569,7 @@ priv_handle_op(VCPU *vcpu, REGS *regs, i
    10.4  #endif
    10.5  	{
    10.6  //printf("*** priv_handle_op: privop bundle @%p not mapped, retrying\n",iip);
    10.7 -		return IA64_RETRY;
    10.8 +		return vcpu_force_data_miss(vcpu,regs->cr_iip);
    10.9  	}
   10.10  #if 0
   10.11  	if (iip==0xa000000100001820) {
   10.12 @@ -732,30 +732,10 @@ priv_emulate(VCPU *vcpu, REGS *regs, UIN
   10.13  	privlvl = (ipsr & IA64_PSR_CPL) >> IA64_PSR_CPL0_BIT;
   10.14  	// its OK for a privified-cover to be executed in user-land
   10.15  	fault = priv_handle_op(vcpu,regs,privlvl);
   10.16 -	if (fault == IA64_NO_FAULT) { // success!!
   10.17 +	if ((fault == IA64_NO_FAULT) || (fault == IA64_EXTINT_VECTOR)) { // success!!
   10.18  		// update iip/ipsr to point to the next instruction
   10.19  		(void)vcpu_increment_iip(vcpu);
   10.20  	}
   10.21 -	else if (fault == IA64_EXTINT_VECTOR) {
   10.22 -		// update iip/ipsr before delivering interrupt
   10.23 -		(void)vcpu_increment_iip(vcpu);
   10.24 -	}
   10.25 -	else if (fault == IA64_RFI_IN_PROGRESS) return fault;
   10.26 -		// success but don't update to next instruction
   10.27 -        else if (fault == IA64_RETRY) {
   10.28 -            //printf("Priv emulate gets IA64_RETRY\n");
   10.29 -	    //printf("priv_emulate: returning RETRY, not implemented!\n");
   10.30 -	    //while (1);
   10.31 -	    // don't update iip/ipsr, deliver 
   10.32 -	
   10.33 -            vcpu_force_data_miss(vcpu,regs->cr_iip);
   10.34 -	    return IA64_RETRY;
   10.35 -        }
   10.36 -	else if (priv_verbose) printf("unhandled operation from handle_op\n");
   10.37 -//	if (fault == IA64_ILLOP_FAULT) {
   10.38 -//		printf("priv_emulate: returning ILLOP, not implemented!\n");
   10.39 -//		while (1);
   10.40 -//	}
   10.41  	return fault;
   10.42  }
   10.43  
   10.44 @@ -1001,7 +981,7 @@ int dump_hyperprivop_counts(char *buf)
   10.45  {
   10.46  	int i;
   10.47  	char *s = buf;
   10.48 -	s += sprintf(s,"Hyperprivops:\n");
   10.49 +	s += sprintf(s,"Slow hyperprivops:\n");
   10.50  	for (i = 1; i <= HYPERPRIVOP_MAX; i++)
   10.51  		if (hyperpriv_cnt[i])
   10.52  			s += sprintf(s,"%10d %s\n",
    11.1 --- a/xen/arch/ia64/process.c	Thu May 26 16:40:45 2005 +0000
    11.2 +++ b/xen/arch/ia64/process.c	Thu May 26 17:54:47 2005 +0000
    11.3 @@ -153,7 +153,8 @@ void reflect_interruption(unsigned long 
    11.4  		}
    11.5  		vector &= ~0xf;
    11.6  		if (vector != IA64_DATA_TLB_VECTOR &&
    11.7 -		    vector != IA64_ALT_DATA_TLB_VECTOR) {
    11.8 +		    vector != IA64_ALT_DATA_TLB_VECTOR &&
    11.9 +		    vector != IA64_VHPT_TRANS_VECTOR) {
   11.10  panic_domain(regs,"psr.ic off, delivering fault=%lx,iip=%p,ifa=%p,isr=%p,PSCB.iip=%p\n",
   11.11  	vector,regs->cr_iip,ifa,isr,PSCB(ed,iip));
   11.12  			
   11.13 @@ -167,20 +168,12 @@ panic_domain(regs,"psr.ic off, deliverin
   11.14  		return;
   11.15  
   11.16  	}
   11.17 -	if ((vector & 0xf) != IA64_FORCED_IFA) PSCB(ed,ifa) = ifa;
   11.18 -	else ifa = PSCB(ed,ifa);
   11.19 +	if ((vector & 0xf) == IA64_FORCED_IFA)
   11.20 +		ifa = PSCB(ed,tmp[0]);
   11.21  	vector &= ~0xf;
   11.22 -//	always deliver on ALT vector (for now?) because no VHPT
   11.23 -//	if (!vcpu_get_rr_ve(ed,ifa)) {
   11.24 -		if (vector == IA64_DATA_TLB_VECTOR)
   11.25 -			vector = IA64_ALT_DATA_TLB_VECTOR;
   11.26 -		else if (vector == IA64_INST_TLB_VECTOR)
   11.27 -			vector = IA64_ALT_INST_TLB_VECTOR;
   11.28 -//	}
   11.29 -	if (vector == IA64_ALT_DATA_TLB_VECTOR ||
   11.30 -	    vector == IA64_ALT_INST_TLB_VECTOR) {
   11.31 -		vcpu_thash(ed,ifa,&PSCB(ed,iha));
   11.32 -	}
   11.33 +	PSCB(ed,ifa) = ifa;
   11.34 +	if (vector < IA64_DATA_NESTED_TLB_VECTOR) /* VHPT miss, TLB miss, Alt TLB miss */
   11.35 +		vcpu_thash(ed,ifa,&PSCB(current,iha));
   11.36  	PSCB(ed,unat) = regs->ar_unat;  // not sure if this is really needed?
   11.37  	PSCB(ed,precover_ifs) = regs->cr_ifs;
   11.38  	vcpu_bsw0(ed);
   11.39 @@ -325,7 +318,7 @@ void ia64_do_page_fault (unsigned long a
   11.40  	unsigned long psr = regs->cr_ipsr, mask, flags;
   11.41  	unsigned long iip = regs->cr_iip;
   11.42  	// FIXME should validate address here
   11.43 -	unsigned long pteval, mpaddr;
   11.44 +	unsigned long iha, pteval, mpaddr;
   11.45  	unsigned long lookup_domain_mpa(struct domain *,unsigned long);
   11.46  	unsigned long is_data = !((isr >> IA64_ISR_X_BIT) & 1UL);
   11.47  	unsigned long vector;
   11.48 @@ -351,8 +344,8 @@ void ia64_do_page_fault (unsigned long a
   11.49  		// FIXME should validate mpaddr here
   11.50  		if (d == dom0) {
   11.51  			if (address < dom0_start || address >= dom0_start + dom0_size) {
   11.52 -				//printk("ia64_do_page_fault: out-of-bounds dom0 mpaddr %p, iip=%p! continuing...\n",address,iip);
   11.53 -				//printk("ia64_do_page_fault: out-of-bounds dom0 mpaddr %p, old iip=%p!\n",address,current->vcpu_info->arch.iip);
   11.54 +				printk("ia64_do_page_fault: out-of-bounds dom0 mpaddr %p, iip=%p! continuing...\n",address,iip);
   11.55 +				printk("ia64_do_page_fault: out-of-bounds dom0 mpaddr %p, old iip=%p!\n",address,current->vcpu_info->arch.iip);
   11.56  				tdpfoo();
   11.57  			}
   11.58  		}
   11.59 @@ -367,10 +360,10 @@ void ia64_do_page_fault (unsigned long a
   11.60  		vcpu_itc_no_srlz(current,is_data?2:1,address,pteval,-1UL,(trp->itir>>2)&0x3f);
   11.61  		return;
   11.62  	}
   11.63 -	vector = is_data ? IA64_DATA_TLB_VECTOR : IA64_INST_TLB_VECTOR;
   11.64 +
   11.65  	if (handle_lazy_cover(current, isr, regs)) return;
   11.66  if (!(address>>61)) {
   11.67 -panic_domain(0,"ia64_do_page_fault: @%p???, iip=%p, itc=%p (spinning...)\n",address,iip,ia64_get_itc());
   11.68 +panic_domain(0,"ia64_do_page_fault: @%p???, iip=%p, b0=%p, itc=%p (spinning...)\n",address,iip,regs->b0,ia64_get_itc());
   11.69  }
   11.70  	if ((isr & IA64_ISR_SP)
   11.71  	    || ((isr & IA64_ISR_NA) && (isr & IA64_ISR_CODE_MASK) == IA64_ISR_CODE_LFETCH))
   11.72 @@ -383,6 +376,37 @@ panic_domain(0,"ia64_do_page_fault: @%p?
   11.73  		ia64_psr(regs)->ed = 1;
   11.74  		return;
   11.75  	}
   11.76 +
   11.77 +	if (vcpu_get_rr_ve(current, address) && (PSCB(current,pta) & IA64_PTA_VE))
   11.78 +	{
   11.79 +		if (PSCB(current,pta) & IA64_PTA_VF)
   11.80 +		{
   11.81 +			/* long format VHPT - not implemented */
   11.82 +			vector = is_data ? IA64_DATA_TLB_VECTOR : IA64_INST_TLB_VECTOR;
   11.83 +		}
   11.84 +		else
   11.85 +		{
   11.86 +			/* short format VHPT */
   11.87 +			vcpu_thash(current, address, &iha);
   11.88 +			if (__copy_from_user(&pteval, iha, sizeof(pteval)) == 0)
   11.89 +			{
   11.90 +				/* 
   11.91 +				 * Optimisation: this VHPT walker aborts on not-present pages
   11.92 +				 * instead of inserting a not-present translation, this allows
   11.93 +				 * vectoring directly to the miss handler.
   11.94 +	\			 */
   11.95 +				if (pteval & _PAGE_P)
   11.96 +				{
   11.97 +					pteval = translate_domain_pte(pteval,address,itir);
   11.98 +					vcpu_itc_no_srlz(current,is_data?2:1,address,pteval,-1UL,(itir>>2)&0x3f);
   11.99 +					return;
  11.100 +				}
  11.101 +				else vector = is_data ? IA64_DATA_TLB_VECTOR : IA64_INST_TLB_VECTOR;
  11.102 +			}
  11.103 +			else vector = IA64_VHPT_TRANS_VECTOR;
  11.104 +		}
  11.105 +	}
  11.106 +	else vector = is_data ? IA64_ALT_DATA_TLB_VECTOR : IA64_ALT_INST_TLB_VECTOR;
  11.107  	reflect_interruption(address, isr, itir, regs, vector);
  11.108  }
  11.109  
  11.110 @@ -746,11 +770,7 @@ ia64_handle_privop (unsigned long ifa, s
  11.111  	// AND ACTUALLY reflect_interruption doesn't use it anyway!
  11.112  	itir = vcpu_get_itir_on_fault(ed,ifa);
  11.113  	vector = priv_emulate(current,regs,isr);
  11.114 -	if (vector == IA64_RETRY) {
  11.115 -		reflect_interruption(ifa,isr,itir,regs,
  11.116 -			IA64_ALT_DATA_TLB_VECTOR | IA64_FORCED_IFA);
  11.117 -	}
  11.118 -	else if (vector != IA64_NO_FAULT && vector != IA64_RFI_IN_PROGRESS) {
  11.119 +	if (vector != IA64_NO_FAULT && vector != IA64_RFI_IN_PROGRESS) {
  11.120  		reflect_interruption(ifa,isr,itir,regs,vector);
  11.121  	}
  11.122  }
    12.1 --- a/xen/arch/ia64/tools/README.xenia64	Thu May 26 16:40:45 2005 +0000
    12.2 +++ b/xen/arch/ia64/tools/README.xenia64	Thu May 26 17:54:47 2005 +0000
    12.3 @@ -6,18 +6,16 @@
    12.4  
    12.5  # unpack linux-2.6.11 in the xenXXX.bk/.. directory
    12.6  tar xzf linux-2.6.11.tar.gz
    12.7 -cd linux-2.6.11
    12.8  
    12.9  # go back to the xen subdirectory of xenXXX.bk
   12.10  cd xenXXX.bk/xen
   12.11  
   12.12  # create and patch the linux/ia64 files
   12.13 -bash arch/ia64/tools/mkbuildtree
   12.14  # this should print out many patch messages but no errors
   12.15  bash arch/ia64/tools/mkbuildtree
   12.16  
   12.17  # build xen/ia64
   12.18  # if using cross-compiler
   12.19 -make TARGET_ARCH=ia64
   12.20 +make XEN_TARGET_ARCH=ia64
   12.21  # else if native
   12.22  make
    13.1 --- a/xen/arch/ia64/tools/README.xenia64linux	Thu May 26 16:40:45 2005 +0000
    13.2 +++ b/xen/arch/ia64/tools/README.xenia64linux	Thu May 26 17:54:47 2005 +0000
    13.3 @@ -6,7 +6,6 @@ 2) vi .config
    13.4  	unset CONFIG_IA32_SUPPORT
    13.5  	unset CONFIG_IDE [for now, need to fix later]
    13.6  	unset CONFIG_VIRTUAL_MEM_MAP [for now, need to fix later]
    13.7 -	set CONFIG_DISABLE_VHPT
    13.8  3) if running on ski, it is useful to make the following change:
    13.9     a) at the beginning of drivers/acpi/motherboard.c:acpi_reserve_resources()
   13.10        add the line:
   13.11 @@ -46,5 +45,6 @@ 6) debug fixes:
   13.12             (It may be necessary also to un-inline the routine, not sure.)
   13.13     c) It can be useful to modify linux/init/main.c to add a printf before
   13.14        or after a lot of the init calls
   13.15 -6) NOTE: mca currently has a problem with binary translation,
   13.16 +6) Start Xen from elilo, passing the Linux kernel as an initrd.
   13.17 +   NOTE: mca currently has a problem with binary translation,
   13.18     must run with "nomca" as a kernel argument
    14.1 --- a/xen/arch/ia64/tools/mkbuildtree	Thu May 26 16:40:45 2005 +0000
    14.2 +++ b/xen/arch/ia64/tools/mkbuildtree	Thu May 26 17:54:47 2005 +0000
    14.3 @@ -307,7 +307,6 @@ softlink include/linux/timex.h include/a
    14.4  softlink include/linux/topology.h include/asm-ia64/linux/topology.h
    14.5  softlink include/linux/seqlock.h include/asm-ia64/linux/seqlock.h
    14.6  softlink include/linux/jiffies.h include/asm-ia64/linux/jiffies.h
    14.7 -softlink include/linux/jiffies.h include/asm-ia64/linux/jiffies.h
    14.8  
    14.9  null include/asm-ia64/linux/file.h
   14.10  null include/asm-ia64/linux/module.h
    15.1 --- a/xen/arch/ia64/vcpu.c	Thu May 26 16:40:45 2005 +0000
    15.2 +++ b/xen/arch/ia64/vcpu.c	Thu May 26 17:54:47 2005 +0000
    15.3 @@ -638,7 +638,15 @@ IA64FAULT vcpu_get_ivr(VCPU *vcpu, UINT6
    15.4  {
    15.5  	int i;
    15.6  	UINT64 vector, mask;
    15.7 -#if 1
    15.8 +
    15.9 +#define HEARTBEAT_FREQ 16	// period in seconds
   15.10 +#ifdef HEARTBEAT_FREQ
   15.11 +#define N_DOMS 16	// period in seconds
   15.12 +	static long count[N_DOMS] = { 0 };
   15.13 +	REGS *regs = vcpu_regs(vcpu);
   15.14 +	unsigned domid = vcpu->domain->domain_id;
   15.15 +#endif
   15.16 +#ifdef IRQ_DEBUG
   15.17  	static char firstivr = 1;
   15.18  	static char firsttime[256];
   15.19  	if (firstivr) {
   15.20 @@ -654,9 +662,21 @@ IA64FAULT vcpu_get_ivr(VCPU *vcpu, UINT6
   15.21  		*pval = vector;
   15.22  		return IA64_NO_FAULT;
   15.23  	}
   15.24 +#ifdef HEARTBEAT_FREQ
   15.25 +	if (domid >= N_DOMS) domid = N_DOMS-1;
   15.26 +	if (vector == (PSCB(vcpu,itv) & 0xff) &&
   15.27 +	    !(++count[domid] & ((HEARTBEAT_FREQ*1024)-1))) {
   15.28 +		printf("Dom%d heartbeat... iip=%p,psr.i=%d,pend=%d\n",
   15.29 +			domid, regs->cr_iip,
   15.30 +			current->vcpu_info->arch.interrupt_delivery_enabled,
   15.31 +			current->vcpu_info->arch.pending_interruption);
   15.32 +		count[domid] = 0;
   15.33 +		dump_runq();
   15.34 +	}
   15.35 +#endif
   15.36  	// now have an unmasked, pending, deliverable vector!
   15.37  	// getting ivr has "side effects"
   15.38 -#if 0
   15.39 +#ifdef IRQ_DEBUG
   15.40  	if (firsttime[vector]) {
   15.41  		printf("*** First get_ivr on vector=%d,itc=%lx\n",
   15.42  			vector,ia64_get_itc());
   15.43 @@ -989,6 +1009,10 @@ IA64FAULT vcpu_set_itc(VCPU *vcpu, UINT6
   15.44  
   15.45  	UINT64 newnow = val, min_delta;
   15.46  
   15.47 +#define DISALLOW_SETTING_ITC_FOR_NOW
   15.48 +#ifdef DISALLOW_SETTING_ITC_FOR_NOW
   15.49 +printf("vcpu_set_itc: Setting ar.itc is currently disabled\n");
   15.50 +#else
   15.51  	local_irq_disable();
   15.52  	if (olditm) {
   15.53  printf("**** vcpu_set_itc(%lx): vitm changed to %lx\n",val,newnow+d);
   15.54 @@ -1008,6 +1032,7 @@ printf("**** vcpu_set_itc(%lx): vitm cha
   15.55  		//using_xen_as_itm++;
   15.56  	}
   15.57  	local_irq_enable();
   15.58 +#endif
   15.59  	return (IA64_NO_FAULT);
   15.60  }
   15.61  
   15.62 @@ -1092,8 +1117,8 @@ Privileged operation emulation routines
   15.63  
   15.64  IA64FAULT vcpu_force_data_miss(VCPU *vcpu, UINT64 ifa)
   15.65  {
   15.66 -	PSCB(vcpu,ifa) = ifa;	// privop traps don't set ifa so do it here
   15.67 -	return (IA64_DATA_TLB_VECTOR | IA64_FORCED_IFA);
   15.68 +	PSCB(vcpu,tmp[0]) = ifa;	// save ifa in vcpu structure, then specify IA64_FORCED_IFA
   15.69 +	return (vcpu_get_rr_ve(vcpu,ifa) ? IA64_DATA_TLB_VECTOR : IA64_ALT_DATA_TLB_VECTOR) | IA64_FORCED_IFA;
   15.70  }
   15.71  
   15.72  
   15.73 @@ -1181,7 +1206,7 @@ IA64FAULT vcpu_thash(VCPU *vcpu, UINT64 
   15.74  		((pta_base >> 15) & 0x3fffffffffff) & compMask_60_15;
   15.75  	UINT64 VHPT_addr2b =
   15.76  		((VHPT_offset >> 15) & 0x3fffffffffff) & Mask_60_15;;
   15.77 -	UINT64 VHPT_addr3 = VHPT_offset & 0x3fff;
   15.78 +	UINT64 VHPT_addr3 = VHPT_offset & 0x7fff;
   15.79  	UINT64 VHPT_addr = VHPT_addr1 | ((VHPT_addr2a | VHPT_addr2b) << 15) |
   15.80  			VHPT_addr3;
   15.81  
   15.82 @@ -1592,7 +1617,7 @@ IA64FAULT vcpu_itc_d(VCPU *vcpu, UINT64 
   15.83  	unsigned long pteval, logps = (itir >> 2) & 0x3f;
   15.84  	unsigned long translate_domain_pte(UINT64,UINT64,UINT64);
   15.85  
   15.86 -	if (((itir & 0xfcL) >> 2) < PAGE_SHIFT) {
   15.87 +	if (logps < PAGE_SHIFT) {
   15.88  		printf("vcpu_itc_d: domain trying to use smaller page size!\n");
   15.89  		//FIXME: kill domain here
   15.90  		while(1);
   15.91 @@ -1610,7 +1635,7 @@ IA64FAULT vcpu_itc_i(VCPU *vcpu, UINT64 
   15.92  	unsigned long translate_domain_pte(UINT64,UINT64,UINT64);
   15.93  
   15.94  	// FIXME: validate ifa here (not in Xen space), COULD MACHINE CHECK!
   15.95 -	if (((itir & 0xfcL) >> 2) < PAGE_SHIFT) {
   15.96 +	if (logps < PAGE_SHIFT) {
   15.97  		printf("vcpu_itc_i: domain trying to use smaller page size!\n");
   15.98  		//FIXME: kill domain here
   15.99  		while(1);
    16.1 --- a/xen/arch/ia64/xenmisc.c	Thu May 26 16:40:45 2005 +0000
    16.2 +++ b/xen/arch/ia64/xenmisc.c	Thu May 26 17:54:47 2005 +0000
    16.3 @@ -262,8 +262,8 @@ void context_switch(struct exec_domain *
    16.4  static long cnt[16] = { 50,50,50,50,50,50,50,50,50,50,50,50,50,50,50,50};
    16.5  static int i = 100;
    16.6  int id = ((struct exec_domain *)current)->domain->domain_id & 0xf;
    16.7 -if (!cnt[id]--) { printk("%x",id); cnt[id] = 50; }
    16.8 -if (!i--) { printk("+",id); cnt[id] = 100; }
    16.9 +if (!cnt[id]--) { printk("%x",id); cnt[id] = 500; }
   16.10 +if (!i--) { printk("+",id); cnt[id] = 1000; }
   16.11  }
   16.12  	clear_bit(_VCPUF_running, &prev->vcpu_flags);
   16.13  	//if (!is_idle_task(next->domain) )
   16.14 @@ -273,7 +273,10 @@ if (!i--) { printk("+",id); cnt[id] = 10
   16.15  		vmx_load_all_rr(current);
   16.16  	return;
   16.17  #else // CONFIG_VTI
   16.18 -	load_region_regs(current);
   16.19 +	if (!is_idle_task(current->domain)) {
   16.20 +		load_region_regs(current);
   16.21 +		if (vcpu_timer_expired(current)) vcpu_pend_timer(current);
   16.22 +	}
   16.23  	if (vcpu_timer_expired(current)) vcpu_pend_timer(current);
   16.24  #endif // CONFIG_VTI
   16.25  }
    17.1 --- a/xen/include/asm-ia64/xensystem.h	Thu May 26 16:40:45 2005 +0000
    17.2 +++ b/xen/include/asm-ia64/xensystem.h	Thu May 26 17:54:47 2005 +0000
    17.3 @@ -14,10 +14,10 @@
    17.4  #include <linux/kernel.h>
    17.5  
    17.6  /* Define HV space hierarchy */
    17.7 -#ifdef CONFIG_VTI
    17.8  #define XEN_VIRT_SPACE_LOW	 0xe800000000000000
    17.9  #define XEN_VIRT_SPACE_HIGH	 0xf800000000000000	
   17.10  /* This is address to mapping rr7 switch stub, in region 5 */
   17.11 +#ifdef CONFIG_VTI
   17.12  #define XEN_RR7_SWITCH_STUB	 0xb700000000000000
   17.13  #endif // CONFIG_VTI
   17.14  
    18.1 --- a/xen/include/public/arch-ia64.h	Thu May 26 16:40:45 2005 +0000
    18.2 +++ b/xen/include/public/arch-ia64.h	Thu May 26 17:54:47 2005 +0000
    18.3 @@ -81,4 +81,11 @@ typedef struct vcpu_guest_context {
    18.4  
    18.5  #endif /* !__ASSEMBLY__ */
    18.6  
    18.7 +#define	XEN_HYPER_RFI			1
    18.8 +#define	XEN_HYPER_RSM_PSR_DT		2
    18.9 +#define	XEN_HYPER_SSM_PSR_DT		3
   18.10 +#define	XEN_HYPER_COVER			4
   18.11 +#define	XEN_HYPER_ITC_D			5
   18.12 +#define	XEN_HYPER_ITC_I			6
   18.13 +
   18.14  #endif /* __HYPERVISOR_IF_IA64_H__ */