ia64/xen-unstable

changeset 19476:0faf7b884711

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x86: Enable S3 for 32bit dom0 on 64bit Xen

Three SYSENTER MSRs should be taken care of at save/restore BSP
context, or else 32bit dom0 rejects working after S3 resume. Thanks
for Jan's help to find this missing part.

Signed-off-by: Guanqun Lu <guanqun.lu@intel.com>
Signed-off-by: Kevin Tian <kevin.tian@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Tue Mar 31 13:28:45 2009 +0100 (2009-03-31)
parents d7bf5a03cf07
children b3daeb123b6f
files xen/arch/x86/acpi/suspend.c
line diff
     1.1 --- a/xen/arch/x86/acpi/suspend.c	Tue Mar 31 13:27:03 2009 +0100
     1.2 +++ b/xen/arch/x86/acpi/suspend.c	Tue Mar 31 13:28:45 2009 +0100
     1.3 @@ -16,6 +16,7 @@
     1.4  
     1.5  #if defined(CONFIG_X86_64)
     1.6  static unsigned long saved_lstar, saved_cstar;
     1.7 +static unsigned long saved_sysenter_esp, saved_sysenter_eip;
     1.8  #endif
     1.9  
    1.10  void save_rest_processor_state(void)
    1.11 @@ -26,6 +27,11 @@ void save_rest_processor_state(void)
    1.12  #if defined(CONFIG_X86_64)
    1.13      rdmsrl(MSR_CSTAR, saved_cstar);
    1.14      rdmsrl(MSR_LSTAR, saved_lstar);
    1.15 +    if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
    1.16 +    {
    1.17 +        rdmsrl(MSR_IA32_SYSENTER_ESP, saved_sysenter_esp);
    1.18 +        rdmsrl(MSR_IA32_SYSENTER_EIP, saved_sysenter_eip);
    1.19 +    }
    1.20  #endif
    1.21  }
    1.22  
    1.23 @@ -41,6 +47,14 @@ void restore_rest_processor_state(void)
    1.24      wrmsrl(MSR_CSTAR, saved_cstar);
    1.25      wrmsr(MSR_STAR, 0, (FLAT_RING3_CS32<<16) | __HYPERVISOR_CS);
    1.26      wrmsr(MSR_SYSCALL_MASK, EF_VM|EF_RF|EF_NT|EF_DF|EF_IE|EF_TF, 0U);    
    1.27 +
    1.28 +    if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
    1.29 +    {
    1.30 +        /* Recover sysenter MSRs */
    1.31 +        wrmsrl(MSR_IA32_SYSENTER_ESP, saved_sysenter_esp);
    1.32 +        wrmsrl(MSR_IA32_SYSENTER_EIP, saved_sysenter_eip);
    1.33 +        wrmsr(MSR_IA32_SYSENTER_CS, __HYPERVISOR_CS, 0);
    1.34 +    }
    1.35  #else /* !defined(CONFIG_X86_64) */
    1.36      if ( supervisor_mode_kernel && cpu_has_sep )
    1.37          wrmsr(MSR_IA32_SYSENTER_ESP, &init_tss[smp_processor_id()].esp1, 0);