ia64/xen-unstable

changeset 7922:0ee00faf332d

Adapt to removal of #ifdef ia64 in xmalloc (handle SMP_CACHE_SHIFT)
author djm@kirby.fc.hp.com
date Wed Nov 23 15:23:28 2005 -0600 (2005-11-23)
parents 3eaab414bdfd
children 0944ee356534
files xen/include/asm-ia64/linux-xen/asm/cache.h
line diff
     1.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
     1.2 +++ b/xen/include/asm-ia64/linux-xen/asm/cache.h	Wed Nov 23 15:23:28 2005 -0600
     1.3 @@ -0,0 +1,35 @@
     1.4 +#ifndef _ASM_IA64_CACHE_H
     1.5 +#define _ASM_IA64_CACHE_H
     1.6 +
     1.7 +#include <linux/config.h>
     1.8 +
     1.9 +/*
    1.10 + * Copyright (C) 1998-2000 Hewlett-Packard Co
    1.11 + *	David Mosberger-Tang <davidm@hpl.hp.com>
    1.12 + */
    1.13 +
    1.14 +/* Bytes per L1 (data) cache line.  */
    1.15 +#define L1_CACHE_SHIFT		CONFIG_IA64_L1_CACHE_SHIFT
    1.16 +#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
    1.17 +
    1.18 +#define L1_CACHE_SHIFT_MAX 7	/* largest L1 which this arch supports */
    1.19 +
    1.20 +#ifdef XEN
    1.21 +# define SMP_CACHE_SHIFT	L1_CACHE_SHIFT
    1.22 +# define SMP_CACHE_BYTES	L1_CACHE_BYTES
    1.23 +#else
    1.24 +#ifdef CONFIG_SMP
    1.25 +# define SMP_CACHE_SHIFT	L1_CACHE_SHIFT
    1.26 +# define SMP_CACHE_BYTES	L1_CACHE_BYTES
    1.27 +#else
    1.28 +  /*
    1.29 +   * The "aligned" directive can only _increase_ alignment, so this is
    1.30 +   * safe and provides an easy way to avoid wasting space on a
    1.31 +   * uni-processor:
    1.32 +   */
    1.33 +# define SMP_CACHE_SHIFT	3
    1.34 +# define SMP_CACHE_BYTES	(1 << 3)
    1.35 +#endif
    1.36 +#endif
    1.37 +
    1.38 +#endif /* _ASM_IA64_CACHE_H */
     2.1 --- a/xen/include/asm-ia64/linux/asm/cache.h	Wed Nov 23 14:43:05 2005 -0600
     2.2 +++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
     2.3 @@ -1,30 +0,0 @@
     2.4 -#ifndef _ASM_IA64_CACHE_H
     2.5 -#define _ASM_IA64_CACHE_H
     2.6 -
     2.7 -#include <linux/config.h>
     2.8 -
     2.9 -/*
    2.10 - * Copyright (C) 1998-2000 Hewlett-Packard Co
    2.11 - *	David Mosberger-Tang <davidm@hpl.hp.com>
    2.12 - */
    2.13 -
    2.14 -/* Bytes per L1 (data) cache line.  */
    2.15 -#define L1_CACHE_SHIFT		CONFIG_IA64_L1_CACHE_SHIFT
    2.16 -#define L1_CACHE_BYTES		(1 << L1_CACHE_SHIFT)
    2.17 -
    2.18 -#define L1_CACHE_SHIFT_MAX 7	/* largest L1 which this arch supports */
    2.19 -
    2.20 -#ifdef CONFIG_SMP
    2.21 -# define SMP_CACHE_SHIFT	L1_CACHE_SHIFT
    2.22 -# define SMP_CACHE_BYTES	L1_CACHE_BYTES
    2.23 -#else
    2.24 -  /*
    2.25 -   * The "aligned" directive can only _increase_ alignment, so this is
    2.26 -   * safe and provides an easy way to avoid wasting space on a
    2.27 -   * uni-processor:
    2.28 -   */
    2.29 -# define SMP_CACHE_SHIFT	3
    2.30 -# define SMP_CACHE_BYTES	(1 << 3)
    2.31 -#endif
    2.32 -
    2.33 -#endif /* _ASM_IA64_CACHE_H */