1.1 --- a/xen/arch/x86/traps.c	Mon May 05 10:13:17 2008 +0100
     1.2 +++ b/xen/arch/x86/traps.c	Mon May 05 10:16:06 2008 +0100
     1.3 @@ -713,11 +713,13 @@ static int emulate_forced_invalid_op(str
     1.4          __clear_bit(X86_FEATURE_PBE, &d);
     1.5  
     1.6          __clear_bit(X86_FEATURE_DTES64 % 32, &c);
     1.7 -        __clear_bit(X86_FEATURE_MWAIT % 32, &c);
     1.8 +        if ( !IS_PRIV(current->domain) )
     1.9 +            __clear_bit(X86_FEATURE_MWAIT % 32, &c);
    1.10          __clear_bit(X86_FEATURE_DSCPL % 32, &c);
    1.11          __clear_bit(X86_FEATURE_VMXE % 32, &c);
    1.12          __clear_bit(X86_FEATURE_SMXE % 32, &c);
    1.13 -        __clear_bit(X86_FEATURE_EST % 32, &c);
    1.14 +        if ( !IS_PRIV(current->domain) )
    1.15 +            __clear_bit(X86_FEATURE_EST % 32, &c);
    1.16          __clear_bit(X86_FEATURE_TM2 % 32, &c);
    1.17          if ( is_pv_32bit_vcpu(current) )
    1.18              __clear_bit(X86_FEATURE_CX16 % 32, &c);
    1.19 @@ -2146,8 +2148,9 @@ static int emulate_privileged_op(struct 
    1.20          case MSR_IA32_MISC_ENABLE:
    1.21              if ( rdmsr_safe(regs->ecx, regs->eax, regs->edx) )
    1.22                  goto fail;
    1.23 -            regs->eax &= ~(MSR_IA32_MISC_ENABLE_PERF_AVAIL |
    1.24 -                           MSR_IA32_MISC_ENABLE_MONITOR_ENABLE);
    1.25 +            regs->eax &= ~MSR_IA32_MISC_ENABLE_PERF_AVAIL;
    1.26 +            if ( !IS_PRIV(current->domain) )
    1.27 +                regs->eax &= ~MSR_IA32_MISC_ENABLE_MONITOR_ENABLE;
    1.28              regs->eax |= MSR_IA32_MISC_ENABLE_BTS_UNAVAIL |
    1.29                           MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL |
    1.30                           MSR_IA32_MISC_ENABLE_XTPR_DISABLE;