ia64/xen-unstable

changeset 9998:07a75bf044b4

[IA64] put hot vhpt entry at VHPT HEADER

Signed-off-by: Anthony Xu <anthony.xu@intel.com>
author awilliam@xenbuild.aw
date Fri May 12 08:13:18 2006 -0600 (2006-05-12)
parents 4de0ff0c1357
children 7bba3c5af9a8
files xen/arch/ia64/vmx/vmx_ivt.S
line diff
     1.1 --- a/xen/arch/ia64/vmx/vmx_ivt.S	Fri May 12 08:10:01 2006 -0600
     1.2 +++ b/xen/arch/ia64/vmx/vmx_ivt.S	Fri May 12 08:13:18 2006 -0600
     1.3 @@ -143,32 +143,58 @@ ENTRY(vmx_itlb_miss)
     1.4      thash r17 = r16
     1.5      ;;
     1.6      ttag r20 = r16
     1.7 +    mov r18 = r17	
     1.8      ;;
     1.9  vmx_itlb_loop:
    1.10      cmp.eq p6,p0 = r0, r17
    1.11 -(p6) br vmx_itlb_out
    1.12 +(p6)br vmx_itlb_out
    1.13      ;;
    1.14 -    adds r22 = VLE_TITAG_OFFSET, r17
    1.15 -    adds r23 = VLE_CCHAIN_OFFSET, r17
    1.16 +    adds r16 = VLE_TITAG_OFFSET, r17
    1.17 +    adds r19 = VLE_CCHAIN_OFFSET, r17
    1.18      ;;
    1.19 -    ld8 r24 = [r22]
    1.20 -    ld8 r25 = [r23]
    1.21 +    ld8 r22 = [r16]
    1.22 +    ld8 r23 = [r19]
    1.23      ;;
    1.24 -    lfetch [r25]
    1.25 -    cmp.eq  p6,p7 = r20, r24
    1.26 +    lfetch [r23]
    1.27 +    cmp.eq  p6,p7 = r20, r22
    1.28      ;;
    1.29 -(p7)    mov r17 = r25;
    1.30 -(p7)    br.sptk vmx_itlb_loop
    1.31 +(p7)mov r17 = r23;
    1.32 +(p7)br.sptk vmx_itlb_loop
    1.33      ;;
    1.34      adds r23 = VLE_PGFLAGS_OFFSET, r17
    1.35      adds r24 = VLE_ITIR_OFFSET, r17
    1.36      ;;
    1.37 -    ld8 r26 = [r23]
    1.38 -    ld8 r25 = [r24]
    1.39 +    ld8 r25 = [r23]
    1.40 +    ld8 r26 = [r24]
    1.41 +    ;;
    1.42 +    cmp.eq p6,p7=r18,r17
    1.43 +(p6) br vmx_itlb_loop1
    1.44 +    ;;
    1.45 +    ld8 r27 = [r18]
    1.46 +    ;;
    1.47 +    extr.u r19 = r27, 56, 8
    1.48 +    extr.u r20 = r25, 56, 8
    1.49 +    ;;
    1.50 +    dep r27 = r20, r27, 56, 8
    1.51 +    dep r25 = r19, r25, 56, 8
    1.52      ;;
    1.53 -    mov cr.itir = r25
    1.54 +    st8 [r18] = r25,8
    1.55 +    st8 [r23] = r27
    1.56 +    ;;
    1.57 +    ld8 r28 = [r18]
    1.58 +    ;;
    1.59 +    st8 [r18] = r26,8
    1.60 +    st8 [r24] = r28
    1.61      ;;
    1.62 -    itc.i r26
    1.63 +    ld8 r30 = [r18]
    1.64 +    ;;
    1.65 +    st8 [r18] = r22
    1.66 +    st8 [r16] = r30 
    1.67 +    ;;
    1.68 +vmx_itlb_loop1:
    1.69 +    mov cr.itir = r26
    1.70 +    ;;
    1.71 +    itc.i r25
    1.72      ;;
    1.73      srlz.i
    1.74      ;;
    1.75 @@ -202,39 +228,64 @@ ENTRY(vmx_dtlb_miss)
    1.76      mov r29=cr.ipsr;
    1.77      ;;
    1.78      tbit.z p6,p7=r29,IA64_PSR_VM_BIT;
    1.79 -    (p6)br.sptk vmx_alt_dtlb_miss_1
    1.80 -//(p6)br.sptk vmx_fault_2
    1.81 +(p6)br.sptk vmx_alt_dtlb_miss_1
    1.82      mov r16 = cr.ifa
    1.83      ;;
    1.84      thash r17 = r16
    1.85      ;;
    1.86      ttag r20 = r16
    1.87 +    mov r18 = r17	
    1.88      ;;
    1.89  vmx_dtlb_loop:
    1.90      cmp.eq p6,p0 = r0, r17
    1.91  (p6)br vmx_dtlb_out
    1.92      ;;
    1.93 -    adds r22 = VLE_TITAG_OFFSET, r17
    1.94 -    adds r23 = VLE_CCHAIN_OFFSET, r17
    1.95 +    adds r16 = VLE_TITAG_OFFSET, r17
    1.96 +    adds r19 = VLE_CCHAIN_OFFSET, r17
    1.97      ;;
    1.98 -    ld8 r24 = [r22]
    1.99 -    ld8 r25 = [r23]
   1.100 +    ld8 r22 = [r16]
   1.101 +    ld8 r23 = [r19]
   1.102      ;;
   1.103 -    lfetch [r25]
   1.104 -    cmp.eq  p6,p7 = r20, r24
   1.105 +    lfetch [r23]
   1.106 +    cmp.eq  p6,p7 = r20, r22
   1.107      ;;
   1.108 -(p7)mov r17 = r25;
   1.109 +(p7)mov r17 = r23;
   1.110  (p7)br.sptk vmx_dtlb_loop
   1.111      ;;
   1.112      adds r23 = VLE_PGFLAGS_OFFSET, r17
   1.113      adds r24 = VLE_ITIR_OFFSET, r17
   1.114      ;;
   1.115 -    ld8 r26 = [r23]
   1.116 -    ld8 r25 = [r24]
   1.117 +    ld8 r25 = [r23]
   1.118 +    ld8 r26 = [r24]
   1.119 +    ;;
   1.120 +    cmp.eq p6,p7=r18,r17
   1.121 +(p6) br vmx_dtlb_loop1
   1.122 +    ;;
   1.123 +    ld8 r27 = [r18]
   1.124 +    ;;
   1.125 +    extr.u r19 = r27, 56, 8
   1.126 +    extr.u r20 = r25, 56, 8
   1.127 +    ;;
   1.128 +    dep r27 = r20, r27, 56, 8
   1.129 +    dep r25 = r19, r25, 56, 8
   1.130      ;;
   1.131 -    mov cr.itir = r25
   1.132 +    st8 [r18] = r25,8
   1.133 +    st8 [r23] = r27
   1.134 +    ;;
   1.135 +    ld8 r28 = [r18]
   1.136 +    ;;
   1.137 +    st8 [r18] = r26,8
   1.138 +    st8 [r24] = r28
   1.139      ;;
   1.140 -    itc.d r26
   1.141 +    ld8 r30 = [r18]
   1.142 +    ;;
   1.143 +    st8 [r18] = r22
   1.144 +    st8 [r16] = r30 
   1.145 +    ;;
   1.146 +vmx_dtlb_loop1:
   1.147 +    mov cr.itir = r26
   1.148 +    ;;
   1.149 +    itc.d r25
   1.150      ;;
   1.151      srlz.d;
   1.152      ;;