ia64/xen-unstable

changeset 9998:07a75bf044b4

[IA64] put hot vhpt entry at VHPT HEADER

Signed-off-by: Anthony Xu <anthony.xu@intel.com>
author awilliam@xenbuild.aw
date Fri May 12 08:13:18 2006 -0600 (2006-05-12)
parents 4de0ff0c1357
children 7bba3c5af9a8
files xen/arch/ia64/vmx/vmx_ivt.S
line diff
     1.1 --- a/xen/arch/ia64/vmx/vmx_ivt.S	Fri May 12 08:10:01 2006 -0600
     1.2 +++ b/xen/arch/ia64/vmx/vmx_ivt.S	Fri May 12 08:13:18 2006 -0600
     1.3 @@ -143,32 +143,58 @@ ENTRY(vmx_itlb_miss)
     1.4      thash r17 = r16
     1.5      ;;
     1.6      ttag r20 = r16
     1.7 +    mov r18 = r17	
     1.8      ;;
     1.9  vmx_itlb_loop:
    1.10      cmp.eq p6,p0 = r0, r17
    1.11 -(p6) br vmx_itlb_out
    1.12 -    ;;
    1.13 -    adds r22 = VLE_TITAG_OFFSET, r17
    1.14 -    adds r23 = VLE_CCHAIN_OFFSET, r17
    1.15 +(p6)br vmx_itlb_out
    1.16      ;;
    1.17 -    ld8 r24 = [r22]
    1.18 -    ld8 r25 = [r23]
    1.19 +    adds r16 = VLE_TITAG_OFFSET, r17
    1.20 +    adds r19 = VLE_CCHAIN_OFFSET, r17
    1.21      ;;
    1.22 -    lfetch [r25]
    1.23 -    cmp.eq  p6,p7 = r20, r24
    1.24 +    ld8 r22 = [r16]
    1.25 +    ld8 r23 = [r19]
    1.26      ;;
    1.27 -(p7)    mov r17 = r25;
    1.28 -(p7)    br.sptk vmx_itlb_loop
    1.29 +    lfetch [r23]
    1.30 +    cmp.eq  p6,p7 = r20, r22
    1.31 +    ;;
    1.32 +(p7)mov r17 = r23;
    1.33 +(p7)br.sptk vmx_itlb_loop
    1.34      ;;
    1.35      adds r23 = VLE_PGFLAGS_OFFSET, r17
    1.36      adds r24 = VLE_ITIR_OFFSET, r17
    1.37      ;;
    1.38 -    ld8 r26 = [r23]
    1.39 -    ld8 r25 = [r24]
    1.40 +    ld8 r25 = [r23]
    1.41 +    ld8 r26 = [r24]
    1.42      ;;
    1.43 -    mov cr.itir = r25
    1.44 +    cmp.eq p6,p7=r18,r17
    1.45 +(p6) br vmx_itlb_loop1
    1.46      ;;
    1.47 -    itc.i r26
    1.48 +    ld8 r27 = [r18]
    1.49 +    ;;
    1.50 +    extr.u r19 = r27, 56, 8
    1.51 +    extr.u r20 = r25, 56, 8
    1.52 +    ;;
    1.53 +    dep r27 = r20, r27, 56, 8
    1.54 +    dep r25 = r19, r25, 56, 8
    1.55 +    ;;
    1.56 +    st8 [r18] = r25,8
    1.57 +    st8 [r23] = r27
    1.58 +    ;;
    1.59 +    ld8 r28 = [r18]
    1.60 +    ;;
    1.61 +    st8 [r18] = r26,8
    1.62 +    st8 [r24] = r28
    1.63 +    ;;
    1.64 +    ld8 r30 = [r18]
    1.65 +    ;;
    1.66 +    st8 [r18] = r22
    1.67 +    st8 [r16] = r30 
    1.68 +    ;;
    1.69 +vmx_itlb_loop1:
    1.70 +    mov cr.itir = r26
    1.71 +    ;;
    1.72 +    itc.i r25
    1.73      ;;
    1.74      srlz.i
    1.75      ;;
    1.76 @@ -202,39 +228,64 @@ ENTRY(vmx_dtlb_miss)
    1.77      mov r29=cr.ipsr;
    1.78      ;;
    1.79      tbit.z p6,p7=r29,IA64_PSR_VM_BIT;
    1.80 -    (p6)br.sptk vmx_alt_dtlb_miss_1
    1.81 -//(p6)br.sptk vmx_fault_2
    1.82 +(p6)br.sptk vmx_alt_dtlb_miss_1
    1.83      mov r16 = cr.ifa
    1.84      ;;
    1.85      thash r17 = r16
    1.86      ;;
    1.87      ttag r20 = r16
    1.88 +    mov r18 = r17	
    1.89      ;;
    1.90  vmx_dtlb_loop:
    1.91      cmp.eq p6,p0 = r0, r17
    1.92  (p6)br vmx_dtlb_out
    1.93      ;;
    1.94 -    adds r22 = VLE_TITAG_OFFSET, r17
    1.95 -    adds r23 = VLE_CCHAIN_OFFSET, r17
    1.96 +    adds r16 = VLE_TITAG_OFFSET, r17
    1.97 +    adds r19 = VLE_CCHAIN_OFFSET, r17
    1.98      ;;
    1.99 -    ld8 r24 = [r22]
   1.100 -    ld8 r25 = [r23]
   1.101 +    ld8 r22 = [r16]
   1.102 +    ld8 r23 = [r19]
   1.103      ;;
   1.104 -    lfetch [r25]
   1.105 -    cmp.eq  p6,p7 = r20, r24
   1.106 +    lfetch [r23]
   1.107 +    cmp.eq  p6,p7 = r20, r22
   1.108      ;;
   1.109 -(p7)mov r17 = r25;
   1.110 +(p7)mov r17 = r23;
   1.111  (p7)br.sptk vmx_dtlb_loop
   1.112      ;;
   1.113      adds r23 = VLE_PGFLAGS_OFFSET, r17
   1.114      adds r24 = VLE_ITIR_OFFSET, r17
   1.115      ;;
   1.116 -    ld8 r26 = [r23]
   1.117 -    ld8 r25 = [r24]
   1.118 +    ld8 r25 = [r23]
   1.119 +    ld8 r26 = [r24]
   1.120      ;;
   1.121 -    mov cr.itir = r25
   1.122 +    cmp.eq p6,p7=r18,r17
   1.123 +(p6) br vmx_dtlb_loop1
   1.124      ;;
   1.125 -    itc.d r26
   1.126 +    ld8 r27 = [r18]
   1.127 +    ;;
   1.128 +    extr.u r19 = r27, 56, 8
   1.129 +    extr.u r20 = r25, 56, 8
   1.130 +    ;;
   1.131 +    dep r27 = r20, r27, 56, 8
   1.132 +    dep r25 = r19, r25, 56, 8
   1.133 +    ;;
   1.134 +    st8 [r18] = r25,8
   1.135 +    st8 [r23] = r27
   1.136 +    ;;
   1.137 +    ld8 r28 = [r18]
   1.138 +    ;;
   1.139 +    st8 [r18] = r26,8
   1.140 +    st8 [r24] = r28
   1.141 +    ;;
   1.142 +    ld8 r30 = [r18]
   1.143 +    ;;
   1.144 +    st8 [r18] = r22
   1.145 +    st8 [r16] = r30 
   1.146 +    ;;
   1.147 +vmx_dtlb_loop1:
   1.148 +    mov cr.itir = r26
   1.149 +    ;;
   1.150 +    itc.d r25
   1.151      ;;
   1.152      srlz.d;
   1.153      ;;