ia64/xen-unstable

changeset 12570:074b4b34e049

[HVM] VPIC (i8259) device model cleanups.
Signed-off-by: Keir Fraser <keir@xensource.com>
author kfraser@localhost.localdomain
date Fri Nov 24 15:42:14 2006 +0000 (2006-11-24)
parents cdd9e366aa59
children d37b210bb8a7
files xen/arch/x86/hvm/hvm.c xen/arch/x86/hvm/i8259.c xen/include/asm-x86/hvm/vpic.h xen/include/asm-x86/hvm/vpt.h
line diff
     1.1 --- a/xen/arch/x86/hvm/hvm.c	Fri Nov 24 14:37:45 2006 +0000
     1.2 +++ b/xen/arch/x86/hvm/hvm.c	Fri Nov 24 15:42:14 2006 +0000
     1.3 @@ -244,21 +244,13 @@ void hvm_vcpu_destroy(struct vcpu *v)
     1.4  
     1.5  int cpu_get_interrupt(struct vcpu *v, int *type)
     1.6  {
     1.7 -    int intno;
     1.8 -    struct vpic *vpic = domain_vpic(v->domain);
     1.9 -    unsigned long flags;
    1.10 +    int irq;
    1.11  
    1.12 -    if ( (intno = cpu_get_apic_interrupt(v, type)) != -1 ) {
    1.13 -        /* set irq request if a PIC irq is still pending */
    1.14 -        /* XXX: improve that */
    1.15 -        spin_lock_irqsave(vpic_lock(vpic), flags);
    1.16 -        pic_update_irq(vpic);
    1.17 -        spin_unlock_irqrestore(vpic_lock(vpic), flags);
    1.18 -        return intno;
    1.19 -    }
    1.20 -    /* read the irq from the PIC */
    1.21 -    if ( v->vcpu_id == 0 && (intno = cpu_get_pic_interrupt(v, type)) != -1 )
    1.22 -        return intno;
    1.23 +    if ( (irq = cpu_get_apic_interrupt(v, type)) != -1 )
    1.24 +        return irq;
    1.25 +
    1.26 +    if ( (v->vcpu_id == 0) && ((irq = cpu_get_pic_interrupt(v, type)) != -1) )
    1.27 +        return irq;
    1.28  
    1.29      return -1;
    1.30  }
     2.1 --- a/xen/arch/x86/hvm/i8259.c	Fri Nov 24 14:37:45 2006 +0000
     2.2 +++ b/xen/arch/x86/hvm/i8259.c	Fri Nov 24 15:42:14 2006 +0000
     2.3 @@ -1,8 +1,9 @@
     2.4  /*
     2.5 - * QEMU 8259 interrupt controller emulation
     2.6 + * i8259 interrupt controller emulation
     2.7   * 
     2.8   * Copyright (c) 2003-2004 Fabrice Bellard
     2.9   * Copyright (c) 2005 Intel Corperation
    2.10 + * Copyright (c) 2006 Keir Fraser, XenSource Inc.
    2.11   * 
    2.12   * Permission is hereby granted, free of charge, to any person obtaining a copy
    2.13   * of this software and associated documentation files (the "Software"), to
    2.14 @@ -35,54 +36,60 @@
    2.15  #include <asm/hvm/support.h>
    2.16  #include <asm/current.h>
    2.17  
    2.18 -#define hw_error(x) ((void)0)
    2.19 -
    2.20 -/* set irq level. If an edge is detected, then the IRR is set to 1 */
    2.21  static inline void pic_set_irq1(PicState *s, int irq, int level)
    2.22  {
    2.23 -    int mask;
    2.24 +    int mask = 1 << irq;
    2.25  
    2.26      ASSERT(spin_is_locked(vpic_lock(s->pics_state)));
    2.27  
    2.28 -    mask = 1 << irq;
    2.29 -    if (s->elcr & mask) {
    2.30 -        /* level triggered */
    2.31 -        if (level) {
    2.32 +    if ( s->elcr & mask )
    2.33 +    {
    2.34 +        /* Level triggered. */
    2.35 +        if ( level )
    2.36 +        {
    2.37              s->irr |= mask;
    2.38              s->last_irr |= mask;
    2.39 -        } else {
    2.40 +        }
    2.41 +        else
    2.42 +        {
    2.43              s->irr &= ~mask;
    2.44              s->last_irr &= ~mask;
    2.45          }
    2.46 -    } else {
    2.47 -        /* edge triggered */
    2.48 -        if (level) {
    2.49 -            if ((s->last_irr & mask) == 0)
    2.50 +    }
    2.51 +    else
    2.52 +    {
    2.53 +        /* Edge triggered. */
    2.54 +        if ( level )
    2.55 +        {
    2.56 +            if ( (s->last_irr & mask) == 0 )
    2.57                  s->irr |= mask;
    2.58              s->last_irr |= mask;
    2.59 -        } else {
    2.60 +        }
    2.61 +        else
    2.62 +        {
    2.63              s->last_irr &= ~mask;
    2.64          }
    2.65      }
    2.66  }
    2.67  
    2.68 -/* return the highest priority found in mask (highest = smallest
    2.69 -   number). Return 8 if no irq */
    2.70 +/* Return the highest priority found in mask. Return 8 if no irq. */
    2.71  static inline int get_priority(PicState *s, int mask)
    2.72  {
    2.73      int priority;
    2.74  
    2.75      ASSERT(spin_is_locked(vpic_lock(s->pics_state)));
    2.76  
    2.77 -    if (mask == 0)
    2.78 +    if ( mask == 0 )
    2.79          return 8;
    2.80 +
    2.81      priority = 0;
    2.82 -    while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
    2.83 +    while ( (mask & (1 << ((priority + s->priority_add) & 7))) == 0 )
    2.84          priority++;
    2.85 +
    2.86      return priority;
    2.87  }
    2.88  
    2.89 -/* return the pic wanted interrupt. return -1 if none */
    2.90 +/* Return the PIC's highest priority pending interrupt. Return -1 if none. */
    2.91  static int pic_get_irq(PicState *s)
    2.92  {
    2.93      int mask, cur_priority, priority;
    2.94 @@ -91,42 +98,44 @@ static int pic_get_irq(PicState *s)
    2.95  
    2.96      mask = s->irr & ~s->imr;
    2.97      priority = get_priority(s, mask);
    2.98 -    if (priority == 8)
    2.99 +    if ( priority == 8 )
   2.100          return -1;
   2.101 -    /* compute current priority. If special fully nested mode on the
   2.102 -       master, the IRQ coming from the slave is not taken into account
   2.103 -       for the priority computation. */
   2.104 +
   2.105 +    /*
   2.106 +     * Compute current priority. If special fully nested mode on the master,
   2.107 +     * the IRQ coming from the slave is not taken into account for the
   2.108 +     * priority computation.
   2.109 +     */
   2.110      mask = s->isr;
   2.111 -    if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
   2.112 +    if ( s->special_fully_nested_mode && (s == &s->pics_state->pics[0]) )
   2.113          mask &= ~(1 << 2);
   2.114      cur_priority = get_priority(s, mask);
   2.115 -    if (priority < cur_priority) {
   2.116 -        /* higher priority found: an irq should be generated */
   2.117 +    if ( priority < cur_priority )
   2.118 +        /* Higher priority found: an irq should be generated. */
   2.119          return (priority + s->priority_add) & 7;
   2.120 -    } else {
   2.121 -        return -1;
   2.122 -    }
   2.123 +
   2.124 +    return -1;
   2.125  }
   2.126  
   2.127 -/* raise irq to CPU if necessary. must be called every time the active
   2.128 -   irq may change */
   2.129 -/* XXX: should not export it, but it is needed for an APIC kludge */
   2.130 -void pic_update_irq(struct vpic *vpic)
   2.131 +/* Raise irq to CPU if necessary. */
   2.132 +static void pic_update_irq(struct vpic *vpic)
   2.133  {
   2.134      int irq2, irq;
   2.135  
   2.136      ASSERT(spin_is_locked(vpic_lock(vpic)));
   2.137  
   2.138 -    /* first look at slave pic */
   2.139 +    /* First look at slave PIC. */
   2.140      irq2 = pic_get_irq(&vpic->pics[1]);
   2.141 -    if (irq2 >= 0) {
   2.142 -        /* if irq request by slave pic, signal master PIC */
   2.143 +    if ( irq2 >= 0 )
   2.144 +    {
   2.145 +        /* If irq request by slave pic, signal master PIC. */
   2.146          pic_set_irq1(&vpic->pics[0], 2, 1);
   2.147          pic_set_irq1(&vpic->pics[0], 2, 0);
   2.148      }
   2.149 -    /* look at requested irq */
   2.150 +
   2.151 +    /* Look at requested IRQ. */
   2.152      irq = pic_get_irq(&vpic->pics[0]);
   2.153 -    if (irq >= 0)
   2.154 +    if ( irq >= 0 )
   2.155          vpic->irq_pending = 1;
   2.156  }
   2.157  
   2.158 @@ -137,53 +146,66 @@ void pic_set_irq(struct vpic *vpic, int 
   2.159      pic_update_irq(vpic);
   2.160  }
   2.161  
   2.162 -/* acknowledge interrupt 'irq' */
   2.163 +/* Acknowledge interrupt @irq. */
   2.164  static inline void pic_intack(PicState *s, int irq)
   2.165  {
   2.166      ASSERT(spin_is_locked(vpic_lock(s->pics_state)));
   2.167  
   2.168 -    if (s->auto_eoi) {
   2.169 -        if (s->rotate_on_auto_eoi)
   2.170 +    if ( s->auto_eoi )
   2.171 +    {
   2.172 +        if ( s->rotate_on_auto_eoi )
   2.173              s->priority_add = (irq + 1) & 7;
   2.174 -    } else {
   2.175 +    }
   2.176 +    else
   2.177 +    {
   2.178          s->isr |= (1 << irq);
   2.179      }
   2.180 +
   2.181      /* We don't clear a level sensitive interrupt here */
   2.182 -    if (!(s->elcr & (1 << irq)))
   2.183 +    if ( !(s->elcr & (1 << irq)) )
   2.184          s->irr &= ~(1 << irq);
   2.185  }
   2.186  
   2.187  static int pic_read_irq(struct vpic *vpic)
   2.188  {
   2.189      int irq, irq2, intno;
   2.190 -    unsigned long flags;
   2.191 +
   2.192 +    spin_lock(vpic_lock(vpic));
   2.193  
   2.194 -    spin_lock_irqsave(vpic_lock(vpic), flags);
   2.195      irq = pic_get_irq(&vpic->pics[0]);
   2.196 -    if (irq >= 0) {
   2.197 +    if ( irq >= 0 )
   2.198 +    {
   2.199          pic_intack(&vpic->pics[0], irq);
   2.200 -        if (irq == 2) {
   2.201 +        if ( irq == 2 )
   2.202 +        {
   2.203              irq2 = pic_get_irq(&vpic->pics[1]);
   2.204 -            if (irq2 >= 0) {
   2.205 +            if ( irq2 >= 0 )
   2.206 +            {
   2.207                  pic_intack(&vpic->pics[1], irq2);
   2.208 -            } else {
   2.209 -                /* spurious IRQ on slave controller */
   2.210 +            }
   2.211 +            else
   2.212 +            {
   2.213  		gdprintk(XENLOG_WARNING, "Spurious irq on slave i8259.\n");
   2.214                  irq2 = 7;
   2.215              }
   2.216              intno = vpic->pics[1].irq_base + irq2;
   2.217              irq = irq2 + 8;
   2.218 -        } else {
   2.219 +        }
   2.220 +        else
   2.221 +        {
   2.222              intno = vpic->pics[0].irq_base + irq;
   2.223          }
   2.224 -    } else {
   2.225 -        /* spurious IRQ on host controller */
   2.226 +    }
   2.227 +    else
   2.228 +    {
   2.229          irq = 7;
   2.230          intno = vpic->pics[0].irq_base + irq;
   2.231  	gdprintk(XENLOG_WARNING, "Spurious irq on master i8259.\n");
   2.232      }
   2.233 +
   2.234      pic_update_irq(vpic);
   2.235 -    spin_unlock_irqrestore(vpic_lock(vpic), flags);
   2.236 +
   2.237 +    spin_unlock(vpic_lock(vpic));
   2.238  
   2.239      return intno;
   2.240  }
   2.241 @@ -192,8 +214,6 @@ static void pic_reset(void *opaque)
   2.242  {
   2.243      PicState *s = opaque;
   2.244  
   2.245 -    ASSERT(spin_is_locked(vpic_lock(s->pics_state)));
   2.246 -
   2.247      s->last_irr = 0;
   2.248      s->irr = 0;
   2.249      s->imr = 0;
   2.250 @@ -219,33 +239,34 @@ static void pic_ioport_write(void *opaqu
   2.251      ASSERT(spin_is_locked(vpic_lock(s->pics_state)));
   2.252  
   2.253      addr &= 1;
   2.254 -    if (addr == 0) {
   2.255 -        if (val & 0x10) {
   2.256 -            /* init */
   2.257 +    if ( addr == 0 )
   2.258 +    {
   2.259 +        if ( val & 0x10 )
   2.260 +        {
   2.261              pic_reset(s);
   2.262 -            /* deassert a pending interrupt */
   2.263              s->pics_state->irq_pending = 0;
   2.264              s->init_state = 1;
   2.265              s->init4 = val & 1;
   2.266 -            if (val & 0x02)
   2.267 -                hw_error("single mode not supported");
   2.268 -            if (val & 0x08)
   2.269 -                hw_error("level sensitive irq not supported");
   2.270 -        } else if (val & 0x08) {
   2.271 -            if (val & 0x04)
   2.272 +        }
   2.273 +        else if ( val & 0x08 )
   2.274 +        {
   2.275 +            if ( val & 0x04 )
   2.276                  s->poll = 1;
   2.277 -            if (val & 0x02)
   2.278 +            if ( val & 0x02 )
   2.279                  s->read_reg_select = val & 1;
   2.280 -            if (val & 0x40)
   2.281 +            if ( val & 0x40 )
   2.282                  s->special_mask = (val >> 5) & 1;
   2.283 -        } else {
   2.284 +        }
   2.285 +        else
   2.286 +        {
   2.287              cmd = val >> 5;
   2.288 -            switch(cmd) {
   2.289 +            switch ( cmd )
   2.290 +            {
   2.291              case 0:
   2.292              case 4:
   2.293                  s->rotate_on_auto_eoi = cmd >> 2;
   2.294                  break;
   2.295 -            case 1: /* end of interrupt */
   2.296 +            case 1:
   2.297              case 5:
   2.298                  priority = get_priority(s, s->isr);
   2.299                  if (priority != 8) {
   2.300 @@ -272,14 +293,15 @@ static void pic_ioport_write(void *opaqu
   2.301                  pic_update_irq(s->pics_state);
   2.302                  break;
   2.303              default:
   2.304 -                /* no operation */
   2.305                  break;
   2.306              }
   2.307          }
   2.308 -    } else {
   2.309 -        switch(s->init_state) {
   2.310 +    }
   2.311 +    else
   2.312 +    {
   2.313 +        switch ( s->init_state )
   2.314 +        {
   2.315          case 0:
   2.316 -            /* normal mode */
   2.317              s->imr = val;
   2.318              pic_update_irq(s->pics_state);
   2.319              break;
   2.320 @@ -288,11 +310,7 @@ static void pic_ioport_write(void *opaqu
   2.321              s->init_state = 2;
   2.322              break;
   2.323          case 2:
   2.324 -            if (s->init4) {
   2.325 -                s->init_state = 3;
   2.326 -            } else {
   2.327 -                s->init_state = 0;
   2.328 -            }
   2.329 +            s->init_state = s->init4 ? 3 : 0;
   2.330              break;
   2.331          case 3:
   2.332              s->special_fully_nested_mode = (val >> 4) & 1;
   2.333 @@ -310,16 +328,20 @@ static uint32_t pic_poll_read (PicState 
   2.334      ASSERT(spin_is_locked(vpic_lock(s->pics_state)));
   2.335  
   2.336      ret = pic_get_irq(s);
   2.337 -    if (ret >= 0) {
   2.338 -        if (addr1 >> 7) {
   2.339 +    if ( ret >= 0 )
   2.340 +    {
   2.341 +        if ( addr1 >> 7 )
   2.342 +        {
   2.343              s->pics_state->pics[0].isr &= ~(1 << 2);
   2.344              s->pics_state->pics[0].irr &= ~(1 << 2);
   2.345          }
   2.346          s->irr &= ~(1 << ret);
   2.347          s->isr &= ~(1 << ret);
   2.348 -        if (addr1 >> 7 || ret != 2)
   2.349 +        if ( (addr1 >> 7) || (ret != 2) )
   2.350              pic_update_irq(s->pics_state);
   2.351 -    } else {
   2.352 +    }
   2.353 +    else
   2.354 +    {
   2.355          ret = 0x07;
   2.356          pic_update_irq(s->pics_state);
   2.357      }
   2.358 @@ -330,27 +352,19 @@ static uint32_t pic_poll_read (PicState 
   2.359  static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
   2.360  {
   2.361      PicState *s = opaque;
   2.362 -    unsigned int addr;
   2.363 -    int ret;
   2.364  
   2.365      ASSERT(spin_is_locked(vpic_lock(s->pics_state)));
   2.366  
   2.367 -    addr = addr1;
   2.368 -    addr &= 1;
   2.369 -    if (s->poll) {
   2.370 -        ret = pic_poll_read(s, addr1);
   2.371 +    if ( s->poll )
   2.372 +    {
   2.373          s->poll = 0;
   2.374 -    } else {
   2.375 -        if (addr == 0) {
   2.376 -            if (s->read_reg_select)
   2.377 -                ret = s->isr;
   2.378 -            else
   2.379 -                ret = s->irr;
   2.380 -        } else {
   2.381 -            ret = s->imr;
   2.382 -        }
   2.383 +        return pic_poll_read(s, addr1);
   2.384      }
   2.385 -    return ret;
   2.386 +
   2.387 +    if ( (addr1 & 1) == 0 )
   2.388 +        return (s->read_reg_select ? s->isr : s->irr);
   2.389 +
   2.390 +    return s->imr;
   2.391  }
   2.392  
   2.393  static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
   2.394 @@ -368,92 +382,86 @@ static uint32_t elcr_ioport_read(void *o
   2.395      return s->elcr;
   2.396  }
   2.397  
   2.398 -/* XXX: add generic master/slave system */
   2.399  static void pic_init1(int io_addr, int elcr_addr, PicState *s)
   2.400  {
   2.401 -    ASSERT(spin_is_locked(vpic_lock(s->pics_state)));
   2.402 -
   2.403      pic_reset(s);
   2.404 -
   2.405 -    /* XXX We set the ELCR to level triggered here, but that should
   2.406 -       really be done by the BIOS, and only for PCI IRQs. */
   2.407 -    s->elcr = 0xff & s->elcr_mask;
   2.408  }
   2.409  
   2.410  void pic_init(struct vpic *vpic)
   2.411  {
   2.412 -    unsigned long flags;
   2.413 -
   2.414      memset(vpic, 0, sizeof(*vpic));
   2.415      spin_lock_init(vpic_lock(vpic));
   2.416      vpic->pics[0].pics_state = vpic;
   2.417      vpic->pics[1].pics_state = vpic;
   2.418      vpic->pics[0].elcr_mask = 0xf8;
   2.419      vpic->pics[1].elcr_mask = 0xde;
   2.420 -    spin_lock_irqsave(vpic_lock(vpic), flags);
   2.421      pic_init1(0x20, 0x4d0, &vpic->pics[0]);
   2.422      pic_init1(0xa0, 0x4d1, &vpic->pics[1]);
   2.423 -    spin_unlock_irqrestore(vpic_lock(vpic), flags);
   2.424  }
   2.425  
   2.426  static int intercept_pic_io(ioreq_t *p)
   2.427  {
   2.428 -    struct vpic *pic;
   2.429 +    struct vpic *vpic = domain_vpic(current->domain);
   2.430      uint32_t data;
   2.431 -    unsigned long flags;
   2.432  
   2.433 -    if ( p->size != 1 || p->count != 1 ) {
   2.434 -        printk("PIC_IO wrong access size %d!\n", (int)p->size);
   2.435 +    if ( (p->size != 1) || (p->count != 1) )
   2.436 +    {
   2.437 +        gdprintk(XENLOG_WARNING,
   2.438 +                 "PIC_IO wrong access size %d!\n", (int)p->size);
   2.439          return 1;
   2.440      }
   2.441  
   2.442 -    pic = domain_vpic(current->domain);
   2.443 -    if ( p->dir == IOREQ_WRITE ) {
   2.444 +    if ( p->dir == IOREQ_WRITE )
   2.445 +    {
   2.446          if ( p->data_is_ptr )
   2.447              (void)hvm_copy_from_guest_phys(&data, p->data, p->size);
   2.448          else
   2.449              data = p->data;
   2.450 -        spin_lock_irqsave(vpic_lock(pic), flags);
   2.451 -        pic_ioport_write((void*)&pic->pics[p->addr>>7],
   2.452 +        spin_lock(vpic_lock(vpic));
   2.453 +        pic_ioport_write((void*)&vpic->pics[p->addr>>7],
   2.454                  (uint32_t) p->addr, (uint32_t) (data & 0xff));
   2.455 -        spin_unlock_irqrestore(vpic_lock(pic), flags);
   2.456 +        spin_unlock(vpic_lock(vpic));
   2.457      }
   2.458 -    else {
   2.459 -        spin_lock_irqsave(vpic_lock(pic), flags);
   2.460 +    else
   2.461 +    {
   2.462 +        spin_lock(vpic_lock(vpic));
   2.463          data = pic_ioport_read(
   2.464 -            (void*)&pic->pics[p->addr>>7], (uint32_t) p->addr);
   2.465 -        spin_unlock_irqrestore(vpic_lock(pic), flags);
   2.466 +            (void*)&vpic->pics[p->addr>>7], (uint32_t) p->addr);
   2.467 +        spin_unlock(vpic_lock(vpic));
   2.468          if ( p->data_is_ptr )
   2.469              (void)hvm_copy_to_guest_phys(p->data, &data, p->size);
   2.470          else
   2.471              p->data = (u64)data;
   2.472      }
   2.473 +
   2.474      return 1;
   2.475  }
   2.476  
   2.477  static int intercept_elcr_io(ioreq_t *p)
   2.478  {
   2.479 -    struct vpic *vpic;
   2.480 +    struct vpic *vpic = domain_vpic(current->domain);
   2.481      uint32_t data;
   2.482 -    unsigned long flags;
   2.483  
   2.484 -    if ( p->size != 1 || p->count != 1 ) {
   2.485 -        printk("PIC_IO wrong access size %d!\n", (int)p->size);
   2.486 +    if ( (p->size != 1) || (p->count != 1) )
   2.487 +    {
   2.488 +        gdprintk(XENLOG_WARNING,
   2.489 +                 "PIC_IO wrong access size %d!\n", (int)p->size);
   2.490          return 1;
   2.491      }
   2.492  
   2.493 -    vpic = domain_vpic(current->domain);
   2.494 -    if ( p->dir == IOREQ_WRITE ) {
   2.495 +    if ( p->dir == IOREQ_WRITE )
   2.496 +    {
   2.497          if ( p->data_is_ptr )
   2.498              (void)hvm_copy_from_guest_phys(&data, p->data, p->size);
   2.499          else
   2.500              data = p->data;
   2.501 -        spin_lock_irqsave(vpic_lock(vpic), flags);
   2.502 +        spin_lock(vpic_lock(vpic));
   2.503          elcr_ioport_write((void*)&vpic->pics[p->addr&1],
   2.504                  (uint32_t) p->addr, (uint32_t)( data & 0xff));
   2.505 -        spin_unlock_irqrestore(vpic_lock(vpic), flags);
   2.506 +        spin_unlock(vpic_lock(vpic));
   2.507      }
   2.508 -    else {
   2.509 +    else
   2.510 +    {
   2.511          data = (u64) elcr_ioport_read(
   2.512                  (void*)&vpic->pics[p->addr&1], (uint32_t) p->addr);
   2.513          if ( p->data_is_ptr )
   2.514 @@ -461,6 +469,7 @@ static int intercept_elcr_io(ioreq_t *p)
   2.515          else
   2.516              p->data = (u64)data;
   2.517      }
   2.518 +
   2.519      return 1;
   2.520  }
   2.521  
   2.522 @@ -472,21 +481,18 @@ void register_pic_io_hook(struct domain 
   2.523      register_portio_handler(d, 0x4d1, 1, intercept_elcr_io);
   2.524  }
   2.525  
   2.526 -
   2.527 -/* IRQ handling */
   2.528  int cpu_get_pic_interrupt(struct vcpu *v, int *type)
   2.529  {
   2.530      int intno;
   2.531      struct vpic *vpic = domain_vpic(v->domain);
   2.532 -    struct hvm_domain *plat = &v->domain->arch.hvm_domain;
   2.533  
   2.534      if ( !vlapic_accept_pic_intr(v) )
   2.535          return -1;
   2.536  
   2.537 -    if ( xchg(&plat->irq.vpic.irq_pending, 0) == 0 )
   2.538 +    if ( xchg(&vpic->irq_pending, 0) == 0 )
   2.539          return -1;
   2.540  
   2.541 -    /* read the irq from the PIC */
   2.542 +    /* Read the irq from the PIC. */
   2.543      intno = pic_read_irq(vpic);
   2.544      *type = APIC_DM_EXTINT;
   2.545      return intno;
   2.546 @@ -495,35 +501,15 @@ int cpu_get_pic_interrupt(struct vcpu *v
   2.547  int is_periodic_irq(struct vcpu *v, int irq, int type)
   2.548  {
   2.549      int vec;
   2.550 -    struct periodic_time *pt =
   2.551 -        &(v->domain->arch.hvm_domain.pl_time.periodic_tm);
   2.552 +    struct periodic_time *pt = &v->domain->arch.hvm_domain.pl_time.periodic_tm;
   2.553  
   2.554 -    if (pt->irq == 0) { /* Is it pit irq? */
   2.555 -        if (type == APIC_DM_EXTINT)
   2.556 -            vec = domain_vpic(v->domain)->pics[0].irq_base;
   2.557 -        else
   2.558 -            vec = domain_vioapic(v->domain)->redirtbl[0].fields.vector;
   2.559 -
   2.560 -        if (irq == vec)
   2.561 -            return 1;
   2.562 -    }
   2.563 -
   2.564 -    return 0;
   2.565 -}
   2.566 +    if ( pt->irq != 0 )
   2.567 +        return 0;
   2.568  
   2.569 -int is_irq_enabled(struct vcpu *v, int irq)
   2.570 -{
   2.571 -    struct vioapic *vioapic = domain_vioapic(v->domain);
   2.572 -    struct vpic    *vpic    = domain_vpic(v->domain);
   2.573 -
   2.574 -    if (vioapic->redirtbl[irq].fields.mask == 0)
   2.575 -       return 1;
   2.576 +    if ( type == APIC_DM_EXTINT )
   2.577 +        vec = domain_vpic(v->domain)->pics[0].irq_base;
   2.578 +    else
   2.579 +        vec = domain_vioapic(v->domain)->redirtbl[0].fields.vector;
   2.580  
   2.581 -    if ( irq & 8 ) {
   2.582 -        return !( (1 << (irq&7)) & vpic->pics[1].imr);
   2.583 -    }
   2.584 -    else {
   2.585 -        return !( (1 << irq) & vpic->pics[0].imr);
   2.586 -    }
   2.587 +    return (irq == vec);
   2.588  }
   2.589 -
     3.1 --- a/xen/include/asm-x86/hvm/vpic.h	Fri Nov 24 14:37:45 2006 +0000
     3.2 +++ b/xen/include/asm-x86/hvm/vpic.h	Fri Nov 24 15:42:14 2006 +0000
     3.3 @@ -1,8 +1,9 @@
     3.4  /*
     3.5 - * QEMU System Emulator header
     3.6 + * i8259 interrupt controller emulation
     3.7   * 
     3.8   * Copyright (c) 2003 Fabrice Bellard
     3.9   * Copyright (c) 2005 Intel Corp
    3.10 + * Copyright (c) 2006 Keir Fraser, XenSource Inc.
    3.11   * 
    3.12   * Permission is hereby granted, free of charge, to any person obtaining a copy
    3.13   * of this software and associated documentation files (the "Software"), to
    3.14 @@ -59,10 +60,8 @@ struct vpic {
    3.15  
    3.16  void pic_set_irq(struct vpic *vpic, int irq, int level);
    3.17  void pic_init(struct vpic *vpic);
    3.18 -void pic_update_irq(struct vpic *vpic); /* Caller must hold vpic->lock */
    3.19  void register_pic_io_hook(struct domain *d);
    3.20  int cpu_get_pic_interrupt(struct vcpu *v, int *type);
    3.21  int is_periodic_irq(struct vcpu *v, int irq, int type);
    3.22 -int is_irq_enabled(struct vcpu *v, int irq);
    3.23  
    3.24  #endif  /* __ASM_X86_HVM_VPIC_H__ */  
     4.1 --- a/xen/include/asm-x86/hvm/vpt.h	Fri Nov 24 14:37:45 2006 +0000
     4.2 +++ b/xen/include/asm-x86/hvm/vpt.h	Fri Nov 24 15:42:14 2006 +0000
     4.3 @@ -111,36 +111,19 @@ struct pl_time {    /* platform time */
     4.4      struct PMTState      vpmt;
     4.5  };
     4.6  
     4.7 -static __inline__ s_time_t get_scheduled(
     4.8 -    struct vcpu *v, int irq,
     4.9 -    struct periodic_time *pt)
    4.10 +extern u64 hvm_get_guest_time(struct vcpu *v);
    4.11 +static inline int64_t hvm_get_clock(struct vcpu *v)
    4.12  {
    4.13 -    if ( is_irq_enabled(v, irq) ) {
    4.14 -        return pt->scheduled;
    4.15 -    }
    4.16 -    else
    4.17 -        return -1;
    4.18 +    return hvm_get_guest_time(v);
    4.19  }
    4.20  
    4.21 -extern u64 hvm_get_guest_time(struct vcpu *v);
    4.22 -/*
    4.23 - * get processor time.
    4.24 - * unit: TSC
    4.25 - */
    4.26 -static __inline__ int64_t hvm_get_clock(struct vcpu *v)
    4.27 -{
    4.28 -    uint64_t  gtsc;
    4.29 -
    4.30 -    gtsc = hvm_get_guest_time(v);
    4.31 -    return gtsc;
    4.32 -}
    4.33 -
    4.34 -#define ticks_per_sec(v)      (v->domain->arch.hvm_domain.tsc_frequency)
    4.35 +#define ticks_per_sec(v) (v->domain->arch.hvm_domain.tsc_frequency)
    4.36  
    4.37  /* to hook the ioreq packet to get the PIT initialization info */
    4.38  extern void hvm_hooks_assist(struct vcpu *v);
    4.39  extern void pickup_deactive_ticks(struct periodic_time *vpit);
    4.40 -extern struct periodic_time *create_periodic_time(u32 period, char irq, char one_shot, time_cb *cb, void *data);
    4.41 +extern struct periodic_time *create_periodic_time(
    4.42 +    u32 period, char irq, char one_shot, time_cb *cb, void *data);
    4.43  extern void destroy_periodic_time(struct periodic_time *pt);
    4.44  void pit_init(struct vcpu *v, unsigned long cpu_khz);
    4.45  void rtc_init(struct vcpu *v, int base, int irq);