ia64/xen-unstable

changeset 15089:05c128b0188a

hvm: Fix ACPI shutdown, broken by my previous changeset.

It turns out that although PIIX4 hardware defines the S5 type code to
be 000, all OSes will discover the correct code by evlauating an \_Sx
object in the ACPI DSDT. And we set the type code in that object to be
111.

So this patch keeps the other cleanups made to the piix4acpi.c file,
but switches back to checking for code 111. It also makes it clearer
in both the ioemu code and in the dsdt source code where these magic
numbers come from.

Let's hope noone actually has the true PIIX4 type codes hardcoded
(it's highly doubtful that anyone would).

Signed-off-by: Keir Fraser <keir@xensource.com>
author Keir Fraser <keir@xensource.com>
date Sat May 12 16:24:50 2007 +0100 (2007-05-12)
parents 174995130550
children 384a29655270
files tools/firmware/hvmloader/acpi/dsdt.asl tools/firmware/hvmloader/acpi/dsdt.c tools/ioemu/hw/piix4acpi.c
line diff
     1.1 --- a/tools/firmware/hvmloader/acpi/dsdt.asl	Sat May 12 12:46:26 2007 +0100
     1.2 +++ b/tools/firmware/hvmloader/acpi/dsdt.asl	Sat May 12 16:24:50 2007 +0100
     1.3 @@ -27,13 +27,13 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, 
     1.4      Name (\APCL, 0x00010000)
     1.5      Name (\PUID, 0x00)
     1.6  
     1.7 -    /* Poweroff support - ties in with qemu emulation */
     1.8 +    /* S5 (power-off) type codes: must match with piix4 emulation! */
     1.9      Name (\_S5, Package (0x04)
    1.10      {
    1.11 -        0x07,
    1.12 -        0x07,
    1.13 -        0x00,
    1.14 -        0x00
    1.15 +        0x07,  /* PM1a_CNT.SLP_TYP */
    1.16 +        0x07,  /* PM1b_CNT.SLP_TYP */
    1.17 +        0x00,  /* reserved */
    1.18 +        0x00   /* reserved */
    1.19      })
    1.20  
    1.21      Name(PICD, 0)
     2.1 --- a/tools/firmware/hvmloader/acpi/dsdt.c	Sat May 12 12:46:26 2007 +0100
     2.2 +++ b/tools/firmware/hvmloader/acpi/dsdt.c	Sat May 12 16:24:50 2007 +0100
     2.3 @@ -1,11 +1,11 @@
     2.4  /*
     2.5   * 
     2.6   * Intel ACPI Component Architecture
     2.7 - * ASL Optimizing Compiler version 20060707 [Feb 16 2007]
     2.8 + * ASL Optimizing Compiler version 20060707 [Dec 30 2006]
     2.9   * Copyright (C) 2000 - 2006 Intel Corporation
    2.10   * Supports ACPI Specification Revision 3.0a
    2.11   * 
    2.12 - * Compilation of "dsdt.asl" - Mon Feb 26 11:09:49 2007
    2.13 + * Compilation of "dsdt.asl" - Sat May 12 16:13:55 2007
    2.14   * 
    2.15   * C source code output
    2.16   *
     3.1 --- a/tools/ioemu/hw/piix4acpi.c	Sat May 12 12:46:26 2007 +0100
     3.2 +++ b/tools/ioemu/hw/piix4acpi.c	Sat May 12 16:24:50 2007 +0100
     3.3 @@ -25,11 +25,15 @@
     3.4  
     3.5  #include "vl.h"
     3.6  
     3.7 -/* PMCNTRL */
     3.8 +/* PM1a_CNT bits, as defined in the ACPI specification. */
     3.9  #define SCI_EN            (1 <<  0)
    3.10  #define GBL_RLS           (1 <<  2)
    3.11 -#define SUS_TYP           (7 << 10)
    3.12 -#define SUS_EN            (1 << 13)
    3.13 +#define SLP_TYP_Sx        (7 << 10)
    3.14 +#define SLP_EN            (1 << 13)
    3.15 +
    3.16 +/* Sleep state type codes as defined by the \_Sx objects in the DSDT. */
    3.17 +/* These must be kept in sync with the DSDT (hvmloader/acpi/dsdt.asl) */
    3.18 +#define SLP_TYP_S5        (7 << 10)
    3.19  
    3.20  typedef struct AcpiDeviceState AcpiDeviceState;
    3.21  AcpiDeviceState *acpi_device_table;
    3.22 @@ -69,7 +73,7 @@ static uint32_t acpiPm1Control_readb(voi
    3.23  {
    3.24      PCIAcpiState *s = opaque;
    3.25      /* Mask out the write-only bits */
    3.26 -    return (uint8_t)(s->pm1_control & ~(GBL_RLS|SUS_EN));
    3.27 +    return (uint8_t)(s->pm1_control & ~(GBL_RLS|SLP_EN));
    3.28  }
    3.29  
    3.30  static void acpiPm1ControlP1_writeb(void *opaque, uint32_t addr, uint32_t val)
    3.31 @@ -77,10 +81,10 @@ static void acpiPm1ControlP1_writeb(void
    3.32      PCIAcpiState *s = opaque;
    3.33  
    3.34      val <<= 8;
    3.35 -    s->pm1_control = ((s->pm1_control & 0xff) | val) & ~SUS_EN;
    3.36 +    s->pm1_control = ((s->pm1_control & 0xff) | val) & ~SLP_EN;
    3.37  
    3.38      /* Check for power off request. */
    3.39 -    if ((val & (SUS_EN|SUS_TYP)) == SUS_EN)
    3.40 +    if ((val & (SLP_EN|SLP_TYP_Sx)) == (SLP_EN|SLP_TYP_S5))
    3.41          qemu_system_shutdown_request();
    3.42  }
    3.43  
    3.44 @@ -88,17 +92,17 @@ static uint32_t acpiPm1ControlP1_readb(v
    3.45  {
    3.46      PCIAcpiState *s = opaque;
    3.47      /* Mask out the write-only bits */
    3.48 -    return (uint8_t)((s->pm1_control & ~(GBL_RLS|SUS_EN)) >> 8);
    3.49 +    return (uint8_t)((s->pm1_control & ~(GBL_RLS|SLP_EN)) >> 8);
    3.50  }
    3.51  
    3.52  static void acpiPm1Control_writew(void *opaque, uint32_t addr, uint32_t val)
    3.53  {
    3.54      PCIAcpiState *s = opaque;
    3.55  
    3.56 -    s->pm1_control = val & ~SUS_EN;
    3.57 +    s->pm1_control = val & ~SLP_EN;
    3.58  
    3.59      /* Check for power off request. */
    3.60 -    if ((val & (SUS_EN|SUS_TYP)) == SUS_EN)
    3.61 +    if ((val & (SLP_EN|SLP_TYP_Sx)) == (SLP_EN|SLP_TYP_S5))
    3.62          qemu_system_shutdown_request();
    3.63  }
    3.64  
    3.65 @@ -106,7 +110,7 @@ static uint32_t acpiPm1Control_readw(voi
    3.66  {
    3.67      PCIAcpiState *s = opaque;
    3.68      /* Mask out the write-only bits */
    3.69 -    return (s->pm1_control & ~(GBL_RLS|SUS_EN));
    3.70 +    return (s->pm1_control & ~(GBL_RLS|SLP_EN));
    3.71  }
    3.72  
    3.73  static void acpi_map(PCIDevice *pci_dev, int region_num,