ia64/xen-unstable

changeset 5046:0554a6615257

bitkeeper revision 1.1389.23.4 (428e13b9Hne7WMFOPqv3id1PNB6EYg)

- CONFIG_VTI=n by default.
- Reorganize code such that the changes to cp_patch files are minimized

Signed-off-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Arun Sharma <arun.sharma@intel.com>
author adsharma@linux-t08.sc.intel.com
date Fri May 20 16:43:37 2005 +0000 (2005-05-20)
parents 6dd98ed3c52a
children 541012edd6e5
files .rootkeys xen/arch/ia64/Rules.mk xen/arch/ia64/mm_init.c xen/arch/ia64/patch/linux-2.6.11/page.h xen/arch/ia64/patch/linux-2.6.11/processor.h xen/arch/ia64/patch/linux-2.6.11/system.h xen/arch/ia64/vmx_init.c xen/arch/ia64/xensetup.c xen/include/asm-ia64/vmx.h xen/include/asm-ia64/xenprocessor.h xen/include/asm-ia64/xensystem.h
line diff
     1.1 --- a/.rootkeys	Wed May 18 21:19:06 2005 +0000
     1.2 +++ b/.rootkeys	Fri May 20 16:43:37 2005 +0000
     1.3 @@ -1354,7 +1354,9 @@ 428b9f38lm0ntDBusHggeQXkx1-1HQ xen/inclu
     1.4  428b9f38XgwHchZEpOzRtWfz0agFNQ xen/include/asm-ia64/vmx_vcpu.h
     1.5  428b9f38tDTTJbkoONcAB9ODP8CiVg xen/include/asm-ia64/vmx_vpd.h
     1.6  428b9f38_o0U5uJqmxZf_bqi6_PqVw xen/include/asm-ia64/vtm.h
     1.7 +428e120a-H-bqn10zOlnhlzlVEuW8A xen/include/asm-ia64/xenprocessor.h
     1.8  421098b7LfwIHQ2lRYWhO4ruEXqIuQ xen/include/asm-ia64/xenserial.h
     1.9 +428e120esS-Tp1mX5VoUrsGJDNY_ow xen/include/asm-ia64/xensystem.h
    1.10  40715b2dWe0tDhx9LkLXzTQkvD49RA xen/include/asm-x86/acpi.h
    1.11  3ddb79c3l4IiQtf6MS2jIzcd-hJS8g xen/include/asm-x86/apic.h
    1.12  3ddb79c3QJYWr8LLGdonLbWmNb9pQQ xen/include/asm-x86/apicdef.h
     2.1 --- a/xen/arch/ia64/Rules.mk	Wed May 18 21:19:06 2005 +0000
     2.2 +++ b/xen/arch/ia64/Rules.mk	Fri May 20 16:43:37 2005 +0000
     2.3 @@ -1,7 +1,7 @@
     2.4  ########################################
     2.5  # ia64-specific definitions
     2.6  
     2.7 -CONFIG_VTI	?= y
     2.8 +CONFIG_VTI	?= n
     2.9  ifneq ($(COMPILE_ARCH),$(TARGET_ARCH))
    2.10  CROSS_COMPILE ?= /usr/local/sp_env/v2.2.5/i686/bin/ia64-unknown-linux-
    2.11  endif
     3.1 --- a/xen/arch/ia64/mm_init.c	Wed May 18 21:19:06 2005 +0000
     3.2 +++ b/xen/arch/ia64/mm_init.c	Fri May 20 16:43:37 2005 +0000
     3.3 @@ -301,20 +301,6 @@ ia64_mmu_init (void *my_cpu_data)
     3.4  		 pte_val(pfn_pte(__pa(my_cpu_data) >> PAGE_SHIFT, PAGE_KERNEL)),
     3.5  		 PERCPU_PAGE_SHIFT);
     3.6  
     3.7 -#ifdef CONFIG_VTI
     3.8 -	{
     3.9 -		u64 base;
    3.10 -		extern void vmx_switch_rr7(void);
    3.11 -
    3.12 -		base = (u64) &vmx_switch_rr7;
    3.13 -		base = *((u64*)base);
    3.14 -		ia64_itr(0x1, IA64_TR_RR7_SWITCH_STUB, XEN_RR7_SWITCH_STUB,
    3.15 -			 pte_val(pfn_pte(__pa(base) >> PAGE_SHIFT, PAGE_KERNEL)),
    3.16 -			 RR7_SWITCH_SHIFT);
    3.17 -		printk("Add TR mapping for rr7 switch stub, with physical: 0x%lx\n", (u64)(__pa(base)));
    3.18 -	}
    3.19 -#endif // CONFIG_VTI
    3.20 -
    3.21  	ia64_set_psr(psr);
    3.22  	ia64_srlz_i();
    3.23  
     4.1 --- a/xen/arch/ia64/patch/linux-2.6.11/page.h	Wed May 18 21:19:06 2005 +0000
     4.2 +++ b/xen/arch/ia64/patch/linux-2.6.11/page.h	Fri May 20 16:43:37 2005 +0000
     4.3 @@ -1,17 +1,14 @@
     4.4 ---- /home/adsharma/disk2/xen-ia64/xeno-unstable-rebase.bk/xen/../../linux-2.6.11/include/asm-ia64/page.h	2005-03-01 23:37:48.000000000 -0800
     4.5 -+++ /home/adsharma/disk2/xen-ia64/xeno-unstable-rebase.bk/xen/include/asm-ia64/page.h	2005-05-18 12:40:50.000000000 -0700
     4.6 -@@ -32,6 +32,10 @@
     4.7 +--- /home/adsharma/xeno-unstable-ia64-staging.bk/xen/../../linux-2.6.11/include/asm-ia64/page.h	2005-03-01 23:37:48.000000000 -0800
     4.8 ++++ /home/adsharma/xeno-unstable-ia64-staging.bk/xen/include/asm-ia64/page.h	2005-05-20 09:36:02.000000000 -0700
     4.9 +@@ -32,6 +32,7 @@
    4.10   #define PAGE_ALIGN(addr)	(((addr) + PAGE_SIZE - 1) & PAGE_MASK)
    4.11   
    4.12   #define PERCPU_PAGE_SHIFT	16	/* log2() of max. size of per-CPU area */
    4.13 -+#ifdef CONFIG_VTI
    4.14 -+#define RR7_SWITCH_SHIFT	12	/* 4k enough */
    4.15 -+#endif // CONFIG_VTI
    4.16  +
    4.17   #define PERCPU_PAGE_SIZE	(__IA64_UL_CONST(1) << PERCPU_PAGE_SHIFT)
    4.18   
    4.19   #define RGN_MAP_LIMIT	((1UL << (4*PAGE_SHIFT - 12)) - PAGE_SIZE)	/* per region addr limit */
    4.20 -@@ -95,9 +99,15 @@
    4.21 +@@ -95,9 +96,15 @@
    4.22   #endif
    4.23   
    4.24   #ifndef CONFIG_DISCONTIGMEM
    4.25 @@ -27,7 +24,7 @@
    4.26   #else
    4.27   extern struct page *vmem_map;
    4.28   extern unsigned long max_low_pfn;
    4.29 -@@ -109,6 +119,11 @@
    4.30 +@@ -109,6 +116,11 @@
    4.31   #define page_to_phys(page)	(page_to_pfn(page) << PAGE_SHIFT)
    4.32   #define virt_to_page(kaddr)	pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
    4.33   
    4.34 @@ -39,7 +36,7 @@
    4.35   typedef union ia64_va {
    4.36   	struct {
    4.37   		unsigned long off : 61;		/* intra-region offset */
    4.38 -@@ -124,8 +139,23 @@
    4.39 +@@ -124,8 +136,23 @@
    4.40    * expressed in this way to ensure they result in a single "dep"
    4.41    * instruction.
    4.42    */
    4.43 @@ -63,7 +60,7 @@
    4.44   
    4.45   #define REGION_NUMBER(x)	({ia64_va _v; _v.l = (long) (x); _v.f.reg;})
    4.46   #define REGION_OFFSET(x)	({ia64_va _v; _v.l = (long) (x); _v.f.off;})
    4.47 -@@ -197,7 +227,11 @@
    4.48 +@@ -197,7 +224,11 @@
    4.49   # define __pgprot(x)	(x)
    4.50   #endif /* !STRICT_MM_TYPECHECKS */
    4.51   
     5.1 --- a/xen/arch/ia64/patch/linux-2.6.11/processor.h	Wed May 18 21:19:06 2005 +0000
     5.2 +++ b/xen/arch/ia64/patch/linux-2.6.11/processor.h	Fri May 20 16:43:37 2005 +0000
     5.3 @@ -1,179 +1,30 @@
     5.4 ---- /home/adsharma/disk2/xen-ia64/xeno-unstable-rebase.bk/xen/../../linux-2.6.11/include/asm-ia64/processor.h	2005-03-01 23:37:58.000000000 -0800
     5.5 -+++ /home/adsharma/disk2/xen-ia64/xeno-unstable-rebase.bk/xen/include/asm-ia64/processor.h	2005-05-18 12:40:50.000000000 -0700
     5.6 -@@ -131,9 +131,166 @@
     5.7 - 	__u64 ri : 2;
     5.8 - 	__u64 ed : 1;
     5.9 - 	__u64 bn : 1;
    5.10 -+#ifdef CONFIG_VTI
    5.11 -+	__u64 ia : 1;
    5.12 -+	__u64 vm : 1;
    5.13 -+	__u64 reserved5 : 17;
    5.14 -+#else // CONFIG_VTI
    5.15 - 	__u64 reserved4 : 19;
    5.16 -+#endif // CONFIG_VTI
    5.17 - };
    5.18 +--- /home/adsharma/xeno-unstable-ia64-staging.bk/xen/../../linux-2.6.11/include/asm-ia64/processor.h	2005-03-01 23:37:58.000000000 -0800
    5.19 ++++ /home/adsharma/xeno-unstable-ia64-staging.bk/xen/include/asm-ia64/processor.h	2005-05-20 09:36:02.000000000 -0700
    5.20 +@@ -94,7 +94,11 @@
    5.21 + #ifdef CONFIG_NUMA
    5.22 + #include <asm/nodedata.h>
    5.23 + #endif
    5.24 ++#ifdef XEN
    5.25 ++#include <asm/xenprocessor.h>
    5.26 ++#endif
    5.27   
    5.28 -+#ifdef  CONFIG_VTI
    5.29 -+/* vmx like above but expressed as bitfields for more efficient access: */
    5.30 -+typedef  union{
    5.31 -+    __u64 val;
    5.32 -+    struct{
    5.33 -+    	__u64 reserved0 : 1;
    5.34 -+	__u64 be : 1;
    5.35 -+    	__u64 up : 1;
    5.36 -+    	__u64 ac : 1;
    5.37 -+    	__u64 mfl : 1;
    5.38 -+    	__u64 mfh : 1;
    5.39 -+    	__u64 reserved1 : 7;
    5.40 -+    	__u64 ic : 1;
    5.41 -+    	__u64 i : 1;
    5.42 -+    	__u64 pk : 1;
    5.43 -+    	__u64 reserved2 : 1;
    5.44 -+    	__u64 dt : 1;
    5.45 -+    	__u64 dfl : 1;
    5.46 -+    	__u64 dfh : 1;
    5.47 -+    	__u64 sp : 1;
    5.48 -+    	__u64 pp : 1;
    5.49 -+    	__u64 di : 1;
    5.50 -+	__u64 si : 1;
    5.51 -+    	__u64 db : 1;
    5.52 -+    	__u64 lp : 1;
    5.53 -+    	__u64 tb : 1;
    5.54 -+    	__u64 rt : 1;
    5.55 -+    	__u64 reserved3 : 4;
    5.56 -+    	__u64 cpl : 2;
    5.57 -+    	__u64 is : 1;
    5.58 -+    	__u64 mc : 1;
    5.59 -+    	__u64 it : 1;
    5.60 -+    	__u64 id : 1;
    5.61 -+    	__u64 da : 1;
    5.62 -+    	__u64 dd : 1;
    5.63 -+    	__u64 ss : 1;
    5.64 -+    	__u64 ri : 2;
    5.65 -+    	__u64 ed : 1;
    5.66 -+    	__u64 bn : 1;
    5.67 -+    	__u64 reserved4 : 19;
    5.68 -+    };
    5.69 -+}   IA64_PSR;
    5.70 -+
    5.71 -+typedef union {
    5.72 -+    __u64 val;
    5.73 -+    struct {
    5.74 -+        __u64 code : 16;
    5.75 -+        __u64 vector : 8;
    5.76 -+        __u64 reserved1 : 8;
    5.77 -+        __u64 x : 1;
    5.78 -+        __u64 w : 1;
    5.79 -+        __u64 r : 1;
    5.80 -+        __u64 na : 1;
    5.81 -+        __u64 sp : 1;
    5.82 -+        __u64 rs : 1;
    5.83 -+        __u64 ir : 1;
    5.84 -+        __u64 ni : 1;
    5.85 -+        __u64 so : 1;
    5.86 -+        __u64 ei : 2;
    5.87 -+        __u64 ed : 1;
    5.88 -+        __u64 reserved2 : 20;
    5.89 -+    };
    5.90 -+}   ISR;
    5.91 -+
    5.92 -+
    5.93 -+typedef union {
    5.94 -+    __u64 val;
    5.95 -+    struct {
    5.96 -+        __u64 ve : 1;
    5.97 -+        __u64 reserved0 : 1;
    5.98 -+        __u64 size : 6;
    5.99 -+        __u64 vf : 1;
   5.100 -+        __u64 reserved1 : 6;
   5.101 -+        __u64 base : 49;
   5.102 -+    };
   5.103 -+}   PTA;
   5.104 -+
   5.105 -+typedef union {
   5.106 -+    __u64 val;
   5.107 -+    struct {
   5.108 -+        __u64  rv  : 16;
   5.109 -+        __u64  eid : 8;
   5.110 -+        __u64  id  : 8;
   5.111 -+        __u64  ig  : 32;
   5.112 -+    };
   5.113 -+} LID;
   5.114 -+
   5.115 -+typedef union{
   5.116 -+    __u64 val;
   5.117 -+    struct {
   5.118 -+        __u64 rv  : 3;
   5.119 -+        __u64 ir  : 1;
   5.120 -+        __u64 eid : 8;
   5.121 -+        __u64 id  : 8;
   5.122 -+        __u64 ib_base : 44;
   5.123 -+    };
   5.124 -+} ipi_a_t;
   5.125 -+
   5.126 -+typedef union{
   5.127 -+    __u64 val;
   5.128 -+    struct {
   5.129 -+        __u64 vector : 8;
   5.130 -+        __u64 dm  : 3;
   5.131 -+        __u64 ig  : 53;
   5.132 -+    };
   5.133 -+} ipi_d_t;
   5.134 -+
   5.135 -+
   5.136 -+#define IA64_ISR_CODE_MASK0     0xf
   5.137 -+#define IA64_UNIMPL_DADDR_FAULT     0x30
   5.138 -+#define IA64_UNIMPL_IADDR_TRAP      0x10
   5.139 -+#define IA64_RESERVED_REG_FAULT     0x30
   5.140 -+#define IA64_REG_NAT_CONSUMPTION_FAULT  0x10
   5.141 -+#define IA64_NAT_CONSUMPTION_FAULT  0x20
   5.142 -+#define IA64_PRIV_OP_FAULT      0x10
   5.143 -+
   5.144 -+/* indirect register type */
   5.145 -+enum {
   5.146 -+    IA64_CPUID,     /*  cpuid */
   5.147 -+    IA64_DBR,       /*  dbr */
   5.148 -+    IA64_IBR,       /*  ibr */
   5.149 -+    IA64_PKR,       /*  pkr */
   5.150 -+    IA64_PMC,       /*  pmc */
   5.151 -+    IA64_PMD,       /*  pmd */
   5.152 -+    IA64_RR         /*  rr */
   5.153 -+};
   5.154 -+
   5.155 -+/* instruction type */
   5.156 -+enum {
   5.157 -+    IA64_INST_TPA=1,
   5.158 -+    IA64_INST_TAK
   5.159 -+};
   5.160 -+
   5.161 -+/* Generate Mask
   5.162 -+ * Parameter:
   5.163 -+ *  bit -- starting bit
   5.164 -+ *  len -- how many bits
   5.165 -+ */
   5.166 -+#define MASK(bit,len)                   \
   5.167 -+({                              \
   5.168 -+        __u64    ret;                    \
   5.169 -+                                \
   5.170 -+        __asm __volatile("dep %0=-1, r0, %1, %2"    \
   5.171 -+                : "=r" (ret):                   \
   5.172 -+          "M" (bit),                    \
   5.173 -+          "M" (len) );                  \
   5.174 -+        ret;                            \
   5.175 -+})
   5.176 -+
   5.177 -+#endif  //  CONFIG_VTI
   5.178 -+
   5.179 ++#ifndef XEN
   5.180 + /* like above but expressed as bitfields for more efficient access: */
   5.181 + struct ia64_psr {
   5.182 + 	__u64 reserved0 : 1;
   5.183 +@@ -133,6 +137,7 @@
   5.184 + 	__u64 bn : 1;
   5.185 + 	__u64 reserved4 : 19;
   5.186 + };
   5.187 ++#endif
   5.188 + 
   5.189   /*
   5.190    * CPU type, hardware bug flags, and per-CPU state.  Frequently used
   5.191 -  * state comes earlier:
   5.192 -@@ -408,12 +565,16 @@
   5.193 +@@ -408,12 +413,14 @@
   5.194    */
   5.195   
   5.196   /* Return TRUE if task T owns the fph partition of the CPU we're running on. */
   5.197 -+#ifdef XEN
   5.198 -+#define ia64_is_local_fpu_owner(t) 0
   5.199 -+#else
   5.200 ++#ifndef XEN
   5.201   #define ia64_is_local_fpu_owner(t)								\
   5.202   ({												\
   5.203   	struct task_struct *__ia64_islfo_task = (t);						\
     6.1 --- a/xen/arch/ia64/patch/linux-2.6.11/system.h	Wed May 18 21:19:06 2005 +0000
     6.2 +++ b/xen/arch/ia64/patch/linux-2.6.11/system.h	Fri May 20 16:43:37 2005 +0000
     6.3 @@ -1,76 +1,38 @@
     6.4 ---- /home/adsharma/disk2/xen-ia64/xeno-unstable-rebase.bk/xen/../../linux-2.6.11/include/asm-ia64/system.h	2005-03-01 23:38:07.000000000 -0800
     6.5 -+++ /home/adsharma/disk2/xen-ia64/xeno-unstable-rebase.bk/xen/include/asm-ia64/system.h	2005-05-18 12:40:50.000000000 -0700
     6.6 -@@ -24,8 +24,22 @@
     6.7 +--- /home/adsharma/xeno-unstable-ia64-staging.bk/xen/../../linux-2.6.11/include/asm-ia64/system.h	2005-03-01 23:38:07.000000000 -0800
     6.8 ++++ /home/adsharma/xeno-unstable-ia64-staging.bk/xen/include/asm-ia64/system.h	2005-05-20 09:36:02.000000000 -0700
     6.9 +@@ -18,14 +18,19 @@
    6.10 + #include <asm/page.h>
    6.11 + #include <asm/pal.h>
    6.12 + #include <asm/percpu.h>
    6.13 ++#ifdef XEN
    6.14 ++#include <asm/xensystem.h>
    6.15 ++#endif
    6.16 + 
    6.17 + #define GATE_ADDR		__IA64_UL_CONST(0xa000000000000000)
    6.18 + /*
    6.19    * 0xa000000000000000+2*PERCPU_PAGE_SIZE
    6.20    * - 0xa000000000000000+3*PERCPU_PAGE_SIZE remain unmapped (guard page)
    6.21    */
    6.22 -+#ifdef XEN
    6.23 -+#ifdef CONFIG_VTI
    6.24 -+#define XEN_VIRT_SPACE_LOW	 0xe800000000000000
    6.25 -+#define XEN_VIRT_SPACE_HIGH	 0xf800000000000000	
    6.26 -+/* This is address to mapping rr7 switch stub, in region 5 */
    6.27 -+#define XEN_RR7_SWITCH_STUB	 0xb700000000000000
    6.28 -+#endif // CONFIG_VTI
    6.29 -+
    6.30 -+#define KERNEL_START		 0xf000000004000000
    6.31 -+#define PERCPU_ADDR		 0xf100000000000000-PERCPU_PAGE_SIZE
    6.32 -+#define SHAREDINFO_ADDR		 0xf100000000000000
    6.33 -+#define VHPT_ADDR		 0xf200000000000000
    6.34 -+#else
    6.35 ++#ifndef XEN
    6.36   #define KERNEL_START		 __IA64_UL_CONST(0xa000000100000000)
    6.37   #define PERCPU_ADDR		(-PERCPU_PAGE_SIZE)
    6.38  +#endif
    6.39   
    6.40   #ifndef __ASSEMBLY__
    6.41   
    6.42 -@@ -205,6 +219,9 @@
    6.43 -  * ia64_ret_from_syscall_clear_r8.
    6.44 -  */
    6.45 - extern struct task_struct *ia64_switch_to (void *next_task);
    6.46 -+#ifdef CONFIG_VTI
    6.47 -+extern struct task_struct *vmx_ia64_switch_to (void *next_task);
    6.48 -+#endif // CONFIG_VTI
    6.49 - 
    6.50 - struct task_struct;
    6.51 - 
    6.52 -@@ -218,10 +235,32 @@
    6.53 +@@ -218,6 +223,7 @@
    6.54   # define PERFMON_IS_SYSWIDE() (0)
    6.55   #endif
    6.56   
    6.57 -+#ifdef XEN
    6.58 -+#define IA64_HAS_EXTRA_STATE(t) 0
    6.59 -+#else
    6.60 ++#ifndef XEN
    6.61   #define IA64_HAS_EXTRA_STATE(t)							\
    6.62   	((t)->thread.flags & (IA64_THREAD_DBG_VALID|IA64_THREAD_PM_VALID)	\
    6.63   	 || IS_IA32_PROCESS(ia64_task_regs(t)) || PERFMON_IS_SYSWIDE())
    6.64 -+#endif
    6.65 - 
    6.66 -+#ifdef CONFIG_VTI
    6.67 -+#define __switch_to(prev,next,last) do {	\
    6.68 -+       if (VMX_DOMAIN(prev))                   \
    6.69 -+               vmx_save_state(prev);           \
    6.70 -+       else {                                  \
    6.71 -+               if (IA64_HAS_EXTRA_STATE(prev)) \
    6.72 -+                       ia64_save_extra(prev);  \
    6.73 -+       }                                       \
    6.74 -+       if (VMX_DOMAIN(next))                   \
    6.75 -+               vmx_load_state(next);           \
    6.76 -+       else {                                  \
    6.77 -+               if (IA64_HAS_EXTRA_STATE(next)) \
    6.78 -+                       ia64_save_extra(next);  \
    6.79 -+       }                                       \
    6.80 -+       ia64_psr(ia64_task_regs(next))->dfh = !ia64_is_local_fpu_owner(next); \
    6.81 -+       (last) = vmx_ia64_switch_to((next));        \
    6.82 -+} while (0)
    6.83 -+#else // CONFIG_VTI
    6.84 - #define __switch_to(prev,next,last) do {							 \
    6.85 - 	if (IA64_HAS_EXTRA_STATE(prev))								 \
    6.86 - 		ia64_save_extra(prev);								 \
    6.87 -@@ -230,6 +269,7 @@
    6.88 +@@ -230,6 +236,7 @@
    6.89   	ia64_psr(ia64_task_regs(next))->dfh = !ia64_is_local_fpu_owner(next);			 \
    6.90   	(last) = ia64_switch_to((next));							 \
    6.91   } while (0)
    6.92 -+#endif // CONFIG_VTI
    6.93 ++#endif 
    6.94   
    6.95   #ifdef CONFIG_SMP
    6.96   /*
     7.1 --- a/xen/arch/ia64/vmx_init.c	Wed May 18 21:19:06 2005 +0000
     7.2 +++ b/xen/arch/ia64/vmx_init.c	Fri May 20 16:43:37 2005 +0000
     7.3 @@ -40,6 +40,7 @@
     7.4  #include <asm/vmmu.h>
     7.5  #include <public/arch-ia64.h>
     7.6  #include <asm/vmx_phy_mode.h>
     7.7 +#include <asm/vmx.h>
     7.8  
     7.9  /* Global flag to identify whether Intel vmx feature is on */
    7.10  u32 vmx_enabled = 0;
    7.11 @@ -122,6 +123,9 @@ vmx_init_env(void)
    7.12  		__vsa_base = tmp_base;
    7.13  	else
    7.14  		ASSERT(tmp_base != __vsa_base);
    7.15 +
    7.16 +	/* Init stub for rr7 switch */
    7.17 +	vmx_init_double_mapping_stub();
    7.18  }
    7.19  
    7.20  typedef union {
    7.21 @@ -184,6 +188,23 @@ vmx_create_vp(struct exec_domain *ed)
    7.22  		panic("ia64_pal_vp_create failed. \n");
    7.23  }
    7.24  
    7.25 +void vmx_init_double_mapping_stub(void)
    7.26 +{
    7.27 +	u64 base, psr;
    7.28 +	extern void vmx_switch_rr7(void);
    7.29 +
    7.30 +	base = (u64) &vmx_switch_rr7;
    7.31 +	base = *((u64*)base);
    7.32 +
    7.33 +	psr = ia64_clear_ic();
    7.34 +	ia64_itr(0x1, IA64_TR_RR7_SWITCH_STUB, XEN_RR7_SWITCH_STUB,
    7.35 +		 pte_val(pfn_pte(__pa(base) >> PAGE_SHIFT, PAGE_KERNEL)),
    7.36 +		 RR7_SWITCH_SHIFT);
    7.37 +	ia64_set_psr(psr);
    7.38 +	ia64_srlz_i();
    7.39 +	printk("Add TR mapping for rr7 switch stub, with physical: 0x%lx\n", (u64)(__pa(base)));
    7.40 +}
    7.41 +
    7.42  /* Other non-context related tasks can be done in context switch */
    7.43  void
    7.44  vmx_save_state(struct exec_domain *ed)
     8.1 --- a/xen/arch/ia64/xensetup.c	Wed May 18 21:19:06 2005 +0000
     8.2 +++ b/xen/arch/ia64/xensetup.c	Fri May 20 16:43:37 2005 +0000
     8.3 @@ -203,12 +203,6 @@ void start_kernel(void)
     8.4      efi_memmap_walk(find_max_pfn, &max_page);
     8.5      printf("find_memory: efi_memmap_walk returns max_page=%lx\n",max_page);
     8.6  
     8.7 -#ifdef CONFIG_VTI
     8.8 -    /* Only support up to 64G physical memory by far */
     8.9 -    if (max_page > (0x1000000000UL / PAGE_SIZE))
    8.10 -	panic("Not suppport memory larger than 16G\n");
    8.11 -#endif // CONFIG_VTI
    8.12 -
    8.13      heap_start = memguard_init(ia64_imva(&_end));
    8.14      printf("Before heap_start: 0x%lx\n", heap_start);
    8.15      heap_start = __va(init_boot_allocator(__pa(heap_start)));
     9.1 --- a/xen/include/asm-ia64/vmx.h	Wed May 18 21:19:06 2005 +0000
     9.2 +++ b/xen/include/asm-ia64/vmx.h	Fri May 20 16:43:37 2005 +0000
     9.3 @@ -22,10 +22,13 @@
     9.4  #ifndef _ASM_IA64_VT_H
     9.5  #define _ASM_IA64_VT_H
     9.6  
     9.7 +#define RR7_SWITCH_SHIFT	12	/* 4k enough */
     9.8 +
     9.9  extern void identify_vmx_feature(void);
    9.10  extern unsigned int vmx_enabled;
    9.11  extern void vmx_init_env(void);
    9.12  extern void vmx_final_setup_domain(struct domain *d);
    9.13 +extern void vmx_init_double_mapping_stub(void);
    9.14  extern void vmx_save_state(struct exec_domain *ed);
    9.15  extern void vmx_load_state(struct exec_domain *ed);
    9.16  extern vmx_insert_double_mapping(u64,u64,u64,u64,u64);
    10.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    10.2 +++ b/xen/include/asm-ia64/xenprocessor.h	Fri May 20 16:43:37 2005 +0000
    10.3 @@ -0,0 +1,213 @@
    10.4 +#ifndef _ASM_IA64_XENPROCESSOR_H
    10.5 +#define _ASM_IA64_XENPROCESSOR_H
    10.6 +/*
    10.7 + * xen specific processor definition
    10.8 + *
    10.9 + * Copyright (C) 2005 Hewlett-Packard Co.
   10.10 + *	Dan Magenheimer (dan.magenheimer@hp.com)
   10.11 + *
   10.12 + * Copyright (C) 2005 Intel Co.
   10.13 + * 	Kun Tian (Kevin Tian) <kevin.tian@intel.com>
   10.14 + *
   10.15 + */
   10.16 +
   10.17 +
   10.18 +#define ia64_is_local_fpu_owner(t) 0
   10.19 +
   10.20 +/* like above but expressed as bitfields for more efficient access: */
   10.21 +struct ia64_psr {
   10.22 +	__u64 reserved0 : 1;
   10.23 +	__u64 be : 1;
   10.24 +	__u64 up : 1;
   10.25 +	__u64 ac : 1;
   10.26 +	__u64 mfl : 1;
   10.27 +	__u64 mfh : 1;
   10.28 +	__u64 reserved1 : 7;
   10.29 +	__u64 ic : 1;
   10.30 +	__u64 i : 1;
   10.31 +	__u64 pk : 1;
   10.32 +	__u64 reserved2 : 1;
   10.33 +	__u64 dt : 1;
   10.34 +	__u64 dfl : 1;
   10.35 +	__u64 dfh : 1;
   10.36 +	__u64 sp : 1;
   10.37 +	__u64 pp : 1;
   10.38 +	__u64 di : 1;
   10.39 +	__u64 si : 1;
   10.40 +	__u64 db : 1;
   10.41 +	__u64 lp : 1;
   10.42 +	__u64 tb : 1;
   10.43 +	__u64 rt : 1;
   10.44 +	__u64 reserved3 : 4;
   10.45 +	__u64 cpl : 2;
   10.46 +	__u64 is : 1;
   10.47 +	__u64 mc : 1;
   10.48 +	__u64 it : 1;
   10.49 +	__u64 id : 1;
   10.50 +	__u64 da : 1;
   10.51 +	__u64 dd : 1;
   10.52 +	__u64 ss : 1;
   10.53 +	__u64 ri : 2;
   10.54 +	__u64 ed : 1;
   10.55 +	__u64 bn : 1;
   10.56 +#ifdef CONFIG_VTI
   10.57 +	__u64 ia : 1;
   10.58 +	__u64 vm : 1;
   10.59 +	__u64 reserved5 : 17;
   10.60 +#else // CONFIG_VTI
   10.61 +	__u64 reserved4 : 19;
   10.62 +#endif // CONFIG_VTI
   10.63 +};
   10.64 +
   10.65 +#ifdef  CONFIG_VTI
   10.66 +/* vmx like above but expressed as bitfields for more efficient access: */
   10.67 +typedef  union{
   10.68 +    __u64 val;
   10.69 +    struct{
   10.70 +    	__u64 reserved0 : 1;
   10.71 +	__u64 be : 1;
   10.72 +    	__u64 up : 1;
   10.73 +    	__u64 ac : 1;
   10.74 +    	__u64 mfl : 1;
   10.75 +    	__u64 mfh : 1;
   10.76 +    	__u64 reserved1 : 7;
   10.77 +    	__u64 ic : 1;
   10.78 +    	__u64 i : 1;
   10.79 +    	__u64 pk : 1;
   10.80 +    	__u64 reserved2 : 1;
   10.81 +    	__u64 dt : 1;
   10.82 +    	__u64 dfl : 1;
   10.83 +    	__u64 dfh : 1;
   10.84 +    	__u64 sp : 1;
   10.85 +    	__u64 pp : 1;
   10.86 +    	__u64 di : 1;
   10.87 +	__u64 si : 1;
   10.88 +    	__u64 db : 1;
   10.89 +    	__u64 lp : 1;
   10.90 +    	__u64 tb : 1;
   10.91 +    	__u64 rt : 1;
   10.92 +    	__u64 reserved3 : 4;
   10.93 +    	__u64 cpl : 2;
   10.94 +    	__u64 is : 1;
   10.95 +    	__u64 mc : 1;
   10.96 +    	__u64 it : 1;
   10.97 +    	__u64 id : 1;
   10.98 +    	__u64 da : 1;
   10.99 +    	__u64 dd : 1;
  10.100 +    	__u64 ss : 1;
  10.101 +    	__u64 ri : 2;
  10.102 +    	__u64 ed : 1;
  10.103 +    	__u64 bn : 1;
  10.104 +    	__u64 reserved4 : 19;
  10.105 +    };
  10.106 +}   IA64_PSR;
  10.107 +
  10.108 +typedef union {
  10.109 +    __u64 val;
  10.110 +    struct {
  10.111 +        __u64 code : 16;
  10.112 +        __u64 vector : 8;
  10.113 +        __u64 reserved1 : 8;
  10.114 +        __u64 x : 1;
  10.115 +        __u64 w : 1;
  10.116 +        __u64 r : 1;
  10.117 +        __u64 na : 1;
  10.118 +        __u64 sp : 1;
  10.119 +        __u64 rs : 1;
  10.120 +        __u64 ir : 1;
  10.121 +        __u64 ni : 1;
  10.122 +        __u64 so : 1;
  10.123 +        __u64 ei : 2;
  10.124 +        __u64 ed : 1;
  10.125 +        __u64 reserved2 : 20;
  10.126 +    };
  10.127 +}   ISR;
  10.128 +
  10.129 +
  10.130 +typedef union {
  10.131 +    __u64 val;
  10.132 +    struct {
  10.133 +        __u64 ve : 1;
  10.134 +        __u64 reserved0 : 1;
  10.135 +        __u64 size : 6;
  10.136 +        __u64 vf : 1;
  10.137 +        __u64 reserved1 : 6;
  10.138 +        __u64 base : 49;
  10.139 +    };
  10.140 +}   PTA;
  10.141 +
  10.142 +typedef union {
  10.143 +    __u64 val;
  10.144 +    struct {
  10.145 +        __u64  rv  : 16;
  10.146 +        __u64  eid : 8;
  10.147 +        __u64  id  : 8;
  10.148 +        __u64  ig  : 32;
  10.149 +    };
  10.150 +} LID;
  10.151 +
  10.152 +typedef union{
  10.153 +    __u64 val;
  10.154 +    struct {
  10.155 +        __u64 rv  : 3;
  10.156 +        __u64 ir  : 1;
  10.157 +        __u64 eid : 8;
  10.158 +        __u64 id  : 8;
  10.159 +        __u64 ib_base : 44;
  10.160 +    };
  10.161 +} ipi_a_t;
  10.162 +
  10.163 +typedef union{
  10.164 +    __u64 val;
  10.165 +    struct {
  10.166 +        __u64 vector : 8;
  10.167 +        __u64 dm  : 3;
  10.168 +        __u64 ig  : 53;
  10.169 +    };
  10.170 +} ipi_d_t;
  10.171 +
  10.172 +
  10.173 +#define IA64_ISR_CODE_MASK0     0xf
  10.174 +#define IA64_UNIMPL_DADDR_FAULT     0x30
  10.175 +#define IA64_UNIMPL_IADDR_TRAP      0x10
  10.176 +#define IA64_RESERVED_REG_FAULT     0x30
  10.177 +#define IA64_REG_NAT_CONSUMPTION_FAULT  0x10
  10.178 +#define IA64_NAT_CONSUMPTION_FAULT  0x20
  10.179 +#define IA64_PRIV_OP_FAULT      0x10
  10.180 +
  10.181 +/* indirect register type */
  10.182 +enum {
  10.183 +    IA64_CPUID,     /*  cpuid */
  10.184 +    IA64_DBR,       /*  dbr */
  10.185 +    IA64_IBR,       /*  ibr */
  10.186 +    IA64_PKR,       /*  pkr */
  10.187 +    IA64_PMC,       /*  pmc */
  10.188 +    IA64_PMD,       /*  pmd */
  10.189 +    IA64_RR         /*  rr */
  10.190 +};
  10.191 +
  10.192 +/* instruction type */
  10.193 +enum {
  10.194 +    IA64_INST_TPA=1,
  10.195 +    IA64_INST_TAK
  10.196 +};
  10.197 +
  10.198 +/* Generate Mask
  10.199 + * Parameter:
  10.200 + *  bit -- starting bit
  10.201 + *  len -- how many bits
  10.202 + */
  10.203 +#define MASK(bit,len)                   \
  10.204 +({                              \
  10.205 +        __u64    ret;                    \
  10.206 +                                \
  10.207 +        __asm __volatile("dep %0=-1, r0, %1, %2"    \
  10.208 +                : "=r" (ret):                   \
  10.209 +          "M" (bit),                    \
  10.210 +          "M" (len) );                  \
  10.211 +        ret;                            \
  10.212 +})
  10.213 +
  10.214 +#endif  //  CONFIG_VTI
  10.215 +
  10.216 +#endif // _ASM_IA64_XENPROCESSOR_H
    11.1 --- /dev/null	Thu Jan 01 00:00:00 1970 +0000
    11.2 +++ b/xen/include/asm-ia64/xensystem.h	Fri May 20 16:43:37 2005 +0000
    11.3 @@ -0,0 +1,63 @@
    11.4 +#ifndef _ASM_IA64_XENSYSTEM_H
    11.5 +#define _ASM_IA64_XENSYSTEM_H
    11.6 +/*
    11.7 + * xen specific context definition
    11.8 + *
    11.9 + * Copyright (C) 2005 Hewlett-Packard Co.
   11.10 + *	Dan Magenheimer (dan.magenheimer@hp.com)
   11.11 + *
   11.12 + * Copyright (C) 2005 Intel Co.
   11.13 + * 	Kun Tian (Kevin Tian) <kevin.tian@intel.com>
   11.14 + *
   11.15 + */
   11.16 +#include <asm/config.h>
   11.17 +#include <linux/kernel.h>
   11.18 +
   11.19 +/* Define HV space hierarchy */
   11.20 +#ifdef CONFIG_VTI
   11.21 +#define XEN_VIRT_SPACE_LOW	 0xe800000000000000
   11.22 +#define XEN_VIRT_SPACE_HIGH	 0xf800000000000000	
   11.23 +/* This is address to mapping rr7 switch stub, in region 5 */
   11.24 +#define XEN_RR7_SWITCH_STUB	 0xb700000000000000
   11.25 +#endif // CONFIG_VTI
   11.26 +
   11.27 +#define KERNEL_START		 0xf000000004000000
   11.28 +#define PERCPU_ADDR		 0xf100000000000000-PERCPU_PAGE_SIZE
   11.29 +#define SHAREDINFO_ADDR		 0xf100000000000000
   11.30 +#define VHPT_ADDR		 0xf200000000000000
   11.31 +
   11.32 +#ifndef __ASSEMBLY__
   11.33 +
   11.34 +#define IA64_HAS_EXTRA_STATE(t) 0
   11.35 +
   11.36 +#ifdef CONFIG_VTI
   11.37 +extern struct task_struct *vmx_ia64_switch_to (void *next_task);
   11.38 +#define __switch_to(prev,next,last) do {	\
   11.39 +       if (VMX_DOMAIN(prev))                   \
   11.40 +               vmx_save_state(prev);           \
   11.41 +       else {                                  \
   11.42 +               if (IA64_HAS_EXTRA_STATE(prev)) \
   11.43 +                       ia64_save_extra(prev);  \
   11.44 +       }                                       \
   11.45 +       if (VMX_DOMAIN(next))                   \
   11.46 +               vmx_load_state(next);           \
   11.47 +       else {                                  \
   11.48 +               if (IA64_HAS_EXTRA_STATE(next)) \
   11.49 +                       ia64_save_extra(next);  \
   11.50 +       }                                       \
   11.51 +       ia64_psr(ia64_task_regs(next))->dfh = !ia64_is_local_fpu_owner(next); \
   11.52 +       (last) = vmx_ia64_switch_to((next));        \
   11.53 +} while (0)
   11.54 +#else // CONFIG_VTI
   11.55 +#define __switch_to(prev,next,last) do {							 \
   11.56 +	if (IA64_HAS_EXTRA_STATE(prev))								 \
   11.57 +		ia64_save_extra(prev);								 \
   11.58 +	if (IA64_HAS_EXTRA_STATE(next))								 \
   11.59 +		ia64_load_extra(next);								 \
   11.60 +	ia64_psr(ia64_task_regs(next))->dfh = !ia64_is_local_fpu_owner(next);			 \
   11.61 +	(last) = ia64_switch_to((next));							 \
   11.62 +} while (0)
   11.63 +#endif // CONFIG_VTI
   11.64 +
   11.65 +#endif // __ASSEMBLY__
   11.66 +#endif // _ASM_IA64_XENSYSTEM_H