1.1 --- a/xen/arch/x86/hvm/svm/svm.c	Thu Jun 21 15:10:04 2007 +0100
     1.2 +++ b/xen/arch/x86/hvm/svm/svm.c	Thu Jun 21 15:17:31 2007 +0100
     1.3 @@ -2086,9 +2086,11 @@ static inline void svm_do_msr_access(
     1.4          case MSR_IA32_TIME_STAMP_COUNTER:
     1.5              msr_content = hvm_get_guest_time(v);
     1.6              break;
     1.7 +
     1.8          case MSR_IA32_APICBASE:
     1.9              msr_content = vcpu_vlapic(v)->hw.apic_base_msr;
    1.10              break;
    1.11 +
    1.12          case MSR_EFER:
    1.13              msr_content = v->arch.hvm_svm.cpu_shadow_efer;
    1.14              break;
    1.15 @@ -2110,6 +2112,10 @@ static inline void svm_do_msr_access(
    1.16              msr_content = 0;
    1.17              break;
    1.18  
    1.19 +        case MSR_K8_VM_HSAVE_PA:
    1.20 +            svm_inject_exception(v, TRAP_gp_fault, 1, 0);
    1.21 +            break;
    1.22 +
    1.23          default:
    1.24              if ( rdmsr_hypervisor_regs(ecx, &eax, &edx) ||
    1.25                   rdmsr_safe(ecx, eax, edx) == 0 )
    1.26 @@ -2143,9 +2149,15 @@ static inline void svm_do_msr_access(
    1.27              hvm_set_guest_time(v, msr_content);
    1.28              pt_reset(v);
    1.29              break;
    1.30 +
    1.31          case MSR_IA32_APICBASE:
    1.32              vlapic_msr_set(vcpu_vlapic(v), msr_content);
    1.33              break;
    1.34 +
    1.35 +        case MSR_K8_VM_HSAVE_PA:
    1.36 +            svm_inject_exception(v, TRAP_gp_fault, 1, 0);
    1.37 +            break;
    1.38 +
    1.39          default:
    1.40              if ( !long_mode_do_msr_write(regs) )
    1.41                  wrmsr_hypervisor_regs(ecx, regs->eax, regs->edx);