ia64/xen-unstable

changeset 19430:0477f9061c8a

x86: Build fixes and cleanups after Intel MCA changes.

Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Mar 20 17:42:46 2009 +0000 (2009-03-20)
parents 891af2c54155
children 0b13d9787622
files xen/arch/x86/cpu/mcheck/mce_intel.c xen/arch/x86/traps.c
line diff
     1.1 --- a/xen/arch/x86/cpu/mcheck/mce_intel.c	Fri Mar 20 17:25:29 2009 +0000
     1.2 +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c	Fri Mar 20 17:42:46 2009 +0000
     1.3 @@ -256,7 +256,7 @@ static int fill_vmsr_data(int cpu, struc
     1.4          d->arch.vmca_msrs.nr_injection++;
     1.5  
     1.6          printk(KERN_DEBUG "MCE: Found error @[CPU%d BANK%d "
     1.7 -                "status %lx addr %lx domid %d]\n ",
     1.8 +                "status %"PRIx64" addr %"PRIx64" domid %d]\n ",
     1.9                  entry->cpu, mc_bank->mc_bank,
    1.10                  mc_bank->mc_status, mc_bank->mc_addr, mc_bank->mc_domid);
    1.11      }
    1.12 @@ -292,7 +292,7 @@ static int mce_actions(void) {
    1.13          if (mic == NULL) {
    1.14              printk(KERN_ERR "MCE: get local buffer entry failed\n ");
    1.15              ret = -1;
    1.16 -       	    goto end;
    1.17 +            goto end;
    1.18          }
    1.19  
    1.20          mc_global = (struct mcinfo_global *)mic;
    1.21 @@ -819,94 +819,97 @@ int intel_mce_wrmsr(u32 msr, u32 lo, u32
    1.22      struct domain *d = current->domain;
    1.23      struct bank_entry *entry = NULL;
    1.24      uint64_t value = (u64)hi << 32 | lo;
    1.25 -    int ret = 0;
    1.26 +    int ret = 1;
    1.27  
    1.28      spin_lock(&mce_locks);
    1.29      switch(msr)
    1.30      {
    1.31 -        case MSR_IA32_MCG_CTL:
    1.32 -            if (value != (u64)~0x0 && value != 0x0) {
    1.33 -                printk(KERN_ERR "MCE: value writen to MCG_CTL"
    1.34 -                    "should be all 0s or 1s\n");
    1.35 -                ret = -1;
    1.36 -                break;
    1.37 -            }
    1.38 -            if (!d || is_idle_domain(d)) {
    1.39 -                printk(KERN_ERR "MCE: wrmsr not in DOM context, skip\n");
    1.40 -                break;
    1.41 -            }
    1.42 -            d->arch.vmca_msrs.mcg_ctl = value;
    1.43 -            break;
    1.44 -        case MSR_IA32_MCG_STATUS:
    1.45 -            if (!d || is_idle_domain(d)) {
    1.46 -                printk(KERN_ERR "MCE: wrmsr not in DOM context, skip\n");
    1.47 -                break;
    1.48 -            }
    1.49 -            d->arch.vmca_msrs.mcg_status = value;
    1.50 -            printk(KERN_DEBUG "MCE: wrmsr MCG_CTL %lx\n", value);
    1.51 -            break;
    1.52 -        case MSR_IA32_MC0_CTL2:
    1.53 -        case MSR_IA32_MC1_CTL2:
    1.54 -        case MSR_IA32_MC2_CTL2:
    1.55 -        case MSR_IA32_MC3_CTL2:
    1.56 -        case MSR_IA32_MC4_CTL2:
    1.57 -        case MSR_IA32_MC5_CTL2:
    1.58 -        case MSR_IA32_MC6_CTL2:
    1.59 -        case MSR_IA32_MC7_CTL2:
    1.60 -        case MSR_IA32_MC8_CTL2:
    1.61 -            printk(KERN_ERR "We have disabled CMCI capability, "
    1.62 -                    "Guest should not write this MSR!\n");
    1.63 +    case MSR_IA32_MCG_CTL:
    1.64 +        if (value != (u64)~0x0 && value != 0x0) {
    1.65 +            gdprintk(XENLOG_WARNING, "MCE: value writen to MCG_CTL"
    1.66 +                     "should be all 0s or 1s\n");
    1.67 +            ret = -1;
    1.68              break;
    1.69 -        case MSR_IA32_MC0_CTL:
    1.70 -        case MSR_IA32_MC1_CTL:
    1.71 -        case MSR_IA32_MC2_CTL:
    1.72 -        case MSR_IA32_MC3_CTL:
    1.73 -        case MSR_IA32_MC4_CTL:
    1.74 -        case MSR_IA32_MC5_CTL:
    1.75 -        case MSR_IA32_MC6_CTL:
    1.76 -        case MSR_IA32_MC7_CTL:
    1.77 -        case MSR_IA32_MC8_CTL:
    1.78 -            if (value != (u64)~0x0 && value != 0x0) {
    1.79 -                printk(KERN_ERR "MCE: value writen to MCi_CTL"
    1.80 -                    "should be all 0s or 1s\n");
    1.81 -                ret = -1;
    1.82 -                break;
    1.83 -            }
    1.84 -            if (!d || is_idle_domain(d)) {
    1.85 -                printk(KERN_ERR "MCE: wrmsr not in DOM context, skip\n");
    1.86 -                break;
    1.87 -            }
    1.88 -            d->arch.vmca_msrs.mci_ctl[(msr - MSR_IA32_MC0_CTL)/4] = value;
    1.89 +        }
    1.90 +        if (!d || is_idle_domain(d)) {
    1.91 +            gdprintk(XENLOG_WARNING, "MCE: wrmsr not in DOM context, skip\n");
    1.92              break;
    1.93 -        case MSR_IA32_MC0_STATUS:
    1.94 -        case MSR_IA32_MC1_STATUS:
    1.95 -        case MSR_IA32_MC2_STATUS:
    1.96 -        case MSR_IA32_MC3_STATUS:
    1.97 -        case MSR_IA32_MC4_STATUS:
    1.98 -        case MSR_IA32_MC5_STATUS:
    1.99 -        case MSR_IA32_MC6_STATUS:
   1.100 -        case MSR_IA32_MC7_STATUS:
   1.101 -        case MSR_IA32_MC8_STATUS:
   1.102 -            if (!d || is_idle_domain(d)) {
   1.103 -                /* Just skip */
   1.104 -                printk(KERN_ERR "mce wrmsr: not in domain context!\n");
   1.105 -                break;
   1.106 +        }
   1.107 +        d->arch.vmca_msrs.mcg_ctl = value;
   1.108 +        break;
   1.109 +    case MSR_IA32_MCG_STATUS:
   1.110 +        if (!d || is_idle_domain(d)) {
   1.111 +            gdprintk(XENLOG_WARNING, "MCE: wrmsr not in DOM context, skip\n");
   1.112 +            break;
   1.113 +        }
   1.114 +        d->arch.vmca_msrs.mcg_status = value;
   1.115 +        gdprintk(XENLOG_DEBUG, "MCE: wrmsr MCG_CTL %"PRIx64"\n", value);
   1.116 +        break;
   1.117 +    case MSR_IA32_MC0_CTL2:
   1.118 +    case MSR_IA32_MC1_CTL2:
   1.119 +    case MSR_IA32_MC2_CTL2:
   1.120 +    case MSR_IA32_MC3_CTL2:
   1.121 +    case MSR_IA32_MC4_CTL2:
   1.122 +    case MSR_IA32_MC5_CTL2:
   1.123 +    case MSR_IA32_MC6_CTL2:
   1.124 +    case MSR_IA32_MC7_CTL2:
   1.125 +    case MSR_IA32_MC8_CTL2:
   1.126 +        gdprintk(XENLOG_WARNING, "We have disabled CMCI capability, "
   1.127 +                 "Guest should not write this MSR!\n");
   1.128 +        break;
   1.129 +    case MSR_IA32_MC0_CTL:
   1.130 +    case MSR_IA32_MC1_CTL:
   1.131 +    case MSR_IA32_MC2_CTL:
   1.132 +    case MSR_IA32_MC3_CTL:
   1.133 +    case MSR_IA32_MC4_CTL:
   1.134 +    case MSR_IA32_MC5_CTL:
   1.135 +    case MSR_IA32_MC6_CTL:
   1.136 +    case MSR_IA32_MC7_CTL:
   1.137 +    case MSR_IA32_MC8_CTL:
   1.138 +        if (value != (u64)~0x0 && value != 0x0) {
   1.139 +            gdprintk(XENLOG_WARNING, "MCE: value writen to MCi_CTL"
   1.140 +                     "should be all 0s or 1s\n");
   1.141 +            ret = -1;
   1.142 +            break;
   1.143 +        }
   1.144 +        if (!d || is_idle_domain(d)) {
   1.145 +            gdprintk(XENLOG_WARNING, "MCE: wrmsr not in DOM context, skip\n");
   1.146 +            break;
   1.147 +        }
   1.148 +        d->arch.vmca_msrs.mci_ctl[(msr - MSR_IA32_MC0_CTL)/4] = value;
   1.149 +        break;
   1.150 +    case MSR_IA32_MC0_STATUS:
   1.151 +    case MSR_IA32_MC1_STATUS:
   1.152 +    case MSR_IA32_MC2_STATUS:
   1.153 +    case MSR_IA32_MC3_STATUS:
   1.154 +    case MSR_IA32_MC4_STATUS:
   1.155 +    case MSR_IA32_MC5_STATUS:
   1.156 +    case MSR_IA32_MC6_STATUS:
   1.157 +    case MSR_IA32_MC7_STATUS:
   1.158 +    case MSR_IA32_MC8_STATUS:
   1.159 +        if (!d || is_idle_domain(d)) {
   1.160 +            /* Just skip */
   1.161 +            gdprintk(XENLOG_WARNING, "mce wrmsr: not in domain context!\n");
   1.162 +            break;
   1.163 +        }
   1.164 +        /* Give the first entry of the list, it corresponds to current
   1.165 +         * vMCE# injection. When vMCE# is finished processing by the
   1.166 +         * the guest, this node will be deleted.
   1.167 +         * Only error bank is written. Non-error bank simply return.
   1.168 +         */
   1.169 +        if ( !list_empty(&d->arch.vmca_msrs.impact_header) ) {
   1.170 +            entry = list_entry(d->arch.vmca_msrs.impact_header.next,
   1.171 +                               struct bank_entry, list);
   1.172 +            if ( entry->bank == (msr - MSR_IA32_MC0_STATUS)/4 ) {
   1.173 +                entry->mci_status = value;
   1.174              }
   1.175 -            /* Give the first entry of the list, it corresponds to current
   1.176 -             * vMCE# injection. When vMCE# is finished processing by the
   1.177 -             * the guest, this node will be deleted.
   1.178 -             * Only error bank is written. Non-error bank simply return.
   1.179 -             */
   1.180 -            if ( !list_empty(&d->arch.vmca_msrs.impact_header) ) {
   1.181 -                entry = list_entry(d->arch.vmca_msrs.impact_header.next,
   1.182 -                    struct bank_entry, list);
   1.183 -                if ( entry->bank == (msr - MSR_IA32_MC0_STATUS)/4 ) {
   1.184 -                    entry->mci_status = value;
   1.185 -                }
   1.186 -                printk(KERN_DEBUG "MCE: wmrsr mci_status in vMCE# context\n");
   1.187 -            }
   1.188 -            printk(KERN_DEBUG "MCE: wrmsr mci_status val:%lx\n", value);
   1.189 -            break;
   1.190 +            gdprintk(XENLOG_DEBUG, "MCE: wmrsr mci_status in vMCE# context\n");
   1.191 +        }
   1.192 +        gdprintk(XENLOG_DEBUG, "MCE: wrmsr mci_status val:%"PRIx64"\n", value);
   1.193 +        break;
   1.194 +    default:
   1.195 +        ret = 0;
   1.196 +        break;
   1.197      }
   1.198      spin_unlock(&mce_locks);
   1.199      return ret;
   1.200 @@ -915,154 +918,155 @@ int intel_mce_wrmsr(u32 msr, u32 lo, u32
   1.201  int intel_mce_rdmsr(u32 msr, u32 *lo, u32 *hi)
   1.202  {
   1.203      struct domain *d = current->domain;
   1.204 -    int ret = 0;
   1.205 +    int ret = 1;
   1.206      struct bank_entry *entry = NULL;
   1.207  
   1.208      *lo = *hi = 0x0;
   1.209      spin_lock(&mce_locks);
   1.210      switch(msr)
   1.211      {
   1.212 -        case MSR_IA32_MCG_STATUS:
   1.213 -            if (!d || is_idle_domain(d)) {
   1.214 -                printk(KERN_ERR "MCE: rdmsr not in domain context!\n");
   1.215 -                *lo = *hi = 0x0;
   1.216 -                break;
   1.217 -            }
   1.218 -            *lo = (u32)d->arch.vmca_msrs.mcg_status;
   1.219 -            *hi = (u32)(d->arch.vmca_msrs.mcg_status >> 32);
   1.220 -            printk(KERN_DEBUG "MCE: rd MCG_STATUS lo %x hi %x\n", *lo, *hi);
   1.221 -            break;
   1.222 -        case MSR_IA32_MCG_CAP:
   1.223 -            if (!d || is_idle_domain(d)) {
   1.224 -                printk(KERN_ERR "MCE: rdmsr not in domain context!\n");
   1.225 -                *lo = *hi = 0x0;
   1.226 -                break;
   1.227 -            }
   1.228 -            *lo = (u32)d->arch.vmca_msrs.mcg_cap;
   1.229 -            *hi = (u32)(d->arch.vmca_msrs.mcg_cap >> 32);
   1.230 -            printk(KERN_DEBUG "MCE: rdmsr MCG_CAP lo %x hi %x\n", *lo, *hi);
   1.231 -            break;
   1.232 -        case MSR_IA32_MCG_CTL:
   1.233 -            if (!d || is_idle_domain(d)) {
   1.234 -                printk(KERN_ERR "MCE: rdmsr not in domain context!\n");
   1.235 -                *lo = *hi = 0x0;
   1.236 -                break;
   1.237 -            }
   1.238 -            *lo = (u32)d->arch.vmca_msrs.mcg_ctl;
   1.239 -            *hi = (u32)(d->arch.vmca_msrs.mcg_ctl >> 32);
   1.240 -            printk(KERN_DEBUG "MCE: rdmsr MCG_CTL lo %x hi %x\n", *lo, *hi);
   1.241 -            break;
   1.242 -        case MSR_IA32_MC0_CTL2:
   1.243 -        case MSR_IA32_MC1_CTL2:
   1.244 -        case MSR_IA32_MC2_CTL2:
   1.245 -        case MSR_IA32_MC3_CTL2:
   1.246 -        case MSR_IA32_MC4_CTL2:
   1.247 -        case MSR_IA32_MC5_CTL2:
   1.248 -        case MSR_IA32_MC6_CTL2:
   1.249 -        case MSR_IA32_MC7_CTL2:
   1.250 -        case MSR_IA32_MC8_CTL2:
   1.251 -            printk(KERN_WARNING "We have disabled CMCI capability, "
   1.252 -                    "Guest should not read this MSR!\n");
   1.253 -            break;
   1.254 -        case MSR_IA32_MC0_CTL:
   1.255 -        case MSR_IA32_MC1_CTL:
   1.256 -        case MSR_IA32_MC2_CTL:
   1.257 -        case MSR_IA32_MC3_CTL:
   1.258 -        case MSR_IA32_MC4_CTL:
   1.259 -        case MSR_IA32_MC5_CTL:
   1.260 -        case MSR_IA32_MC6_CTL:
   1.261 -        case MSR_IA32_MC7_CTL:
   1.262 -        case MSR_IA32_MC8_CTL:
   1.263 -            if (!d || is_idle_domain(d)) {
   1.264 -                printk(KERN_ERR "MCE: rdmsr not in domain context!\n");
   1.265 -                *lo = *hi = 0x0;
   1.266 -                break;
   1.267 -            }
   1.268 -            *lo = (u32)d->arch.vmca_msrs.mci_ctl[(msr - MSR_IA32_MC0_CTL)/4];
   1.269 -            *hi =
   1.270 -                (u32)(d->arch.vmca_msrs.mci_ctl[(msr - MSR_IA32_MC0_CTL)/4]
   1.271 -                    >> 32);
   1.272 -            printk(KERN_DEBUG "MCE: rdmsr MCi_CTL lo %x hi %x\n", *lo, *hi);
   1.273 +    case MSR_IA32_MCG_STATUS:
   1.274 +        if (!d || is_idle_domain(d)) {
   1.275 +            gdprintk(XENLOG_WARNING, "MCE: rdmsr not in domain context!\n");
   1.276 +            *lo = *hi = 0x0;
   1.277              break;
   1.278 -        case MSR_IA32_MC0_STATUS:
   1.279 -        case MSR_IA32_MC1_STATUS:
   1.280 -        case MSR_IA32_MC2_STATUS:
   1.281 -        case MSR_IA32_MC3_STATUS:
   1.282 -        case MSR_IA32_MC4_STATUS:
   1.283 -        case MSR_IA32_MC5_STATUS:
   1.284 -        case MSR_IA32_MC6_STATUS:
   1.285 -        case MSR_IA32_MC7_STATUS:
   1.286 -        case MSR_IA32_MC8_STATUS:
   1.287 -            /* Only error bank is read. Non-error bank simply return */
   1.288 -            *lo = *hi = 0x0;
   1.289 -            printk(KERN_DEBUG "MCE: rdmsr mci_status\n");
   1.290 -            if (!d || is_idle_domain(d)) {
   1.291 -                printk(KERN_ERR "mce_rdmsr: not in domain context!\n");
   1.292 -                break;
   1.293 -            }
   1.294 -            if (!list_empty(&d->arch.vmca_msrs.impact_header)) {
   1.295 -                entry = list_entry(d->arch.vmca_msrs.impact_header.next,
   1.296 -                    struct bank_entry, list);
   1.297 -                if ( entry->bank == (msr - MSR_IA32_MC0_STATUS)/4 ) {
   1.298 -                    *lo = entry->mci_status;
   1.299 -                    *hi = entry->mci_status >> 32;
   1.300 -                    printk(KERN_DEBUG "MCE: rdmsr MCi_STATUS in vmCE# context "
   1.301 -                        "lo %x hi %x\n", *lo, *hi);
   1.302 -                }
   1.303 -            }
   1.304 -            break;
   1.305 -        case MSR_IA32_MC0_ADDR:
   1.306 -        case MSR_IA32_MC1_ADDR:
   1.307 -        case MSR_IA32_MC2_ADDR:
   1.308 -        case MSR_IA32_MC3_ADDR:
   1.309 -        case MSR_IA32_MC4_ADDR:
   1.310 -        case MSR_IA32_MC5_ADDR:
   1.311 -        case MSR_IA32_MC6_ADDR:
   1.312 -        case MSR_IA32_MC7_ADDR:
   1.313 -        case MSR_IA32_MC8_ADDR:
   1.314 +        }
   1.315 +        *lo = (u32)d->arch.vmca_msrs.mcg_status;
   1.316 +        *hi = (u32)(d->arch.vmca_msrs.mcg_status >> 32);
   1.317 +        gdprintk(XENLOG_DEBUG, "MCE: rd MCG_STATUS lo %x hi %x\n", *lo, *hi);
   1.318 +        break;
   1.319 +    case MSR_IA32_MCG_CAP:
   1.320 +        if (!d || is_idle_domain(d)) {
   1.321 +            gdprintk(XENLOG_WARNING, "MCE: rdmsr not in domain context!\n");
   1.322              *lo = *hi = 0x0;
   1.323 -            if (!d || is_idle_domain(d)) {
   1.324 -                printk(KERN_ERR "mce_rdmsr: not in domain context!\n");
   1.325 -                break;
   1.326 -            }
   1.327 -            if (!list_empty(&d->arch.vmca_msrs.impact_header)) {
   1.328 -                entry = list_entry(d->arch.vmca_msrs.impact_header.next,
   1.329 -                    struct bank_entry, list);
   1.330 -                if ( entry->bank == (msr - MSR_IA32_MC0_ADDR)/4 ) {
   1.331 -                    *lo = entry->mci_addr;
   1.332 -                    *hi = entry->mci_addr >> 32;
   1.333 -                    printk(KERN_DEBUG "MCE: rdmsr MCi_ADDR in vMCE# context "
   1.334 -                        "lo %x hi %x\n", *lo, *hi);
   1.335 -                }
   1.336 -            }
   1.337              break;
   1.338 -        case MSR_IA32_MC0_MISC:
   1.339 -        case MSR_IA32_MC1_MISC:
   1.340 -        case MSR_IA32_MC2_MISC:
   1.341 -        case MSR_IA32_MC3_MISC:
   1.342 -        case MSR_IA32_MC4_MISC:
   1.343 -        case MSR_IA32_MC5_MISC:
   1.344 -        case MSR_IA32_MC6_MISC:
   1.345 -        case MSR_IA32_MC7_MISC:
   1.346 -        case MSR_IA32_MC8_MISC:
   1.347 +        }
   1.348 +        *lo = (u32)d->arch.vmca_msrs.mcg_cap;
   1.349 +        *hi = (u32)(d->arch.vmca_msrs.mcg_cap >> 32);
   1.350 +        gdprintk(XENLOG_DEBUG, "MCE: rdmsr MCG_CAP lo %x hi %x\n", *lo, *hi);
   1.351 +        break;
   1.352 +    case MSR_IA32_MCG_CTL:
   1.353 +        if (!d || is_idle_domain(d)) {
   1.354 +            gdprintk(XENLOG_WARNING, "MCE: rdmsr not in domain context!\n");
   1.355              *lo = *hi = 0x0;
   1.356 -            if (!d || is_idle_domain(d)) {
   1.357 -                printk(KERN_ERR "MCE: rdmsr not in domain context!\n");
   1.358 -                break;
   1.359 +            break;
   1.360 +        }
   1.361 +        *lo = (u32)d->arch.vmca_msrs.mcg_ctl;
   1.362 +        *hi = (u32)(d->arch.vmca_msrs.mcg_ctl >> 32);
   1.363 +        gdprintk(XENLOG_DEBUG, "MCE: rdmsr MCG_CTL lo %x hi %x\n", *lo, *hi);
   1.364 +        break;
   1.365 +    case MSR_IA32_MC0_CTL2:
   1.366 +    case MSR_IA32_MC1_CTL2:
   1.367 +    case MSR_IA32_MC2_CTL2:
   1.368 +    case MSR_IA32_MC3_CTL2:
   1.369 +    case MSR_IA32_MC4_CTL2:
   1.370 +    case MSR_IA32_MC5_CTL2:
   1.371 +    case MSR_IA32_MC6_CTL2:
   1.372 +    case MSR_IA32_MC7_CTL2:
   1.373 +    case MSR_IA32_MC8_CTL2:
   1.374 +        gdprintk(XENLOG_WARNING, "We have disabled CMCI capability, "
   1.375 +                 "Guest should not read this MSR!\n");
   1.376 +        break;
   1.377 +    case MSR_IA32_MC0_CTL:
   1.378 +    case MSR_IA32_MC1_CTL:
   1.379 +    case MSR_IA32_MC2_CTL:
   1.380 +    case MSR_IA32_MC3_CTL:
   1.381 +    case MSR_IA32_MC4_CTL:
   1.382 +    case MSR_IA32_MC5_CTL:
   1.383 +    case MSR_IA32_MC6_CTL:
   1.384 +    case MSR_IA32_MC7_CTL:
   1.385 +    case MSR_IA32_MC8_CTL:
   1.386 +        if (!d || is_idle_domain(d)) {
   1.387 +            gdprintk(XENLOG_WARNING, "MCE: rdmsr not in domain context!\n");
   1.388 +            *lo = *hi = 0x0;
   1.389 +            break;
   1.390 +        }
   1.391 +        *lo = (u32)d->arch.vmca_msrs.mci_ctl[(msr - MSR_IA32_MC0_CTL)/4];
   1.392 +        *hi =
   1.393 +            (u32)(d->arch.vmca_msrs.mci_ctl[(msr - MSR_IA32_MC0_CTL)/4]
   1.394 +                  >> 32);
   1.395 +        gdprintk(XENLOG_DEBUG, "MCE: rdmsr MCi_CTL lo %x hi %x\n", *lo, *hi);
   1.396 +        break;
   1.397 +    case MSR_IA32_MC0_STATUS:
   1.398 +    case MSR_IA32_MC1_STATUS:
   1.399 +    case MSR_IA32_MC2_STATUS:
   1.400 +    case MSR_IA32_MC3_STATUS:
   1.401 +    case MSR_IA32_MC4_STATUS:
   1.402 +    case MSR_IA32_MC5_STATUS:
   1.403 +    case MSR_IA32_MC6_STATUS:
   1.404 +    case MSR_IA32_MC7_STATUS:
   1.405 +    case MSR_IA32_MC8_STATUS:
   1.406 +        /* Only error bank is read. Non-error bank simply return */
   1.407 +        *lo = *hi = 0x0;
   1.408 +        gdprintk(XENLOG_DEBUG, "MCE: rdmsr mci_status\n");
   1.409 +        if (!d || is_idle_domain(d)) {
   1.410 +            gdprintk(XENLOG_WARNING, "mce_rdmsr: not in domain context!\n");
   1.411 +            break;
   1.412 +        }
   1.413 +        if (!list_empty(&d->arch.vmca_msrs.impact_header)) {
   1.414 +            entry = list_entry(d->arch.vmca_msrs.impact_header.next,
   1.415 +                               struct bank_entry, list);
   1.416 +            if ( entry->bank == (msr - MSR_IA32_MC0_STATUS)/4 ) {
   1.417 +                *lo = entry->mci_status;
   1.418 +                *hi = entry->mci_status >> 32;
   1.419 +                gdprintk(XENLOG_DEBUG, "MCE: rdmsr MCi_STATUS in vmCE# context "
   1.420 +                         "lo %x hi %x\n", *lo, *hi);
   1.421              }
   1.422 -            if (!list_empty(&d->arch.vmca_msrs.impact_header)) {
   1.423 -                entry = list_entry(d->arch.vmca_msrs.impact_header.next,
   1.424 -                    struct bank_entry, list);
   1.425 -                if ( entry->bank == (msr - MSR_IA32_MC0_MISC)/4 ) {
   1.426 -                    *lo = entry->mci_misc;
   1.427 -                    *hi = entry->mci_misc >> 32;
   1.428 -                    printk(KERN_DEBUG "MCE: rdmsr MCi_MISC in vMCE# context "
   1.429 -                        " lo %x hi %x\n", *lo, *hi);
   1.430 -                }
   1.431 +        }
   1.432 +        break;
   1.433 +    case MSR_IA32_MC0_ADDR:
   1.434 +    case MSR_IA32_MC1_ADDR:
   1.435 +    case MSR_IA32_MC2_ADDR:
   1.436 +    case MSR_IA32_MC3_ADDR:
   1.437 +    case MSR_IA32_MC4_ADDR:
   1.438 +    case MSR_IA32_MC5_ADDR:
   1.439 +    case MSR_IA32_MC6_ADDR:
   1.440 +    case MSR_IA32_MC7_ADDR:
   1.441 +    case MSR_IA32_MC8_ADDR:
   1.442 +        *lo = *hi = 0x0;
   1.443 +        if (!d || is_idle_domain(d)) {
   1.444 +            gdprintk(XENLOG_WARNING, "mce_rdmsr: not in domain context!\n");
   1.445 +            break;
   1.446 +        }
   1.447 +        if (!list_empty(&d->arch.vmca_msrs.impact_header)) {
   1.448 +            entry = list_entry(d->arch.vmca_msrs.impact_header.next,
   1.449 +                               struct bank_entry, list);
   1.450 +            if ( entry->bank == (msr - MSR_IA32_MC0_ADDR)/4 ) {
   1.451 +                *lo = entry->mci_addr;
   1.452 +                *hi = entry->mci_addr >> 32;
   1.453 +                gdprintk(XENLOG_DEBUG, "MCE: rdmsr MCi_ADDR in vMCE# context "
   1.454 +                         "lo %x hi %x\n", *lo, *hi);
   1.455              }
   1.456 +        }
   1.457 +        break;
   1.458 +    case MSR_IA32_MC0_MISC:
   1.459 +    case MSR_IA32_MC1_MISC:
   1.460 +    case MSR_IA32_MC2_MISC:
   1.461 +    case MSR_IA32_MC3_MISC:
   1.462 +    case MSR_IA32_MC4_MISC:
   1.463 +    case MSR_IA32_MC5_MISC:
   1.464 +    case MSR_IA32_MC6_MISC:
   1.465 +    case MSR_IA32_MC7_MISC:
   1.466 +    case MSR_IA32_MC8_MISC:
   1.467 +        *lo = *hi = 0x0;
   1.468 +        if (!d || is_idle_domain(d)) {
   1.469 +            gdprintk(XENLOG_WARNING, "MCE: rdmsr not in domain context!\n");
   1.470              break;
   1.471 -        default:
   1.472 -            break;
   1.473 +        }
   1.474 +        if (!list_empty(&d->arch.vmca_msrs.impact_header)) {
   1.475 +            entry = list_entry(d->arch.vmca_msrs.impact_header.next,
   1.476 +                               struct bank_entry, list);
   1.477 +            if ( entry->bank == (msr - MSR_IA32_MC0_MISC)/4 ) {
   1.478 +                *lo = entry->mci_misc;
   1.479 +                *hi = entry->mci_misc >> 32;
   1.480 +                gdprintk(XENLOG_DEBUG, "MCE: rdmsr MCi_MISC in vMCE# context "
   1.481 +                         " lo %x hi %x\n", *lo, *hi);
   1.482 +            }
   1.483 +        }
   1.484 +        break;
   1.485 +    default:
   1.486 +        ret = 0;
   1.487 +        break;
   1.488      }
   1.489      spin_unlock(&mce_locks);
   1.490      return ret;
     2.1 --- a/xen/arch/x86/traps.c	Fri Mar 20 17:25:29 2009 +0000
     2.2 +++ b/xen/arch/x86/traps.c	Fri Mar 20 17:42:46 2009 +0000
     2.3 @@ -2208,13 +2208,13 @@ static int emulate_privileged_op(struct 
     2.4          default:
     2.5              if ( wrmsr_hypervisor_regs(regs->ecx, eax, edx) )
     2.6                  break;
     2.7 -            if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
     2.8 -                if ( intel_mce_wrmsr(regs->ecx, eax, edx) != 0) {
     2.9 -                    gdprintk(XENLOG_ERR, "MCE: vMCE MSRS(%lx) Write"
    2.10 -                        " (%x:%x) Fails! ", regs->ecx, edx, eax);
    2.11 +            if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
    2.12 +            {
    2.13 +                int rc = intel_mce_wrmsr(regs->ecx, eax, edx);
    2.14 +                if ( rc == -1 )
    2.15                      goto fail;
    2.16 -                }
    2.17 -                break;
    2.18 +                if ( rc == 0 )
    2.19 +                    break;
    2.20              }
    2.21  
    2.22              if ( (rdmsr_safe(regs->ecx, l, h) != 0) ||
    2.23 @@ -2301,9 +2301,13 @@ static int emulate_privileged_op(struct 
    2.24              if ( rdmsr_safe(regs->ecx, regs->eax, regs->edx) )
    2.25                  goto fail;
    2.26  
    2.27 -            if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {
    2.28 -                if ( intel_mce_rdmsr(regs->ecx, &eax, &edx) != 0)
    2.29 -                    printk(KERN_ERR "MCE: Not MCE MSRs %lx\n", regs->ecx);
    2.30 +            if ( boot_cpu_data.x86_vendor == X86_VENDOR_INTEL )
    2.31 +            {
    2.32 +                int rc = intel_mce_rdmsr(regs->ecx, &eax, &edx);
    2.33 +                if ( rc == -1 )
    2.34 +                    goto fail;
    2.35 +                if ( rc == 0 )
    2.36 +                    break;
    2.37              }
    2.38  
    2.39              break;