ia64/xen-unstable

changeset 9392:00111084c70a

[IA64] Remove warning messages

This patch removed warning messages in vmx_phy_mode.c
and vmx_virt.c.

Signed-off-by: Masaki Kanno <kanno.masaki@jp.fujitsu.com>
author awilliam@xenbuild.aw
date Thu Mar 23 13:22:56 2006 -0700 (2006-03-23)
parents f517be67eeac
children 2ecf39c54693
files xen/arch/ia64/vmx/vmx_phy_mode.c xen/arch/ia64/vmx/vmx_virt.c
line diff
     1.1 --- a/xen/arch/ia64/vmx/vmx_phy_mode.c	Thu Mar 23 13:19:14 2006 -0700
     1.2 +++ b/xen/arch/ia64/vmx/vmx_phy_mode.c	Thu Mar 23 13:22:56 2006 -0700
     1.3 @@ -177,6 +177,7 @@ vmx_load_all_rr(VCPU *vcpu)
     1.4  {
     1.5  	unsigned long psr;
     1.6  	ia64_rr phy_rr;
     1.7 +	extern void * pal_vaddr;
     1.8  
     1.9  	local_irq_save(psr);
    1.10  
    1.11 @@ -188,13 +189,13 @@ vmx_load_all_rr(VCPU *vcpu)
    1.12  		if (vcpu->arch.mode_flags & GUEST_PHY_EMUL)
    1.13  			panic("Unexpected domain switch in phy emul\n");
    1.14  		phy_rr.rrval = vcpu->arch.metaphysical_rr0;
    1.15 - //   	phy_rr.ps = PAGE_SHIFT;
    1.16 -    	phy_rr.ve = 1;
    1.17 +//		phy_rr.ps = PAGE_SHIFT;
    1.18 +		phy_rr.ve = 1;
    1.19  
    1.20  		ia64_set_rr((VRN0 << VRN_SHIFT), phy_rr.rrval);
    1.21  		phy_rr.rrval = vcpu->arch.metaphysical_rr4;
    1.22 -//    	phy_rr.ps = PAGE_SHIFT;
    1.23 -	    phy_rr.ve = 1;
    1.24 +//		phy_rr.ps = PAGE_SHIFT;
    1.25 +		phy_rr.ve = 1;
    1.26  
    1.27  		ia64_set_rr((VRN4 << VRN_SHIFT), phy_rr.rrval);
    1.28  	} else {
    1.29 @@ -206,24 +207,24 @@ vmx_load_all_rr(VCPU *vcpu)
    1.30  
    1.31  	/* rr567 will be postponed to last point when resuming back to guest */
    1.32  	ia64_set_rr((VRN1 << VRN_SHIFT),
    1.33 -		     vmx_vrrtomrr(vcpu, VMX(vcpu, vrr[VRN1])));
    1.34 +			vmx_vrrtomrr(vcpu, VMX(vcpu, vrr[VRN1])));
    1.35  	ia64_set_rr((VRN2 << VRN_SHIFT),
    1.36 -		     vmx_vrrtomrr(vcpu, VMX(vcpu, vrr[VRN2])));
    1.37 +			vmx_vrrtomrr(vcpu, VMX(vcpu, vrr[VRN2])));
    1.38  	ia64_set_rr((VRN3 << VRN_SHIFT),
    1.39 -		     vmx_vrrtomrr(vcpu, VMX(vcpu, vrr[VRN3])));
    1.40 -    ia64_set_rr((VRN5 << VRN_SHIFT),
    1.41 -            vmx_vrrtomrr(vcpu, VMX(vcpu, vrr[VRN5])));
    1.42 -    ia64_set_rr((VRN6 << VRN_SHIFT),
    1.43 -            vmx_vrrtomrr(vcpu, VMX(vcpu, vrr[VRN6])));
    1.44 -    extern void * pal_vaddr;
    1.45 -    vmx_switch_rr7(vmx_vrrtomrr(vcpu,VMX(vcpu, vrr[VRN7])),(void *)vcpu->domain->shared_info,
    1.46 -                (void *)vcpu->arch.privregs,
    1.47 -                (void *)vcpu->arch.vtlb->vhpt->hash, pal_vaddr );
    1.48 -    ia64_set_pta(vcpu->arch.arch_vmx.mpta);
    1.49 +			vmx_vrrtomrr(vcpu, VMX(vcpu, vrr[VRN3])));
    1.50 +	ia64_set_rr((VRN5 << VRN_SHIFT),
    1.51 +			vmx_vrrtomrr(vcpu, VMX(vcpu, vrr[VRN5])));
    1.52 +	ia64_set_rr((VRN6 << VRN_SHIFT),
    1.53 +			vmx_vrrtomrr(vcpu, VMX(vcpu, vrr[VRN6])));
    1.54 +	vmx_switch_rr7(vmx_vrrtomrr(vcpu,VMX(vcpu, vrr[VRN7])),
    1.55 +			(void *)vcpu->domain->shared_info,
    1.56 +			(void *)vcpu->arch.privregs,
    1.57 +			(void *)vcpu->arch.vtlb->vhpt->hash, pal_vaddr );
    1.58 +	ia64_set_pta(vcpu->arch.arch_vmx.mpta);
    1.59  
    1.60  	ia64_srlz_d();
    1.61  	ia64_set_psr(psr);
    1.62 -    ia64_srlz_i();
    1.63 +	ia64_srlz_i();
    1.64  }
    1.65  
    1.66  void
     2.1 --- a/xen/arch/ia64/vmx/vmx_virt.c	Thu Mar 23 13:19:14 2006 -0700
     2.2 +++ b/xen/arch/ia64/vmx/vmx_virt.c	Thu Mar 23 13:22:56 2006 -0700
     2.3 @@ -714,6 +714,7 @@ IA64FAULT vmx_emul_itc_i(VCPU *vcpu, INS
     2.4  IA64FAULT vmx_emul_mov_to_ar_imm(VCPU *vcpu, INST64 inst)
     2.5  {
     2.6      // I27 and M30 are identical for these fields
     2.7 +    UINT64  imm;
     2.8      if(inst.M30.ar3!=44){
     2.9          panic("Can't support ar register other than itc");
    2.10      }
    2.11 @@ -727,7 +728,6 @@ IA64FAULT vmx_emul_mov_to_ar_imm(VCPU *v
    2.12          return IA64_FAULT;
    2.13      }
    2.14  #endif // CHECK_FAULT
    2.15 -    UINT64  imm;
    2.16      if(inst.M30.s){
    2.17          imm = -inst.M30.imm;
    2.18      }else{
    2.19 @@ -767,6 +767,7 @@ IA64FAULT vmx_emul_mov_to_ar_reg(VCPU *v
    2.20  IA64FAULT vmx_emul_mov_from_ar_reg(VCPU *vcpu, INST64 inst)
    2.21  {
    2.22      // I27 and M30 are identical for these fields
    2.23 +    u64 r1;
    2.24      if(inst.M31.ar3!=44){
    2.25          panic("Can't support ar register other than itc");
    2.26      }
    2.27 @@ -785,7 +786,6 @@ IA64FAULT vmx_emul_mov_from_ar_reg(VCPU 
    2.28          return IA64_FAULT;
    2.29      }
    2.30  #endif // CHECK_FAULT
    2.31 -    u64 r1;
    2.32      vmx_vcpu_get_itc(vcpu,&r1);
    2.33      vcpu_set_gr(vcpu,inst.M31.r1,r1,0);
    2.34      return IA64_NO_FAULT;
    2.35 @@ -844,8 +844,8 @@ IA64FAULT vmx_emul_mov_to_rr(VCPU *vcpu,
    2.36  
    2.37  IA64FAULT vmx_emul_mov_to_dbr(VCPU *vcpu, INST64 inst)
    2.38  {
    2.39 +    u64 r3,r2;
    2.40      return IA64_NO_FAULT;
    2.41 -    u64 r3,r2;
    2.42  #ifdef  CHECK_FAULT
    2.43      IA64_PSR vpsr;
    2.44      vpsr.val=vmx_vcpu_get_psr(vcpu);
    2.45 @@ -868,8 +868,8 @@ IA64FAULT vmx_emul_mov_to_dbr(VCPU *vcpu
    2.46  
    2.47  IA64FAULT vmx_emul_mov_to_ibr(VCPU *vcpu, INST64 inst)
    2.48  {
    2.49 +    u64 r3,r2;
    2.50      return IA64_NO_FAULT;
    2.51 -    u64 r3,r2;
    2.52  #ifdef  CHECK_FAULT
    2.53      IA64_PSR vpsr;
    2.54      vpsr.val=vmx_vcpu_get_psr(vcpu);
    2.55 @@ -1156,6 +1156,7 @@ IA64FAULT vmx_emul_mov_from_cpuid(VCPU *
    2.56  IA64FAULT vmx_emul_mov_to_cr(VCPU *vcpu, INST64 inst)
    2.57  {
    2.58      u64 r2;
    2.59 +    extern u64 cr_igfld_mask(int index, u64 value);
    2.60  #ifdef  CHECK_FAULT
    2.61      IA64_PSR  vpsr;
    2.62      vpsr.val=vmx_vcpu_get_psr(vcpu);
    2.63 @@ -1187,7 +1188,6 @@ IA64FAULT vmx_emul_mov_to_cr(VCPU *vcpu,
    2.64          return IA64_FAULT;
    2.65      }
    2.66  #endif  //CHECK_FAULT
    2.67 -    extern u64 cr_igfld_mask(int index, u64 value);
    2.68      r2 = cr_igfld_mask(inst.M32.cr3,r2);
    2.69      VCPU(vcpu, vcr[inst.M32.cr3]) = r2;
    2.70      switch (inst.M32.cr3) {