ia64/xen-unstable

view xen/include/asm-ia64/linux-xen/asm/io.h @ 19848:5839491bbf20

[IA64] replace MAX_VCPUS with d->max_vcpus where necessary.

don't use MAX_VCPUS, and use vcpu::max_vcpus.
The changeset of 2f9e1348aa98 introduced max_vcpus to allow more vcpus
per guest. This patch is ia64 counter part.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Isaku Yamahata <yamahata@valinux.co.jp>
date Mon Jun 29 11:26:05 2009 +0900 (2009-06-29)
parents c17bfb091790
children
line source
1 #ifndef _ASM_IA64_IO_H
2 #define _ASM_IA64_IO_H
4 /*
5 * This file contains the definitions for the emulated IO instructions
6 * inb/inw/inl/outb/outw/outl and the "string versions" of the same
7 * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
8 * versions of the single-IO instructions (inb_p/inw_p/..).
9 *
10 * This file is not meant to be obfuscating: it's just complicated to
11 * (a) handle it all in a way that makes gcc able to optimize it as
12 * well as possible and (b) trying to avoid writing the same thing
13 * over and over again with slight variations and possibly making a
14 * mistake somewhere.
15 *
16 * Copyright (C) 1998-2003 Hewlett-Packard Co
17 * David Mosberger-Tang <davidm@hpl.hp.com>
18 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
19 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
20 */
22 /* We don't use IO slowdowns on the ia64, but.. */
23 #define __SLOW_DOWN_IO do { } while (0)
24 #define SLOW_DOWN_IO do { } while (0)
26 #ifdef XEN
27 #include <asm/xensystem.h>
28 #else
29 #define __IA64_UNCACHED_OFFSET 0xc000000000000000UL /* region 6 */
30 #endif
32 /*
33 * The legacy I/O space defined by the ia64 architecture supports only 65536 ports, but
34 * large machines may have multiple other I/O spaces so we can't place any a priori limit
35 * on IO_SPACE_LIMIT. These additional spaces are described in ACPI.
36 */
37 #define IO_SPACE_LIMIT 0xffffffffffffffffUL
39 #define MAX_IO_SPACES_BITS 4
40 #define MAX_IO_SPACES (1UL << MAX_IO_SPACES_BITS)
41 #define IO_SPACE_BITS 24
42 #define IO_SPACE_SIZE (1UL << IO_SPACE_BITS)
44 #define IO_SPACE_NR(port) ((port) >> IO_SPACE_BITS)
45 #define IO_SPACE_BASE(space) ((space) << IO_SPACE_BITS)
46 #define IO_SPACE_PORT(port) ((port) & (IO_SPACE_SIZE - 1))
48 #define IO_SPACE_SPARSE_ENCODING(p) ((((p) >> 2) << 12) | (p & 0xfff))
50 #ifdef XEN
51 /* Offset to IO port; do not catch error. */
52 #define IO_SPACE_SPARSE_DECODING(off) ((((off) >> 12) << 2) | ((off) & 0x3))
53 #define IO_SPACE_SPARSE_PORTS_PER_PAGE (0x4 << (PAGE_SHIFT - 12))
54 #endif
56 struct io_space {
57 unsigned long mmio_base; /* base in MMIO space */
58 int sparse;
59 };
61 extern struct io_space io_space[];
62 extern unsigned int num_io_spaces;
64 # ifdef __KERNEL__
66 /*
67 * All MMIO iomem cookies are in region 6; anything less is a PIO cookie:
68 * 0xCxxxxxxxxxxxxxxx MMIO cookie (return from ioremap)
69 * 0x000000001SPPPPPP PIO cookie (S=space number, P..P=port)
70 *
71 * ioread/writeX() uses the leading 1 in PIO cookies (PIO_OFFSET) to catch
72 * code that uses bare port numbers without the prerequisite pci_iomap().
73 */
74 #define PIO_OFFSET (1UL << (MAX_IO_SPACES_BITS + IO_SPACE_BITS))
75 #define PIO_MASK (PIO_OFFSET - 1)
76 #define PIO_RESERVED __IA64_UNCACHED_OFFSET
77 #define HAVE_ARCH_PIO_SIZE
79 #include <asm/intrinsics.h>
80 #include <asm/machvec.h>
81 #include <asm/page.h>
82 #include <asm/system.h>
83 #include <asm-generic/iomap.h>
86 #ifndef XEN
87 /*
88 * Change virtual addresses to physical addresses and vv.
89 */
90 static inline unsigned long
91 virt_to_maddr (volatile void *address)
92 {
93 return (unsigned long) address - PAGE_OFFSET;
94 }
95 #endif
97 static inline void*
98 maddr_to_virt (unsigned long address)
99 {
100 return (void *) (address + PAGE_OFFSET);
101 }
104 #define ARCH_HAS_VALID_PHYS_ADDR_RANGE
105 extern int valid_phys_addr_range (unsigned long addr, size_t *count); /* efi.c */
107 /*
108 * The following two macros are deprecated and scheduled for removal.
109 * Please use the PCI-DMA interface defined in <asm/pci.h> instead.
110 */
111 #define bus_to_virt maddr_to_virt
112 #define virt_to_bus virt_to_maddr
113 #define page_to_bus page_to_maddr
115 # endif /* KERNEL */
117 /*
118 * Memory fence w/accept. This should never be used in code that is
119 * not IA-64 specific.
120 */
121 #define __ia64_mf_a() ia64_mfa()
123 /**
124 * ___ia64_mmiowb - I/O write barrier
125 *
126 * Ensure ordering of I/O space writes. This will make sure that writes
127 * following the barrier will arrive after all previous writes. For most
128 * ia64 platforms, this is a simple 'mf.a' instruction.
129 *
130 * See Documentation/DocBook/deviceiobook.tmpl for more information.
131 */
132 static inline void ___ia64_mmiowb(void)
133 {
134 ia64_mfa();
135 }
137 static inline void*
138 __ia64_mk_io_addr (unsigned long port)
139 {
140 struct io_space *space;
141 unsigned long offset;
143 space = &io_space[IO_SPACE_NR(port)];
144 port = IO_SPACE_PORT(port);
145 if (space->sparse)
146 offset = IO_SPACE_SPARSE_ENCODING(port);
147 else
148 offset = port;
150 return (void *) (space->mmio_base | offset);
151 }
153 #define __ia64_inb ___ia64_inb
154 #define __ia64_inw ___ia64_inw
155 #define __ia64_inl ___ia64_inl
156 #define __ia64_outb ___ia64_outb
157 #define __ia64_outw ___ia64_outw
158 #define __ia64_outl ___ia64_outl
159 #define __ia64_readb ___ia64_readb
160 #define __ia64_readw ___ia64_readw
161 #define __ia64_readl ___ia64_readl
162 #define __ia64_readq ___ia64_readq
163 #define __ia64_readb_relaxed ___ia64_readb
164 #define __ia64_readw_relaxed ___ia64_readw
165 #define __ia64_readl_relaxed ___ia64_readl
166 #define __ia64_readq_relaxed ___ia64_readq
167 #define __ia64_writeb ___ia64_writeb
168 #define __ia64_writew ___ia64_writew
169 #define __ia64_writel ___ia64_writel
170 #define __ia64_writeq ___ia64_writeq
171 #define __ia64_mmiowb ___ia64_mmiowb
173 /*
174 * For the in/out routines, we need to do "mf.a" _after_ doing the I/O access to ensure
175 * that the access has completed before executing other I/O accesses. Since we're doing
176 * the accesses through an uncachable (UC) translation, the CPU will execute them in
177 * program order. However, we still need to tell the compiler not to shuffle them around
178 * during optimization, which is why we use "volatile" pointers.
179 */
181 static inline unsigned int
182 ___ia64_inb (unsigned long port)
183 {
184 volatile unsigned char *addr = __ia64_mk_io_addr(port);
185 unsigned char ret;
187 ret = *addr;
188 __ia64_mf_a();
189 return ret;
190 }
192 static inline unsigned int
193 ___ia64_inw (unsigned long port)
194 {
195 volatile unsigned short *addr = __ia64_mk_io_addr(port);
196 unsigned short ret;
198 ret = *addr;
199 __ia64_mf_a();
200 return ret;
201 }
203 static inline unsigned int
204 ___ia64_inl (unsigned long port)
205 {
206 volatile unsigned int *addr = __ia64_mk_io_addr(port);
207 unsigned int ret;
209 ret = *addr;
210 __ia64_mf_a();
211 return ret;
212 }
214 static inline void
215 ___ia64_outb (unsigned char val, unsigned long port)
216 {
217 volatile unsigned char *addr = __ia64_mk_io_addr(port);
219 *addr = val;
220 __ia64_mf_a();
221 }
223 static inline void
224 ___ia64_outw (unsigned short val, unsigned long port)
225 {
226 volatile unsigned short *addr = __ia64_mk_io_addr(port);
228 *addr = val;
229 __ia64_mf_a();
230 }
232 static inline void
233 ___ia64_outl (unsigned int val, unsigned long port)
234 {
235 volatile unsigned int *addr = __ia64_mk_io_addr(port);
237 *addr = val;
238 __ia64_mf_a();
239 }
241 static inline void
242 __insb (unsigned long port, void *dst, unsigned long count)
243 {
244 unsigned char *dp = dst;
246 while (count--)
247 *dp++ = platform_inb(port);
248 }
250 static inline void
251 __insw (unsigned long port, void *dst, unsigned long count)
252 {
253 unsigned short *dp = dst;
255 while (count--)
256 *dp++ = platform_inw(port);
257 }
259 static inline void
260 __insl (unsigned long port, void *dst, unsigned long count)
261 {
262 unsigned int *dp = dst;
264 while (count--)
265 *dp++ = platform_inl(port);
266 }
268 static inline void
269 __outsb (unsigned long port, const void *src, unsigned long count)
270 {
271 const unsigned char *sp = src;
273 while (count--)
274 platform_outb(*sp++, port);
275 }
277 static inline void
278 __outsw (unsigned long port, const void *src, unsigned long count)
279 {
280 const unsigned short *sp = src;
282 while (count--)
283 platform_outw(*sp++, port);
284 }
286 static inline void
287 __outsl (unsigned long port, const void *src, unsigned long count)
288 {
289 const unsigned int *sp = src;
291 while (count--)
292 platform_outl(*sp++, port);
293 }
295 /*
296 * Unfortunately, some platforms are broken and do not follow the IA-64 architecture
297 * specification regarding legacy I/O support. Thus, we have to make these operations
298 * platform dependent...
299 */
300 #define __inb platform_inb
301 #define __inw platform_inw
302 #define __inl platform_inl
303 #define __outb platform_outb
304 #define __outw platform_outw
305 #define __outl platform_outl
306 #define __mmiowb platform_mmiowb
308 #define inb(p) __inb(p)
309 #define inw(p) __inw(p)
310 #define inl(p) __inl(p)
311 #define insb(p,d,c) __insb(p,d,c)
312 #define insw(p,d,c) __insw(p,d,c)
313 #define insl(p,d,c) __insl(p,d,c)
314 #define outb(v,p) __outb(v,p)
315 #define outw(v,p) __outw(v,p)
316 #define outl(v,p) __outl(v,p)
317 #define outsb(p,s,c) __outsb(p,s,c)
318 #define outsw(p,s,c) __outsw(p,s,c)
319 #define outsl(p,s,c) __outsl(p,s,c)
320 #define mmiowb() __mmiowb()
322 /*
323 * The address passed to these functions are ioremap()ped already.
324 *
325 * We need these to be machine vectors since some platforms don't provide
326 * DMA coherence via PIO reads (PCI drivers and the spec imply that this is
327 * a good idea). Writes are ok though for all existing ia64 platforms (and
328 * hopefully it'll stay that way).
329 */
330 static inline unsigned char
331 ___ia64_readb (const volatile void __iomem *addr)
332 {
333 return *(volatile unsigned char __force *)addr;
334 }
336 static inline unsigned short
337 ___ia64_readw (const volatile void __iomem *addr)
338 {
339 return *(volatile unsigned short __force *)addr;
340 }
342 static inline unsigned int
343 ___ia64_readl (const volatile void __iomem *addr)
344 {
345 return *(volatile unsigned int __force *) addr;
346 }
348 static inline unsigned long
349 ___ia64_readq (const volatile void __iomem *addr)
350 {
351 return *(volatile unsigned long __force *) addr;
352 }
354 static inline void
355 __writeb (unsigned char val, volatile void __iomem *addr)
356 {
357 *(volatile unsigned char __force *) addr = val;
358 }
360 static inline void
361 __writew (unsigned short val, volatile void __iomem *addr)
362 {
363 *(volatile unsigned short __force *) addr = val;
364 }
366 static inline void
367 __writel (unsigned int val, volatile void __iomem *addr)
368 {
369 *(volatile unsigned int __force *) addr = val;
370 }
372 static inline void
373 __writeq (unsigned long val, volatile void __iomem *addr)
374 {
375 *(volatile unsigned long __force *) addr = val;
376 }
378 #define __readb platform_readb
379 #define __readw platform_readw
380 #define __readl platform_readl
381 #define __readq platform_readq
382 #define __readb_relaxed platform_readb_relaxed
383 #define __readw_relaxed platform_readw_relaxed
384 #define __readl_relaxed platform_readl_relaxed
385 #define __readq_relaxed platform_readq_relaxed
387 #define readb(a) __readb((a))
388 #define readw(a) __readw((a))
389 #define readl(a) __readl((a))
390 #define readq(a) __readq((a))
391 #define readb_relaxed(a) __readb_relaxed((a))
392 #define readw_relaxed(a) __readw_relaxed((a))
393 #define readl_relaxed(a) __readl_relaxed((a))
394 #define readq_relaxed(a) __readq_relaxed((a))
395 #define __raw_readb readb
396 #define __raw_readw readw
397 #define __raw_readl readl
398 #define __raw_readq readq
399 #define __raw_readb_relaxed readb_relaxed
400 #define __raw_readw_relaxed readw_relaxed
401 #define __raw_readl_relaxed readl_relaxed
402 #define __raw_readq_relaxed readq_relaxed
403 #define writeb(v,a) __writeb((v), (a))
404 #define writew(v,a) __writew((v), (a))
405 #define writel(v,a) __writel((v), (a))
406 #define writeq(v,a) __writeq((v), (a))
407 #define __raw_writeb writeb
408 #define __raw_writew writew
409 #define __raw_writel writel
410 #define __raw_writeq writeq
412 #ifndef inb_p
413 # define inb_p inb
414 #endif
415 #ifndef inw_p
416 # define inw_p inw
417 #endif
418 #ifndef inl_p
419 # define inl_p inl
420 #endif
422 #ifndef outb_p
423 # define outb_p outb
424 #endif
425 #ifndef outw_p
426 # define outw_p outw
427 #endif
428 #ifndef outl_p
429 # define outl_p outl
430 #endif
432 /*
433 * An "address" in IO memory space is not clearly either an integer or a pointer. We will
434 * accept both, thus the casts.
435 *
436 * On ia-64, we access the physical I/O memory space through the uncached kernel region.
437 */
438 static inline void __iomem *
439 ioremap (unsigned long offset, unsigned long size)
440 {
441 return (void __iomem *) (__IA64_UNCACHED_OFFSET | (offset));
442 }
444 static inline void
445 iounmap (volatile void __iomem *addr)
446 {
447 }
449 #define ioremap_nocache(o,s) ioremap(o,s)
451 # ifdef __KERNEL__
453 /*
454 * String version of IO memory access ops:
455 */
456 extern void memcpy_fromio(void *dst, const volatile void __iomem *src, long n);
457 extern void memcpy_toio(volatile void __iomem *dst, const void *src, long n);
458 extern void memset_io(volatile void __iomem *s, int c, long n);
460 #define dma_cache_inv(_start,_size) do { } while (0)
461 #define dma_cache_wback(_start,_size) do { } while (0)
462 #define dma_cache_wback_inv(_start,_size) do { } while (0)
464 # endif /* __KERNEL__ */
466 /*
467 * Enabling BIO_VMERGE_BOUNDARY forces us to turn off I/O MMU bypassing. It is said that
468 * BIO-level virtual merging can give up to 4% performance boost (not verified for ia64).
469 * On the other hand, we know that I/O MMU bypassing gives ~8% performance improvement on
470 * SPECweb-like workloads on zx1-based machines. Thus, for now we favor I/O MMU bypassing
471 * over BIO-level virtual merging.
472 */
473 extern unsigned long ia64_max_iommu_merge_mask;
474 #if 1
475 #define BIO_VMERGE_BOUNDARY 0
476 #else
477 /*
478 * It makes no sense at all to have this BIO_VMERGE_BOUNDARY macro here. Should be
479 * replaced by dma_merge_mask() or something of that sort. Note: the only way
480 * BIO_VMERGE_BOUNDARY is used is to mask off bits. Effectively, our definition gets
481 * expanded into:
482 *
483 * addr & ((ia64_max_iommu_merge_mask + 1) - 1) == (addr & ia64_max_iommu_vmerge_mask)
484 *
485 * which is precisely what we want.
486 */
487 #define BIO_VMERGE_BOUNDARY (ia64_max_iommu_merge_mask + 1)
488 #endif
490 #endif /* _ASM_IA64_IO_H */