ia64/xen-unstable

view xen/arch/ia64/linux-xen/setup.c @ 19848:5839491bbf20

[IA64] replace MAX_VCPUS with d->max_vcpus where necessary.

don't use MAX_VCPUS, and use vcpu::max_vcpus.
The changeset of 2f9e1348aa98 introduced max_vcpus to allow more vcpus
per guest. This patch is ia64 counter part.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Isaku Yamahata <yamahata@valinux.co.jp>
date Mon Jun 29 11:26:05 2009 +0900 (2009-06-29)
parents 00721ef8d8ef
children
line source
1 /*
2 * Architecture-specific setup.
3 *
4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 * Stephane Eranian <eranian@hpl.hp.com>
7 * Copyright (C) 2000, 2004 Intel Corp
8 * Rohit Seth <rohit.seth@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Gordon Jin <gordon.jin@intel.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
13 *
14 * 12/26/04 S.Siddha, G.Jin, R.Seth
15 * Add multi-threading and multi-core detection
16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes
19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes...
20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP
21 * 01/07/99 S.Eranian added the support for command line argument
22 * 06/24/99 W.Drummond added boot_cpu_data.
23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()"
24 */
25 #include <linux/config.h>
26 #include <linux/module.h>
27 #include <linux/init.h>
29 #include <linux/acpi.h>
30 #include <linux/bootmem.h>
31 #include <linux/console.h>
32 #include <linux/delay.h>
33 #include <linux/kernel.h>
34 #include <linux/shutdown.h>
35 #include <linux/sched.h>
36 #include <linux/seq_file.h>
37 #include <linux/string.h>
38 #include <linux/threads.h>
39 #include <linux/tty.h>
40 #include <linux/serial.h>
41 #include <linux/serial_core.h>
42 #include <linux/efi.h>
43 #include <linux/initrd.h>
44 #include <linux/platform.h>
45 #include <linux/pm.h>
47 #include <asm/ia32.h>
48 #include <asm/machvec.h>
49 #include <asm/mca.h>
50 #include <asm/meminit.h>
51 #include <asm/page.h>
52 #include <asm/patch.h>
53 #include <asm/pgtable.h>
54 #include <asm/processor.h>
55 #include <asm/sal.h>
56 #include <asm/sections.h>
57 #include <asm/serial.h>
58 #include <asm/setup.h>
59 #include <asm/smp.h>
60 #include <asm/system.h>
61 #include <asm/unistd.h>
62 #ifdef XEN
63 #include <asm/vmx.h>
64 #include <asm/io.h>
65 #include <asm/kexec.h>
66 #include <public/kexec.h>
67 #include <xen/kexec.h>
68 #endif
70 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
71 # error "struct cpuinfo_ia64 too big!"
72 #endif
74 #ifdef CONFIG_SMP
75 unsigned long __per_cpu_offset[NR_CPUS];
76 EXPORT_SYMBOL(__per_cpu_offset);
77 #endif
79 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
80 #ifdef XEN
81 DEFINE_PER_CPU(cpu_kr_ia64_t, cpu_kr);
82 #endif
83 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
84 DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8);
85 unsigned long ia64_cycles_per_usec;
86 struct ia64_boot_param *ia64_boot_param;
87 struct screen_info screen_info;
88 unsigned long vga_console_iobase;
89 unsigned long vga_console_membase;
91 unsigned long ia64_max_cacheline_size;
92 unsigned long ia64_iobase; /* virtual address for I/O accesses */
93 EXPORT_SYMBOL(ia64_iobase);
94 struct io_space io_space[MAX_IO_SPACES];
95 EXPORT_SYMBOL(io_space);
96 unsigned int num_io_spaces;
98 #ifdef XEN
99 extern void early_cmdline_parse(char **);
100 extern unsigned int ns16550_com1_gsi;
101 #endif
103 /*
104 * "flush_icache_range()" needs to know what processor dependent stride size to use
105 * when it makes i-cache(s) coherent with d-caches.
106 */
107 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */
108 unsigned long ia64_i_cache_stride_shift = ~0;
110 #ifdef XEN
111 #define D_CACHE_STRIDE_SHIFT 5 /* Safest. */
112 unsigned long ia64_d_cache_stride_shift = ~0;
113 #endif
115 /*
116 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
117 * mask specifies a mask of address bits that must be 0 in order for two buffers to be
118 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
119 * address of the second buffer must be aligned to (merge_mask+1) in order to be
120 * mergeable). By default, we assume there is no I/O MMU which can merge physically
121 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
122 * page-size of 2^64.
123 */
124 unsigned long ia64_max_iommu_merge_mask = ~0UL;
125 EXPORT_SYMBOL(ia64_max_iommu_merge_mask);
127 /*
128 * We use a special marker for the end of memory and it uses the extra (+1) slot
129 */
130 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1];
131 int num_rsvd_regions;
134 /*
135 * Filter incoming memory segments based on the primitive map created from the boot
136 * parameters. Segments contained in the map are removed from the memory ranges. A
137 * caller-specified function is called with the memory ranges that remain after filtering.
138 * This routine does not assume the incoming segments are sorted.
139 */
140 int
141 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg)
142 {
143 unsigned long range_start, range_end, prev_start;
144 void (*func)(unsigned long, unsigned long, int);
145 int i;
147 #if IGNORE_PFN0
148 if (start == PAGE_OFFSET) {
149 printk(KERN_WARNING "warning: skipping physical page 0\n");
150 start += PAGE_SIZE;
151 if (start >= end) return 0;
152 }
153 #endif
154 /*
155 * lowest possible address(walker uses virtual)
156 */
157 prev_start = PAGE_OFFSET;
158 func = arg;
160 for (i = 0; i < num_rsvd_regions; ++i) {
161 range_start = max(start, prev_start);
162 range_end = min(end, rsvd_region[i].start);
164 if (range_start < range_end)
165 #ifdef XEN
166 {
167 /* init_boot_pages requires "ps, pe" */
168 printk("Init boot pages: 0x%lx -> 0x%lx.\n",
169 __pa(range_start), __pa(range_end));
170 (*func)(__pa(range_start), __pa(range_end), 0);
171 }
172 #else
173 call_pernode_memory(__pa(range_start), range_end - range_start, func);
174 #endif
176 /* nothing more available in this segment */
177 if (range_end == end) return 0;
179 prev_start = rsvd_region[i].end;
180 }
181 /* end of memory marker allows full processing inside loop body */
182 return 0;
183 }
185 static void
186 sort_regions (struct rsvd_region *rsvd_region, int max)
187 {
188 int j;
190 /* simple bubble sorting */
191 while (max--) {
192 for (j = 0; j < max; ++j) {
193 if (rsvd_region[j].start > rsvd_region[j+1].start) {
194 struct rsvd_region tmp;
195 tmp = rsvd_region[j];
196 rsvd_region[j] = rsvd_region[j + 1];
197 rsvd_region[j + 1] = tmp;
198 }
199 }
200 }
201 }
203 /**
204 * reserve_memory - setup reserved memory areas
205 *
206 * Setup the reserved memory areas set aside for the boot parameters,
207 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined,
208 * see include/asm-ia64/meminit.h if you need to define more.
209 */
210 void
211 reserve_memory (void)
212 {
213 int n = 0;
215 /*
216 * none of the entries in this table overlap
217 */
218 rsvd_region[n].start = (unsigned long) ia64_boot_param;
219 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param);
220 n++;
222 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
223 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
224 n++;
226 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
227 rsvd_region[n].end = (rsvd_region[n].start
228 + strlen(__va(ia64_boot_param->command_line)) + 1);
229 n++;
231 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
232 #ifdef XEN
233 /* Reserve xen image/bitmap/xen-heap */
234 rsvd_region[n].end = rsvd_region[n].start + xenheap_size;
235 #else
236 rsvd_region[n].end = (unsigned long) ia64_imva(_end);
237 #endif
238 n++;
240 #ifdef XEN
241 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->domain_start);
242 rsvd_region[n].end = (rsvd_region[n].start + ia64_boot_param->domain_size);
243 n++;
244 #endif
246 #if defined(XEN)||defined(CONFIG_BLK_DEV_INITRD)
247 if (ia64_boot_param->initrd_start) {
248 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
249 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size;
250 n++;
251 }
252 #endif
254 efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end);
255 n++;
257 #ifdef XEN
258 /* crashkernel=size@offset specifies the size to reserve for a crash
259 * kernel. If offset is 0, then it is determined automatically.
260 * By reserving this memory we guarantee that linux never set's it
261 * up as a DMA target. Useful for holding code to do something
262 * appropriate after a kernel panic.
263 */
264 if (kexec_crash_area.size > 0) {
265 if (!kexec_crash_area.start) {
266 sort_regions(rsvd_region, n);
267 kexec_crash_area.start =
268 kdump_find_rsvd_region(kexec_crash_area.size,
269 rsvd_region, n);
270 }
271 if (kexec_crash_area.start != ~0UL) {
272 printk("Kdump: %luMB (%lukB) at 0x%lx\n",
273 kexec_crash_area.size >> 20,
274 kexec_crash_area.size >> 10,
275 kexec_crash_area.start);
276 rsvd_region[n].start =
277 (unsigned long)__va(kexec_crash_area.start);
278 rsvd_region[n].end =
279 (unsigned long)__va(kexec_crash_area.start +
280 kexec_crash_area.size);
281 n++;
282 }
283 else {
284 kexec_crash_area.size = 0;
285 kexec_crash_area.start = 0;
286 }
287 }
288 #endif
290 /* end of memory marker */
291 rsvd_region[n].start = ~0UL;
292 rsvd_region[n].end = ~0UL;
293 n++;
295 num_rsvd_regions = n;
297 sort_regions(rsvd_region, num_rsvd_regions);
298 }
300 /**
301 * find_initrd - get initrd parameters from the boot parameter structure
302 *
303 * Grab the initrd start and end from the boot parameter struct given us by
304 * the boot loader.
305 */
306 void
307 find_initrd (void)
308 {
309 #ifdef CONFIG_BLK_DEV_INITRD
310 if (ia64_boot_param->initrd_start) {
311 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
312 initrd_end = initrd_start+ia64_boot_param->initrd_size;
314 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
315 initrd_start, ia64_boot_param->initrd_size);
316 }
317 #endif
318 }
320 static void __init
321 io_port_init (void)
322 {
323 extern unsigned long ia64_iobase;
324 unsigned long phys_iobase;
326 /*
327 * Set `iobase' to the appropriate address in region 6 (uncached access range).
328 *
329 * The EFI memory map is the "preferred" location to get the I/O port space base,
330 * rather the relying on AR.KR0. This should become more clear in future SAL
331 * specs. We'll fall back to getting it out of AR.KR0 if no appropriate entry is
332 * found in the memory map.
333 */
334 phys_iobase = efi_get_iobase();
335 if (phys_iobase)
336 /* set AR.KR0 since this is all we use it for anyway */
337 ia64_set_kr(IA64_KR_IO_BASE, phys_iobase);
338 else {
339 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
340 printk(KERN_INFO "No I/O port range found in EFI memory map, falling back "
341 "to AR.KR0\n");
342 printk(KERN_INFO "I/O port base = 0x%lx\n", phys_iobase);
343 }
344 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
346 /* setup legacy IO port space */
347 io_space[0].mmio_base = ia64_iobase;
348 io_space[0].sparse = 1;
349 num_io_spaces = 1;
350 }
352 #ifdef XEN
353 static int __init
354 acpi_oem_console_setup(void)
355 {
356 extern struct ns16550_defaults ns16550_com1;
357 efi_system_table_t *systab;
358 efi_config_table_t *tables;
359 struct acpi_table_rsdp *rsdp = NULL;
360 struct acpi_table_xsdt *xsdt;
361 struct acpi_table_header *hdr;
362 int i;
364 /* Don't duplicate setup if an HCDP table is present */
365 if (efi.hcdp != EFI_INVALID_TABLE_ADDR)
366 return -ENODEV;
368 /* Manually walk firmware provided tables to get to the XSDT. */
369 systab = __va(ia64_boot_param->efi_systab);
371 if (!systab || systab->hdr.signature != EFI_SYSTEM_TABLE_SIGNATURE)
372 return -ENODEV;
374 tables = __va(systab->tables);
376 for (i = 0 ; i < (int)systab->nr_tables && !rsdp ; i++) {
377 if (efi_guidcmp(tables[i].guid, ACPI_20_TABLE_GUID) == 0)
378 rsdp =
379 (struct acpi_table_rsdp *)__va(tables[i].table);
380 }
382 if (!rsdp ||
383 strncmp(rsdp->signature, ACPI_SIG_RSDP, sizeof(ACPI_SIG_RSDP) - 1))
384 return -ENODEV;
386 xsdt = (struct acpi_table_xsdt *)__va(rsdp->xsdt_physical_address);
387 hdr = &xsdt->header;
389 if (strncmp(hdr->signature, ACPI_SIG_XSDT, sizeof(ACPI_SIG_XSDT) - 1))
390 return -ENODEV;
392 /* Looking for Fujitsu PRIMEQUEST systems */
393 if (!strncmp(hdr->oem_id, "FUJITSPQ", 8) &&
394 (!strncmp(hdr->oem_table_id, "PQ", 2))){
395 ns16550_com1.baud = BAUD_AUTO;
396 ns16550_com1.io_base = 0x3f8;
397 ns16550_com1.irq = ns16550_com1_gsi = 4;
398 return 0;
399 }
401 /*
402 * Looking for Intel Tiger systems
403 * Tiger 2: SR870BH2
404 * Tiger 4: SR870BN4
405 */
406 if (!strncmp(hdr->oem_id, "INTEL", 5)) {
407 if (!strncmp(hdr->oem_table_id, "SR870BH2", 8) ||
408 !strncmp(hdr->oem_table_id, "SR870BN4", 8)) {
409 ns16550_com1.baud = BAUD_AUTO;
410 ns16550_com1.io_base = 0x2f8;
411 ns16550_com1.irq = 3;
412 return 0;
413 } else {
414 ns16550_com1.baud = BAUD_AUTO;
415 ns16550_com1.io_base = 0x3f8;
416 ns16550_com1.irq = ns16550_com1_gsi = 4;
417 return 0;
418 }
419 }
420 return -ENODEV;
421 }
422 #endif
424 /**
425 * early_console_setup - setup debugging console
426 *
427 * Consoles started here require little enough setup that we can start using
428 * them very early in the boot process, either right after the machine
429 * vector initialization, or even before if the drivers can detect their hw.
430 *
431 * Returns non-zero if a console couldn't be setup.
432 */
433 static inline int __init
434 early_console_setup (char *cmdline)
435 {
436 int earlycons = 0;
438 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
439 {
440 extern int sn_serial_console_early_setup(void);
441 if (!sn_serial_console_early_setup())
442 earlycons++;
443 }
444 #endif
445 #ifdef CONFIG_EFI_PCDP
446 if (!efi_setup_pcdp_console(cmdline))
447 earlycons++;
448 #endif
449 #ifdef CONFIG_SERIAL_8250_CONSOLE
450 if (!early_serial_console_init(cmdline))
451 earlycons++;
452 #endif
454 #ifdef XEN
455 if (!acpi_oem_console_setup())
456 earlycons++;
457 #endif
458 return (earlycons) ? 0 : -1;
459 }
461 static inline void
462 mark_bsp_online (void)
463 {
464 #ifdef CONFIG_SMP
465 /* If we register an early console, allow CPU 0 to printk */
466 cpu_set(smp_processor_id(), cpu_online_map);
467 #endif
468 }
470 #ifdef CONFIG_SMP
471 static void
472 check_for_logical_procs (void)
473 {
474 pal_logical_to_physical_t info;
475 s64 status;
477 status = ia64_pal_logical_to_phys(0, &info);
478 if (status == -1) {
479 printk(KERN_INFO "No logical to physical processor mapping "
480 "available\n");
481 return;
482 }
483 if (status) {
484 printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n",
485 status);
486 return;
487 }
488 /*
489 * Total number of siblings that BSP has. Though not all of them
490 * may have booted successfully. The correct number of siblings
491 * booted is in info.overview_num_log.
492 */
493 smp_num_siblings = info.overview_tpc;
494 smp_num_cpucores = info.overview_cpp;
495 }
496 #endif
498 void __init
499 #ifdef XEN
500 early_setup_arch (char **cmdline_p)
501 #else
502 setup_arch (char **cmdline_p)
503 #endif
504 {
505 unw_init();
507 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
509 *cmdline_p = __va(ia64_boot_param->command_line);
510 #ifndef XEN
511 strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE);
512 #else
513 early_cmdline_parse(cmdline_p);
514 cmdline_parse(*cmdline_p);
515 #endif
517 efi_init();
518 io_port_init();
520 #ifdef CONFIG_IA64_GENERIC
521 {
522 const char *mvec_name = strstr (*cmdline_p, "machvec=");
523 char str[64];
525 if (mvec_name) {
526 const char *end;
527 size_t len;
529 mvec_name += 8;
530 end = strchr (mvec_name, ' ');
531 if (end)
532 len = end - mvec_name;
533 else
534 len = strlen (mvec_name);
535 len = min(len, sizeof (str) - 1);
536 strlcpy (str, mvec_name, len);
537 mvec_name = str;
538 } else
539 mvec_name = acpi_get_sysname();
540 machvec_init(mvec_name);
541 }
542 #endif
544 if (early_console_setup(*cmdline_p) == 0)
545 mark_bsp_online();
547 #ifdef CONFIG_ACPI_BOOT
548 /* Initialize the ACPI boot-time table parser */
549 acpi_table_init();
550 # ifdef CONFIG_ACPI_NUMA
551 acpi_numa_init();
552 # endif
553 #else
554 # ifdef CONFIG_SMP
555 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */
556 # endif
557 #endif /* CONFIG_APCI_BOOT */
559 #ifdef XEN
560 }
562 void __init
563 late_setup_arch (char **cmdline_p)
564 {
565 #endif
566 #ifndef XEN
567 find_memory();
569 /* process SAL system table: */
570 ia64_sal_init(efi.sal_systab);
571 #endif
573 #ifdef CONFIG_SMP
574 #ifdef XEN
575 init_smp_config ();
576 #endif
578 cpu_physical_id(0) = hard_smp_processor_id();
580 cpu_set(0, cpu_sibling_map[0]);
581 cpu_set(0, cpu_core_map[0]);
583 check_for_logical_procs();
584 if (smp_num_cpucores > 1)
585 printk(KERN_INFO
586 "cpu package is Multi-Core capable: number of cores=%d\n",
587 smp_num_cpucores);
588 if (smp_num_siblings > 1)
589 printk(KERN_INFO
590 "cpu package is Multi-Threading capable: number of siblings=%d\n",
591 smp_num_siblings);
592 #endif
594 cpu_init(); /* initialize the bootstrap CPU */
596 #ifdef CONFIG_ACPI_BOOT
597 acpi_boot_init();
598 #endif
600 #ifdef CONFIG_VT
601 if (!conswitchp) {
602 # if defined(CONFIG_DUMMY_CONSOLE)
603 conswitchp = &dummy_con;
604 # endif
605 # if defined(CONFIG_VGA_CONSOLE)
606 /*
607 * Non-legacy systems may route legacy VGA MMIO range to system
608 * memory. vga_con probes the MMIO hole, so memory looks like
609 * a VGA device to it. The EFI memory map can tell us if it's
610 * memory so we can avoid this problem.
611 */
612 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
613 conswitchp = &vga_con;
614 # endif
615 }
616 #endif
618 /* enable IA-64 Machine Check Abort Handling unless disabled */
619 if (!strstr(saved_command_line, "nomca"))
620 ia64_mca_init();
622 platform_setup(cmdline_p);
623 paging_init();
624 }
626 #ifndef XEN
627 /*
628 * Display cpu info for all cpu's.
629 */
630 static int
631 show_cpuinfo (struct seq_file *m, void *v)
632 {
633 #ifdef CONFIG_SMP
634 # define lpj c->loops_per_jiffy
635 # define cpunum c->cpu
636 #else
637 # define lpj loops_per_jiffy
638 # define cpunum 0
639 #endif
640 static struct {
641 unsigned long mask;
642 const char *feature_name;
643 } feature_bits[] = {
644 { 1UL << 0, "branchlong" },
645 { 1UL << 1, "spontaneous deferral"},
646 { 1UL << 2, "16-byte atomic ops" }
647 };
648 char family[32], features[128], *cp, sep;
649 struct cpuinfo_ia64 *c = v;
650 unsigned long mask;
651 int i;
653 mask = c->features;
655 switch (c->family) {
656 case 0x07: memcpy(family, "Itanium", 8); break;
657 case 0x1f: memcpy(family, "Itanium 2", 10); break;
658 default: snprintf(family, sizeof(family), "%u", c->family); break;
659 }
661 /* build the feature string: */
662 memcpy(features, " standard", 10);
663 cp = features;
664 sep = 0;
665 for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) {
666 if (mask & feature_bits[i].mask) {
667 if (sep)
668 *cp++ = sep;
669 sep = ',';
670 *cp++ = ' ';
671 strlcpy(cp, feature_bits[i].feature_name, sizeof(features));
672 cp += strlen(feature_bits[i].feature_name);
673 mask &= ~feature_bits[i].mask;
674 }
675 }
676 if (mask) {
677 /* print unknown features as a hex value: */
678 if (sep)
679 *cp++ = sep;
680 snprintf(cp, sizeof(features) - (cp - features), " 0x%lx", mask);
681 }
683 seq_printf(m,
684 "processor : %d\n"
685 "vendor : %s\n"
686 "arch : IA-64\n"
687 "family : %s\n"
688 "model : %u\n"
689 "revision : %u\n"
690 "archrev : %u\n"
691 "features :%s\n" /* don't change this---it _is_ right! */
692 "cpu number : %lu\n"
693 "cpu regs : %u\n"
694 "cpu MHz : %lu.%06lu\n"
695 "itc MHz : %lu.%06lu\n"
696 "BogoMIPS : %lu.%02lu\n",
697 cpunum, c->vendor, family, c->model, c->revision, c->archrev,
698 features, c->ppn, c->number,
699 c->proc_freq / 1000000, c->proc_freq % 1000000,
700 c->itc_freq / 1000000, c->itc_freq % 1000000,
701 lpj*HZ/500000, (lpj*HZ/5000) % 100);
702 #ifdef CONFIG_SMP
703 seq_printf(m, "siblings : %u\n", c->num_log);
704 if (c->threads_per_core > 1 || c->cores_per_socket > 1)
705 seq_printf(m,
706 "physical id: %u\n"
707 "core id : %u\n"
708 "thread id : %u\n",
709 c->socket_id, c->core_id, c->thread_id);
710 #endif
711 seq_printf(m,"\n");
713 return 0;
714 }
716 static void *
717 c_start (struct seq_file *m, loff_t *pos)
718 {
719 #ifdef CONFIG_SMP
720 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map))
721 ++*pos;
722 #endif
723 return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
724 }
726 static void *
727 c_next (struct seq_file *m, void *v, loff_t *pos)
728 {
729 ++*pos;
730 return c_start(m, pos);
731 }
733 static void
734 c_stop (struct seq_file *m, void *v)
735 {
736 }
738 struct seq_operations cpuinfo_op = {
739 .start = c_start,
740 .next = c_next,
741 .stop = c_stop,
742 .show = show_cpuinfo
743 };
744 #endif /* XEN */
746 void
747 identify_cpu (struct cpuinfo_ia64 *c)
748 {
749 union {
750 unsigned long bits[5];
751 struct {
752 /* id 0 & 1: */
753 char vendor[16];
755 /* id 2 */
756 u64 ppn; /* processor serial number */
758 /* id 3: */
759 unsigned number : 8;
760 unsigned revision : 8;
761 unsigned model : 8;
762 unsigned family : 8;
763 unsigned archrev : 8;
764 unsigned reserved : 24;
766 /* id 4: */
767 u64 features;
768 } field;
769 } cpuid;
770 pal_vm_info_1_u_t vm1;
771 pal_vm_info_2_u_t vm2;
772 pal_status_t status;
773 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */
774 int i;
776 for (i = 0; i < 5; ++i)
777 cpuid.bits[i] = ia64_get_cpuid(i);
779 memcpy(c->vendor, cpuid.field.vendor, 16);
780 #ifdef CONFIG_SMP
781 c->cpu = smp_processor_id();
783 /* below default values will be overwritten by identify_siblings()
784 * for Multi-Threading/Multi-Core capable cpu's
785 */
786 c->threads_per_core = c->cores_per_socket = c->num_log = 1;
787 c->socket_id = -1;
789 identify_siblings(c);
790 #endif
791 c->ppn = cpuid.field.ppn;
792 c->number = cpuid.field.number;
793 c->revision = cpuid.field.revision;
794 c->model = cpuid.field.model;
795 c->family = cpuid.field.family;
796 c->archrev = cpuid.field.archrev;
797 c->features = cpuid.field.features;
799 status = ia64_pal_vm_summary(&vm1, &vm2);
800 if (status == PAL_STATUS_SUCCESS) {
801 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
802 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
803 }
804 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
805 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
806 }
808 void
809 setup_per_cpu_areas (void)
810 {
811 /* start_kernel() requires this... */
812 }
814 /*
815 * Calculate the max. cache line size.
816 *
817 * In addition, the minimum of the i-cache stride sizes is calculated for
818 * "flush_icache_range()".
819 */
820 static void
821 get_max_cacheline_size (void)
822 {
823 unsigned long line_size, max = 1;
824 u64 l, levels, unique_caches;
825 pal_cache_config_info_t cci;
826 s64 status;
828 status = ia64_pal_cache_summary(&levels, &unique_caches);
829 if (status != 0) {
830 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
831 __FUNCTION__, status);
832 max = SMP_CACHE_BYTES;
833 /* Safest setup for "flush_icache_range()" */
834 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
835 #ifdef XEN
836 ia64_d_cache_stride_shift = D_CACHE_STRIDE_SHIFT;
837 #endif
838 goto out;
839 }
841 for (l = 0; l < levels; ++l) {
842 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2,
843 &cci);
844 if (status != 0) {
845 printk(KERN_ERR
846 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n",
847 __FUNCTION__, l, status);
848 max = SMP_CACHE_BYTES;
849 /* The safest setup for "flush_icache_range()" */
850 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
851 cci.pcci_unified = 1;
852 }
853 #ifdef XEN
854 if (cci.pcci_stride < ia64_d_cache_stride_shift)
855 ia64_d_cache_stride_shift = cci.pcci_stride;
856 #endif
857 line_size = 1 << cci.pcci_line_size;
858 if (line_size > max)
859 max = line_size;
860 if (!cci.pcci_unified) {
861 status = ia64_pal_cache_config_info(l,
862 /* cache_type (instruction)= */ 1,
863 &cci);
864 if (status != 0) {
865 printk(KERN_ERR
866 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n",
867 __FUNCTION__, l, status);
868 /* The safest setup for "flush_icache_range()" */
869 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
870 }
871 }
872 if (cci.pcci_stride < ia64_i_cache_stride_shift)
873 ia64_i_cache_stride_shift = cci.pcci_stride;
874 }
875 out:
876 if (max > ia64_max_cacheline_size)
877 ia64_max_cacheline_size = max;
878 #ifdef XEN
879 if (ia64_d_cache_stride_shift > ia64_i_cache_stride_shift)
880 ia64_d_cache_stride_shift = ia64_i_cache_stride_shift;
881 #endif
883 }
885 /*
886 * cpu_init() initializes state that is per-CPU. This function acts
887 * as a 'CPU state barrier', nothing should get across.
888 */
889 void
890 cpu_init (void)
891 {
892 extern void __devinit ia64_mmu_init (void *);
893 unsigned long num_phys_stacked;
894 #ifndef XEN
895 pal_vm_info_2_u_t vmi;
896 unsigned int max_ctx;
897 #endif
898 struct cpuinfo_ia64 *cpu_info;
899 void *cpu_data;
901 cpu_data = per_cpu_init();
903 #ifdef XEN
904 printk(XENLOG_DEBUG "cpu_init: current=%p\n", current);
905 #endif
907 /*
908 * We set ar.k3 so that assembly code in MCA handler can compute
909 * physical addresses of per cpu variables with a simple:
910 * phys = ar.k3 + &per_cpu_var
911 */
912 ia64_set_kr(IA64_KR_PER_CPU_DATA,
913 ia64_tpa(cpu_data) - (long) __per_cpu_start);
915 get_max_cacheline_size();
917 /*
918 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
919 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it
920 * depends on the data returned by identify_cpu(). We break the dependency by
921 * accessing cpu_data() through the canonical per-CPU address.
922 */
923 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start);
924 identify_cpu(cpu_info);
926 #ifdef CONFIG_MCKINLEY
927 {
928 # define FEATURE_SET 16
929 struct ia64_pal_retval iprv;
931 if (cpu_info->family == 0x1f) {
932 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
933 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
934 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
935 (iprv.v1 | 0x80), FEATURE_SET, 0);
936 }
937 }
938 #endif
940 /* Clear the stack memory reserved for pt_regs: */
941 memset(ia64_task_regs(current), 0, sizeof(struct pt_regs));
943 ia64_set_kr(IA64_KR_FPU_OWNER, 0);
945 /*
946 * Initialize the page-table base register to a global
947 * directory with all zeroes. This ensure that we can handle
948 * TLB-misses to user address-space even before we created the
949 * first user address-space. This may happen, e.g., due to
950 * aggressive use of lfetch.fault.
951 */
952 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page)));
954 /*
955 * Initialize default control register to defer speculative faults except
956 * for those arising from TLB misses, which are not deferred. The
957 * kernel MUST NOT depend on a particular setting of these bits (in other words,
958 * the kernel must have recovery code for all speculative accesses). Turn on
959 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps
960 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
961 * be fine).
962 */
963 #ifdef XEN
964 ia64_setreg(_IA64_REG_CR_DCR, IA64_DEFAULT_DCR_BITS);
965 #else
966 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
967 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
968 #endif
969 #ifndef XEN
970 atomic_inc(&init_mm.mm_count);
971 current->active_mm = &init_mm;
972 #endif
973 #ifndef XEN
974 if (current->mm)
975 BUG();
976 #endif
979 #ifdef XEN
980 ia64_fph_enable();
981 __ia64_init_fpu();
982 #endif
984 ia64_mmu_init(ia64_imva(cpu_data));
985 ia64_mca_cpu_init(ia64_imva(cpu_data));
987 #ifdef CONFIG_IA32_SUPPORT
988 ia32_cpu_init();
989 #endif
991 /* Clear ITC to eliminiate sched_clock() overflows in human time. */
992 ia64_set_itc(0);
994 /* disable all local interrupt sources: */
995 ia64_set_itv(1 << 16);
996 ia64_set_lrr0(1 << 16);
997 ia64_set_lrr1(1 << 16);
998 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
999 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
1001 /* clear TPR & XTP to enable all interrupt classes: */
1002 ia64_setreg(_IA64_REG_CR_TPR, 0);
1003 #ifdef CONFIG_SMP
1004 normal_xtp();
1005 #endif
1007 #ifndef XEN
1008 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
1009 if (ia64_pal_vm_summary(NULL, &vmi) == 0)
1010 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
1011 else {
1012 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
1013 max_ctx = (1U << 15) - 1; /* use architected minimum */
1015 while (max_ctx < ia64_ctx.max_ctx) {
1016 unsigned int old = ia64_ctx.max_ctx;
1017 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
1018 break;
1020 #endif
1022 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) {
1023 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
1024 "stacked regs\n");
1025 num_phys_stacked = 96;
1027 /* size of physical stacked register partition plus 8 bytes: */
1028 __get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8;
1029 platform_cpu_init();
1030 #ifndef XEN
1031 pm_idle = default_idle;
1032 #endif
1034 #ifdef XEN
1035 /* surrender usage of kernel registers to domain, use percpu area instead */
1036 __get_cpu_var(cpu_kr)._kr[IA64_KR_IO_BASE] = ia64_get_kr(IA64_KR_IO_BASE);
1037 __get_cpu_var(cpu_kr)._kr[IA64_KR_PER_CPU_DATA] = ia64_get_kr(IA64_KR_PER_CPU_DATA);
1038 __get_cpu_var(cpu_kr)._kr[IA64_KR_CURRENT_STACK] = ia64_get_kr(IA64_KR_CURRENT_STACK);
1039 __get_cpu_var(cpu_kr)._kr[IA64_KR_FPU_OWNER] = ia64_get_kr(IA64_KR_FPU_OWNER);
1040 __get_cpu_var(cpu_kr)._kr[IA64_KR_CURRENT] = ia64_get_kr(IA64_KR_CURRENT);
1041 __get_cpu_var(cpu_kr)._kr[IA64_KR_PT_BASE] = ia64_get_kr(IA64_KR_PT_BASE);
1042 #endif
1045 #ifndef XEN
1046 void
1047 check_bugs (void)
1049 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
1050 (unsigned long) __end___mckinley_e9_bundles);
1052 #endif