ia64/xen-unstable

view xen/arch/ia64/vmx/vmx_ivt.S @ 9766:ffba1376c4fb

[IA64] Use16M page size in identity mapping

Signed-off-by: Anthony Xu <anthony.xu@intel.com>
author awilliam@xenbuild.aw
date Tue Apr 25 22:10:05 2006 -0600 (2006-04-25)
parents f6e8c269f6af
children 4174856876f9
line source
1 /*
2 * arch/ia64/kernel/vmx_ivt.S
3 *
4 * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
5 * Stephane Eranian <eranian@hpl.hp.com>
6 * David Mosberger <davidm@hpl.hp.com>
7 * Copyright (C) 2000, 2002-2003 Intel Co
8 * Asit Mallick <asit.k.mallick@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Kenneth Chen <kenneth.w.chen@intel.com>
11 * Fenghua Yu <fenghua.yu@intel.com>
12 *
13 *
14 * 00/08/23 Asit Mallick <asit.k.mallick@intel.com> TLB handling for SMP
15 * 00/12/20 David Mosberger-Tang <davidm@hpl.hp.com> DTLB/ITLB handler now uses virtual PT.
16 *
17 * 05/3/20 Xuefei Xu (Anthony Xu) (anthony.xu@intel.com)
18 * Supporting Intel virtualization architecture
19 *
20 */
22 /*
23 * This file defines the interruption vector table used by the CPU.
24 * It does not include one entry per possible cause of interruption.
25 *
26 * The first 20 entries of the table contain 64 bundles each while the
27 * remaining 48 entries contain only 16 bundles each.
28 *
29 * The 64 bundles are used to allow inlining the whole handler for critical
30 * interruptions like TLB misses.
31 *
32 * For each entry, the comment is as follows:
33 *
34 * // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
35 * entry offset ----/ / / / /
36 * entry number ---------/ / / /
37 * size of the entry -------------/ / /
38 * vector name -------------------------------------/ /
39 * interruptions triggering this vector ----------------------/
40 *
41 * The table is 32KB in size and must be aligned on 32KB boundary.
42 * (The CPU ignores the 15 lower bits of the address)
43 *
44 * Table is based upon EAS2.6 (Oct 1999)
45 */
47 #include <linux/config.h>
49 #include <asm/asmmacro.h>
50 #include <asm/break.h>
51 #include <asm/ia32.h>
52 #include <asm/kregs.h>
53 #include <asm/offsets.h>
54 #include <asm/pgtable.h>
55 #include <asm/processor.h>
56 #include <asm/ptrace.h>
57 #include <asm/system.h>
58 #include <asm/thread_info.h>
59 #include <asm/unistd.h>
60 #include <asm/vhpt.h>
62 #ifdef VTI_DEBUG
63 /*
64 * This lets you track the last eight faults that occurred on the CPU. Make sure ar.k2 isn't
65 * needed for something else before enabling this...
66 */
67 #define VMX_DBG_FAULT(i) \
68 add r16=IVT_CUR_OFS,r21; \
69 add r17=IVT_DBG_OFS,r21;; \
70 ld8 r18=[r16];; \
71 add r17=r18,r17; \
72 mov r19=cr.iip; \
73 mov r20=cr.ipsr; \
74 mov r22=cr.ifa; \
75 mov r23=i;; \
76 st8 [r17]=r19,8; \
77 add r18=32,r18;; \
78 st8 [r17]=r20,8; \
79 mov r19=0xfe0;; \
80 st8 [r17]=r22,8; \
81 and r18=r19,r18;; \
82 st8 [r17]=r23; \
83 st8 [r16]=r18;; \
84 //# define VMX_DBG_FAULT(i) mov r16=ar.k2;; shl r16=r16,8;; add r16=(i),r16;;mov ar.k2=r16
85 #else
86 # define VMX_DBG_FAULT(i)
87 #endif
89 #include "vmx_minstate.h"
93 #define VMX_FAULT(n) \
94 vmx_fault_##n:; \
95 br.sptk vmx_fault_##n; \
96 ;; \
99 #define VMX_REFLECT(n) \
100 mov r31=pr; \
101 mov r19=n; /* prepare to save predicates */ \
102 mov r29=cr.ipsr; \
103 ;; \
104 tbit.z p6,p7=r29,IA64_PSR_VM_BIT; \
105 (p7) br.sptk.many vmx_dispatch_reflection; \
106 VMX_FAULT(n); \
109 GLOBAL_ENTRY(vmx_panic)
110 br.sptk.many vmx_panic
111 ;;
112 END(vmx_panic)
118 .section .text.ivt,"ax"
120 .align 32768 // align on 32KB boundary
121 .global vmx_ia64_ivt
122 vmx_ia64_ivt:
123 /////////////////////////////////////////////////////////////////////////////////////////
124 // 0x0000 Entry 0 (size 64 bundles) VHPT Translation (8,20,47)
125 ENTRY(vmx_vhpt_miss)
126 VMX_DBG_FAULT(0)
127 VMX_FAULT(0)
128 END(vmx_vhpt_miss)
130 .org vmx_ia64_ivt+0x400
131 /////////////////////////////////////////////////////////////////////////////////////////
132 // 0x0400 Entry 1 (size 64 bundles) ITLB (21)
133 ENTRY(vmx_itlb_miss)
134 VMX_DBG_FAULT(1)
135 mov r31 = pr
136 mov r29=cr.ipsr;
137 ;;
138 tbit.z p6,p7=r29,IA64_PSR_VM_BIT;
139 (p6) br.sptk vmx_alt_itlb_miss_1
140 //(p6) br.sptk vmx_fault_1
141 mov r16 = cr.ifa
142 ;;
143 thash r17 = r16
144 ;;
145 ttag r20 = r16
146 ;;
147 vmx_itlb_loop:
148 cmp.eq p6,p0 = r0, r17
149 (p6) br vmx_itlb_out
150 ;;
151 adds r22 = VLE_TITAG_OFFSET, r17
152 adds r23 = VLE_CCHAIN_OFFSET, r17
153 ;;
154 ld8 r24 = [r22]
155 ld8 r25 = [r23]
156 ;;
157 lfetch [r25]
158 cmp.eq p6,p7 = r20, r24
159 ;;
160 (p7) mov r17 = r25;
161 (p7) br.sptk vmx_itlb_loop
162 ;;
163 adds r23 = VLE_PGFLAGS_OFFSET, r17
164 adds r24 = VLE_ITIR_OFFSET, r17
165 ;;
166 ld8 r26 = [r23]
167 ld8 r25 = [r24]
168 ;;
169 mov cr.itir = r25
170 ;;
171 itc.i r26
172 ;;
173 srlz.i
174 ;;
175 mov r23=r31
176 mov r22=b0
177 adds r16=IA64_VPD_BASE_OFFSET,r21
178 ;;
179 ld8 r18=[r16]
180 ;;
181 adds r19=VPD(VPSR),r18
182 movl r20=__vsa_base
183 ;;
184 ld8 r19=[r19]
185 ld8 r20=[r20]
186 ;;
187 br.sptk ia64_vmm_entry
188 ;;
189 vmx_itlb_out:
190 mov r19 = 1
191 br.sptk vmx_dispatch_tlb_miss
192 VMX_FAULT(1);
193 END(vmx_itlb_miss)
195 .org vmx_ia64_ivt+0x0800
196 /////////////////////////////////////////////////////////////////////////////////////////
197 // 0x0800 Entry 2 (size 64 bundles) DTLB (9,48)
198 ENTRY(vmx_dtlb_miss)
199 VMX_DBG_FAULT(2)
200 mov r31 = pr
201 mov r29=cr.ipsr;
202 ;;
203 tbit.z p6,p7=r29,IA64_PSR_VM_BIT;
204 (p6)br.sptk vmx_alt_dtlb_miss_1
205 //(p6)br.sptk vmx_fault_2
206 mov r16 = cr.ifa
207 ;;
208 thash r17 = r16
209 ;;
210 ttag r20 = r16
211 ;;
212 vmx_dtlb_loop:
213 cmp.eq p6,p0 = r0, r17
214 (p6)br vmx_dtlb_out
215 ;;
216 adds r22 = VLE_TITAG_OFFSET, r17
217 adds r23 = VLE_CCHAIN_OFFSET, r17
218 ;;
219 ld8 r24 = [r22]
220 ld8 r25 = [r23]
221 ;;
222 lfetch [r25]
223 cmp.eq p6,p7 = r20, r24
224 ;;
225 (p7)mov r17 = r25;
226 (p7)br.sptk vmx_dtlb_loop
227 ;;
228 adds r23 = VLE_PGFLAGS_OFFSET, r17
229 adds r24 = VLE_ITIR_OFFSET, r17
230 ;;
231 ld8 r26 = [r23]
232 ld8 r25 = [r24]
233 ;;
234 mov cr.itir = r25
235 ;;
236 itc.d r26
237 ;;
238 srlz.d;
239 ;;
240 mov r23=r31
241 mov r22=b0
242 adds r16=IA64_VPD_BASE_OFFSET,r21
243 ;;
244 ld8 r18=[r16]
245 ;;
246 adds r19=VPD(VPSR),r18
247 movl r20=__vsa_base
248 ;;
249 ld8 r19=[r19]
250 ld8 r20=[r20]
251 ;;
252 br.sptk ia64_vmm_entry
253 ;;
254 vmx_dtlb_out:
255 mov r19 = 2
256 br.sptk vmx_dispatch_tlb_miss
257 VMX_FAULT(2);
258 END(vmx_dtlb_miss)
260 .org vmx_ia64_ivt+0x0c00
261 /////////////////////////////////////////////////////////////////////////////////////////
262 // 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19)
263 ENTRY(vmx_alt_itlb_miss)
264 VMX_DBG_FAULT(3)
265 mov r31 = pr
266 mov r29=cr.ipsr;
267 ;;
268 tbit.z p6,p7=r29,IA64_PSR_VM_BIT;
269 (p7)br.spnt vmx_fault_3
270 vmx_alt_itlb_miss_1:
271 mov r16=cr.ifa // get address that caused the TLB miss
272 ;;
273 tbit.z p6,p7=r16,63
274 (p6)br.spnt vmx_fault_3
275 ;;
276 movl r17=PAGE_KERNEL
277 mov r24=cr.ipsr
278 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
279 ;;
280 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
281 shr.u r18=r16,55 // move address bit 59 to bit 4
282 ;;
283 and r18=0x10,r18 // bit 4=address-bit(61)
284 or r19=r17,r19 // insert PTE control bits into r19
285 ;;
286 movl r20=IA64_GRANULE_SHIFT<<2
287 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6
288 ;;
289 mov cr.itir=r20
290 ;;
291 srlz.i
292 ;;
293 itc.i r19 // insert the TLB entry
294 mov pr=r31,-1
295 rfi
296 VMX_FAULT(3);
297 END(vmx_alt_itlb_miss)
300 .org vmx_ia64_ivt+0x1000
301 /////////////////////////////////////////////////////////////////////////////////////////
302 // 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46)
303 ENTRY(vmx_alt_dtlb_miss)
304 VMX_DBG_FAULT(4)
305 mov r31=pr
306 mov r29=cr.ipsr;
307 ;;
308 tbit.z p6,p7=r29,IA64_PSR_VM_BIT;
309 (p7)br.spnt vmx_fault_4
310 vmx_alt_dtlb_miss_1:
311 mov r16=cr.ifa // get address that caused the TLB miss
312 ;;
313 #ifdef CONFIG_VIRTUAL_FRAME_TABLE
314 // Test for the address of virtual frame_table
315 shr r22=r16,56;;
316 cmp.eq p8,p0=((VIRT_FRAME_TABLE_ADDR>>56)&0xff)-0x100,r22
317 (p8) br.cond.sptk frametable_miss ;;
318 #endif
319 tbit.z p6,p7=r16,63
320 (p6)br.spnt vmx_fault_4
321 ;;
322 movl r17=PAGE_KERNEL
323 mov r20=cr.isr
324 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
325 mov r24=cr.ipsr
326 ;;
327 and r22=IA64_ISR_CODE_MASK,r20 // get the isr.code field
328 tbit.nz p6,p7=r20,IA64_ISR_SP_BIT // is speculation bit on?
329 shr.u r18=r16,55 // move address bit 59 to bit 4
330 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
331 tbit.nz p9,p0=r20,IA64_ISR_NA_BIT // is non-access bit on?
332 ;;
333 and r18=0x10,r18 // bit 4=address-bit(61)
334 (p9) cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22 // check isr.code field
335 dep r24=-1,r24,IA64_PSR_ED_BIT,1
336 or r19=r19,r17 // insert PTE control bits into r19
337 ;;
338 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6
339 (p6) mov cr.ipsr=r24
340 movl r20=IA64_GRANULE_SHIFT<<2
341 ;;
342 mov cr.itir=r20
343 ;;
344 srlz.i
345 ;;
346 (p7) itc.d r19 // insert the TLB entry
347 mov pr=r31,-1
348 rfi
349 VMX_FAULT(4);
350 END(vmx_alt_dtlb_miss)
352 .org vmx_ia64_ivt+0x1400
353 /////////////////////////////////////////////////////////////////////////////////////////
354 // 0x1400 Entry 5 (size 64 bundles) Data nested TLB (6,45)
355 ENTRY(vmx_nested_dtlb_miss)
356 VMX_DBG_FAULT(5)
357 VMX_FAULT(5)
358 END(vmx_nested_dtlb_miss)
360 .org vmx_ia64_ivt+0x1800
361 /////////////////////////////////////////////////////////////////////////////////////////
362 // 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24)
363 ENTRY(vmx_ikey_miss)
364 VMX_DBG_FAULT(6)
365 VMX_REFLECT(6)
366 END(vmx_ikey_miss)
368 .org vmx_ia64_ivt+0x1c00
369 /////////////////////////////////////////////////////////////////////////////////////////
370 // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
371 ENTRY(vmx_dkey_miss)
372 VMX_DBG_FAULT(7)
373 VMX_REFLECT(7)
374 END(vmx_dkey_miss)
376 .org vmx_ia64_ivt+0x2000
377 /////////////////////////////////////////////////////////////////////////////////////////
378 // 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54)
379 ENTRY(vmx_dirty_bit)
380 VMX_DBG_FAULT(8)
381 VMX_REFLECT(8)
382 END(vmx_idirty_bit)
384 .org vmx_ia64_ivt+0x2400
385 /////////////////////////////////////////////////////////////////////////////////////////
386 // 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27)
387 ENTRY(vmx_iaccess_bit)
388 VMX_DBG_FAULT(9)
389 VMX_REFLECT(9)
390 END(vmx_iaccess_bit)
392 .org vmx_ia64_ivt+0x2800
393 /////////////////////////////////////////////////////////////////////////////////////////
394 // 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55)
395 ENTRY(vmx_daccess_bit)
396 VMX_DBG_FAULT(10)
397 VMX_REFLECT(10)
398 END(vmx_daccess_bit)
400 .org vmx_ia64_ivt+0x2c00
401 /////////////////////////////////////////////////////////////////////////////////////////
402 // 0x2c00 Entry 11 (size 64 bundles) Break instruction (33)
403 ENTRY(vmx_break_fault)
404 VMX_DBG_FAULT(11)
405 mov r31=pr
406 mov r19=11
407 mov r30=cr.iim
408 movl r29=0x1100
409 ;;
410 #ifdef VTI_DEBUG
411 // break 0 is already handled in vmx_ia64_handle_break.
412 cmp.eq p6,p7=r30,r0
413 (p6) br.sptk vmx_fault_11
414 ;;
415 #endif
416 cmp.eq p6,p7=r29,r30
417 (p6) br.dptk.few vmx_hypercall_dispatch
418 (p7) br.sptk.many vmx_dispatch_break_fault
419 ;;
420 VMX_FAULT(11);
421 END(vmx_break_fault)
423 .org vmx_ia64_ivt+0x3000
424 /////////////////////////////////////////////////////////////////////////////////////////
425 // 0x3000 Entry 12 (size 64 bundles) External Interrupt (4)
426 ENTRY(vmx_interrupt)
427 // VMX_DBG_FAULT(12)
428 mov r31=pr // prepare to save predicates
429 mov r19=12
430 mov r29=cr.ipsr
431 ;;
432 tbit.z p6,p7=r29,IA64_PSR_VM_BIT
433 tbit.z p0,p15=r29,IA64_PSR_I_BIT
434 ;;
435 (p7) br.sptk vmx_dispatch_interrupt
436 ;;
437 mov r27=ar.rsc /* M */
438 mov r20=r1 /* A */
439 mov r25=ar.unat /* M */
440 mov r26=ar.pfs /* I */
441 mov r28=cr.iip /* M */
442 cover /* B (or nothing) */
443 ;;
444 mov r1=sp
445 ;;
446 invala /* M */
447 mov r30=cr.ifs
448 ;;
449 addl r1=-IA64_PT_REGS_SIZE,r1
450 ;;
451 adds r17=2*L1_CACHE_BYTES,r1 /* really: biggest cache-line size */
452 adds r16=PT(CR_IPSR),r1
453 ;;
454 lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES
455 st8 [r16]=r29 /* save cr.ipsr */
456 ;;
457 lfetch.fault.excl.nt1 [r17]
458 mov r29=b0
459 ;;
460 adds r16=PT(R8),r1 /* initialize first base pointer */
461 adds r17=PT(R9),r1 /* initialize second base pointer */
462 mov r18=r0 /* make sure r18 isn't NaT */
463 ;;
464 .mem.offset 0,0; st8.spill [r16]=r8,16
465 .mem.offset 8,0; st8.spill [r17]=r9,16
466 ;;
467 .mem.offset 0,0; st8.spill [r16]=r10,24
468 .mem.offset 8,0; st8.spill [r17]=r11,24
469 ;;
470 st8 [r16]=r28,16 /* save cr.iip */
471 st8 [r17]=r30,16 /* save cr.ifs */
472 mov r8=ar.fpsr /* M */
473 mov r9=ar.csd
474 mov r10=ar.ssd
475 movl r11=FPSR_DEFAULT /* L-unit */
476 ;;
477 st8 [r16]=r25,16 /* save ar.unat */
478 st8 [r17]=r26,16 /* save ar.pfs */
479 shl r18=r18,16 /* compute ar.rsc to be used for "loadrs" */
480 ;;
481 st8 [r16]=r27,16 /* save ar.rsc */
482 adds r17=16,r17 /* skip over ar_rnat field */
483 ;; /* avoid RAW on r16 & r17 */
484 st8 [r17]=r31,16 /* save predicates */
485 adds r16=16,r16 /* skip over ar_bspstore field */
486 ;;
487 st8 [r16]=r29,16 /* save b0 */
488 st8 [r17]=r18,16 /* save ar.rsc value for "loadrs" */
489 ;;
490 .mem.offset 0,0; st8.spill [r16]=r20,16 /* save original r1 */
491 .mem.offset 8,0; st8.spill [r17]=r12,16
492 adds r12=-16,r1 /* switch to kernel memory stack (with 16 bytes of scratch) */
493 ;;
494 .mem.offset 0,0; st8.spill [r16]=r13,16
495 .mem.offset 8,0; st8.spill [r17]=r8,16 /* save ar.fpsr */
496 mov r13=r21 /* establish `current' */
497 ;;
498 .mem.offset 0,0; st8.spill [r16]=r15,16
499 .mem.offset 8,0; st8.spill [r17]=r14,16
500 dep r14=-1,r0,60,4
501 ;;
502 .mem.offset 0,0; st8.spill [r16]=r2,16
503 .mem.offset 8,0; st8.spill [r17]=r3,16
504 adds r2=IA64_PT_REGS_R16_OFFSET,r1
505 ;;
506 mov r8=ar.ccv
507 movl r1=__gp /* establish kernel global pointer */
508 ;; \
509 bsw.1
510 ;;
511 alloc r14=ar.pfs,0,0,2,0 // must be first in an insn group
512 mov out0=cr.ivr // pass cr.ivr as first arg
513 add out1=16,sp // pass pointer to pt_regs as second arg
515 ssm psr.ic
516 ;;
517 srlz.i
518 ;;
519 (p15) ssm psr.i
520 adds r3=8,r2 // set up second base pointer for SAVE_REST
521 srlz.i // ensure everybody knows psr.ic is back on
522 ;;
523 .mem.offset 0,0; st8.spill [r2]=r16,16
524 .mem.offset 8,0; st8.spill [r3]=r17,16
525 ;;
526 .mem.offset 0,0; st8.spill [r2]=r18,16
527 .mem.offset 8,0; st8.spill [r3]=r19,16
528 ;;
529 .mem.offset 0,0; st8.spill [r2]=r20,16
530 .mem.offset 8,0; st8.spill [r3]=r21,16
531 mov r18=b6
532 ;;
533 .mem.offset 0,0; st8.spill [r2]=r22,16
534 .mem.offset 8,0; st8.spill [r3]=r23,16
535 mov r19=b7
536 ;;
537 .mem.offset 0,0; st8.spill [r2]=r24,16
538 .mem.offset 8,0; st8.spill [r3]=r25,16
539 ;;
540 .mem.offset 0,0; st8.spill [r2]=r26,16
541 .mem.offset 8,0; st8.spill [r3]=r27,16
542 ;;
543 .mem.offset 0,0; st8.spill [r2]=r28,16
544 .mem.offset 8,0; st8.spill [r3]=r29,16
545 ;;
546 .mem.offset 0,0; st8.spill [r2]=r30,16
547 .mem.offset 8,0; st8.spill [r3]=r31,32
548 ;;
549 mov ar.fpsr=r11 /* M-unit */
550 st8 [r2]=r8,8 /* ar.ccv */
551 adds r24=PT(B6)-PT(F7),r3
552 ;;
553 stf.spill [r2]=f6,32
554 stf.spill [r3]=f7,32
555 ;;
556 stf.spill [r2]=f8,32
557 stf.spill [r3]=f9,32
558 ;;
559 stf.spill [r2]=f10
560 stf.spill [r3]=f11
561 adds r25=PT(B7)-PT(F11),r3
562 ;;
563 st8 [r24]=r18,16 /* b6 */
564 st8 [r25]=r19,16 /* b7 */
565 ;;
566 st8 [r24]=r9 /* ar.csd */
567 st8 [r25]=r10 /* ar.ssd */
568 ;;
569 srlz.d // make sure we see the effect of cr.ivr
570 movl r14=ia64_leave_nested
571 ;;
572 mov rp=r14
573 br.call.sptk.many b6=ia64_handle_irq
574 ;;
575 END(vmx_interrupt)
577 .org vmx_ia64_ivt+0x3400
578 /////////////////////////////////////////////////////////////////////////////////////////
579 // 0x3400 Entry 13 (size 64 bundles) Reserved
580 ENTRY(vmx_virtual_exirq)
581 VMX_DBG_FAULT(13)
582 mov r31=pr
583 mov r19=13
584 br.sptk vmx_dispatch_vexirq
585 END(vmx_virtual_exirq)
587 .org vmx_ia64_ivt+0x3800
588 /////////////////////////////////////////////////////////////////////////////////////////
589 // 0x3800 Entry 14 (size 64 bundles) Reserved
590 VMX_DBG_FAULT(14)
591 VMX_FAULT(14)
594 .org vmx_ia64_ivt+0x3c00
595 /////////////////////////////////////////////////////////////////////////////////////////
596 // 0x3c00 Entry 15 (size 64 bundles) Reserved
597 VMX_DBG_FAULT(15)
598 VMX_FAULT(15)
601 .org vmx_ia64_ivt+0x4000
602 /////////////////////////////////////////////////////////////////////////////////////////
603 // 0x4000 Entry 16 (size 64 bundles) Reserved
604 VMX_DBG_FAULT(16)
605 VMX_FAULT(16)
607 .org vmx_ia64_ivt+0x4400
608 /////////////////////////////////////////////////////////////////////////////////////////
609 // 0x4400 Entry 17 (size 64 bundles) Reserved
610 VMX_DBG_FAULT(17)
611 VMX_FAULT(17)
613 .org vmx_ia64_ivt+0x4800
614 /////////////////////////////////////////////////////////////////////////////////////////
615 // 0x4800 Entry 18 (size 64 bundles) Reserved
616 VMX_DBG_FAULT(18)
617 VMX_FAULT(18)
619 .org vmx_ia64_ivt+0x4c00
620 /////////////////////////////////////////////////////////////////////////////////////////
621 // 0x4c00 Entry 19 (size 64 bundles) Reserved
622 VMX_DBG_FAULT(19)
623 VMX_FAULT(19)
625 .org vmx_ia64_ivt+0x5000
626 /////////////////////////////////////////////////////////////////////////////////////////
627 // 0x5000 Entry 20 (size 16 bundles) Page Not Present
628 ENTRY(vmx_page_not_present)
629 VMX_DBG_FAULT(20)
630 VMX_REFLECT(20)
631 END(vmx_page_not_present)
633 .org vmx_ia64_ivt+0x5100
634 /////////////////////////////////////////////////////////////////////////////////////////
635 // 0x5100 Entry 21 (size 16 bundles) Key Permission vector
636 ENTRY(vmx_key_permission)
637 VMX_DBG_FAULT(21)
638 VMX_REFLECT(21)
639 END(vmx_key_permission)
641 .org vmx_ia64_ivt+0x5200
642 /////////////////////////////////////////////////////////////////////////////////////////
643 // 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26)
644 ENTRY(vmx_iaccess_rights)
645 VMX_DBG_FAULT(22)
646 VMX_REFLECT(22)
647 END(vmx_iaccess_rights)
649 .org vmx_ia64_ivt+0x5300
650 /////////////////////////////////////////////////////////////////////////////////////////
651 // 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53)
652 ENTRY(vmx_daccess_rights)
653 VMX_DBG_FAULT(23)
654 VMX_REFLECT(23)
655 END(vmx_daccess_rights)
657 .org vmx_ia64_ivt+0x5400
658 /////////////////////////////////////////////////////////////////////////////////////////
659 // 0x5400 Entry 24 (size 16 bundles) General Exception (5,32,34,36,38,39)
660 ENTRY(vmx_general_exception)
661 VMX_DBG_FAULT(24)
662 VMX_REFLECT(24)
663 // VMX_FAULT(24)
664 END(vmx_general_exception)
666 .org vmx_ia64_ivt+0x5500
667 /////////////////////////////////////////////////////////////////////////////////////////
668 // 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35)
669 ENTRY(vmx_disabled_fp_reg)
670 VMX_DBG_FAULT(25)
671 VMX_REFLECT(25)
672 END(vmx_disabled_fp_reg)
674 .org vmx_ia64_ivt+0x5600
675 /////////////////////////////////////////////////////////////////////////////////////////
676 // 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50)
677 ENTRY(vmx_nat_consumption)
678 VMX_DBG_FAULT(26)
679 VMX_REFLECT(26)
680 END(vmx_nat_consumption)
682 .org vmx_ia64_ivt+0x5700
683 /////////////////////////////////////////////////////////////////////////////////////////
684 // 0x5700 Entry 27 (size 16 bundles) Speculation (40)
685 ENTRY(vmx_speculation_vector)
686 VMX_DBG_FAULT(27)
687 VMX_REFLECT(27)
688 END(vmx_speculation_vector)
690 .org vmx_ia64_ivt+0x5800
691 /////////////////////////////////////////////////////////////////////////////////////////
692 // 0x5800 Entry 28 (size 16 bundles) Reserved
693 VMX_DBG_FAULT(28)
694 VMX_FAULT(28)
696 .org vmx_ia64_ivt+0x5900
697 /////////////////////////////////////////////////////////////////////////////////////////
698 // 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56)
699 ENTRY(vmx_debug_vector)
700 VMX_DBG_FAULT(29)
701 VMX_FAULT(29)
702 END(vmx_debug_vector)
704 .org vmx_ia64_ivt+0x5a00
705 /////////////////////////////////////////////////////////////////////////////////////////
706 // 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57)
707 ENTRY(vmx_unaligned_access)
708 VMX_DBG_FAULT(30)
709 VMX_REFLECT(30)
710 END(vmx_unaligned_access)
712 .org vmx_ia64_ivt+0x5b00
713 /////////////////////////////////////////////////////////////////////////////////////////
714 // 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57)
715 ENTRY(vmx_unsupported_data_reference)
716 VMX_DBG_FAULT(31)
717 VMX_REFLECT(31)
718 END(vmx_unsupported_data_reference)
720 .org vmx_ia64_ivt+0x5c00
721 /////////////////////////////////////////////////////////////////////////////////////////
722 // 0x5c00 Entry 32 (size 16 bundles) Floating-Point Fault (64)
723 ENTRY(vmx_floating_point_fault)
724 VMX_DBG_FAULT(32)
725 VMX_REFLECT(32)
726 END(vmx_floating_point_fault)
728 .org vmx_ia64_ivt+0x5d00
729 /////////////////////////////////////////////////////////////////////////////////////////
730 // 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66)
731 ENTRY(vmx_floating_point_trap)
732 VMX_DBG_FAULT(33)
733 VMX_REFLECT(33)
734 END(vmx_floating_point_trap)
736 .org vmx_ia64_ivt+0x5e00
737 /////////////////////////////////////////////////////////////////////////////////////////
738 // 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Transfer Trap (66)
739 ENTRY(vmx_lower_privilege_trap)
740 VMX_DBG_FAULT(34)
741 VMX_REFLECT(34)
742 END(vmx_lower_privilege_trap)
744 .org vmx_ia64_ivt+0x5f00
745 /////////////////////////////////////////////////////////////////////////////////////////
746 // 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68)
747 ENTRY(vmx_taken_branch_trap)
748 VMX_DBG_FAULT(35)
749 VMX_REFLECT(35)
750 END(vmx_taken_branch_trap)
752 .org vmx_ia64_ivt+0x6000
753 /////////////////////////////////////////////////////////////////////////////////////////
754 // 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69)
755 ENTRY(vmx_single_step_trap)
756 VMX_DBG_FAULT(36)
757 VMX_REFLECT(36)
758 END(vmx_single_step_trap)
760 .org vmx_ia64_ivt+0x6100
761 /////////////////////////////////////////////////////////////////////////////////////////
762 // 0x6100 Entry 37 (size 16 bundles) Virtualization Fault
763 ENTRY(vmx_virtualization_fault)
764 // VMX_DBG_FAULT(37)
765 mov r31=pr
766 mov r19=37
767 adds r16 = IA64_VCPU_CAUSE_OFFSET,r21
768 adds r17 = IA64_VCPU_OPCODE_OFFSET,r21
769 ;;
770 st8 [r16] = r24
771 st8 [r17] = r25
772 ;;
773 br.sptk vmx_dispatch_virtualization_fault
774 END(vmx_virtualization_fault)
776 .org vmx_ia64_ivt+0x6200
777 /////////////////////////////////////////////////////////////////////////////////////////
778 // 0x6200 Entry 38 (size 16 bundles) Reserved
779 VMX_DBG_FAULT(38)
780 VMX_FAULT(38)
782 .org vmx_ia64_ivt+0x6300
783 /////////////////////////////////////////////////////////////////////////////////////////
784 // 0x6300 Entry 39 (size 16 bundles) Reserved
785 VMX_DBG_FAULT(39)
786 VMX_FAULT(39)
788 .org vmx_ia64_ivt+0x6400
789 /////////////////////////////////////////////////////////////////////////////////////////
790 // 0x6400 Entry 40 (size 16 bundles) Reserved
791 VMX_DBG_FAULT(40)
792 VMX_FAULT(40)
794 .org vmx_ia64_ivt+0x6500
795 /////////////////////////////////////////////////////////////////////////////////////////
796 // 0x6500 Entry 41 (size 16 bundles) Reserved
797 VMX_DBG_FAULT(41)
798 VMX_FAULT(41)
800 .org vmx_ia64_ivt+0x6600
801 /////////////////////////////////////////////////////////////////////////////////////////
802 // 0x6600 Entry 42 (size 16 bundles) Reserved
803 VMX_DBG_FAULT(42)
804 VMX_FAULT(42)
806 .org vmx_ia64_ivt+0x6700
807 /////////////////////////////////////////////////////////////////////////////////////////
808 // 0x6700 Entry 43 (size 16 bundles) Reserved
809 VMX_DBG_FAULT(43)
810 VMX_FAULT(43)
812 .org vmx_ia64_ivt+0x6800
813 /////////////////////////////////////////////////////////////////////////////////////////
814 // 0x6800 Entry 44 (size 16 bundles) Reserved
815 VMX_DBG_FAULT(44)
816 VMX_FAULT(44)
818 .org vmx_ia64_ivt+0x6900
819 /////////////////////////////////////////////////////////////////////////////////////////
820 // 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,44,58,60,61,62,72,73,75,76,77)
821 ENTRY(vmx_ia32_exception)
822 VMX_DBG_FAULT(45)
823 VMX_FAULT(45)
824 END(vmx_ia32_exception)
826 .org vmx_ia64_ivt+0x6a00
827 /////////////////////////////////////////////////////////////////////////////////////////
828 // 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept (30,31,59,70,71)
829 ENTRY(vmx_ia32_intercept)
830 VMX_DBG_FAULT(46)
831 VMX_FAULT(46)
832 END(vmx_ia32_intercept)
834 .org vmx_ia64_ivt+0x6b00
835 /////////////////////////////////////////////////////////////////////////////////////////
836 // 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt (74)
837 ENTRY(vmx_ia32_interrupt)
838 VMX_DBG_FAULT(47)
839 VMX_FAULT(47)
840 END(vmx_ia32_interrupt)
842 .org vmx_ia64_ivt+0x6c00
843 /////////////////////////////////////////////////////////////////////////////////////////
844 // 0x6c00 Entry 48 (size 16 bundles) Reserved
845 VMX_DBG_FAULT(48)
846 VMX_FAULT(48)
848 .org vmx_ia64_ivt+0x6d00
849 /////////////////////////////////////////////////////////////////////////////////////////
850 // 0x6d00 Entry 49 (size 16 bundles) Reserved
851 VMX_DBG_FAULT(49)
852 VMX_FAULT(49)
854 .org vmx_ia64_ivt+0x6e00
855 /////////////////////////////////////////////////////////////////////////////////////////
856 // 0x6e00 Entry 50 (size 16 bundles) Reserved
857 VMX_DBG_FAULT(50)
858 VMX_FAULT(50)
860 .org vmx_ia64_ivt+0x6f00
861 /////////////////////////////////////////////////////////////////////////////////////////
862 // 0x6f00 Entry 51 (size 16 bundles) Reserved
863 VMX_DBG_FAULT(51)
864 VMX_FAULT(51)
866 .org vmx_ia64_ivt+0x7000
867 /////////////////////////////////////////////////////////////////////////////////////////
868 // 0x7000 Entry 52 (size 16 bundles) Reserved
869 VMX_DBG_FAULT(52)
870 VMX_FAULT(52)
872 .org vmx_ia64_ivt+0x7100
873 /////////////////////////////////////////////////////////////////////////////////////////
874 // 0x7100 Entry 53 (size 16 bundles) Reserved
875 VMX_DBG_FAULT(53)
876 VMX_FAULT(53)
878 .org vmx_ia64_ivt+0x7200
879 /////////////////////////////////////////////////////////////////////////////////////////
880 // 0x7200 Entry 54 (size 16 bundles) Reserved
881 VMX_DBG_FAULT(54)
882 VMX_FAULT(54)
884 .org vmx_ia64_ivt+0x7300
885 /////////////////////////////////////////////////////////////////////////////////////////
886 // 0x7300 Entry 55 (size 16 bundles) Reserved
887 VMX_DBG_FAULT(55)
888 VMX_FAULT(55)
890 .org vmx_ia64_ivt+0x7400
891 /////////////////////////////////////////////////////////////////////////////////////////
892 // 0x7400 Entry 56 (size 16 bundles) Reserved
893 VMX_DBG_FAULT(56)
894 VMX_FAULT(56)
896 .org vmx_ia64_ivt+0x7500
897 /////////////////////////////////////////////////////////////////////////////////////////
898 // 0x7500 Entry 57 (size 16 bundles) Reserved
899 VMX_DBG_FAULT(57)
900 VMX_FAULT(57)
902 .org vmx_ia64_ivt+0x7600
903 /////////////////////////////////////////////////////////////////////////////////////////
904 // 0x7600 Entry 58 (size 16 bundles) Reserved
905 VMX_DBG_FAULT(58)
906 VMX_FAULT(58)
908 .org vmx_ia64_ivt+0x7700
909 /////////////////////////////////////////////////////////////////////////////////////////
910 // 0x7700 Entry 59 (size 16 bundles) Reserved
911 VMX_DBG_FAULT(59)
912 VMX_FAULT(59)
914 .org vmx_ia64_ivt+0x7800
915 /////////////////////////////////////////////////////////////////////////////////////////
916 // 0x7800 Entry 60 (size 16 bundles) Reserved
917 VMX_DBG_FAULT(60)
918 VMX_FAULT(60)
920 .org vmx_ia64_ivt+0x7900
921 /////////////////////////////////////////////////////////////////////////////////////////
922 // 0x7900 Entry 61 (size 16 bundles) Reserved
923 VMX_DBG_FAULT(61)
924 VMX_FAULT(61)
926 .org vmx_ia64_ivt+0x7a00
927 /////////////////////////////////////////////////////////////////////////////////////////
928 // 0x7a00 Entry 62 (size 16 bundles) Reserved
929 VMX_DBG_FAULT(62)
930 VMX_FAULT(62)
932 .org vmx_ia64_ivt+0x7b00
933 /////////////////////////////////////////////////////////////////////////////////////////
934 // 0x7b00 Entry 63 (size 16 bundles) Reserved
935 VMX_DBG_FAULT(63)
936 VMX_FAULT(63)
938 .org vmx_ia64_ivt+0x7c00
939 /////////////////////////////////////////////////////////////////////////////////////////
940 // 0x7c00 Entry 64 (size 16 bundles) Reserved
941 VMX_DBG_FAULT(64)
942 VMX_FAULT(64)
944 .org vmx_ia64_ivt+0x7d00
945 /////////////////////////////////////////////////////////////////////////////////////////
946 // 0x7d00 Entry 65 (size 16 bundles) Reserved
947 VMX_DBG_FAULT(65)
948 VMX_FAULT(65)
950 .org vmx_ia64_ivt+0x7e00
951 /////////////////////////////////////////////////////////////////////////////////////////
952 // 0x7e00 Entry 66 (size 16 bundles) Reserved
953 VMX_DBG_FAULT(66)
954 VMX_FAULT(66)
956 .org vmx_ia64_ivt+0x7f00
957 /////////////////////////////////////////////////////////////////////////////////////////
958 // 0x7f00 Entry 67 (size 16 bundles) Reserved
959 VMX_DBG_FAULT(67)
960 VMX_FAULT(67)
962 .org vmx_ia64_ivt+0x8000
963 // There is no particular reason for this code to be here, other than that
964 // there happens to be space here that would go unused otherwise. If this
965 // fault ever gets "unreserved", simply moved the following code to a more
966 // suitable spot...
969 ENTRY(vmx_dispatch_reflection)
970 /*
971 * Input:
972 * psr.ic: off
973 * r19: intr type (offset into ivt, see ia64_int.h)
974 * r31: contains saved predicates (pr)
975 */
976 VMX_SAVE_MIN_WITH_COVER_R19
977 alloc r14=ar.pfs,0,0,5,0
978 mov out0=cr.ifa
979 mov out1=cr.isr
980 mov out2=cr.iim
981 mov out3=r15
982 adds r3=8,r2 // set up second base pointer
983 ;;
984 ssm psr.ic
985 ;;
986 srlz.i // guarantee that interruption collection is on
987 ;;
988 (p15) ssm psr.i // restore psr.i
989 movl r14=ia64_leave_hypervisor
990 ;;
991 VMX_SAVE_REST
992 mov rp=r14
993 ;;
994 adds out4=16,r12
995 br.call.sptk.many b6=vmx_reflect_interruption
996 END(vmx_dispatch_reflection)
998 ENTRY(vmx_dispatch_virtualization_fault)
999 VMX_SAVE_MIN_WITH_COVER_R19
1000 ;;
1001 alloc r14=ar.pfs,0,0,2,0 // now it's safe (must be first in insn group!)
1002 mov out0=r13 //vcpu
1003 adds r3=8,r2 // set up second base pointer
1004 ;;
1005 ssm psr.ic
1006 ;;
1007 srlz.i // guarantee that interruption collection is on
1008 ;;
1009 (p15) ssm psr.i // restore psr.i
1010 movl r14=ia64_leave_hypervisor
1011 ;;
1012 VMX_SAVE_REST
1013 mov rp=r14
1014 ;;
1015 adds out1=16,sp //regs
1016 br.call.sptk.many b6=vmx_emulate
1017 END(vmx_dispatch_virtualization_fault)
1020 ENTRY(vmx_dispatch_vexirq)
1021 VMX_SAVE_MIN_WITH_COVER_R19
1022 alloc r14=ar.pfs,0,0,1,0
1023 mov out0=r13
1025 ssm psr.ic
1026 ;;
1027 srlz.i // guarantee that interruption collection is on
1028 ;;
1029 (p15) ssm psr.i // restore psr.i
1030 adds r3=8,r2 // set up second base pointer
1031 ;;
1032 VMX_SAVE_REST
1033 movl r14=ia64_leave_hypervisor
1034 ;;
1035 mov rp=r14
1036 br.call.sptk.many b6=vmx_vexirq
1037 END(vmx_dispatch_vexirq)
1039 ENTRY(vmx_dispatch_tlb_miss)
1040 VMX_SAVE_MIN_WITH_COVER_R19
1041 alloc r14=ar.pfs,0,0,3,0
1042 mov out0=cr.ifa
1043 mov out1=r15
1044 adds r3=8,r2 // set up second base pointer
1045 ;;
1046 ssm psr.ic
1047 ;;
1048 srlz.i // guarantee that interruption collection is on
1049 ;;
1050 (p15) ssm psr.i // restore psr.i
1051 movl r14=ia64_leave_hypervisor
1052 ;;
1053 VMX_SAVE_REST
1054 mov rp=r14
1055 ;;
1056 adds out2=16,r12
1057 br.call.sptk.many b6=vmx_hpw_miss
1058 END(vmx_dispatch_tlb_miss)
1061 ENTRY(vmx_dispatch_break_fault)
1062 VMX_SAVE_MIN_WITH_COVER_R19
1063 ;;
1064 ;;
1065 alloc r14=ar.pfs,0,0,4,0 // now it's safe (must be first in insn group!)
1066 mov out0=cr.ifa
1067 mov out2=cr.isr // FIXME: pity to make this slow access twice
1068 mov out3=cr.iim // FIXME: pity to make this slow access twice
1069 adds r3=8,r2 // set up second base pointer
1070 ;;
1071 ssm psr.ic
1072 ;;
1073 srlz.i // guarantee that interruption collection is on
1074 ;;
1075 (p15)ssm psr.i // restore psr.i
1076 movl r14=ia64_leave_hypervisor
1077 ;;
1078 VMX_SAVE_REST
1079 mov rp=r14
1080 ;;
1081 adds out1=16,sp
1082 br.call.sptk.many b6=vmx_ia64_handle_break
1083 ;;
1084 END(vmx_dispatch_break_fault)
1087 ENTRY(vmx_hypercall_dispatch)
1088 VMX_SAVE_MIN_WITH_COVER
1089 ssm psr.ic
1090 ;;
1091 srlz.i // guarantee that interruption collection is on
1092 ;;
1093 (p15) ssm psr.i // restore psr.i
1094 adds r3=8,r2 // set up second base pointer
1095 ;;
1096 VMX_SAVE_REST
1097 ;;
1098 movl r14=ia64_leave_hypervisor
1099 movl r2=hyper_call_table
1100 ;;
1101 mov rp=r14
1102 shladd r2=r15,3,r2
1103 ;;
1104 ld8 r2=[r2]
1105 ;;
1106 mov b6=r2
1107 ;;
1108 br.call.sptk.many b6=b6
1109 ;;
1110 END(vmx_hypercall_dispatch)
1114 ENTRY(vmx_dispatch_interrupt)
1115 VMX_SAVE_MIN_WITH_COVER_R19 // uses r31; defines r2 and r3
1116 ;;
1117 alloc r14=ar.pfs,0,0,2,0 // must be first in an insn group
1118 mov out0=cr.ivr // pass cr.ivr as first arg
1119 adds r3=8,r2 // set up second base pointer for SAVE_REST
1120 ;;
1121 ssm psr.ic
1122 ;;
1123 srlz.i
1124 ;;
1125 (p15) ssm psr.i
1126 movl r14=ia64_leave_hypervisor
1127 ;;
1128 VMX_SAVE_REST
1129 mov rp=r14
1130 ;;
1131 add out1=16,sp // pass pointer to pt_regs as second arg
1132 br.call.sptk.many b6=ia64_handle_irq
1133 END(vmx_dispatch_interrupt)
1137 .rodata
1138 .align 8
1139 .globl hyper_call_table
1140 hyper_call_table:
1141 data8 hyper_not_support //hyper_set_trap_table /* 0 */
1142 data8 hyper_mmu_update
1143 data8 hyper_not_support //hyper_set_gdt
1144 data8 hyper_not_support //hyper_stack_switch
1145 data8 hyper_not_support //hyper_set_callbacks
1146 data8 hyper_not_support //hyper_fpu_taskswitch /* 5 */
1147 data8 hyper_sched_op_compat
1148 data8 hyper_dom0_op
1149 data8 hyper_not_support //hyper_set_debugreg
1150 data8 hyper_not_support //hyper_get_debugreg
1151 data8 hyper_not_support //hyper_update_descriptor /* 10 */
1152 data8 hyper_not_support //hyper_set_fast_trap
1153 data8 hyper_dom_mem_op
1154 data8 hyper_not_support //hyper_multicall
1155 data8 hyper_not_support //hyper_update_va_mapping
1156 data8 hyper_not_support //hyper_set_timer_op /* 15 */
1157 data8 hyper_event_channel_op
1158 data8 hyper_xen_version
1159 data8 hyper_not_support //hyper_console_io
1160 data8 hyper_not_support //hyper_physdev_op
1161 data8 hyper_not_support //hyper_grant_table_op /* 20 */
1162 data8 hyper_not_support //hyper_vm_assist
1163 data8 hyper_not_support //hyper_update_va_mapping_otherdomain
1164 data8 hyper_not_support //hyper_switch_vm86
1165 data8 hyper_not_support //hyper_boot_vcpu
1166 data8 hyper_not_support //hyper_ni_hypercall /* 25 */
1167 data8 hyper_not_support //hyper_mmuext_op
1168 data8 hyper_not_support //tata8 hyper_lock_page
1169 data8 hyper_set_shared_page