ia64/xen-unstable

view xen/include/asm-x86/hvm/vmx/vmx.h @ 16427:fd3f6d814f6d

x86: single step after instruction emulation

Inject single step trap after emulating instructions if guest's
EFLAGS.TF is set.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Keir Fraser <keir.fraser@eu.citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Nov 22 18:28:47 2007 +0000 (2007-11-22)
parents 8d8d179b9b05
children 51082cf273d4
line source
1 /*
2 * vmx.h: VMX Architecture related definitions
3 * Copyright (c) 2004, Intel Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
16 * Place - Suite 330, Boston, MA 02111-1307 USA.
17 *
18 */
19 #ifndef __ASM_X86_HVM_VMX_VMX_H__
20 #define __ASM_X86_HVM_VMX_VMX_H__
22 #include <xen/sched.h>
23 #include <asm/types.h>
24 #include <asm/regs.h>
25 #include <asm/processor.h>
26 #include <asm/hvm/vmx/vmcs.h>
27 #include <asm/i387.h>
28 #include <asm/hvm/trace.h>
30 void vmx_asm_vmexit_handler(struct cpu_user_regs);
31 void vmx_asm_do_vmentry(void);
32 void vmx_intr_assist(void);
33 void vmx_do_resume(struct vcpu *);
34 void set_guest_time(struct vcpu *v, u64 gtime);
35 void vmx_vlapic_msr_changed(struct vcpu *v);
37 /*
38 * Exit Reasons
39 */
40 #define VMX_EXIT_REASONS_FAILED_VMENTRY 0x80000000
42 #define EXIT_REASON_EXCEPTION_NMI 0
43 #define EXIT_REASON_EXTERNAL_INTERRUPT 1
44 #define EXIT_REASON_TRIPLE_FAULT 2
45 #define EXIT_REASON_INIT 3
46 #define EXIT_REASON_SIPI 4
47 #define EXIT_REASON_IO_SMI 5
48 #define EXIT_REASON_OTHER_SMI 6
49 #define EXIT_REASON_PENDING_VIRT_INTR 7
50 #define EXIT_REASON_PENDING_VIRT_NMI 8
51 #define EXIT_REASON_TASK_SWITCH 9
52 #define EXIT_REASON_CPUID 10
53 #define EXIT_REASON_HLT 12
54 #define EXIT_REASON_INVD 13
55 #define EXIT_REASON_INVLPG 14
56 #define EXIT_REASON_RDPMC 15
57 #define EXIT_REASON_RDTSC 16
58 #define EXIT_REASON_RSM 17
59 #define EXIT_REASON_VMCALL 18
60 #define EXIT_REASON_VMCLEAR 19
61 #define EXIT_REASON_VMLAUNCH 20
62 #define EXIT_REASON_VMPTRLD 21
63 #define EXIT_REASON_VMPTRST 22
64 #define EXIT_REASON_VMREAD 23
65 #define EXIT_REASON_VMRESUME 24
66 #define EXIT_REASON_VMWRITE 25
67 #define EXIT_REASON_VMXOFF 26
68 #define EXIT_REASON_VMXON 27
69 #define EXIT_REASON_CR_ACCESS 28
70 #define EXIT_REASON_DR_ACCESS 29
71 #define EXIT_REASON_IO_INSTRUCTION 30
72 #define EXIT_REASON_MSR_READ 31
73 #define EXIT_REASON_MSR_WRITE 32
74 #define EXIT_REASON_INVALID_GUEST_STATE 33
75 #define EXIT_REASON_MSR_LOADING 34
76 #define EXIT_REASON_MWAIT_INSTRUCTION 36
77 #define EXIT_REASON_MONITOR_INSTRUCTION 39
78 #define EXIT_REASON_PAUSE_INSTRUCTION 40
79 #define EXIT_REASON_MACHINE_CHECK 41
80 #define EXIT_REASON_TPR_BELOW_THRESHOLD 43
81 #define EXIT_REASON_APIC_ACCESS 44
82 #define EXIT_REASON_WBINVD 54
84 /*
85 * Interruption-information format
86 */
87 #define INTR_INFO_VECTOR_MASK 0xff /* 7:0 */
88 #define INTR_INFO_INTR_TYPE_MASK 0x700 /* 10:8 */
89 #define INTR_INFO_DELIVER_CODE_MASK 0x800 /* 11 */
90 #define INTR_INFO_NMI_UNBLOCKED_BY_IRET 0x1000 /* 12 */
91 #define INTR_INFO_VALID_MASK 0x80000000 /* 31 */
92 #define INTR_INFO_RESVD_BITS_MASK 0x7ffff000
94 /*
95 * Exit Qualifications for MOV for Control Register Access
96 */
97 #define CONTROL_REG_ACCESS_NUM 0xf /* 3:0, number of control register */
98 #define CONTROL_REG_ACCESS_TYPE 0x30 /* 5:4, access type */
99 #define CONTROL_REG_ACCESS_REG 0xf00 /* 10:8, general purpose register */
100 #define LMSW_SOURCE_DATA (0xFFFF << 16) /* 16:31 lmsw source */
101 #define REG_EAX (0 << 8)
102 #define REG_ECX (1 << 8)
103 #define REG_EDX (2 << 8)
104 #define REG_EBX (3 << 8)
105 #define REG_ESP (4 << 8)
106 #define REG_EBP (5 << 8)
107 #define REG_ESI (6 << 8)
108 #define REG_EDI (7 << 8)
109 #define REG_R8 (8 << 8)
110 #define REG_R9 (9 << 8)
111 #define REG_R10 (10 << 8)
112 #define REG_R11 (11 << 8)
113 #define REG_R12 (12 << 8)
114 #define REG_R13 (13 << 8)
115 #define REG_R14 (14 << 8)
116 #define REG_R15 (15 << 8)
118 /*
119 * Exit Qualifications for MOV for Debug Register Access
120 */
121 #define DEBUG_REG_ACCESS_NUM 0x7 /* 2:0, number of debug register */
122 #define DEBUG_REG_ACCESS_TYPE 0x10 /* 4, direction of access */
123 #define TYPE_MOV_TO_DR (0 << 4)
124 #define TYPE_MOV_FROM_DR (1 << 4)
125 #define DEBUG_REG_ACCESS_REG 0xf00 /* 11:8, general purpose register */
127 /*
128 * Access Rights
129 */
130 #define X86_SEG_AR_SEG_TYPE 0xf /* 3:0, segment type */
131 #define X86_SEG_AR_DESC_TYPE (1u << 4) /* 4, descriptor type */
132 #define X86_SEG_AR_DPL 0x60 /* 6:5, descriptor privilege level */
133 #define X86_SEG_AR_SEG_PRESENT (1u << 7) /* 7, segment present */
134 #define X86_SEG_AR_AVL (1u << 12) /* 12, available for system software */
135 #define X86_SEG_AR_CS_LM_ACTIVE (1u << 13) /* 13, long mode active (CS only) */
136 #define X86_SEG_AR_DEF_OP_SIZE (1u << 14) /* 14, default operation size */
137 #define X86_SEG_AR_GRANULARITY (1u << 15) /* 15, granularity */
138 #define X86_SEG_AR_SEG_UNUSABLE (1u << 16) /* 16, segment unusable */
140 #define VMCALL_OPCODE ".byte 0x0f,0x01,0xc1\n"
141 #define VMCLEAR_OPCODE ".byte 0x66,0x0f,0xc7\n" /* reg/opcode: /6 */
142 #define VMLAUNCH_OPCODE ".byte 0x0f,0x01,0xc2\n"
143 #define VMPTRLD_OPCODE ".byte 0x0f,0xc7\n" /* reg/opcode: /6 */
144 #define VMPTRST_OPCODE ".byte 0x0f,0xc7\n" /* reg/opcode: /7 */
145 #define VMREAD_OPCODE ".byte 0x0f,0x78\n"
146 #define VMRESUME_OPCODE ".byte 0x0f,0x01,0xc3\n"
147 #define VMWRITE_OPCODE ".byte 0x0f,0x79\n"
148 #define VMXOFF_OPCODE ".byte 0x0f,0x01,0xc4\n"
149 #define VMXON_OPCODE ".byte 0xf3,0x0f,0xc7\n"
151 #define MODRM_EAX_06 ".byte 0x30\n" /* [EAX], with reg/opcode: /6 */
152 #define MODRM_EAX_07 ".byte 0x38\n" /* [EAX], with reg/opcode: /7 */
153 #define MODRM_EAX_ECX ".byte 0xc1\n" /* [EAX], [ECX] */
155 static inline void __vmptrld(u64 addr)
156 {
157 __asm__ __volatile__ ( VMPTRLD_OPCODE
158 MODRM_EAX_06
159 /* CF==1 or ZF==1 --> crash (ud2) */
160 "ja 1f ; ud2 ; 1:\n"
161 :
162 : "a" (&addr)
163 : "memory");
164 }
166 static inline void __vmptrst(u64 addr)
167 {
168 __asm__ __volatile__ ( VMPTRST_OPCODE
169 MODRM_EAX_07
170 :
171 : "a" (&addr)
172 : "memory");
173 }
175 static inline void __vmpclear(u64 addr)
176 {
177 __asm__ __volatile__ ( VMCLEAR_OPCODE
178 MODRM_EAX_06
179 /* CF==1 or ZF==1 --> crash (ud2) */
180 "ja 1f ; ud2 ; 1:\n"
181 :
182 : "a" (&addr)
183 : "memory");
184 }
186 static inline unsigned long __vmread(unsigned long field)
187 {
188 unsigned long ecx;
190 __asm__ __volatile__ ( VMREAD_OPCODE
191 MODRM_EAX_ECX
192 /* CF==1 or ZF==1 --> crash (ud2) */
193 "ja 1f ; ud2 ; 1:\n"
194 : "=c" (ecx)
195 : "a" (field)
196 : "memory");
198 return ecx;
199 }
201 static inline void __vmwrite(unsigned long field, unsigned long value)
202 {
203 __asm__ __volatile__ ( VMWRITE_OPCODE
204 MODRM_EAX_ECX
205 /* CF==1 or ZF==1 --> crash (ud2) */
206 "ja 1f ; ud2 ; 1:\n"
207 :
208 : "a" (field) , "c" (value)
209 : "memory");
210 }
212 static inline unsigned long __vmread_safe(unsigned long field, int *error)
213 {
214 unsigned long ecx;
216 __asm__ __volatile__ ( VMREAD_OPCODE
217 MODRM_EAX_ECX
218 /* CF==1 or ZF==1 --> rc = -1 */
219 "setna %b0 ; neg %0"
220 : "=q" (*error), "=c" (ecx)
221 : "0" (0), "a" (field)
222 : "memory");
224 return ecx;
225 }
227 static inline void __vm_set_bit(unsigned long field, unsigned int bit)
228 {
229 __vmwrite(field, __vmread(field) | (1UL << bit));
230 }
232 static inline void __vm_clear_bit(unsigned long field, unsigned int bit)
233 {
234 __vmwrite(field, __vmread(field) & ~(1UL << bit));
235 }
237 static inline void __vmxoff (void)
238 {
239 __asm__ __volatile__ ( VMXOFF_OPCODE
240 ::: "memory");
241 }
243 static inline int __vmxon (u64 addr)
244 {
245 int rc;
247 __asm__ __volatile__ ( VMXON_OPCODE
248 MODRM_EAX_06
249 /* CF==1 or ZF==1 --> rc = -1 */
250 "setna %b0 ; neg %0"
251 : "=q" (rc)
252 : "0" (0), "a" (&addr)
253 : "memory");
255 return rc;
256 }
258 static inline void __vmx_inject_exception(
259 struct vcpu *v, int trap, int type, int error_code)
260 {
261 unsigned long intr_fields;
263 /*
264 * NB. Callers do not need to worry about clearing STI/MOV-SS blocking:
265 * "If the VM entry is injecting, there is no blocking by STI or by
266 * MOV SS following the VM entry, regardless of the contents of the
267 * interruptibility-state field [in the guest-state area before the
268 * VM entry]", PRM Vol. 3, 22.6.1 (Interruptibility State).
269 */
271 intr_fields = (INTR_INFO_VALID_MASK | (type<<8) | trap);
272 if ( error_code != HVM_DELIVER_NO_ERROR_CODE ) {
273 __vmwrite(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
274 intr_fields |= INTR_INFO_DELIVER_CODE_MASK;
275 }
277 __vmwrite(VM_ENTRY_INTR_INFO, intr_fields);
279 if ( trap == TRAP_page_fault )
280 HVMTRACE_2D(PF_INJECT, v, v->arch.hvm_vcpu.guest_cr[2], error_code);
281 else
282 HVMTRACE_2D(INJ_EXC, v, trap, error_code);
283 }
285 static inline void vmx_inject_hw_exception(
286 struct vcpu *v, int trap, int error_code)
287 {
288 __vmx_inject_exception(v, trap, X86_EVENTTYPE_HW_EXCEPTION, error_code);
289 }
291 static inline void vmx_inject_extint(struct vcpu *v, int trap)
292 {
293 __vmx_inject_exception(v, trap, X86_EVENTTYPE_EXT_INTR,
294 HVM_DELIVER_NO_ERROR_CODE);
295 }
297 static inline void vmx_inject_nmi(struct vcpu *v)
298 {
299 __vmx_inject_exception(v, 2, X86_EVENTTYPE_NMI,
300 HVM_DELIVER_NO_ERROR_CODE);
301 }
303 #endif /* __ASM_X86_HVM_VMX_VMX_H__ */