ia64/xen-unstable

view xen/arch/ia64/xen/ivt.S @ 8908:f94931b07c67

[IA64] tlb miss fix

make dtlb miss handler to handle xen/ia64 identity mapping area.
xen/ia64 enables vhpt walker for all regions unlink Linux.
So dtlb misses on identity mapping area are catched by
dtlb miss handler, not alt dltb miss handler.

- dtlb miss on identity mapping area must be handled
- alt dtlb miss must be handled
- itlb miss on the identity mapping area must not occur
panic via page_fault().
- alt itlb miss by a guest must be handled
it occurs during dom0 boot.
- alt itlb miss by xen must not occur
panic by FORCE_CRASH

vmx_ivt.S already has such tweaks by checking psr.vm bit.

TODO: optimization
dtlb miss handlers are performance critical so that
it should be heavily optimized like alt_dtlb_miss.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author awilliam@xenbuild.aw
date Fri Feb 24 08:34:11 2006 -0700 (2006-02-24)
parents 34f2b388beb0
children 815758308556
line source
2 #ifdef XEN
3 //#define CONFIG_DISABLE_VHPT // FIXME: change when VHPT is enabled??
4 // these are all hacked out for now as the entire IVT
5 // will eventually be replaced... just want to use it
6 // for startup code to handle TLB misses
7 //#define ia64_leave_kernel 0
8 //#define ia64_ret_from_syscall 0
9 //#define ia64_handle_irq 0
10 //#define ia64_fault 0
11 #define ia64_illegal_op_fault 0
12 #define ia64_prepare_handle_unaligned 0
13 #define ia64_bad_break 0
14 #define ia64_trace_syscall 0
15 #define sys_call_table 0
16 #define sys_ni_syscall 0
17 #include <asm/vhpt.h>
18 #include <asm/debugger.h>
19 #endif
20 /*
21 * arch/ia64/kernel/ivt.S
22 *
23 * Copyright (C) 1998-2001, 2003 Hewlett-Packard Co
24 * Stephane Eranian <eranian@hpl.hp.com>
25 * David Mosberger <davidm@hpl.hp.com>
26 * Copyright (C) 2000, 2002-2003 Intel Co
27 * Asit Mallick <asit.k.mallick@intel.com>
28 * Suresh Siddha <suresh.b.siddha@intel.com>
29 * Kenneth Chen <kenneth.w.chen@intel.com>
30 * Fenghua Yu <fenghua.yu@intel.com>
31 *
32 * 00/08/23 Asit Mallick <asit.k.mallick@intel.com> TLB handling for SMP
33 * 00/12/20 David Mosberger-Tang <davidm@hpl.hp.com> DTLB/ITLB handler now uses virtual PT.
34 */
35 /*
36 * This file defines the interruption vector table used by the CPU.
37 * It does not include one entry per possible cause of interruption.
38 *
39 * The first 20 entries of the table contain 64 bundles each while the
40 * remaining 48 entries contain only 16 bundles each.
41 *
42 * The 64 bundles are used to allow inlining the whole handler for critical
43 * interruptions like TLB misses.
44 *
45 * For each entry, the comment is as follows:
46 *
47 * // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
48 * entry offset ----/ / / / /
49 * entry number ---------/ / / /
50 * size of the entry -------------/ / /
51 * vector name -------------------------------------/ /
52 * interruptions triggering this vector ----------------------/
53 *
54 * The table is 32KB in size and must be aligned on 32KB boundary.
55 * (The CPU ignores the 15 lower bits of the address)
56 *
57 * Table is based upon EAS2.6 (Oct 1999)
58 */
60 #include <linux/config.h>
62 #include <asm/asmmacro.h>
63 #include <asm/break.h>
64 #include <asm/ia32.h>
65 #include <asm/kregs.h>
66 #include <asm/offsets.h>
67 #include <asm/pgtable.h>
68 #include <asm/processor.h>
69 #include <asm/ptrace.h>
70 #include <asm/system.h>
71 #include <asm/thread_info.h>
72 #include <asm/unistd.h>
73 #include <asm/errno.h>
75 #if 1
76 # define PSR_DEFAULT_BITS psr.ac
77 #else
78 # define PSR_DEFAULT_BITS 0
79 #endif
81 #if 0
82 /*
83 * This lets you track the last eight faults that occurred on the CPU. Make sure ar.k2 isn't
84 * needed for something else before enabling this...
85 */
86 # define DBG_FAULT(i) mov r16=ar.k2;; shl r16=r16,8;; add r16=(i),r16;;mov ar.k2=r16
87 #else
88 # define DBG_FAULT(i)
89 #endif
91 #define MINSTATE_VIRT /* needed by minstate.h */
92 #include "minstate.h"
94 #define FAULT(n) \
95 mov r31=pr; \
96 mov r19=n;; /* prepare to save predicates */ \
97 br.sptk.many dispatch_to_fault_handler
99 #ifdef XEN
100 #define REFLECT(n) \
101 mov r31=pr; \
102 mov r19=n;; /* prepare to save predicates */ \
103 br.sptk.many dispatch_reflection
104 #endif
106 .section .text.ivt,"ax"
108 .align 32768 // align on 32KB boundary
109 .global ia64_ivt
110 ia64_ivt:
111 /////////////////////////////////////////////////////////////////////////////////////////
112 // 0x0000 Entry 0 (size 64 bundles) VHPT Translation (8,20,47)
113 ENTRY(vhpt_miss)
114 DBG_FAULT(0)
115 /*
116 * The VHPT vector is invoked when the TLB entry for the virtual page table
117 * is missing. This happens only as a result of a previous
118 * (the "original") TLB miss, which may either be caused by an instruction
119 * fetch or a data access (or non-access).
120 *
121 * What we do here is normal TLB miss handing for the _original_ miss, followed
122 * by inserting the TLB entry for the virtual page table page that the VHPT
123 * walker was attempting to access. The latter gets inserted as long
124 * as both L1 and L2 have valid mappings for the faulting address.
125 * The TLB entry for the original miss gets inserted only if
126 * the L3 entry indicates that the page is present.
127 *
128 * do_page_fault gets invoked in the following cases:
129 * - the faulting virtual address uses unimplemented address bits
130 * - the faulting virtual address has no L1, L2, or L3 mapping
131 */
132 mov r16=cr.ifa // get address that caused the TLB miss
133 #ifdef CONFIG_HUGETLB_PAGE
134 movl r18=PAGE_SHIFT
135 mov r25=cr.itir
136 #endif
137 ;;
138 rsm psr.dt // use physical addressing for data
139 mov r31=pr // save the predicate registers
140 #ifdef XEN
141 movl r19=THIS_CPU(cpu_kr)+IA64_KR_PT_BASE_OFFSET;;
142 #else
143 mov r19=IA64_KR(PT_BASE) // get page table base address
144 #endif
145 shl r21=r16,3 // shift bit 60 into sign bit
146 shr.u r17=r16,61 // get the region number into r17
147 ;;
148 shr r22=r21,3
149 #ifdef CONFIG_HUGETLB_PAGE
150 extr.u r26=r25,2,6
151 ;;
152 cmp.ne p8,p0=r18,r26
153 sub r27=r26,r18
154 ;;
155 (p8) dep r25=r18,r25,2,6
156 (p8) shr r22=r22,r27
157 #endif
158 ;;
159 cmp.eq p6,p7=5,r17 // is IFA pointing into to region 5?
160 shr.u r18=r22,PGDIR_SHIFT // get bits 33-63 of the faulting address
161 ;;
162 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
164 srlz.d
165 LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir
167 .pred.rel "mutex", p6, p7
168 (p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT
169 (p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3
170 ;;
171 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=PTA + IFA(33,42)*8
172 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8)
173 cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
174 shr.u r18=r22,PMD_SHIFT // shift L2 index into position
175 ;;
176 ld8 r17=[r17] // fetch the L1 entry (may be 0)
177 ;;
178 (p7) cmp.eq p6,p7=r17,r0 // was L1 entry NULL?
179 dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
180 ;;
181 (p7) ld8 r20=[r17] // fetch the L2 entry (may be 0)
182 shr.u r19=r22,PAGE_SHIFT // shift L3 index into position
183 ;;
184 (p7) cmp.eq.or.andcm p6,p7=r20,r0 // was L2 entry NULL?
185 dep r21=r19,r20,3,(PAGE_SHIFT-3) // compute address of L3 page table entry
186 ;;
187 (p7) ld8 r18=[r21] // read the L3 PTE
188 mov r19=cr.isr // cr.isr bit 0 tells us if this is an insn miss
189 ;;
190 (p7) tbit.z p6,p7=r18,_PAGE_P_BIT // page present bit cleared?
191 mov r22=cr.iha // get the VHPT address that caused the TLB miss
192 ;; // avoid RAW on p7
193 (p7) tbit.nz.unc p10,p11=r19,32 // is it an instruction TLB miss?
194 dep r23=0,r20,0,PAGE_SHIFT // clear low bits to get page address
195 ;;
196 (p10) itc.i r18 // insert the instruction TLB entry
197 (p11) itc.d r18 // insert the data TLB entry
198 (p6) br.cond.spnt.many page_fault // handle bad address/page not present (page fault)
199 mov cr.ifa=r22
201 #ifdef CONFIG_HUGETLB_PAGE
202 (p8) mov cr.itir=r25 // change to default page-size for VHPT
203 #endif
205 /*
206 * Now compute and insert the TLB entry for the virtual page table. We never
207 * execute in a page table page so there is no need to set the exception deferral
208 * bit.
209 */
210 adds r24=__DIRTY_BITS_NO_ED|_PAGE_PL_0|_PAGE_AR_RW,r23
211 ;;
212 (p7) itc.d r24
213 ;;
214 #ifdef CONFIG_SMP
215 /*
216 * Tell the assemblers dependency-violation checker that the above "itc" instructions
217 * cannot possibly affect the following loads:
218 */
219 dv_serialize_data
221 /*
222 * Re-check L2 and L3 pagetable. If they changed, we may have received a ptc.g
223 * between reading the pagetable and the "itc". If so, flush the entry we
224 * inserted and retry.
225 */
226 ld8 r25=[r21] // read L3 PTE again
227 ld8 r26=[r17] // read L2 entry again
228 ;;
229 cmp.ne p6,p7=r26,r20 // did L2 entry change
230 mov r27=PAGE_SHIFT<<2
231 ;;
232 (p6) ptc.l r22,r27 // purge PTE page translation
233 (p7) cmp.ne.or.andcm p6,p7=r25,r18 // did L3 PTE change
234 ;;
235 (p6) ptc.l r16,r27 // purge translation
236 #endif
238 mov pr=r31,-1 // restore predicate registers
239 rfi
240 END(vhpt_miss)
242 .org ia64_ivt+0x400
243 /////////////////////////////////////////////////////////////////////////////////////////
244 // 0x0400 Entry 1 (size 64 bundles) ITLB (21)
245 ENTRY(itlb_miss)
246 DBG_FAULT(1)
247 #ifdef XEN
248 VHPT_CCHAIN_LOOKUP(itlb_miss,i)
249 #ifdef VHPT_GLOBAL
250 // br.cond.sptk page_fault
251 br.cond.sptk fast_tlb_miss_reflect
252 ;;
253 #endif
254 #endif
255 /*
256 * The ITLB handler accesses the L3 PTE via the virtually mapped linear
257 * page table. If a nested TLB miss occurs, we switch into physical
258 * mode, walk the page table, and then re-execute the L3 PTE read
259 * and go on normally after that.
260 */
261 mov r16=cr.ifa // get virtual address
262 mov r29=b0 // save b0
263 mov r31=pr // save predicates
264 .itlb_fault:
265 mov r17=cr.iha // get virtual address of L3 PTE
266 movl r30=1f // load nested fault continuation point
267 ;;
268 1: ld8 r18=[r17] // read L3 PTE
269 ;;
270 mov b0=r29
271 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
272 (p6) br.cond.spnt page_fault
273 ;;
274 itc.i r18
275 ;;
276 #ifdef CONFIG_SMP
277 /*
278 * Tell the assemblers dependency-violation checker that the above "itc" instructions
279 * cannot possibly affect the following loads:
280 */
281 dv_serialize_data
283 ld8 r19=[r17] // read L3 PTE again and see if same
284 mov r20=PAGE_SHIFT<<2 // setup page size for purge
285 ;;
286 cmp.ne p7,p0=r18,r19
287 ;;
288 (p7) ptc.l r16,r20
289 #endif
290 mov pr=r31,-1
291 rfi
292 END(itlb_miss)
294 .org ia64_ivt+0x0800
295 /////////////////////////////////////////////////////////////////////////////////////////
296 // 0x0800 Entry 2 (size 64 bundles) DTLB (9,48)
297 ENTRY(dtlb_miss)
298 DBG_FAULT(2)
299 #ifdef XEN
300 VHPT_CCHAIN_LOOKUP(dtlb_miss,d)
301 #if VHPT_ENABLED
302 // XXX TODO optimization
303 mov r31=pr // save predicates
304 mov r30=cr.ipsr
305 mov r28=cr.iip
306 mov r16=cr.ifa // get virtual address
307 mov r17=cr.isr // save predicates
308 ;;
310 extr.u r18 = r30, IA64_PSR_CPL0_BIT, 2 // extract psr.cpl
311 ;;
312 cmp.ne p6, p0 = r0, r18 // cpl == 0?
313 (p6) br.cond.sptk 2f
315 // is speculation bit on?
316 tbit.nz p7,p0=r17,IA64_ISR_SP_BIT
317 ;;
318 (p7) br.cond.spnt 2f
320 // is non-access bit on?
321 tbit.nz p8,p0=r17,IA64_ISR_NA_BIT
322 ;;
323 (p8) br.cond.spnt 2f
325 // cr.isr.code == IA64_ISR_CODE_LFETCH?
326 and r18=IA64_ISR_CODE_MASK,r17 // get the isr.code field
327 ;;
328 cmp.eq p9,p0=IA64_ISR_CODE_LFETCH,r18 // check isr.code field
329 (p9) br.cond.spnt 2f
331 // Is the faulted iip in vmm area?
332 // check [59:58] bit
333 // 00, 11: guest
334 // 01, 10: vmm
335 extr.u r19 = r28, 58, 2
336 ;;
337 cmp.eq p10, p0 = 0x0, r19
338 (p10) br.cond.sptk 2f
339 cmp.eq p11, p0 = 0x3, r19
340 (p11) br.cond.sptk 2f
342 // Is the faulted address is in the identity mapping area?
343 // 0xf000... or 0xe8000...
344 extr.u r20 = r16, 59, 5
345 ;;
346 cmp.eq p12, p0 = 0x1e, r20 // (0xf0 >> 3) = 0x1e
347 (p12) br.cond.spnt 1f
348 cmp.eq p0, p13 = 0x1d, r20 // (0xe8 >> 3) = 0x1d
349 (p13) br.cond.sptk 2f
351 1:
352 // xen identity mappin area.
353 movl r24=PAGE_KERNEL
354 movl r25=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
355 ;;
356 shr.u r26=r16,55 // move address bit 59 to bit 4
357 and r25=r25,r16 // clear ed, reserved bits, and PTE control bits
358 ;;
359 and r26=0x10,r26 // bit 4=address-bit(59)
360 ;;
361 or r25=r25,r24 // insert PTE control bits into r25
362 ;;
363 or r25=r25,r26 // set bit 4 (uncached) if the access was to region 6
364 ;;
365 itc.d r25 // insert the TLB entry
366 mov pr=r31,-1
367 rfi
369 2:
370 #endif
371 #ifdef VHPT_GLOBAL
372 // br.cond.sptk page_fault
373 br.cond.sptk fast_tlb_miss_reflect
374 ;;
375 #endif
376 mov r29=b0 // save b0
377 #else
378 /*
379 * The DTLB handler accesses the L3 PTE via the virtually mapped linear
380 * page table. If a nested TLB miss occurs, we switch into physical
381 * mode, walk the page table, and then re-execute the L3 PTE read
382 * and go on normally after that.
383 */
384 mov r16=cr.ifa // get virtual address
385 mov r29=b0 // save b0
386 mov r31=pr // save predicates
387 #endif
388 dtlb_fault:
389 mov r17=cr.iha // get virtual address of L3 PTE
390 movl r30=1f // load nested fault continuation point
391 ;;
392 1: ld8 r18=[r17] // read L3 PTE
393 ;;
394 mov b0=r29
395 tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
396 (p6) br.cond.spnt page_fault
397 ;;
398 itc.d r18
399 ;;
400 #ifdef CONFIG_SMP
401 /*
402 * Tell the assemblers dependency-violation checker that the above "itc" instructions
403 * cannot possibly affect the following loads:
404 */
405 dv_serialize_data
407 ld8 r19=[r17] // read L3 PTE again and see if same
408 mov r20=PAGE_SHIFT<<2 // setup page size for purge
409 ;;
410 cmp.ne p7,p0=r18,r19
411 ;;
412 (p7) ptc.l r16,r20
413 #endif
414 mov pr=r31,-1
415 rfi
416 END(dtlb_miss)
418 .org ia64_ivt+0x0c00
419 /////////////////////////////////////////////////////////////////////////////////////////
420 // 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19)
421 ENTRY(alt_itlb_miss)
422 DBG_FAULT(3)
423 #ifdef XEN
424 //#ifdef VHPT_GLOBAL
425 // VHPT_CCHAIN_LOOKUP(alt_itlb_miss,i)
426 // br.cond.sptk page_fault
427 // ;;
428 //#endif
429 #endif
430 #ifdef XEN
431 mov r31=pr
432 mov r16=cr.ifa // get address that caused the TLB miss
433 ;;
434 late_alt_itlb_miss:
435 movl r17=PAGE_KERNEL
436 mov r21=cr.ipsr
437 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
438 ;;
439 #else
440 mov r16=cr.ifa // get address that caused the TLB miss
441 movl r17=PAGE_KERNEL
442 mov r21=cr.ipsr
443 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
444 mov r31=pr
445 ;;
446 #endif
447 #ifdef CONFIG_DISABLE_VHPT
448 shr.u r22=r16,61 // get the region number into r21
449 ;;
450 cmp.gt p8,p0=6,r22 // user mode
451 ;;
452 (p8) thash r17=r16
453 ;;
454 (p8) mov cr.iha=r17
455 (p8) mov r29=b0 // save b0
456 (p8) br.cond.dptk .itlb_fault
457 #endif
458 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
459 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
460 #ifdef XEN
461 shr.u r18=r16,55 // move address bit 59 to bit 4
462 ;;
463 and r18=0x10,r18 // bit 4=address-bit(59)
464 #else
465 shr.u r18=r16,57 // move address bit 61 to bit 4
466 ;;
467 andcm r18=0x10,r18 // bit 4=~address-bit(61)
468 #endif
469 cmp.ne p8,p0=r0,r23 // psr.cpl != 0?
470 or r19=r17,r19 // insert PTE control bits into r19
471 ;;
472 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6
473 (p8) br.cond.spnt page_fault
474 #ifdef XEN
475 FORCE_CRASH
476 #endif
477 ;;
478 itc.i r19 // insert the TLB entry
479 mov pr=r31,-1
480 rfi
481 END(alt_itlb_miss)
483 .org ia64_ivt+0x1000
484 /////////////////////////////////////////////////////////////////////////////////////////
485 // 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46)
486 ENTRY(alt_dtlb_miss)
487 DBG_FAULT(4)
488 #ifdef XEN
489 //#ifdef VHPT_GLOBAL
490 // VHPT_CCHAIN_LOOKUP(alt_dtlb_miss,d)
491 // br.cond.sptk page_fault
492 // ;;
493 //#endif
494 #endif
495 #ifdef XEN
496 mov r31=pr
497 mov r16=cr.ifa // get address that caused the TLB miss
498 ;;
499 late_alt_dtlb_miss:
500 movl r17=PAGE_KERNEL
501 mov r20=cr.isr
502 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
503 mov r21=cr.ipsr
504 ;;
505 #else
506 #endif
507 #ifdef CONFIG_DISABLE_VHPT
508 shr.u r22=r16,61 // get the region number into r21
509 ;;
510 cmp.gt p8,p0=6,r22 // access to region 0-5
511 ;;
512 (p8) thash r17=r16
513 ;;
514 (p8) mov cr.iha=r17
515 (p8) mov r29=b0 // save b0
516 (p8) br.cond.dptk dtlb_fault
517 #endif
518 extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl
519 and r22=IA64_ISR_CODE_MASK,r20 // get the isr.code field
520 tbit.nz p6,p7=r20,IA64_ISR_SP_BIT // is speculation bit on?
521 #ifdef XEN
522 shr.u r18=r16,55 // move address bit 59 to bit 4
523 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
524 tbit.nz p9,p0=r20,IA64_ISR_NA_BIT // is non-access bit on?
525 ;;
526 and r18=0x10,r18 // bit 4=address-bit(59)
527 #else
528 shr.u r18=r16,57 // move address bit 61 to bit 4
529 and r19=r19,r16 // clear ed, reserved bits, and PTE control bits
530 tbit.nz p9,p0=r20,IA64_ISR_NA_BIT // is non-access bit on?
531 ;;
532 andcm r18=0x10,r18 // bit 4=~address-bit(61)
533 #endif
534 cmp.ne p8,p0=r0,r23
535 (p9) cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22 // check isr.code field
536 (p8) br.cond.spnt page_fault
537 #ifdef XEN
538 ;;
539 // Test for Xen address, if not handle via page_fault
540 // note that 0xf000 (cached) and 0xe800 (uncached) addresses
541 // should be OK.
542 extr.u r22=r16,59,5;;
543 cmp.eq p8,p0=0x1e,r22
544 (p8) br.cond.spnt 1f;;
545 cmp.ne p8,p0=0x1d,r22
546 (p8) br.cond.sptk page_fault ;;
547 1:
548 #endif
550 dep r21=-1,r21,IA64_PSR_ED_BIT,1
551 or r19=r19,r17 // insert PTE control bits into r19
552 ;;
553 or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6
554 (p6) mov cr.ipsr=r21
555 ;;
556 (p7) itc.d r19 // insert the TLB entry
557 mov pr=r31,-1
558 rfi
559 END(alt_dtlb_miss)
561 .org ia64_ivt+0x1400
562 /////////////////////////////////////////////////////////////////////////////////////////
563 // 0x1400 Entry 5 (size 64 bundles) Data nested TLB (6,45)
564 ENTRY(nested_dtlb_miss)
565 DBG_FAULT(5)
566 #ifdef XEN
567 mov b0=r30
568 br.sptk.many b0 // return to continuation point
569 ;;
570 #endif
571 /*
572 * In the absence of kernel bugs, we get here when the virtually mapped linear
573 * page table is accessed non-speculatively (e.g., in the Dirty-bit, Instruction
574 * Access-bit, or Data Access-bit faults). If the DTLB entry for the virtual page
575 * table is missing, a nested TLB miss fault is triggered and control is
576 * transferred to this point. When this happens, we lookup the pte for the
577 * faulting address by walking the page table in physical mode and return to the
578 * continuation point passed in register r30 (or call page_fault if the address is
579 * not mapped).
580 *
581 * Input: r16: faulting address
582 * r29: saved b0
583 * r30: continuation address
584 * r31: saved pr
585 *
586 * Output: r17: physical address of L3 PTE of faulting address
587 * r29: saved b0
588 * r30: continuation address
589 * r31: saved pr
590 *
591 * Clobbered: b0, r18, r19, r21, psr.dt (cleared)
592 */
593 rsm psr.dt // switch to using physical data addressing
594 #ifdef XEN
595 movl r19=THIS_CPU(cpu_kr)+IA64_KR_PT_BASE_OFFSET;;
596 #else
597 mov r19=IA64_KR(PT_BASE) // get the page table base address
598 #endif
599 shl r21=r16,3 // shift bit 60 into sign bit
600 ;;
601 shr.u r17=r16,61 // get the region number into r17
602 ;;
603 cmp.eq p6,p7=5,r17 // is faulting address in region 5?
604 shr.u r18=r16,PGDIR_SHIFT // get bits 33-63 of faulting address
605 ;;
606 (p7) dep r17=r17,r19,(PAGE_SHIFT-3),3 // put region number bits in place
608 srlz.d
609 LOAD_PHYSICAL(p6, r19, swapper_pg_dir) // region 5 is rooted at swapper_pg_dir
611 .pred.rel "mutex", p6, p7
612 (p6) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT
613 (p7) shr.u r21=r21,PGDIR_SHIFT+PAGE_SHIFT-3
614 ;;
615 (p6) dep r17=r18,r19,3,(PAGE_SHIFT-3) // r17=PTA + IFA(33,42)*8
616 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=PTA + (((IFA(61,63) << 7) | IFA(33,39))*8)
617 cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
618 shr.u r18=r16,PMD_SHIFT // shift L2 index into position
619 ;;
620 ld8 r17=[r17] // fetch the L1 entry (may be 0)
621 ;;
622 (p7) cmp.eq p6,p7=r17,r0 // was L1 entry NULL?
623 dep r17=r18,r17,3,(PAGE_SHIFT-3) // compute address of L2 page table entry
624 ;;
625 (p7) ld8 r17=[r17] // fetch the L2 entry (may be 0)
626 shr.u r19=r16,PAGE_SHIFT // shift L3 index into position
627 ;;
628 (p7) cmp.eq.or.andcm p6,p7=r17,r0 // was L2 entry NULL?
629 dep r17=r19,r17,3,(PAGE_SHIFT-3) // compute address of L3 page table entry
630 (p6) br.cond.spnt page_fault
631 mov b0=r30
632 br.sptk.many b0 // return to continuation point
633 END(nested_dtlb_miss)
635 .org ia64_ivt+0x1800
636 /////////////////////////////////////////////////////////////////////////////////////////
637 // 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24)
638 ENTRY(ikey_miss)
639 DBG_FAULT(6)
640 #ifdef XEN
641 REFLECT(6)
642 #endif
643 FAULT(6)
644 END(ikey_miss)
646 //-----------------------------------------------------------------------------------
647 // call do_page_fault (predicates are in r31, psr.dt may be off, r16 is faulting address)
648 #ifdef XEN
649 GLOBAL_ENTRY(page_fault)
650 #else
651 ENTRY(page_fault)
652 #endif
653 ssm psr.dt
654 ;;
655 srlz.i
656 ;;
657 SAVE_MIN_WITH_COVER
658 #ifdef XEN
659 alloc r15=ar.pfs,0,0,4,0
660 mov out0=cr.ifa
661 mov out1=cr.isr
662 mov out3=cr.itir
663 #else
664 alloc r15=ar.pfs,0,0,3,0
665 mov out0=cr.ifa
666 mov out1=cr.isr
667 #endif
668 adds r3=8,r2 // set up second base pointer
669 ;;
670 ssm psr.ic | PSR_DEFAULT_BITS
671 ;;
672 srlz.i // guarantee that interruption collectin is on
673 ;;
674 (p15) ssm psr.i // restore psr.i
675 movl r14=ia64_leave_kernel
676 ;;
677 SAVE_REST
678 mov rp=r14
679 ;;
680 adds out2=16,r12 // out2 = pointer to pt_regs
681 br.call.sptk.many b6=ia64_do_page_fault // ignore return address
682 END(page_fault)
684 .org ia64_ivt+0x1c00
685 /////////////////////////////////////////////////////////////////////////////////////////
686 // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
687 ENTRY(dkey_miss)
688 DBG_FAULT(7)
689 #ifdef XEN
690 REFLECT(7)
691 #endif
692 FAULT(7)
693 END(dkey_miss)
695 .org ia64_ivt+0x2000
696 /////////////////////////////////////////////////////////////////////////////////////////
697 // 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54)
698 ENTRY(dirty_bit)
699 DBG_FAULT(8)
700 #ifdef XEN
701 REFLECT(8)
702 #endif
703 /*
704 * What we do here is to simply turn on the dirty bit in the PTE. We need to
705 * update both the page-table and the TLB entry. To efficiently access the PTE,
706 * we address it through the virtual page table. Most likely, the TLB entry for
707 * the relevant virtual page table page is still present in the TLB so we can
708 * normally do this without additional TLB misses. In case the necessary virtual
709 * page table TLB entry isn't present, we take a nested TLB miss hit where we look
710 * up the physical address of the L3 PTE and then continue at label 1 below.
711 */
712 mov r16=cr.ifa // get the address that caused the fault
713 movl r30=1f // load continuation point in case of nested fault
714 ;;
715 thash r17=r16 // compute virtual address of L3 PTE
716 mov r29=b0 // save b0 in case of nested fault
717 mov r31=pr // save pr
718 #ifdef CONFIG_SMP
719 mov r28=ar.ccv // save ar.ccv
720 ;;
721 1: ld8 r18=[r17]
722 ;; // avoid RAW on r18
723 mov ar.ccv=r18 // set compare value for cmpxchg
724 or r25=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits
725 ;;
726 cmpxchg8.acq r26=[r17],r25,ar.ccv
727 mov r24=PAGE_SHIFT<<2
728 ;;
729 cmp.eq p6,p7=r26,r18
730 ;;
731 (p6) itc.d r25 // install updated PTE
732 ;;
733 /*
734 * Tell the assemblers dependency-violation checker that the above "itc" instructions
735 * cannot possibly affect the following loads:
736 */
737 dv_serialize_data
739 ld8 r18=[r17] // read PTE again
740 ;;
741 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
742 ;;
743 (p7) ptc.l r16,r24
744 mov b0=r29 // restore b0
745 mov ar.ccv=r28
746 #else
747 ;;
748 1: ld8 r18=[r17]
749 ;; // avoid RAW on r18
750 or r18=_PAGE_D|_PAGE_A,r18 // set the dirty and accessed bits
751 mov b0=r29 // restore b0
752 ;;
753 st8 [r17]=r18 // store back updated PTE
754 itc.d r18 // install updated PTE
755 #endif
756 mov pr=r31,-1 // restore pr
757 rfi
758 END(dirty_bit)
760 .org ia64_ivt+0x2400
761 /////////////////////////////////////////////////////////////////////////////////////////
762 // 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27)
763 ENTRY(iaccess_bit)
764 DBG_FAULT(9)
765 #ifdef XEN
766 mov r31=pr;
767 mov r16=cr.isr
768 mov r17=cr.ifa
769 mov r19=9
770 movl r20=0x2400
771 br.sptk.many fast_access_reflect;;
772 #endif
773 // Like Entry 8, except for instruction access
774 mov r16=cr.ifa // get the address that caused the fault
775 movl r30=1f // load continuation point in case of nested fault
776 mov r31=pr // save predicates
777 #ifdef CONFIG_ITANIUM
778 /*
779 * Erratum 10 (IFA may contain incorrect address) has "NoFix" status.
780 */
781 mov r17=cr.ipsr
782 ;;
783 mov r18=cr.iip
784 tbit.z p6,p0=r17,IA64_PSR_IS_BIT // IA64 instruction set?
785 ;;
786 (p6) mov r16=r18 // if so, use cr.iip instead of cr.ifa
787 #endif /* CONFIG_ITANIUM */
788 ;;
789 thash r17=r16 // compute virtual address of L3 PTE
790 mov r29=b0 // save b0 in case of nested fault)
791 #ifdef CONFIG_SMP
792 mov r28=ar.ccv // save ar.ccv
793 ;;
794 1: ld8 r18=[r17]
795 ;;
796 mov ar.ccv=r18 // set compare value for cmpxchg
797 or r25=_PAGE_A,r18 // set the accessed bit
798 ;;
799 cmpxchg8.acq r26=[r17],r25,ar.ccv
800 mov r24=PAGE_SHIFT<<2
801 ;;
802 cmp.eq p6,p7=r26,r18
803 ;;
804 (p6) itc.i r25 // install updated PTE
805 ;;
806 /*
807 * Tell the assemblers dependency-violation checker that the above "itc" instructions
808 * cannot possibly affect the following loads:
809 */
810 dv_serialize_data
812 ld8 r18=[r17] // read PTE again
813 ;;
814 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
815 ;;
816 (p7) ptc.l r16,r24
817 mov b0=r29 // restore b0
818 mov ar.ccv=r28
819 #else /* !CONFIG_SMP */
820 ;;
821 1: ld8 r18=[r17]
822 ;;
823 or r18=_PAGE_A,r18 // set the accessed bit
824 mov b0=r29 // restore b0
825 ;;
826 st8 [r17]=r18 // store back updated PTE
827 itc.i r18 // install updated PTE
828 #endif /* !CONFIG_SMP */
829 mov pr=r31,-1
830 rfi
831 END(iaccess_bit)
833 .org ia64_ivt+0x2800
834 /////////////////////////////////////////////////////////////////////////////////////////
835 // 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55)
836 ENTRY(daccess_bit)
837 DBG_FAULT(10)
838 #ifdef XEN
839 mov r31=pr;
840 mov r16=cr.isr
841 mov r17=cr.ifa
842 mov r19=10
843 movl r20=0x2800
844 br.sptk.many fast_access_reflect;;
845 #endif
846 // Like Entry 8, except for data access
847 mov r16=cr.ifa // get the address that caused the fault
848 movl r30=1f // load continuation point in case of nested fault
849 ;;
850 thash r17=r16 // compute virtual address of L3 PTE
851 mov r31=pr
852 mov r29=b0 // save b0 in case of nested fault)
853 #ifdef CONFIG_SMP
854 mov r28=ar.ccv // save ar.ccv
855 ;;
856 1: ld8 r18=[r17]
857 ;; // avoid RAW on r18
858 mov ar.ccv=r18 // set compare value for cmpxchg
859 or r25=_PAGE_A,r18 // set the dirty bit
860 ;;
861 cmpxchg8.acq r26=[r17],r25,ar.ccv
862 mov r24=PAGE_SHIFT<<2
863 ;;
864 cmp.eq p6,p7=r26,r18
865 ;;
866 (p6) itc.d r25 // install updated PTE
867 /*
868 * Tell the assemblers dependency-violation checker that the above "itc" instructions
869 * cannot possibly affect the following loads:
870 */
871 dv_serialize_data
872 ;;
873 ld8 r18=[r17] // read PTE again
874 ;;
875 cmp.eq p6,p7=r18,r25 // is it same as the newly installed
876 ;;
877 (p7) ptc.l r16,r24
878 mov ar.ccv=r28
879 #else
880 ;;
881 1: ld8 r18=[r17]
882 ;; // avoid RAW on r18
883 or r18=_PAGE_A,r18 // set the accessed bit
884 ;;
885 st8 [r17]=r18 // store back updated PTE
886 itc.d r18 // install updated PTE
887 #endif
888 mov b0=r29 // restore b0
889 mov pr=r31,-1
890 rfi
891 END(daccess_bit)
893 .org ia64_ivt+0x2c00
894 /////////////////////////////////////////////////////////////////////////////////////////
895 // 0x2c00 Entry 11 (size 64 bundles) Break instruction (33)
896 ENTRY(break_fault)
897 /*
898 * The streamlined system call entry/exit paths only save/restore the initial part
899 * of pt_regs. This implies that the callers of system-calls must adhere to the
900 * normal procedure calling conventions.
901 *
902 * Registers to be saved & restored:
903 * CR registers: cr.ipsr, cr.iip, cr.ifs
904 * AR registers: ar.unat, ar.pfs, ar.rsc, ar.rnat, ar.bspstore, ar.fpsr
905 * others: pr, b0, b6, loadrs, r1, r11, r12, r13, r15
906 * Registers to be restored only:
907 * r8-r11: output value from the system call.
908 *
909 * During system call exit, scratch registers (including r15) are modified/cleared
910 * to prevent leaking bits from kernel to user level.
911 */
912 DBG_FAULT(11)
913 #ifdef XEN
914 mov r16=cr.isr
915 mov r17=cr.iim
916 mov r31=pr
917 ;;
918 cmp.eq p7,p0=r17,r0
919 (p7) br.spnt.few dispatch_break_fault ;;
920 #ifdef CRASH_DEBUG
921 // panic can occur before domain0 is created.
922 // in such case referencing XSI_PSR_IC causes nested_dtlb_miss
923 movl r18=CDB_BREAK_NUM ;;
924 cmp.eq p7,p0=r17,r18 ;;
925 (p7) br.spnt.few dispatch_break_fault ;;
926 #endif
927 movl r18=XSI_PSR_IC
928 ;;
929 ld8 r19=[r18]
930 ;;
931 cmp.eq p7,p0=r0,r17 // is this a psuedo-cover?
932 (p7) br.spnt.many dispatch_privop_fault
933 ;;
934 // if vpsr.ic is off, we have a hyperprivop
935 // A hyperprivop is hand-coded assembly with psr.ic off
936 // which means no calls, no use of r1-r15 and no memory accesses
937 // except to pinned addresses!
938 cmp4.eq p7,p0=r0,r19
939 (p7) br.sptk.many fast_hyperprivop
940 ;;
941 movl r22=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
942 ld8 r22 = [r22]
943 ;;
944 adds r22=IA64_VCPU_BREAKIMM_OFFSET,r22;;
945 ld4 r23=[r22];;
946 cmp4.eq p6,p7=r23,r17 // Xen-reserved breakimm?
947 (p6) br.spnt.many dispatch_break_fault
948 ;;
949 br.sptk.many fast_break_reflect
950 ;;
951 #endif
952 movl r16=THIS_CPU(cpu_kr)+IA64_KR_CURRENT_OFFSET;;
953 ld8 r16=[r16]
954 mov r17=cr.iim
955 mov r18=__IA64_BREAK_SYSCALL
956 mov r21=ar.fpsr
957 mov r29=cr.ipsr
958 mov r19=b6
959 mov r25=ar.unat
960 mov r27=ar.rsc
961 mov r26=ar.pfs
962 mov r28=cr.iip
963 #ifndef XEN
964 mov r31=pr // prepare to save predicates
965 #endif
966 mov r20=r1
967 ;;
968 adds r16=IA64_TASK_THREAD_ON_USTACK_OFFSET,r16
969 cmp.eq p0,p7=r18,r17 // is this a system call? (p7 <- false, if so)
970 (p7) br.cond.spnt non_syscall
971 ;;
972 ld1 r17=[r16] // load current->thread.on_ustack flag
973 st1 [r16]=r0 // clear current->thread.on_ustack flag
974 add r1=-IA64_TASK_THREAD_ON_USTACK_OFFSET,r16 // set r1 for MINSTATE_START_SAVE_MIN_VIRT
975 ;;
976 invala
978 /* adjust return address so we skip over the break instruction: */
980 extr.u r8=r29,41,2 // extract ei field from cr.ipsr
981 ;;
982 cmp.eq p6,p7=2,r8 // isr.ei==2?
983 mov r2=r1 // setup r2 for ia64_syscall_setup
984 ;;
985 (p6) mov r8=0 // clear ei to 0
986 (p6) adds r28=16,r28 // switch cr.iip to next bundle cr.ipsr.ei wrapped
987 (p7) adds r8=1,r8 // increment ei to next slot
988 ;;
989 cmp.eq pKStk,pUStk=r0,r17 // are we in kernel mode already?
990 dep r29=r8,r29,41,2 // insert new ei into cr.ipsr
991 ;;
993 // switch from user to kernel RBS:
994 MINSTATE_START_SAVE_MIN_VIRT
995 br.call.sptk.many b7=ia64_syscall_setup
996 ;;
997 MINSTATE_END_SAVE_MIN_VIRT // switch to bank 1
998 ssm psr.ic | PSR_DEFAULT_BITS
999 ;;
1000 srlz.i // guarantee that interruption collection is on
1001 mov r3=NR_syscalls - 1
1002 ;;
1003 (p15) ssm psr.i // restore psr.i
1004 // p10==true means out registers are more than 8 or r15's Nat is true
1005 (p10) br.cond.spnt.many ia64_ret_from_syscall
1006 ;;
1007 movl r16=sys_call_table
1009 adds r15=-1024,r15 // r15 contains the syscall number---subtract 1024
1010 movl r2=ia64_ret_from_syscall
1011 ;;
1012 shladd r20=r15,3,r16 // r20 = sys_call_table + 8*(syscall-1024)
1013 cmp.leu p6,p7=r15,r3 // (syscall > 0 && syscall < 1024 + NR_syscalls) ?
1014 mov rp=r2 // set the real return addr
1015 ;;
1016 (p6) ld8 r20=[r20] // load address of syscall entry point
1017 (p7) movl r20=sys_ni_syscall
1019 add r2=TI_FLAGS+IA64_TASK_SIZE,r13
1020 ;;
1021 ld4 r2=[r2] // r2 = current_thread_info()->flags
1022 ;;
1023 and r2=_TIF_SYSCALL_TRACEAUDIT,r2 // mask trace or audit
1024 ;;
1025 cmp.eq p8,p0=r2,r0
1026 mov b6=r20
1027 ;;
1028 (p8) br.call.sptk.many b6=b6 // ignore this return addr
1029 br.cond.sptk ia64_trace_syscall
1030 // NOT REACHED
1031 END(break_fault)
1033 .org ia64_ivt+0x3000
1034 /////////////////////////////////////////////////////////////////////////////////////////
1035 // 0x3000 Entry 12 (size 64 bundles) External Interrupt (4)
1036 ENTRY(interrupt)
1037 DBG_FAULT(12)
1038 mov r31=pr // prepare to save predicates
1039 ;;
1040 #ifdef XEN
1041 mov r30=cr.ivr // pass cr.ivr as first arg
1042 // FIXME: this is a hack... use cpuinfo.ksoftirqd because its
1043 // not used anywhere else and we need a place to stash ivr and
1044 // there's no registers available unused by SAVE_MIN/REST
1045 movl r29=THIS_CPU(cpu_info)+IA64_CPUINFO_KSOFTIRQD_OFFSET;;
1046 st8 [r29]=r30;;
1047 movl r28=slow_interrupt;;
1048 mov r29=rp;;
1049 mov rp=r28;;
1050 br.cond.sptk.many fast_tick_reflect
1051 ;;
1052 slow_interrupt:
1053 mov rp=r29;;
1054 #endif
1055 SAVE_MIN_WITH_COVER // uses r31; defines r2 and r3
1056 ssm psr.ic | PSR_DEFAULT_BITS
1057 ;;
1058 adds r3=8,r2 // set up second base pointer for SAVE_REST
1059 srlz.i // ensure everybody knows psr.ic is back on
1060 ;;
1061 SAVE_REST
1062 ;;
1063 alloc r14=ar.pfs,0,0,2,0 // must be first in an insn group
1064 #ifdef XEN
1065 movl out0=THIS_CPU(cpu_info)+IA64_CPUINFO_KSOFTIRQD_OFFSET;;
1066 ld8 out0=[out0];;
1067 #else
1068 mov out0=cr.ivr // pass cr.ivr as first arg
1069 #endif
1070 add out1=16,sp // pass pointer to pt_regs as second arg
1071 #ifndef XEN
1072 ;;
1073 srlz.d // make sure we see the effect of cr.ivr
1074 #endif
1075 movl r14=ia64_leave_kernel
1076 ;;
1077 mov rp=r14
1078 br.call.sptk.many b6=ia64_handle_irq
1079 END(interrupt)
1081 .org ia64_ivt+0x3400
1082 /////////////////////////////////////////////////////////////////////////////////////////
1083 // 0x3400 Entry 13 (size 64 bundles) Reserved
1084 DBG_FAULT(13)
1085 FAULT(13)
1087 #ifdef XEN
1088 // There is no particular reason for this code to be here, other than that
1089 // there happens to be space here that would go unused otherwise. If this
1090 // fault ever gets "unreserved", simply moved the following code to a more
1091 // suitable spot...
1093 GLOBAL_ENTRY(dispatch_break_fault)
1094 SAVE_MIN_WITH_COVER
1095 ;;
1096 dispatch_break_fault_post_save:
1097 alloc r14=ar.pfs,0,0,4,0 // now it's safe (must be first in insn group!)
1098 mov out0=cr.ifa
1099 adds out1=16,sp
1100 mov out2=cr.isr // FIXME: pity to make this slow access twice
1101 mov out3=cr.iim // FIXME: pity to make this slow access twice
1103 ssm psr.ic | PSR_DEFAULT_BITS
1104 ;;
1105 srlz.i // guarantee that interruption collection is on
1106 ;;
1107 (p15) ssm psr.i // restore psr.i
1108 adds r3=8,r2 // set up second base pointer
1109 ;;
1110 SAVE_REST
1111 movl r14=ia64_leave_kernel
1112 ;;
1113 mov rp=r14
1114 // br.sptk.many ia64_prepare_handle_break
1115 br.call.sptk.many b6=ia64_handle_break
1116 END(dispatch_break_fault)
1117 #endif
1119 .org ia64_ivt+0x3800
1120 /////////////////////////////////////////////////////////////////////////////////////////
1121 // 0x3800 Entry 14 (size 64 bundles) Reserved
1122 DBG_FAULT(14)
1123 FAULT(14)
1125 /*
1126 * There is no particular reason for this code to be here, other than that
1127 * there happens to be space here that would go unused otherwise. If this
1128 * fault ever gets "unreserved", simply moved the following code to a more
1129 * suitable spot...
1131 * ia64_syscall_setup() is a separate subroutine so that it can
1132 * allocate stacked registers so it can safely demine any
1133 * potential NaT values from the input registers.
1135 * On entry:
1136 * - executing on bank 0 or bank 1 register set (doesn't matter)
1137 * - r1: stack pointer
1138 * - r2: current task pointer
1139 * - r3: preserved
1140 * - r11: original contents (saved ar.pfs to be saved)
1141 * - r12: original contents (sp to be saved)
1142 * - r13: original contents (tp to be saved)
1143 * - r15: original contents (syscall # to be saved)
1144 * - r18: saved bsp (after switching to kernel stack)
1145 * - r19: saved b6
1146 * - r20: saved r1 (gp)
1147 * - r21: saved ar.fpsr
1148 * - r22: kernel's register backing store base (krbs_base)
1149 * - r23: saved ar.bspstore
1150 * - r24: saved ar.rnat
1151 * - r25: saved ar.unat
1152 * - r26: saved ar.pfs
1153 * - r27: saved ar.rsc
1154 * - r28: saved cr.iip
1155 * - r29: saved cr.ipsr
1156 * - r31: saved pr
1157 * - b0: original contents (to be saved)
1158 * On exit:
1159 * - executing on bank 1 registers
1160 * - psr.ic enabled, interrupts restored
1161 * - p10: TRUE if syscall is invoked with more than 8 out
1162 * registers or r15's Nat is true
1163 * - r1: kernel's gp
1164 * - r3: preserved (same as on entry)
1165 * - r8: -EINVAL if p10 is true
1166 * - r12: points to kernel stack
1167 * - r13: points to current task
1168 * - p15: TRUE if interrupts need to be re-enabled
1169 * - ar.fpsr: set to kernel settings
1170 */
1171 GLOBAL_ENTRY(ia64_syscall_setup)
1172 #ifndef XEN
1173 #if PT(B6) != 0
1174 # error This code assumes that b6 is the first field in pt_regs.
1175 #endif
1176 #endif
1177 st8 [r1]=r19 // save b6
1178 add r16=PT(CR_IPSR),r1 // initialize first base pointer
1179 add r17=PT(R11),r1 // initialize second base pointer
1180 ;;
1181 alloc r19=ar.pfs,8,0,0,0 // ensure in0-in7 are writable
1182 st8 [r16]=r29,PT(AR_PFS)-PT(CR_IPSR) // save cr.ipsr
1183 tnat.nz p8,p0=in0
1185 st8.spill [r17]=r11,PT(CR_IIP)-PT(R11) // save r11
1186 tnat.nz p9,p0=in1
1187 (pKStk) mov r18=r0 // make sure r18 isn't NaT
1188 ;;
1190 st8 [r16]=r26,PT(CR_IFS)-PT(AR_PFS) // save ar.pfs
1191 st8 [r17]=r28,PT(AR_UNAT)-PT(CR_IIP) // save cr.iip
1192 mov r28=b0 // save b0 (2 cyc)
1193 ;;
1195 st8 [r17]=r25,PT(AR_RSC)-PT(AR_UNAT) // save ar.unat
1196 dep r19=0,r19,38,26 // clear all bits but 0..37 [I0]
1197 (p8) mov in0=-1
1198 ;;
1200 st8 [r16]=r19,PT(AR_RNAT)-PT(CR_IFS) // store ar.pfs.pfm in cr.ifs
1201 extr.u r11=r19,7,7 // I0 // get sol of ar.pfs
1202 and r8=0x7f,r19 // A // get sof of ar.pfs
1204 st8 [r17]=r27,PT(AR_BSPSTORE)-PT(AR_RSC)// save ar.rsc
1205 tbit.nz p15,p0=r29,IA64_PSR_I_BIT // I0
1206 (p9) mov in1=-1
1207 ;;
1209 (pUStk) sub r18=r18,r22 // r18=RSE.ndirty*8
1210 tnat.nz p10,p0=in2
1211 add r11=8,r11
1212 ;;
1213 (pKStk) adds r16=PT(PR)-PT(AR_RNAT),r16 // skip over ar_rnat field
1214 (pKStk) adds r17=PT(B0)-PT(AR_BSPSTORE),r17 // skip over ar_bspstore field
1215 tnat.nz p11,p0=in3
1216 ;;
1217 (p10) mov in2=-1
1218 tnat.nz p12,p0=in4 // [I0]
1219 (p11) mov in3=-1
1220 ;;
1221 (pUStk) st8 [r16]=r24,PT(PR)-PT(AR_RNAT) // save ar.rnat
1222 (pUStk) st8 [r17]=r23,PT(B0)-PT(AR_BSPSTORE) // save ar.bspstore
1223 shl r18=r18,16 // compute ar.rsc to be used for "loadrs"
1224 ;;
1225 st8 [r16]=r31,PT(LOADRS)-PT(PR) // save predicates
1226 st8 [r17]=r28,PT(R1)-PT(B0) // save b0
1227 tnat.nz p13,p0=in5 // [I0]
1228 ;;
1229 st8 [r16]=r18,PT(R12)-PT(LOADRS) // save ar.rsc value for "loadrs"
1230 st8.spill [r17]=r20,PT(R13)-PT(R1) // save original r1
1231 (p12) mov in4=-1
1232 ;;
1234 .mem.offset 0,0; st8.spill [r16]=r12,PT(AR_FPSR)-PT(R12) // save r12
1235 .mem.offset 8,0; st8.spill [r17]=r13,PT(R15)-PT(R13) // save r13
1236 (p13) mov in5=-1
1237 ;;
1238 st8 [r16]=r21,PT(R8)-PT(AR_FPSR) // save ar.fpsr
1239 tnat.nz p14,p0=in6
1240 cmp.lt p10,p9=r11,r8 // frame size can't be more than local+8
1241 ;;
1242 stf8 [r16]=f1 // ensure pt_regs.r8 != 0 (see handle_syscall_error)
1243 (p9) tnat.nz p10,p0=r15
1244 adds r12=-16,r1 // switch to kernel memory stack (with 16 bytes of scratch)
1246 st8.spill [r17]=r15 // save r15
1247 tnat.nz p8,p0=in7
1248 nop.i 0
1250 mov r13=r2 // establish `current'
1251 movl r1=__gp // establish kernel global pointer
1252 ;;
1253 (p14) mov in6=-1
1254 (p8) mov in7=-1
1255 nop.i 0
1257 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
1258 movl r17=FPSR_DEFAULT
1259 ;;
1260 mov.m ar.fpsr=r17 // set ar.fpsr to kernel default value
1261 (p10) mov r8=-EINVAL
1262 br.ret.sptk.many b7
1263 END(ia64_syscall_setup)
1265 .org ia64_ivt+0x3c00
1266 /////////////////////////////////////////////////////////////////////////////////////////
1267 // 0x3c00 Entry 15 (size 64 bundles) Reserved
1268 DBG_FAULT(15)
1269 FAULT(15)
1271 /*
1272 * Squatting in this space ...
1274 * This special case dispatcher for illegal operation faults allows preserved
1275 * registers to be modified through a callback function (asm only) that is handed
1276 * back from the fault handler in r8. Up to three arguments can be passed to the
1277 * callback function by returning an aggregate with the callback as its first
1278 * element, followed by the arguments.
1279 */
1280 ENTRY(dispatch_illegal_op_fault)
1281 SAVE_MIN_WITH_COVER
1282 ssm psr.ic | PSR_DEFAULT_BITS
1283 ;;
1284 srlz.i // guarantee that interruption collection is on
1285 ;;
1286 (p15) ssm psr.i // restore psr.i
1287 adds r3=8,r2 // set up second base pointer for SAVE_REST
1288 ;;
1289 alloc r14=ar.pfs,0,0,1,0 // must be first in insn group
1290 mov out0=ar.ec
1291 ;;
1292 SAVE_REST
1293 ;;
1294 br.call.sptk.many rp=ia64_illegal_op_fault
1295 .ret0: ;;
1296 alloc r14=ar.pfs,0,0,3,0 // must be first in insn group
1297 mov out0=r9
1298 mov out1=r10
1299 mov out2=r11
1300 movl r15=ia64_leave_kernel
1301 ;;
1302 mov rp=r15
1303 mov b6=r8
1304 ;;
1305 cmp.ne p6,p0=0,r8
1306 (p6) br.call.dpnt.many b6=b6 // call returns to ia64_leave_kernel
1307 br.sptk.many ia64_leave_kernel
1308 END(dispatch_illegal_op_fault)
1310 .org ia64_ivt+0x4000
1311 /////////////////////////////////////////////////////////////////////////////////////////
1312 // 0x4000 Entry 16 (size 64 bundles) Reserved
1313 DBG_FAULT(16)
1314 FAULT(16)
1316 #ifdef XEN
1317 // There is no particular reason for this code to be here, other than that
1318 // there happens to be space here that would go unused otherwise. If this
1319 // fault ever gets "unreserved", simply moved the following code to a more
1320 // suitable spot...
1322 ENTRY(dispatch_privop_fault)
1323 SAVE_MIN_WITH_COVER
1324 ;;
1325 alloc r14=ar.pfs,0,0,4,0 // now it's safe (must be first in insn group!)
1326 mov out0=cr.ifa
1327 adds out1=16,sp
1328 mov out2=cr.isr // FIXME: pity to make this slow access twice
1329 mov out3=cr.itir
1331 ssm psr.ic | PSR_DEFAULT_BITS
1332 ;;
1333 srlz.i // guarantee that interruption collection is on
1334 ;;
1335 (p15) ssm psr.i // restore psr.i
1336 adds r3=8,r2 // set up second base pointer
1337 ;;
1338 SAVE_REST
1339 movl r14=ia64_leave_kernel
1340 ;;
1341 mov rp=r14
1342 // br.sptk.many ia64_prepare_handle_privop
1343 br.call.sptk.many b6=ia64_handle_privop
1344 END(dispatch_privop_fault)
1345 #endif
1348 .org ia64_ivt+0x4400
1349 /////////////////////////////////////////////////////////////////////////////////////////
1350 // 0x4400 Entry 17 (size 64 bundles) Reserved
1351 DBG_FAULT(17)
1352 FAULT(17)
1354 ENTRY(non_syscall)
1355 SAVE_MIN_WITH_COVER
1357 // There is no particular reason for this code to be here, other than that
1358 // there happens to be space here that would go unused otherwise. If this
1359 // fault ever gets "unreserved", simply moved the following code to a more
1360 // suitable spot...
1362 alloc r14=ar.pfs,0,0,2,0
1363 mov out0=cr.iim
1364 add out1=16,sp
1365 adds r3=8,r2 // set up second base pointer for SAVE_REST
1367 ssm psr.ic | PSR_DEFAULT_BITS
1368 ;;
1369 srlz.i // guarantee that interruption collection is on
1370 ;;
1371 (p15) ssm psr.i // restore psr.i
1372 movl r15=ia64_leave_kernel
1373 ;;
1374 SAVE_REST
1375 mov rp=r15
1376 ;;
1377 br.call.sptk.many b6=ia64_bad_break // avoid WAW on CFM and ignore return addr
1378 END(non_syscall)
1380 .org ia64_ivt+0x4800
1381 /////////////////////////////////////////////////////////////////////////////////////////
1382 // 0x4800 Entry 18 (size 64 bundles) Reserved
1383 DBG_FAULT(18)
1384 FAULT(18)
1386 /*
1387 * There is no particular reason for this code to be here, other than that
1388 * there happens to be space here that would go unused otherwise. If this
1389 * fault ever gets "unreserved", simply moved the following code to a more
1390 * suitable spot...
1391 */
1393 ENTRY(dispatch_unaligned_handler)
1394 SAVE_MIN_WITH_COVER
1395 ;;
1396 alloc r14=ar.pfs,0,0,2,0 // now it's safe (must be first in insn group!)
1397 mov out0=cr.ifa
1398 adds out1=16,sp
1400 ssm psr.ic | PSR_DEFAULT_BITS
1401 ;;
1402 srlz.i // guarantee that interruption collection is on
1403 ;;
1404 (p15) ssm psr.i // restore psr.i
1405 adds r3=8,r2 // set up second base pointer
1406 ;;
1407 SAVE_REST
1408 movl r14=ia64_leave_kernel
1409 ;;
1410 mov rp=r14
1411 // br.sptk.many ia64_prepare_handle_unaligned
1412 br.call.sptk.many b6=ia64_handle_unaligned
1413 END(dispatch_unaligned_handler)
1415 .org ia64_ivt+0x4c00
1416 /////////////////////////////////////////////////////////////////////////////////////////
1417 // 0x4c00 Entry 19 (size 64 bundles) Reserved
1418 DBG_FAULT(19)
1419 FAULT(19)
1421 /*
1422 * There is no particular reason for this code to be here, other than that
1423 * there happens to be space here that would go unused otherwise. If this
1424 * fault ever gets "unreserved", simply moved the following code to a more
1425 * suitable spot...
1426 */
1428 ENTRY(dispatch_to_fault_handler)
1429 /*
1430 * Input:
1431 * psr.ic: off
1432 * r19: fault vector number (e.g., 24 for General Exception)
1433 * r31: contains saved predicates (pr)
1434 */
1435 SAVE_MIN_WITH_COVER_R19
1436 alloc r14=ar.pfs,0,0,5,0
1437 mov out0=r15
1438 mov out1=cr.isr
1439 mov out2=cr.ifa
1440 mov out3=cr.iim
1441 mov out4=cr.itir
1442 ;;
1443 ssm psr.ic | PSR_DEFAULT_BITS
1444 ;;
1445 srlz.i // guarantee that interruption collection is on
1446 ;;
1447 (p15) ssm psr.i // restore psr.i
1448 adds r3=8,r2 // set up second base pointer for SAVE_REST
1449 ;;
1450 SAVE_REST
1451 movl r14=ia64_leave_kernel
1452 ;;
1453 mov rp=r14
1454 br.call.sptk.many b6=ia64_fault
1455 END(dispatch_to_fault_handler)
1457 //
1458 // --- End of long entries, Beginning of short entries
1459 //
1461 .org ia64_ivt+0x5000
1462 /////////////////////////////////////////////////////////////////////////////////////////
1463 // 0x5000 Entry 20 (size 16 bundles) Page Not Present (10,22,49)
1464 ENTRY(page_not_present)
1465 DBG_FAULT(20)
1466 #ifdef XEN
1467 REFLECT(20)
1468 #endif
1469 mov r16=cr.ifa
1470 rsm psr.dt
1471 /*
1472 * The Linux page fault handler doesn't expect non-present pages to be in
1473 * the TLB. Flush the existing entry now, so we meet that expectation.
1474 */
1475 mov r17=PAGE_SHIFT<<2
1476 ;;
1477 ptc.l r16,r17
1478 ;;
1479 mov r31=pr
1480 srlz.d
1481 br.sptk.many page_fault
1482 END(page_not_present)
1484 .org ia64_ivt+0x5100
1485 /////////////////////////////////////////////////////////////////////////////////////////
1486 // 0x5100 Entry 21 (size 16 bundles) Key Permission (13,25,52)
1487 ENTRY(key_permission)
1488 DBG_FAULT(21)
1489 #ifdef XEN
1490 REFLECT(21)
1491 #endif
1492 mov r16=cr.ifa
1493 rsm psr.dt
1494 mov r31=pr
1495 ;;
1496 srlz.d
1497 br.sptk.many page_fault
1498 END(key_permission)
1500 .org ia64_ivt+0x5200
1501 /////////////////////////////////////////////////////////////////////////////////////////
1502 // 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26)
1503 ENTRY(iaccess_rights)
1504 DBG_FAULT(22)
1505 #ifdef XEN
1506 REFLECT(22)
1507 #endif
1508 mov r16=cr.ifa
1509 rsm psr.dt
1510 mov r31=pr
1511 ;;
1512 srlz.d
1513 br.sptk.many page_fault
1514 END(iaccess_rights)
1516 .org ia64_ivt+0x5300
1517 /////////////////////////////////////////////////////////////////////////////////////////
1518 // 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53)
1519 ENTRY(daccess_rights)
1520 DBG_FAULT(23)
1521 #ifdef XEN
1522 mov r31=pr;
1523 mov r16=cr.isr
1524 mov r17=cr.ifa
1525 mov r19=23
1526 movl r20=0x5300
1527 br.sptk.many fast_access_reflect;;
1528 #endif
1529 mov r16=cr.ifa
1530 rsm psr.dt
1531 mov r31=pr
1532 ;;
1533 srlz.d
1534 br.sptk.many page_fault
1535 END(daccess_rights)
1537 .org ia64_ivt+0x5400
1538 /////////////////////////////////////////////////////////////////////////////////////////
1539 // 0x5400 Entry 24 (size 16 bundles) General Exception (5,32,34,36,38,39)
1540 ENTRY(general_exception)
1541 DBG_FAULT(24)
1542 mov r16=cr.isr
1543 mov r31=pr
1544 ;;
1545 #ifdef XEN
1546 cmp4.ge p6,p0=0x20,r16
1547 (p6) br.sptk.many dispatch_privop_fault
1548 #else
1549 cmp4.eq p6,p0=0,r16
1550 (p6) br.sptk.many dispatch_illegal_op_fault
1551 #endif
1552 ;;
1553 mov r19=24 // fault number
1554 br.sptk.many dispatch_to_fault_handler
1555 END(general_exception)
1557 .org ia64_ivt+0x5500
1558 /////////////////////////////////////////////////////////////////////////////////////////
1559 // 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35)
1560 ENTRY(disabled_fp_reg)
1561 DBG_FAULT(25)
1562 #ifdef XEN
1563 #if 0
1564 mov r20=pr
1565 movl r16=0x2000000000000000
1566 movl r17=0x2000000000176b60
1567 mov r18=cr.iip
1568 mov r19=rr[r16]
1569 movl r22=0xe95d0439
1570 ;;
1571 mov pr=r0,-1
1572 ;;
1573 cmp.eq p6,p7=r22,r19
1574 ;;
1575 (p6) cmp.eq p8,p9=r17,r18
1576 (p8) br.sptk.few floating_panic
1577 ;;
1578 mov pr=r20,-1
1579 ;;
1580 #endif
1581 REFLECT(25)
1582 //floating_panic:
1583 // br.sptk.many floating_panic
1584 ;;
1585 #endif
1586 rsm psr.dfh // ensure we can access fph
1587 ;;
1588 srlz.d
1589 mov r31=pr
1590 mov r19=25
1591 br.sptk.many dispatch_to_fault_handler
1592 END(disabled_fp_reg)
1594 .org ia64_ivt+0x5600
1595 /////////////////////////////////////////////////////////////////////////////////////////
1596 // 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50)
1597 ENTRY(nat_consumption)
1598 DBG_FAULT(26)
1599 #ifdef XEN
1600 REFLECT(26)
1601 #endif
1602 FAULT(26)
1603 END(nat_consumption)
1605 .org ia64_ivt+0x5700
1606 /////////////////////////////////////////////////////////////////////////////////////////
1607 // 0x5700 Entry 27 (size 16 bundles) Speculation (40)
1608 ENTRY(speculation_vector)
1609 DBG_FAULT(27)
1610 #ifdef XEN
1611 // this probably need not reflect...
1612 REFLECT(27)
1613 #endif
1614 /*
1615 * A [f]chk.[as] instruction needs to take the branch to the recovery code but
1616 * this part of the architecture is not implemented in hardware on some CPUs, such
1617 * as Itanium. Thus, in general we need to emulate the behavior. IIM contains
1618 * the relative target (not yet sign extended). So after sign extending it we
1619 * simply add it to IIP. We also need to reset the EI field of the IPSR to zero,
1620 * i.e., the slot to restart into.
1622 * cr.imm contains zero_ext(imm21)
1623 */
1624 mov r18=cr.iim
1625 ;;
1626 mov r17=cr.iip
1627 shl r18=r18,43 // put sign bit in position (43=64-21)
1628 ;;
1630 mov r16=cr.ipsr
1631 shr r18=r18,39 // sign extend (39=43-4)
1632 ;;
1634 add r17=r17,r18 // now add the offset
1635 ;;
1636 mov cr.iip=r17
1637 dep r16=0,r16,41,2 // clear EI
1638 ;;
1640 mov cr.ipsr=r16
1641 ;;
1643 rfi // and go back
1644 END(speculation_vector)
1646 .org ia64_ivt+0x5800
1647 /////////////////////////////////////////////////////////////////////////////////////////
1648 // 0x5800 Entry 28 (size 16 bundles) Reserved
1649 DBG_FAULT(28)
1650 FAULT(28)
1652 .org ia64_ivt+0x5900
1653 /////////////////////////////////////////////////////////////////////////////////////////
1654 // 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56)
1655 ENTRY(debug_vector)
1656 DBG_FAULT(29)
1657 #ifdef XEN
1658 REFLECT(29)
1659 #endif
1660 FAULT(29)
1661 END(debug_vector)
1663 .org ia64_ivt+0x5a00
1664 /////////////////////////////////////////////////////////////////////////////////////////
1665 // 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57)
1666 ENTRY(unaligned_access)
1667 DBG_FAULT(30)
1668 #ifdef XEN
1669 REFLECT(30)
1670 #endif
1671 mov r16=cr.ipsr
1672 mov r31=pr // prepare to save predicates
1673 ;;
1674 br.sptk.many dispatch_unaligned_handler
1675 END(unaligned_access)
1677 .org ia64_ivt+0x5b00
1678 /////////////////////////////////////////////////////////////////////////////////////////
1679 // 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57)
1680 ENTRY(unsupported_data_reference)
1681 DBG_FAULT(31)
1682 #ifdef XEN
1683 REFLECT(31)
1684 #endif
1685 FAULT(31)
1686 END(unsupported_data_reference)
1688 .org ia64_ivt+0x5c00
1689 /////////////////////////////////////////////////////////////////////////////////////////
1690 // 0x5c00 Entry 32 (size 16 bundles) Floating-Point Fault (64)
1691 ENTRY(floating_point_fault)
1692 DBG_FAULT(32)
1693 #ifdef XEN
1694 REFLECT(32)
1695 #endif
1696 FAULT(32)
1697 END(floating_point_fault)
1699 .org ia64_ivt+0x5d00
1700 /////////////////////////////////////////////////////////////////////////////////////////
1701 // 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66)
1702 ENTRY(floating_point_trap)
1703 DBG_FAULT(33)
1704 #ifdef XEN
1705 REFLECT(33)
1706 #endif
1707 FAULT(33)
1708 END(floating_point_trap)
1710 .org ia64_ivt+0x5e00
1711 /////////////////////////////////////////////////////////////////////////////////////////
1712 // 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Transfer Trap (66)
1713 ENTRY(lower_privilege_trap)
1714 DBG_FAULT(34)
1715 #ifdef XEN
1716 REFLECT(34)
1717 #endif
1718 FAULT(34)
1719 END(lower_privilege_trap)
1721 .org ia64_ivt+0x5f00
1722 /////////////////////////////////////////////////////////////////////////////////////////
1723 // 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68)
1724 ENTRY(taken_branch_trap)
1725 DBG_FAULT(35)
1726 #ifdef XEN
1727 REFLECT(35)
1728 #endif
1729 FAULT(35)
1730 END(taken_branch_trap)
1732 .org ia64_ivt+0x6000
1733 /////////////////////////////////////////////////////////////////////////////////////////
1734 // 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69)
1735 ENTRY(single_step_trap)
1736 DBG_FAULT(36)
1737 #ifdef XEN
1738 REFLECT(36)
1739 #endif
1740 FAULT(36)
1741 END(single_step_trap)
1743 .org ia64_ivt+0x6100
1744 /////////////////////////////////////////////////////////////////////////////////////////
1745 // 0x6100 Entry 37 (size 16 bundles) Reserved
1746 DBG_FAULT(37)
1747 FAULT(37)
1749 .org ia64_ivt+0x6200
1750 /////////////////////////////////////////////////////////////////////////////////////////
1751 // 0x6200 Entry 38 (size 16 bundles) Reserved
1752 DBG_FAULT(38)
1753 FAULT(38)
1755 .org ia64_ivt+0x6300
1756 /////////////////////////////////////////////////////////////////////////////////////////
1757 // 0x6300 Entry 39 (size 16 bundles) Reserved
1758 DBG_FAULT(39)
1759 FAULT(39)
1761 .org ia64_ivt+0x6400
1762 /////////////////////////////////////////////////////////////////////////////////////////
1763 // 0x6400 Entry 40 (size 16 bundles) Reserved
1764 DBG_FAULT(40)
1765 FAULT(40)
1767 .org ia64_ivt+0x6500
1768 /////////////////////////////////////////////////////////////////////////////////////////
1769 // 0x6500 Entry 41 (size 16 bundles) Reserved
1770 DBG_FAULT(41)
1771 FAULT(41)
1773 .org ia64_ivt+0x6600
1774 /////////////////////////////////////////////////////////////////////////////////////////
1775 // 0x6600 Entry 42 (size 16 bundles) Reserved
1776 DBG_FAULT(42)
1777 FAULT(42)
1779 .org ia64_ivt+0x6700
1780 /////////////////////////////////////////////////////////////////////////////////////////
1781 // 0x6700 Entry 43 (size 16 bundles) Reserved
1782 DBG_FAULT(43)
1783 FAULT(43)
1785 .org ia64_ivt+0x6800
1786 /////////////////////////////////////////////////////////////////////////////////////////
1787 // 0x6800 Entry 44 (size 16 bundles) Reserved
1788 DBG_FAULT(44)
1789 FAULT(44)
1791 .org ia64_ivt+0x6900
1792 /////////////////////////////////////////////////////////////////////////////////////////
1793 // 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,44,58,60,61,62,72,73,75,76,77)
1794 ENTRY(ia32_exception)
1795 DBG_FAULT(45)
1796 #ifdef XEN
1797 REFLECT(45)
1798 #endif
1799 FAULT(45)
1800 END(ia32_exception)
1802 .org ia64_ivt+0x6a00
1803 /////////////////////////////////////////////////////////////////////////////////////////
1804 // 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept (30,31,59,70,71)
1805 ENTRY(ia32_intercept)
1806 DBG_FAULT(46)
1807 #ifdef XEN
1808 REFLECT(46)
1809 #endif
1810 #ifdef CONFIG_IA32_SUPPORT
1811 mov r31=pr
1812 mov r16=cr.isr
1813 ;;
1814 extr.u r17=r16,16,8 // get ISR.code
1815 mov r18=ar.eflag
1816 mov r19=cr.iim // old eflag value
1817 ;;
1818 cmp.ne p6,p0=2,r17
1819 (p6) br.cond.spnt 1f // not a system flag fault
1820 xor r16=r18,r19
1821 ;;
1822 extr.u r17=r16,18,1 // get the eflags.ac bit
1823 ;;
1824 cmp.eq p6,p0=0,r17
1825 (p6) br.cond.spnt 1f // eflags.ac bit didn't change
1826 ;;
1827 mov pr=r31,-1 // restore predicate registers
1828 rfi
1830 1:
1831 #endif // CONFIG_IA32_SUPPORT
1832 FAULT(46)
1833 END(ia32_intercept)
1835 .org ia64_ivt+0x6b00
1836 /////////////////////////////////////////////////////////////////////////////////////////
1837 // 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt (74)
1838 ENTRY(ia32_interrupt)
1839 DBG_FAULT(47)
1840 #ifdef XEN
1841 REFLECT(47)
1842 #endif
1843 #ifdef CONFIG_IA32_SUPPORT
1844 mov r31=pr
1845 br.sptk.many dispatch_to_ia32_handler
1846 #else
1847 FAULT(47)
1848 #endif
1849 END(ia32_interrupt)
1851 .org ia64_ivt+0x6c00
1852 /////////////////////////////////////////////////////////////////////////////////////////
1853 // 0x6c00 Entry 48 (size 16 bundles) Reserved
1854 DBG_FAULT(48)
1855 FAULT(48)
1857 .org ia64_ivt+0x6d00
1858 /////////////////////////////////////////////////////////////////////////////////////////
1859 // 0x6d00 Entry 49 (size 16 bundles) Reserved
1860 DBG_FAULT(49)
1861 FAULT(49)
1863 .org ia64_ivt+0x6e00
1864 /////////////////////////////////////////////////////////////////////////////////////////
1865 // 0x6e00 Entry 50 (size 16 bundles) Reserved
1866 DBG_FAULT(50)
1867 FAULT(50)
1869 .org ia64_ivt+0x6f00
1870 /////////////////////////////////////////////////////////////////////////////////////////
1871 // 0x6f00 Entry 51 (size 16 bundles) Reserved
1872 DBG_FAULT(51)
1873 FAULT(51)
1875 .org ia64_ivt+0x7000
1876 /////////////////////////////////////////////////////////////////////////////////////////
1877 // 0x7000 Entry 52 (size 16 bundles) Reserved
1878 DBG_FAULT(52)
1879 FAULT(52)
1881 .org ia64_ivt+0x7100
1882 /////////////////////////////////////////////////////////////////////////////////////////
1883 // 0x7100 Entry 53 (size 16 bundles) Reserved
1884 DBG_FAULT(53)
1885 FAULT(53)
1887 .org ia64_ivt+0x7200
1888 /////////////////////////////////////////////////////////////////////////////////////////
1889 // 0x7200 Entry 54 (size 16 bundles) Reserved
1890 DBG_FAULT(54)
1891 FAULT(54)
1893 .org ia64_ivt+0x7300
1894 /////////////////////////////////////////////////////////////////////////////////////////
1895 // 0x7300 Entry 55 (size 16 bundles) Reserved
1896 DBG_FAULT(55)
1897 FAULT(55)
1899 .org ia64_ivt+0x7400
1900 /////////////////////////////////////////////////////////////////////////////////////////
1901 // 0x7400 Entry 56 (size 16 bundles) Reserved
1902 DBG_FAULT(56)
1903 FAULT(56)
1905 .org ia64_ivt+0x7500
1906 /////////////////////////////////////////////////////////////////////////////////////////
1907 // 0x7500 Entry 57 (size 16 bundles) Reserved
1908 DBG_FAULT(57)
1909 FAULT(57)
1911 .org ia64_ivt+0x7600
1912 /////////////////////////////////////////////////////////////////////////////////////////
1913 // 0x7600 Entry 58 (size 16 bundles) Reserved
1914 DBG_FAULT(58)
1915 FAULT(58)
1917 .org ia64_ivt+0x7700
1918 /////////////////////////////////////////////////////////////////////////////////////////
1919 // 0x7700 Entry 59 (size 16 bundles) Reserved
1920 DBG_FAULT(59)
1921 FAULT(59)
1923 .org ia64_ivt+0x7800
1924 /////////////////////////////////////////////////////////////////////////////////////////
1925 // 0x7800 Entry 60 (size 16 bundles) Reserved
1926 DBG_FAULT(60)
1927 FAULT(60)
1929 .org ia64_ivt+0x7900
1930 /////////////////////////////////////////////////////////////////////////////////////////
1931 // 0x7900 Entry 61 (size 16 bundles) Reserved
1932 DBG_FAULT(61)
1933 FAULT(61)
1935 .org ia64_ivt+0x7a00
1936 /////////////////////////////////////////////////////////////////////////////////////////
1937 // 0x7a00 Entry 62 (size 16 bundles) Reserved
1938 DBG_FAULT(62)
1939 FAULT(62)
1941 .org ia64_ivt+0x7b00
1942 /////////////////////////////////////////////////////////////////////////////////////////
1943 // 0x7b00 Entry 63 (size 16 bundles) Reserved
1944 DBG_FAULT(63)
1945 FAULT(63)
1947 .org ia64_ivt+0x7c00
1948 /////////////////////////////////////////////////////////////////////////////////////////
1949 // 0x7c00 Entry 64 (size 16 bundles) Reserved
1950 DBG_FAULT(64)
1951 FAULT(64)
1953 .org ia64_ivt+0x7d00
1954 /////////////////////////////////////////////////////////////////////////////////////////
1955 // 0x7d00 Entry 65 (size 16 bundles) Reserved
1956 DBG_FAULT(65)
1957 FAULT(65)
1959 .org ia64_ivt+0x7e00
1960 /////////////////////////////////////////////////////////////////////////////////////////
1961 // 0x7e00 Entry 66 (size 16 bundles) Reserved
1962 DBG_FAULT(66)
1963 FAULT(66)
1965 .org ia64_ivt+0x7f00
1966 /////////////////////////////////////////////////////////////////////////////////////////
1967 // 0x7f00 Entry 67 (size 16 bundles) Reserved
1968 DBG_FAULT(67)
1969 FAULT(67)
1971 #ifdef XEN
1972 .org ia64_ivt+0x8000
1973 GLOBAL_ENTRY(dispatch_reflection)
1974 /*
1975 * Input:
1976 * psr.ic: off
1977 * r19: intr type (offset into ivt, see ia64_int.h)
1978 * r31: contains saved predicates (pr)
1979 */
1980 SAVE_MIN_WITH_COVER_R19
1981 alloc r14=ar.pfs,0,0,5,0
1982 mov out4=r15
1983 mov out0=cr.ifa
1984 adds out1=16,sp
1985 mov out2=cr.isr
1986 mov out3=cr.iim
1987 // mov out3=cr.itir
1989 ssm psr.ic | PSR_DEFAULT_BITS
1990 ;;
1991 srlz.i // guarantee that interruption collection is on
1992 ;;
1993 (p15) ssm psr.i // restore psr.i
1994 adds r3=8,r2 // set up second base pointer
1995 ;;
1996 SAVE_REST
1997 movl r14=ia64_leave_kernel
1998 ;;
1999 mov rp=r14
2000 // br.sptk.many ia64_prepare_handle_reflection
2001 br.call.sptk.many b6=ia64_handle_reflection
2002 END(dispatch_reflection)
2004 #define SAVE_MIN_COVER_DONE DO_SAVE_MIN(,mov r30=cr.ifs,)
2006 // same as dispatch_break_fault except cover has already been done
2007 GLOBAL_ENTRY(dispatch_slow_hyperprivop)
2008 SAVE_MIN_COVER_DONE
2009 ;;
2010 br.sptk.many dispatch_break_fault_post_save
2011 END(dispatch_slow_hyperprivop)
2012 #endif
2014 #ifdef CONFIG_IA32_SUPPORT
2016 /*
2017 * There is no particular reason for this code to be here, other than that
2018 * there happens to be space here that would go unused otherwise. If this
2019 * fault ever gets "unreserved", simply moved the following code to a more
2020 * suitable spot...
2021 */
2023 // IA32 interrupt entry point
2025 ENTRY(dispatch_to_ia32_handler)
2026 SAVE_MIN
2027 ;;
2028 mov r14=cr.isr
2029 ssm psr.ic | PSR_DEFAULT_BITS
2030 ;;
2031 srlz.i // guarantee that interruption collection is on
2032 ;;
2033 (p15) ssm psr.i
2034 adds r3=8,r2 // Base pointer for SAVE_REST
2035 ;;
2036 SAVE_REST
2037 ;;
2038 mov r15=0x80
2039 shr r14=r14,16 // Get interrupt number
2040 ;;
2041 cmp.ne p6,p0=r14,r15
2042 (p6) br.call.dpnt.many b6=non_ia32_syscall
2044 adds r14=IA64_PT_REGS_R8_OFFSET + 16,sp // 16 byte hole per SW conventions
2045 adds r15=IA64_PT_REGS_R1_OFFSET + 16,sp
2046 ;;
2047 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
2048 ld8 r8=[r14] // get r8
2049 ;;
2050 st8 [r15]=r8 // save original EAX in r1 (IA32 procs don't use the GP)
2051 ;;
2052 alloc r15=ar.pfs,0,0,6,0 // must first in an insn group
2053 ;;
2054 ld4 r8=[r14],8 // r8 == eax (syscall number)
2055 mov r15=IA32_NR_syscalls
2056 ;;
2057 cmp.ltu.unc p6,p7=r8,r15
2058 ld4 out1=[r14],8 // r9 == ecx
2059 ;;
2060 ld4 out2=[r14],8 // r10 == edx
2061 ;;
2062 ld4 out0=[r14] // r11 == ebx
2063 adds r14=(IA64_PT_REGS_R13_OFFSET) + 16,sp
2064 ;;
2065 ld4 out5=[r14],PT(R14)-PT(R13) // r13 == ebp
2066 ;;
2067 ld4 out3=[r14],PT(R15)-PT(R14) // r14 == esi
2068 adds r2=TI_FLAGS+IA64_TASK_SIZE,r13
2069 ;;
2070 ld4 out4=[r14] // r15 == edi
2071 movl r16=ia32_syscall_table
2072 ;;
2073 (p6) shladd r16=r8,3,r16 // force ni_syscall if not valid syscall number
2074 ld4 r2=[r2] // r2 = current_thread_info()->flags
2075 ;;
2076 ld8 r16=[r16]
2077 and r2=_TIF_SYSCALL_TRACEAUDIT,r2 // mask trace or audit
2078 ;;
2079 mov b6=r16
2080 movl r15=ia32_ret_from_syscall
2081 cmp.eq p8,p0=r2,r0
2082 ;;
2083 mov rp=r15
2084 (p8) br.call.sptk.many b6=b6
2085 br.cond.sptk ia32_trace_syscall
2087 non_ia32_syscall:
2088 alloc r15=ar.pfs,0,0,2,0
2089 mov out0=r14 // interrupt #
2090 add out1=16,sp // pointer to pt_regs
2091 ;; // avoid WAW on CFM
2092 br.call.sptk.many rp=ia32_bad_interrupt
2093 .ret1: movl r15=ia64_leave_kernel
2094 ;;
2095 mov rp=r15
2096 br.ret.sptk.many rp
2097 END(dispatch_to_ia32_handler)
2099 #endif /* CONFIG_IA32_SUPPORT */