ia64/xen-unstable

view xen/arch/ia64/linux-xen/unaligned.c @ 13410:f159e81e0b44

[IA64]: noreturn cannot be used if function may return

The functions die_if_kernel and vmx_die_if_kernel can certainly
return. This disqualifies them from using the noreturn keyword
which is reserved for functions that never return.

Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
author kfraser@localhost.localdomain
date Fri Jan 12 14:50:01 2007 +0000 (2007-01-12)
parents 997bd5fcf307
children bd69e83b65ea
line source
1 /*
2 * Architecture-specific unaligned trap handling.
3 *
4 * Copyright (C) 1999-2002, 2004 Hewlett-Packard Co
5 * Stephane Eranian <eranian@hpl.hp.com>
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 *
8 * 2002/12/09 Fix rotating register handling (off-by-1 error, missing fr-rotation). Fix
9 * get_rse_reg() to not leak kernel bits to user-level (reading an out-of-frame
10 * stacked register returns an undefined value; it does NOT trigger a
11 * "rsvd register fault").
12 * 2001/10/11 Fix unaligned access to rotating registers in s/w pipelined loops.
13 * 2001/08/13 Correct size of extended floats (float_fsz) from 16 to 10 bytes.
14 * 2001/01/17 Add support emulation of unaligned kernel accesses.
15 */
16 #include <linux/kernel.h>
17 #include <linux/sched.h>
18 #include <linux/smp_lock.h>
19 #include <linux/tty.h>
21 #include <asm/intrinsics.h>
22 #include <asm/processor.h>
23 #include <asm/rse.h>
24 #include <asm/uaccess.h>
25 #include <asm/unaligned.h>
27 extern void die_if_kernel(char *str, struct pt_regs *regs, long err);
29 #undef DEBUG_UNALIGNED_TRAP
31 #ifdef DEBUG_UNALIGNED_TRAP
32 # define DPRINT(a...) do { printk("%s %u: ", __FUNCTION__, __LINE__); printk (a); } while (0)
33 # define DDUMP(str,vp,len) dump(str, vp, len)
35 static void
36 dump (const char *str, void *vp, size_t len)
37 {
38 unsigned char *cp = vp;
39 int i;
41 printk("%s", str);
42 for (i = 0; i < len; ++i)
43 printk (" %02x", *cp++);
44 printk("\n");
45 }
46 #else
47 # define DPRINT(a...)
48 # define DDUMP(str,vp,len)
49 #endif
51 #define IA64_FIRST_STACKED_GR 32
52 #define IA64_FIRST_ROTATING_FR 32
53 #define SIGN_EXT9 0xffffffffffffff00ul
55 /*
56 * For M-unit:
57 *
58 * opcode | m | x6 |
59 * --------|------|---------|
60 * [40-37] | [36] | [35:30] |
61 * --------|------|---------|
62 * 4 | 1 | 6 | = 11 bits
63 * --------------------------
64 * However bits [31:30] are not directly useful to distinguish between
65 * load/store so we can use [35:32] instead, which gives the following
66 * mask ([40:32]) using 9 bits. The 'e' comes from the fact that we defer
67 * checking the m-bit until later in the load/store emulation.
68 */
69 #define IA64_OPCODE_MASK 0x1ef
70 #define IA64_OPCODE_SHIFT 32
72 /*
73 * Table C-28 Integer Load/Store
74 *
75 * We ignore [35:32]= 0x6, 0x7, 0xE, 0xF
76 *
77 * ld8.fill, st8.fill MUST be aligned because the RNATs are based on
78 * the address (bits [8:3]), so we must failed.
79 */
80 #define LD_OP 0x080
81 #define LDS_OP 0x081
82 #define LDA_OP 0x082
83 #define LDSA_OP 0x083
84 #define LDBIAS_OP 0x084
85 #define LDACQ_OP 0x085
86 /* 0x086, 0x087 are not relevant */
87 #define LDCCLR_OP 0x088
88 #define LDCNC_OP 0x089
89 #define LDCCLRACQ_OP 0x08a
90 #define ST_OP 0x08c
91 #define STREL_OP 0x08d
92 /* 0x08e,0x8f are not relevant */
94 /*
95 * Table C-29 Integer Load +Reg
96 *
97 * we use the ld->m (bit [36:36]) field to determine whether or not we have
98 * a load/store of this form.
99 */
101 /*
102 * Table C-30 Integer Load/Store +Imm
103 *
104 * We ignore [35:32]= 0x6, 0x7, 0xE, 0xF
105 *
106 * ld8.fill, st8.fill must be aligned because the Nat register are based on
107 * the address, so we must fail and the program must be fixed.
108 */
109 #define LD_IMM_OP 0x0a0
110 #define LDS_IMM_OP 0x0a1
111 #define LDA_IMM_OP 0x0a2
112 #define LDSA_IMM_OP 0x0a3
113 #define LDBIAS_IMM_OP 0x0a4
114 #define LDACQ_IMM_OP 0x0a5
115 /* 0x0a6, 0xa7 are not relevant */
116 #define LDCCLR_IMM_OP 0x0a8
117 #define LDCNC_IMM_OP 0x0a9
118 #define LDCCLRACQ_IMM_OP 0x0aa
119 #define ST_IMM_OP 0x0ac
120 #define STREL_IMM_OP 0x0ad
121 /* 0x0ae,0xaf are not relevant */
123 /*
124 * Table C-32 Floating-point Load/Store
125 */
126 #define LDF_OP 0x0c0
127 #define LDFS_OP 0x0c1
128 #define LDFA_OP 0x0c2
129 #define LDFSA_OP 0x0c3
130 /* 0x0c6 is irrelevant */
131 #define LDFCCLR_OP 0x0c8
132 #define LDFCNC_OP 0x0c9
133 /* 0x0cb is irrelevant */
134 #define STF_OP 0x0cc
136 /*
137 * Table C-33 Floating-point Load +Reg
138 *
139 * we use the ld->m (bit [36:36]) field to determine whether or not we have
140 * a load/store of this form.
141 */
143 /*
144 * Table C-34 Floating-point Load/Store +Imm
145 */
146 #define LDF_IMM_OP 0x0e0
147 #define LDFS_IMM_OP 0x0e1
148 #define LDFA_IMM_OP 0x0e2
149 #define LDFSA_IMM_OP 0x0e3
150 /* 0x0e6 is irrelevant */
151 #define LDFCCLR_IMM_OP 0x0e8
152 #define LDFCNC_IMM_OP 0x0e9
153 #define STF_IMM_OP 0x0ec
155 typedef struct {
156 unsigned long qp:6; /* [0:5] */
157 unsigned long r1:7; /* [6:12] */
158 unsigned long imm:7; /* [13:19] */
159 unsigned long r3:7; /* [20:26] */
160 unsigned long x:1; /* [27:27] */
161 unsigned long hint:2; /* [28:29] */
162 unsigned long x6_sz:2; /* [30:31] */
163 unsigned long x6_op:4; /* [32:35], x6 = x6_sz|x6_op */
164 unsigned long m:1; /* [36:36] */
165 unsigned long op:4; /* [37:40] */
166 unsigned long pad:23; /* [41:63] */
167 } load_store_t;
170 typedef enum {
171 UPD_IMMEDIATE, /* ldXZ r1=[r3],imm(9) */
172 UPD_REG /* ldXZ r1=[r3],r2 */
173 } update_t;
175 /*
176 * We use tables to keep track of the offsets of registers in the saved state.
177 * This way we save having big switch/case statements.
178 *
179 * We use bit 0 to indicate switch_stack or pt_regs.
180 * The offset is simply shifted by 1 bit.
181 * A 2-byte value should be enough to hold any kind of offset
182 *
183 * In case the calling convention changes (and thus pt_regs/switch_stack)
184 * simply use RSW instead of RPT or vice-versa.
185 */
187 #define RPO(x) ((size_t) &((struct pt_regs *)0)->x)
188 #define RSO(x) ((size_t) &((struct switch_stack *)0)->x)
190 #define RPT(x) (RPO(x) << 1)
191 #define RSW(x) (1| RSO(x)<<1)
193 #define GR_OFFS(x) (gr_info[x]>>1)
194 #define GR_IN_SW(x) (gr_info[x] & 0x1)
196 #define FR_OFFS(x) (fr_info[x]>>1)
197 #define FR_IN_SW(x) (fr_info[x] & 0x1)
199 static u16 gr_info[32]={
200 0, /* r0 is read-only : WE SHOULD NEVER GET THIS */
202 RPT(r1), RPT(r2), RPT(r3),
204 #if defined(XEN)
205 RPT(r4), RPT(r5), RPT(r6), RPT(r7),
206 #else
207 RSW(r4), RSW(r5), RSW(r6), RSW(r7),
208 #endif
210 RPT(r8), RPT(r9), RPT(r10), RPT(r11),
211 RPT(r12), RPT(r13), RPT(r14), RPT(r15),
213 RPT(r16), RPT(r17), RPT(r18), RPT(r19),
214 RPT(r20), RPT(r21), RPT(r22), RPT(r23),
215 RPT(r24), RPT(r25), RPT(r26), RPT(r27),
216 RPT(r28), RPT(r29), RPT(r30), RPT(r31)
217 };
219 #ifndef XEN
220 static u16 fr_info[32]={
221 0, /* constant : WE SHOULD NEVER GET THIS */
222 0, /* constant : WE SHOULD NEVER GET THIS */
224 RSW(f2), RSW(f3), RSW(f4), RSW(f5),
226 RPT(f6), RPT(f7), RPT(f8), RPT(f9),
227 RPT(f10), RPT(f11),
229 RSW(f12), RSW(f13), RSW(f14),
230 RSW(f15), RSW(f16), RSW(f17), RSW(f18), RSW(f19),
231 RSW(f20), RSW(f21), RSW(f22), RSW(f23), RSW(f24),
232 RSW(f25), RSW(f26), RSW(f27), RSW(f28), RSW(f29),
233 RSW(f30), RSW(f31)
234 };
236 /* Invalidate ALAT entry for integer register REGNO. */
237 static void
238 invala_gr (int regno)
239 {
240 # define F(reg) case reg: ia64_invala_gr(reg); break
242 switch (regno) {
243 F( 0); F( 1); F( 2); F( 3); F( 4); F( 5); F( 6); F( 7);
244 F( 8); F( 9); F( 10); F( 11); F( 12); F( 13); F( 14); F( 15);
245 F( 16); F( 17); F( 18); F( 19); F( 20); F( 21); F( 22); F( 23);
246 F( 24); F( 25); F( 26); F( 27); F( 28); F( 29); F( 30); F( 31);
247 F( 32); F( 33); F( 34); F( 35); F( 36); F( 37); F( 38); F( 39);
248 F( 40); F( 41); F( 42); F( 43); F( 44); F( 45); F( 46); F( 47);
249 F( 48); F( 49); F( 50); F( 51); F( 52); F( 53); F( 54); F( 55);
250 F( 56); F( 57); F( 58); F( 59); F( 60); F( 61); F( 62); F( 63);
251 F( 64); F( 65); F( 66); F( 67); F( 68); F( 69); F( 70); F( 71);
252 F( 72); F( 73); F( 74); F( 75); F( 76); F( 77); F( 78); F( 79);
253 F( 80); F( 81); F( 82); F( 83); F( 84); F( 85); F( 86); F( 87);
254 F( 88); F( 89); F( 90); F( 91); F( 92); F( 93); F( 94); F( 95);
255 F( 96); F( 97); F( 98); F( 99); F(100); F(101); F(102); F(103);
256 F(104); F(105); F(106); F(107); F(108); F(109); F(110); F(111);
257 F(112); F(113); F(114); F(115); F(116); F(117); F(118); F(119);
258 F(120); F(121); F(122); F(123); F(124); F(125); F(126); F(127);
259 }
260 # undef F
261 }
263 /* Invalidate ALAT entry for floating-point register REGNO. */
264 static void
265 invala_fr (int regno)
266 {
267 # define F(reg) case reg: ia64_invala_fr(reg); break
269 switch (regno) {
270 F( 0); F( 1); F( 2); F( 3); F( 4); F( 5); F( 6); F( 7);
271 F( 8); F( 9); F( 10); F( 11); F( 12); F( 13); F( 14); F( 15);
272 F( 16); F( 17); F( 18); F( 19); F( 20); F( 21); F( 22); F( 23);
273 F( 24); F( 25); F( 26); F( 27); F( 28); F( 29); F( 30); F( 31);
274 F( 32); F( 33); F( 34); F( 35); F( 36); F( 37); F( 38); F( 39);
275 F( 40); F( 41); F( 42); F( 43); F( 44); F( 45); F( 46); F( 47);
276 F( 48); F( 49); F( 50); F( 51); F( 52); F( 53); F( 54); F( 55);
277 F( 56); F( 57); F( 58); F( 59); F( 60); F( 61); F( 62); F( 63);
278 F( 64); F( 65); F( 66); F( 67); F( 68); F( 69); F( 70); F( 71);
279 F( 72); F( 73); F( 74); F( 75); F( 76); F( 77); F( 78); F( 79);
280 F( 80); F( 81); F( 82); F( 83); F( 84); F( 85); F( 86); F( 87);
281 F( 88); F( 89); F( 90); F( 91); F( 92); F( 93); F( 94); F( 95);
282 F( 96); F( 97); F( 98); F( 99); F(100); F(101); F(102); F(103);
283 F(104); F(105); F(106); F(107); F(108); F(109); F(110); F(111);
284 F(112); F(113); F(114); F(115); F(116); F(117); F(118); F(119);
285 F(120); F(121); F(122); F(123); F(124); F(125); F(126); F(127);
286 }
287 # undef F
288 }
289 #endif /* XEN */
291 static inline unsigned long
292 rotate_reg (unsigned long sor, unsigned long rrb, unsigned long reg)
293 {
294 reg += rrb;
295 if (reg >= sor)
296 reg -= sor;
297 return reg;
298 }
300 #if defined(XEN)
301 void
302 set_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long val, unsigned long nat)
303 {
304 unsigned long *bsp, *bspstore, *addr, *rnat_addr;
305 unsigned long *kbs = (void *) current + IA64_RBS_OFFSET;
306 unsigned long nat_mask;
307 unsigned long old_rsc, new_rsc, psr;
308 unsigned long rnat;
309 long sof = (regs->cr_ifs) & 0x7f;
310 long sor = 8 * ((regs->cr_ifs >> 14) & 0xf);
311 long rrb_gr = (regs->cr_ifs >> 18) & 0x7f;
312 long ridx = r1 - 32;
314 if (ridx >= sof) {
315 /* this should never happen, as the "rsvd register fault" has higher priority */
316 DPRINT("ignoring write to r%lu; only %lu registers are allocated!\n", r1, sof);
317 return;
318 }
320 if (ridx < sor)
321 ridx = rotate_reg(sor, rrb_gr, ridx);
323 old_rsc=ia64_get_rsc();
324 /* put RSC to lazy mode, and set loadrs 0 */
325 new_rsc = old_rsc & (~0x3fff0003);
326 ia64_set_rsc(new_rsc);
327 bsp = kbs + (regs->loadrs >> 19); /* 16 + 3 */
329 addr = ia64_rse_skip_regs(bsp, -sof + ridx);
330 nat_mask = 1UL << ia64_rse_slot_num(addr);
331 rnat_addr = ia64_rse_rnat_addr(addr);
333 local_irq_save(psr);
334 bspstore = (unsigned long*)ia64_get_bspstore();
335 if(addr >= bspstore){
337 ia64_flushrs ();
338 ia64_mf ();
339 *addr = val;
340 bspstore = (unsigned long*)ia64_get_bspstore();
341 rnat = ia64_get_rnat ();
342 if(bspstore < rnat_addr){
343 rnat=rnat&(~nat_mask);
344 }else{
345 *rnat_addr = (*rnat_addr)&(~nat_mask);
346 }
347 ia64_mf();
348 ia64_loadrs();
349 ia64_set_rnat(rnat);
350 }else{
352 rnat = ia64_get_rnat ();
353 *addr = val;
354 if(bspstore < rnat_addr){
355 rnat=rnat&(~nat_mask);
356 }else{
357 *rnat_addr = (*rnat_addr)&(~nat_mask);
358 }
359 ia64_set_bspstore (bspstore);
360 ia64_set_rnat(rnat);
361 }
362 local_irq_restore(psr);
363 ia64_set_rsc(old_rsc);
364 }
367 static void
368 get_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long *val, int*nat)
369 {
370 unsigned long *bsp, *addr, *rnat_addr, *bspstore;
371 unsigned long *kbs = (void *) current + IA64_RBS_OFFSET;
372 unsigned long nat_mask;
373 unsigned long old_rsc, new_rsc;
374 long sof = (regs->cr_ifs) & 0x7f;
375 long sor = 8 * ((regs->cr_ifs >> 14) & 0xf);
376 long rrb_gr = (regs->cr_ifs >> 18) & 0x7f;
377 long ridx = r1 - 32;
379 if (ridx >= sof) {
380 /* read of out-of-frame register returns an undefined value; 0 in our case. */
381 DPRINT("ignoring read from r%lu; only %lu registers are allocated!\n", r1, sof);
382 panic("wrong stack register number (iip=%lx)\n", regs->cr_iip);
383 }
385 if (ridx < sor)
386 ridx = rotate_reg(sor, rrb_gr, ridx);
388 old_rsc=ia64_get_rsc();
389 new_rsc=old_rsc&(~(0x3));
390 ia64_set_rsc(new_rsc);
392 bspstore = (unsigned long*)ia64_get_bspstore();
393 bsp =kbs + (regs->loadrs >> 19); //16+3;
395 addr = ia64_rse_skip_regs(bsp, -sof + ridx);
396 nat_mask = 1UL << ia64_rse_slot_num(addr);
397 rnat_addr = ia64_rse_rnat_addr(addr);
399 if(addr >= bspstore){
401 ia64_flushrs ();
402 ia64_mf ();
403 bspstore = (unsigned long*)ia64_get_bspstore();
404 }
405 *val=*addr;
406 if(nat){
407 if(bspstore < rnat_addr){
408 *nat=(int)!!(ia64_get_rnat()&nat_mask);
409 }else{
410 *nat = (int)!!((*rnat_addr)&nat_mask);
411 }
412 ia64_set_rsc(old_rsc);
413 }
414 }
416 #else
417 static void
418 set_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long val, int nat)
419 {
420 struct switch_stack *sw = (struct switch_stack *) regs - 1;
421 unsigned long *bsp, *bspstore, *addr, *rnat_addr, *ubs_end;
422 unsigned long *kbs = (void *) current + IA64_RBS_OFFSET;
423 unsigned long rnats, nat_mask;
424 unsigned long on_kbs;
425 long sof = (regs->cr_ifs) & 0x7f;
426 long sor = 8 * ((regs->cr_ifs >> 14) & 0xf);
427 long rrb_gr = (regs->cr_ifs >> 18) & 0x7f;
428 long ridx = r1 - 32;
430 if (ridx >= sof) {
431 /* this should never happen, as the "rsvd register fault" has higher priority */
432 DPRINT("ignoring write to r%lu; only %lu registers are allocated!\n", r1, sof);
433 return;
434 }
436 if (ridx < sor)
437 ridx = rotate_reg(sor, rrb_gr, ridx);
439 DPRINT("r%lu, sw.bspstore=%lx pt.bspstore=%lx sof=%ld sol=%ld ridx=%ld\n",
440 r1, sw->ar_bspstore, regs->ar_bspstore, sof, (regs->cr_ifs >> 7) & 0x7f, ridx);
442 on_kbs = ia64_rse_num_regs(kbs, (unsigned long *) sw->ar_bspstore);
443 addr = ia64_rse_skip_regs((unsigned long *) sw->ar_bspstore, -sof + ridx);
444 if (addr >= kbs) {
445 /* the register is on the kernel backing store: easy... */
446 rnat_addr = ia64_rse_rnat_addr(addr);
447 if ((unsigned long) rnat_addr >= sw->ar_bspstore)
448 rnat_addr = &sw->ar_rnat;
449 nat_mask = 1UL << ia64_rse_slot_num(addr);
451 *addr = val;
452 if (nat)
453 *rnat_addr |= nat_mask;
454 else
455 *rnat_addr &= ~nat_mask;
456 return;
457 }
459 if (!user_stack(current, regs)) {
460 DPRINT("ignoring kernel write to r%lu; register isn't on the kernel RBS!", r1);
461 return;
462 }
464 bspstore = (unsigned long *)regs->ar_bspstore;
465 ubs_end = ia64_rse_skip_regs(bspstore, on_kbs);
466 bsp = ia64_rse_skip_regs(ubs_end, -sof);
467 addr = ia64_rse_skip_regs(bsp, ridx);
469 DPRINT("ubs_end=%p bsp=%p addr=%p\n", (void *) ubs_end, (void *) bsp, (void *) addr);
471 ia64_poke(current, sw, (unsigned long) ubs_end, (unsigned long) addr, val);
473 rnat_addr = ia64_rse_rnat_addr(addr);
475 ia64_peek(current, sw, (unsigned long) ubs_end, (unsigned long) rnat_addr, &rnats);
476 DPRINT("rnat @%p = 0x%lx nat=%d old nat=%ld\n",
477 (void *) rnat_addr, rnats, nat, (rnats >> ia64_rse_slot_num(addr)) & 1);
479 nat_mask = 1UL << ia64_rse_slot_num(addr);
480 if (nat)
481 rnats |= nat_mask;
482 else
483 rnats &= ~nat_mask;
484 ia64_poke(current, sw, (unsigned long) ubs_end, (unsigned long) rnat_addr, rnats);
486 DPRINT("rnat changed to @%p = 0x%lx\n", (void *) rnat_addr, rnats);
487 }
490 static void
491 get_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long *val, int *nat)
492 {
493 struct switch_stack *sw = (struct switch_stack *) regs - 1;
494 unsigned long *bsp, *addr, *rnat_addr, *ubs_end, *bspstore;
495 unsigned long *kbs = (void *) current + IA64_RBS_OFFSET;
496 unsigned long rnats, nat_mask;
497 unsigned long on_kbs;
498 long sof = (regs->cr_ifs) & 0x7f;
499 long sor = 8 * ((regs->cr_ifs >> 14) & 0xf);
500 long rrb_gr = (regs->cr_ifs >> 18) & 0x7f;
501 long ridx = r1 - 32;
503 if (ridx >= sof) {
504 /* read of out-of-frame register returns an undefined value; 0 in our case. */
505 DPRINT("ignoring read from r%lu; only %lu registers are allocated!\n", r1, sof);
506 goto fail;
507 }
509 if (ridx < sor)
510 ridx = rotate_reg(sor, rrb_gr, ridx);
512 DPRINT("r%lu, sw.bspstore=%lx pt.bspstore=%lx sof=%ld sol=%ld ridx=%ld\n",
513 r1, sw->ar_bspstore, regs->ar_bspstore, sof, (regs->cr_ifs >> 7) & 0x7f, ridx);
515 on_kbs = ia64_rse_num_regs(kbs, (unsigned long *) sw->ar_bspstore);
516 addr = ia64_rse_skip_regs((unsigned long *) sw->ar_bspstore, -sof + ridx);
517 if (addr >= kbs) {
518 /* the register is on the kernel backing store: easy... */
519 *val = *addr;
520 if (nat) {
521 rnat_addr = ia64_rse_rnat_addr(addr);
522 if ((unsigned long) rnat_addr >= sw->ar_bspstore)
523 rnat_addr = &sw->ar_rnat;
524 nat_mask = 1UL << ia64_rse_slot_num(addr);
525 *nat = (*rnat_addr & nat_mask) != 0;
526 }
527 return;
528 }
530 if (!user_stack(current, regs)) {
531 DPRINT("ignoring kernel read of r%lu; register isn't on the RBS!", r1);
532 goto fail;
533 }
535 bspstore = (unsigned long *)regs->ar_bspstore;
536 ubs_end = ia64_rse_skip_regs(bspstore, on_kbs);
537 bsp = ia64_rse_skip_regs(ubs_end, -sof);
538 addr = ia64_rse_skip_regs(bsp, ridx);
540 DPRINT("ubs_end=%p bsp=%p addr=%p\n", (void *) ubs_end, (void *) bsp, (void *) addr);
542 ia64_peek(current, sw, (unsigned long) ubs_end, (unsigned long) addr, val);
544 if (nat) {
545 rnat_addr = ia64_rse_rnat_addr(addr);
546 nat_mask = 1UL << ia64_rse_slot_num(addr);
548 DPRINT("rnat @%p = 0x%lx\n", (void *) rnat_addr, rnats);
550 ia64_peek(current, sw, (unsigned long) ubs_end, (unsigned long) rnat_addr, &rnats);
551 *nat = (rnats & nat_mask) != 0;
552 }
553 return;
555 fail:
556 *val = 0;
557 if (nat)
558 *nat = 0;
559 return;
560 }
561 #endif
564 #ifdef XEN
565 void
566 #else
567 static void
568 #endif
569 setreg (unsigned long regnum, unsigned long val, int nat, struct pt_regs *regs)
570 {
571 struct switch_stack *sw = (struct switch_stack *) regs - 1;
572 unsigned long addr;
573 unsigned long bitmask;
574 unsigned long *unat;
576 /*
577 * First takes care of stacked registers
578 */
579 if (regnum >= IA64_FIRST_STACKED_GR) {
580 set_rse_reg(regs, regnum, val, nat);
581 return;
582 }
584 /*
585 * Using r0 as a target raises a General Exception fault which has higher priority
586 * than the Unaligned Reference fault.
587 */
589 /*
590 * Now look at registers in [0-31] range and init correct UNAT
591 */
592 if (GR_IN_SW(regnum)) {
593 addr = (unsigned long)sw;
594 unat = &sw->ar_unat;
595 } else {
596 addr = (unsigned long)regs;
597 #if defined(XEN)
598 unat = &regs->eml_unat;
599 #else
600 unat = &sw->caller_unat;
601 #endif
602 }
603 DPRINT("tmp_base=%lx switch_stack=%s offset=%d\n",
604 addr, unat==&sw->ar_unat ? "yes":"no", GR_OFFS(regnum));
605 /*
606 * add offset from base of struct
607 * and do it !
608 */
609 addr += GR_OFFS(regnum);
611 *(unsigned long *)addr = val;
613 /*
614 * We need to clear the corresponding UNAT bit to fully emulate the load
615 * UNAT bit_pos = GR[r3]{8:3} form EAS-2.4
616 */
617 bitmask = 1UL << (addr >> 3 & 0x3f);
618 DPRINT("*0x%lx=0x%lx NaT=%d prev_unat @%p=%lx\n", addr, val, nat, (void *) unat, *unat);
619 if (nat) {
620 *unat |= bitmask;
621 } else {
622 *unat &= ~bitmask;
623 }
624 DPRINT("*0x%lx=0x%lx NaT=%d new unat: %p=%lx\n", addr, val, nat, (void *) unat,*unat);
625 }
627 /*
628 * Return the (rotated) index for floating point register REGNUM (REGNUM must be in the
629 * range from 32-127, result is in the range from 0-95.
630 */
631 static inline unsigned long
632 fph_index (struct pt_regs *regs, long regnum)
633 {
634 unsigned long rrb_fr = (regs->cr_ifs >> 25) & 0x7f;
635 return rotate_reg(96, rrb_fr, (regnum - IA64_FIRST_ROTATING_FR));
636 }
638 #ifndef XEN
639 static void
640 setfpreg (unsigned long regnum, struct ia64_fpreg *fpval, struct pt_regs *regs)
641 {
642 struct switch_stack *sw = (struct switch_stack *)regs - 1;
643 unsigned long addr;
645 /*
646 * From EAS-2.5: FPDisableFault has higher priority than Unaligned
647 * Fault. Thus, when we get here, we know the partition is enabled.
648 * To update f32-f127, there are three choices:
649 *
650 * (1) save f32-f127 to thread.fph and update the values there
651 * (2) use a gigantic switch statement to directly access the registers
652 * (3) generate code on the fly to update the desired register
653 *
654 * For now, we are using approach (1).
655 */
656 if (regnum >= IA64_FIRST_ROTATING_FR) {
657 ia64_sync_fph(current);
658 #ifdef XEN
659 current->arch._thread.fph[fph_index(regs, regnum)] = *fpval;
660 #else
661 current->thread.fph[fph_index(regs, regnum)] = *fpval;
662 #endif
663 } else {
664 /*
665 * pt_regs or switch_stack ?
666 */
667 if (FR_IN_SW(regnum)) {
668 addr = (unsigned long)sw;
669 } else {
670 addr = (unsigned long)regs;
671 }
673 DPRINT("tmp_base=%lx offset=%d\n", addr, FR_OFFS(regnum));
675 addr += FR_OFFS(regnum);
676 *(struct ia64_fpreg *)addr = *fpval;
678 /*
679 * mark the low partition as being used now
680 *
681 * It is highly unlikely that this bit is not already set, but
682 * let's do it for safety.
683 */
684 regs->cr_ipsr |= IA64_PSR_MFL;
685 }
686 }
687 #endif /* XEN */
689 /*
690 * Those 2 inline functions generate the spilled versions of the constant floating point
691 * registers which can be used with stfX
692 */
693 static inline void
694 float_spill_f0 (struct ia64_fpreg *final)
695 {
696 ia64_stf_spill(final, 0);
697 }
699 static inline void
700 float_spill_f1 (struct ia64_fpreg *final)
701 {
702 ia64_stf_spill(final, 1);
703 }
705 #ifndef XEN
706 static void
707 getfpreg (unsigned long regnum, struct ia64_fpreg *fpval, struct pt_regs *regs)
708 {
709 struct switch_stack *sw = (struct switch_stack *) regs - 1;
710 unsigned long addr;
712 /*
713 * From EAS-2.5: FPDisableFault has higher priority than
714 * Unaligned Fault. Thus, when we get here, we know the partition is
715 * enabled.
716 *
717 * When regnum > 31, the register is still live and we need to force a save
718 * to current->thread.fph to get access to it. See discussion in setfpreg()
719 * for reasons and other ways of doing this.
720 */
721 if (regnum >= IA64_FIRST_ROTATING_FR) {
722 ia64_flush_fph(current);
723 #ifdef XEN
724 *fpval = current->arch._thread.fph[fph_index(regs, regnum)];
725 #else
726 *fpval = current->thread.fph[fph_index(regs, regnum)];
727 #endif
728 } else {
729 /*
730 * f0 = 0.0, f1= 1.0. Those registers are constant and are thus
731 * not saved, we must generate their spilled form on the fly
732 */
733 switch(regnum) {
734 case 0:
735 float_spill_f0(fpval);
736 break;
737 case 1:
738 float_spill_f1(fpval);
739 break;
740 default:
741 /*
742 * pt_regs or switch_stack ?
743 */
744 addr = FR_IN_SW(regnum) ? (unsigned long)sw
745 : (unsigned long)regs;
747 DPRINT("is_sw=%d tmp_base=%lx offset=0x%x\n",
748 FR_IN_SW(regnum), addr, FR_OFFS(regnum));
750 addr += FR_OFFS(regnum);
751 *fpval = *(struct ia64_fpreg *)addr;
752 }
753 }
754 }
755 #else
756 void
757 getfpreg (unsigned long regnum, struct ia64_fpreg *fpval, struct pt_regs *regs)
758 {
759 // Take floating register rotation into consideration
760 if(regnum >= IA64_FIRST_ROTATING_FR)
761 regnum = IA64_FIRST_ROTATING_FR + fph_index(regs, regnum);
762 #define CASE_FIXED_FP(reg) \
763 case reg: \
764 ia64_stf_spill(fpval,reg); \
765 break
766 #define CASE_SAVED_FP(reg) \
767 case reg: \
768 fpval->u.bits[0] = regs->f##reg.u.bits[0]; \
769 fpval->u.bits[1] = regs->f##reg.u.bits[1]; \
770 break
771 switch(regnum) {
772 CASE_FIXED_FP(0);
773 CASE_FIXED_FP(1);
774 CASE_FIXED_FP(2);
775 CASE_FIXED_FP(3);
776 CASE_FIXED_FP(4);
777 CASE_FIXED_FP(5);
779 CASE_SAVED_FP(6);
780 CASE_SAVED_FP(7);
781 CASE_SAVED_FP(8);
782 CASE_SAVED_FP(9);
783 CASE_SAVED_FP(10);
784 CASE_SAVED_FP(11);
786 CASE_FIXED_FP(12);
787 CASE_FIXED_FP(13);
788 CASE_FIXED_FP(14);
789 CASE_FIXED_FP(15);
790 CASE_FIXED_FP(16);
791 CASE_FIXED_FP(17);
792 CASE_FIXED_FP(18);
793 CASE_FIXED_FP(19);
794 CASE_FIXED_FP(20);
795 CASE_FIXED_FP(21);
796 CASE_FIXED_FP(22);
797 CASE_FIXED_FP(23);
798 CASE_FIXED_FP(24);
799 CASE_FIXED_FP(25);
800 CASE_FIXED_FP(26);
801 CASE_FIXED_FP(27);
802 CASE_FIXED_FP(28);
803 CASE_FIXED_FP(29);
804 CASE_FIXED_FP(30);
805 CASE_FIXED_FP(31);
806 CASE_FIXED_FP(32);
807 CASE_FIXED_FP(33);
808 CASE_FIXED_FP(34);
809 CASE_FIXED_FP(35);
810 CASE_FIXED_FP(36);
811 CASE_FIXED_FP(37);
812 CASE_FIXED_FP(38);
813 CASE_FIXED_FP(39);
814 CASE_FIXED_FP(40);
815 CASE_FIXED_FP(41);
816 CASE_FIXED_FP(42);
817 CASE_FIXED_FP(43);
818 CASE_FIXED_FP(44);
819 CASE_FIXED_FP(45);
820 CASE_FIXED_FP(46);
821 CASE_FIXED_FP(47);
822 CASE_FIXED_FP(48);
823 CASE_FIXED_FP(49);
824 CASE_FIXED_FP(50);
825 CASE_FIXED_FP(51);
826 CASE_FIXED_FP(52);
827 CASE_FIXED_FP(53);
828 CASE_FIXED_FP(54);
829 CASE_FIXED_FP(55);
830 CASE_FIXED_FP(56);
831 CASE_FIXED_FP(57);
832 CASE_FIXED_FP(58);
833 CASE_FIXED_FP(59);
834 CASE_FIXED_FP(60);
835 CASE_FIXED_FP(61);
836 CASE_FIXED_FP(62);
837 CASE_FIXED_FP(63);
838 CASE_FIXED_FP(64);
839 CASE_FIXED_FP(65);
840 CASE_FIXED_FP(66);
841 CASE_FIXED_FP(67);
842 CASE_FIXED_FP(68);
843 CASE_FIXED_FP(69);
844 CASE_FIXED_FP(70);
845 CASE_FIXED_FP(71);
846 CASE_FIXED_FP(72);
847 CASE_FIXED_FP(73);
848 CASE_FIXED_FP(74);
849 CASE_FIXED_FP(75);
850 CASE_FIXED_FP(76);
851 CASE_FIXED_FP(77);
852 CASE_FIXED_FP(78);
853 CASE_FIXED_FP(79);
854 CASE_FIXED_FP(80);
855 CASE_FIXED_FP(81);
856 CASE_FIXED_FP(82);
857 CASE_FIXED_FP(83);
858 CASE_FIXED_FP(84);
859 CASE_FIXED_FP(85);
860 CASE_FIXED_FP(86);
861 CASE_FIXED_FP(87);
862 CASE_FIXED_FP(88);
863 CASE_FIXED_FP(89);
864 CASE_FIXED_FP(90);
865 CASE_FIXED_FP(91);
866 CASE_FIXED_FP(92);
867 CASE_FIXED_FP(93);
868 CASE_FIXED_FP(94);
869 CASE_FIXED_FP(95);
870 CASE_FIXED_FP(96);
871 CASE_FIXED_FP(97);
872 CASE_FIXED_FP(98);
873 CASE_FIXED_FP(99);
874 CASE_FIXED_FP(100);
875 CASE_FIXED_FP(101);
876 CASE_FIXED_FP(102);
877 CASE_FIXED_FP(103);
878 CASE_FIXED_FP(104);
879 CASE_FIXED_FP(105);
880 CASE_FIXED_FP(106);
881 CASE_FIXED_FP(107);
882 CASE_FIXED_FP(108);
883 CASE_FIXED_FP(109);
884 CASE_FIXED_FP(110);
885 CASE_FIXED_FP(111);
886 CASE_FIXED_FP(112);
887 CASE_FIXED_FP(113);
888 CASE_FIXED_FP(114);
889 CASE_FIXED_FP(115);
890 CASE_FIXED_FP(116);
891 CASE_FIXED_FP(117);
892 CASE_FIXED_FP(118);
893 CASE_FIXED_FP(119);
894 CASE_FIXED_FP(120);
895 CASE_FIXED_FP(121);
896 CASE_FIXED_FP(122);
897 CASE_FIXED_FP(123);
898 CASE_FIXED_FP(124);
899 CASE_FIXED_FP(125);
900 CASE_FIXED_FP(126);
901 CASE_FIXED_FP(127);
902 }
903 #undef CASE_FIXED_FP
904 #undef CASE_SAVED_FP
905 }
908 void
909 setfpreg (unsigned long regnum, struct ia64_fpreg *fpval, struct pt_regs *regs)
910 {
911 // Take floating register rotation into consideration
912 ia64_fph_enable();
913 if(regnum >= IA64_FIRST_ROTATING_FR)
914 regnum = IA64_FIRST_ROTATING_FR + fph_index(regs, regnum);
916 #define CASE_FIXED_FP(reg) \
917 case reg: \
918 ia64_ldf_fill(reg,fpval); \
919 break
920 #define CASE_RESTORED_FP(reg) \
921 case reg: \
922 regs->f##reg.u.bits[0] = fpval->u.bits[0]; \
923 regs->f##reg.u.bits[1] = fpval->u.bits[1] ; \
924 break
925 switch(regnum) {
926 CASE_FIXED_FP(2);
927 CASE_FIXED_FP(3);
928 CASE_FIXED_FP(4);
929 CASE_FIXED_FP(5);
931 CASE_RESTORED_FP(6);
932 CASE_RESTORED_FP(7);
933 CASE_RESTORED_FP(8);
934 CASE_RESTORED_FP(9);
935 CASE_RESTORED_FP(10);
936 CASE_RESTORED_FP(11);
938 CASE_FIXED_FP(12);
939 CASE_FIXED_FP(13);
940 CASE_FIXED_FP(14);
941 CASE_FIXED_FP(15);
942 CASE_FIXED_FP(16);
943 CASE_FIXED_FP(17);
944 CASE_FIXED_FP(18);
945 CASE_FIXED_FP(19);
946 CASE_FIXED_FP(20);
947 CASE_FIXED_FP(21);
948 CASE_FIXED_FP(22);
949 CASE_FIXED_FP(23);
950 CASE_FIXED_FP(24);
951 CASE_FIXED_FP(25);
952 CASE_FIXED_FP(26);
953 CASE_FIXED_FP(27);
954 CASE_FIXED_FP(28);
955 CASE_FIXED_FP(29);
956 CASE_FIXED_FP(30);
957 CASE_FIXED_FP(31);
958 CASE_FIXED_FP(32);
959 CASE_FIXED_FP(33);
960 CASE_FIXED_FP(34);
961 CASE_FIXED_FP(35);
962 CASE_FIXED_FP(36);
963 CASE_FIXED_FP(37);
964 CASE_FIXED_FP(38);
965 CASE_FIXED_FP(39);
966 CASE_FIXED_FP(40);
967 CASE_FIXED_FP(41);
968 CASE_FIXED_FP(42);
969 CASE_FIXED_FP(43);
970 CASE_FIXED_FP(44);
971 CASE_FIXED_FP(45);
972 CASE_FIXED_FP(46);
973 CASE_FIXED_FP(47);
974 CASE_FIXED_FP(48);
975 CASE_FIXED_FP(49);
976 CASE_FIXED_FP(50);
977 CASE_FIXED_FP(51);
978 CASE_FIXED_FP(52);
979 CASE_FIXED_FP(53);
980 CASE_FIXED_FP(54);
981 CASE_FIXED_FP(55);
982 CASE_FIXED_FP(56);
983 CASE_FIXED_FP(57);
984 CASE_FIXED_FP(58);
985 CASE_FIXED_FP(59);
986 CASE_FIXED_FP(60);
987 CASE_FIXED_FP(61);
988 CASE_FIXED_FP(62);
989 CASE_FIXED_FP(63);
990 CASE_FIXED_FP(64);
991 CASE_FIXED_FP(65);
992 CASE_FIXED_FP(66);
993 CASE_FIXED_FP(67);
994 CASE_FIXED_FP(68);
995 CASE_FIXED_FP(69);
996 CASE_FIXED_FP(70);
997 CASE_FIXED_FP(71);
998 CASE_FIXED_FP(72);
999 CASE_FIXED_FP(73);
1000 CASE_FIXED_FP(74);
1001 CASE_FIXED_FP(75);
1002 CASE_FIXED_FP(76);
1003 CASE_FIXED_FP(77);
1004 CASE_FIXED_FP(78);
1005 CASE_FIXED_FP(79);
1006 CASE_FIXED_FP(80);
1007 CASE_FIXED_FP(81);
1008 CASE_FIXED_FP(82);
1009 CASE_FIXED_FP(83);
1010 CASE_FIXED_FP(84);
1011 CASE_FIXED_FP(85);
1012 CASE_FIXED_FP(86);
1013 CASE_FIXED_FP(87);
1014 CASE_FIXED_FP(88);
1015 CASE_FIXED_FP(89);
1016 CASE_FIXED_FP(90);
1017 CASE_FIXED_FP(91);
1018 CASE_FIXED_FP(92);
1019 CASE_FIXED_FP(93);
1020 CASE_FIXED_FP(94);
1021 CASE_FIXED_FP(95);
1022 CASE_FIXED_FP(96);
1023 CASE_FIXED_FP(97);
1024 CASE_FIXED_FP(98);
1025 CASE_FIXED_FP(99);
1026 CASE_FIXED_FP(100);
1027 CASE_FIXED_FP(101);
1028 CASE_FIXED_FP(102);
1029 CASE_FIXED_FP(103);
1030 CASE_FIXED_FP(104);
1031 CASE_FIXED_FP(105);
1032 CASE_FIXED_FP(106);
1033 CASE_FIXED_FP(107);
1034 CASE_FIXED_FP(108);
1035 CASE_FIXED_FP(109);
1036 CASE_FIXED_FP(110);
1037 CASE_FIXED_FP(111);
1038 CASE_FIXED_FP(112);
1039 CASE_FIXED_FP(113);
1040 CASE_FIXED_FP(114);
1041 CASE_FIXED_FP(115);
1042 CASE_FIXED_FP(116);
1043 CASE_FIXED_FP(117);
1044 CASE_FIXED_FP(118);
1045 CASE_FIXED_FP(119);
1046 CASE_FIXED_FP(120);
1047 CASE_FIXED_FP(121);
1048 CASE_FIXED_FP(122);
1049 CASE_FIXED_FP(123);
1050 CASE_FIXED_FP(124);
1051 CASE_FIXED_FP(125);
1052 CASE_FIXED_FP(126);
1053 CASE_FIXED_FP(127);
1055 #undef CASE_FIXED_FP
1056 #undef CASE_RESTORED_FP
1059 #endif /* XEN */
1062 #ifdef XEN
1063 void
1064 #else
1065 static void
1066 #endif
1067 getreg (unsigned long regnum, unsigned long *val, int *nat, struct pt_regs *regs)
1069 struct switch_stack *sw = (struct switch_stack *) regs - 1;
1070 unsigned long addr, *unat;
1072 if (regnum >= IA64_FIRST_STACKED_GR) {
1073 get_rse_reg(regs, regnum, val, nat);
1074 return;
1077 /*
1078 * take care of r0 (read-only always evaluate to 0)
1079 */
1080 if (regnum == 0) {
1081 *val = 0;
1082 if (nat)
1083 *nat = 0;
1084 return;
1087 /*
1088 * Now look at registers in [0-31] range and init correct UNAT
1089 */
1090 if (GR_IN_SW(regnum)) {
1091 addr = (unsigned long)sw;
1092 unat = &sw->ar_unat;
1093 } else {
1094 addr = (unsigned long)regs;
1095 #if defined(XEN)
1096 unat = &regs->eml_unat;;
1097 #else
1098 unat = &sw->caller_unat;
1099 #endif
1102 DPRINT("addr_base=%lx offset=0x%x\n", addr, GR_OFFS(regnum));
1104 addr += GR_OFFS(regnum);
1106 *val = *(unsigned long *)addr;
1108 /*
1109 * do it only when requested
1110 */
1111 if (nat)
1112 *nat = (*unat >> (addr >> 3 & 0x3f)) & 0x1UL;
1115 #ifndef XEN
1116 static void
1117 emulate_load_updates (update_t type, load_store_t ld, struct pt_regs *regs, unsigned long ifa)
1119 /*
1120 * IMPORTANT:
1121 * Given the way we handle unaligned speculative loads, we should
1122 * not get to this point in the code but we keep this sanity check,
1123 * just in case.
1124 */
1125 if (ld.x6_op == 1 || ld.x6_op == 3) {
1126 printk(KERN_ERR "%s: register update on speculative load, error\n", __FUNCTION__);
1127 die_if_kernel("unaligned reference on speculative load with register update\n",
1128 regs, 30);
1132 /*
1133 * at this point, we know that the base register to update is valid i.e.,
1134 * it's not r0
1135 */
1136 if (type == UPD_IMMEDIATE) {
1137 unsigned long imm;
1139 /*
1140 * Load +Imm: ldXZ r1=[r3],imm(9)
1143 * form imm9: [13:19] contain the first 7 bits
1144 */
1145 imm = ld.x << 7 | ld.imm;
1147 /*
1148 * sign extend (1+8bits) if m set
1149 */
1150 if (ld.m) imm |= SIGN_EXT9;
1152 /*
1153 * ifa == r3 and we know that the NaT bit on r3 was clear so
1154 * we can directly use ifa.
1155 */
1156 ifa += imm;
1158 setreg(ld.r3, ifa, 0, regs);
1160 DPRINT("ld.x=%d ld.m=%d imm=%ld r3=0x%lx\n", ld.x, ld.m, imm, ifa);
1162 } else if (ld.m) {
1163 unsigned long r2;
1164 int nat_r2;
1166 /*
1167 * Load +Reg Opcode: ldXZ r1=[r3],r2
1169 * Note: that we update r3 even in the case of ldfX.a
1170 * (where the load does not happen)
1172 * The way the load algorithm works, we know that r3 does not
1173 * have its NaT bit set (would have gotten NaT consumption
1174 * before getting the unaligned fault). So we can use ifa
1175 * which equals r3 at this point.
1177 * IMPORTANT:
1178 * The above statement holds ONLY because we know that we
1179 * never reach this code when trying to do a ldX.s.
1180 * If we ever make it to here on an ldfX.s then
1181 */
1182 getreg(ld.imm, &r2, &nat_r2, regs);
1184 ifa += r2;
1186 /*
1187 * propagate Nat r2 -> r3
1188 */
1189 setreg(ld.r3, ifa, nat_r2, regs);
1191 DPRINT("imm=%d r2=%ld r3=0x%lx nat_r2=%d\n",ld.imm, r2, ifa, nat_r2);
1196 static int
1197 emulate_load_int (unsigned long ifa, load_store_t ld, struct pt_regs *regs)
1199 unsigned int len = 1 << ld.x6_sz;
1200 unsigned long val = 0;
1202 /*
1203 * r0, as target, doesn't need to be checked because Illegal Instruction
1204 * faults have higher priority than unaligned faults.
1206 * r0 cannot be found as the base as it would never generate an
1207 * unaligned reference.
1208 */
1210 /*
1211 * ldX.a we will emulate load and also invalidate the ALAT entry.
1212 * See comment below for explanation on how we handle ldX.a
1213 */
1215 if (len != 2 && len != 4 && len != 8) {
1216 DPRINT("unknown size: x6=%d\n", ld.x6_sz);
1217 return -1;
1219 /* this assumes little-endian byte-order: */
1220 if (copy_from_user(&val, (void __user *) ifa, len))
1221 return -1;
1222 setreg(ld.r1, val, 0, regs);
1224 /*
1225 * check for updates on any kind of loads
1226 */
1227 if (ld.op == 0x5 || ld.m)
1228 emulate_load_updates(ld.op == 0x5 ? UPD_IMMEDIATE: UPD_REG, ld, regs, ifa);
1230 /*
1231 * handling of various loads (based on EAS2.4):
1233 * ldX.acq (ordered load):
1234 * - acquire semantics would have been used, so force fence instead.
1236 * ldX.c.clr (check load and clear):
1237 * - if we get to this handler, it's because the entry was not in the ALAT.
1238 * Therefore the operation reverts to a normal load
1240 * ldX.c.nc (check load no clear):
1241 * - same as previous one
1243 * ldX.c.clr.acq (ordered check load and clear):
1244 * - same as above for c.clr part. The load needs to have acquire semantics. So
1245 * we use the fence semantics which is stronger and thus ensures correctness.
1247 * ldX.a (advanced load):
1248 * - suppose ldX.a r1=[r3]. If we get to the unaligned trap it's because the
1249 * address doesn't match requested size alignment. This means that we would
1250 * possibly need more than one load to get the result.
1252 * The load part can be handled just like a normal load, however the difficult
1253 * part is to get the right thing into the ALAT. The critical piece of information
1254 * in the base address of the load & size. To do that, a ld.a must be executed,
1255 * clearly any address can be pushed into the table by using ld1.a r1=[r3]. Now
1256 * if we use the same target register, we will be okay for the check.a instruction.
1257 * If we look at the store, basically a stX [r3]=r1 checks the ALAT for any entry
1258 * which would overlap within [r3,r3+X] (the size of the load was store in the
1259 * ALAT). If such an entry is found the entry is invalidated. But this is not good
1260 * enough, take the following example:
1261 * r3=3
1262 * ld4.a r1=[r3]
1264 * Could be emulated by doing:
1265 * ld1.a r1=[r3],1
1266 * store to temporary;
1267 * ld1.a r1=[r3],1
1268 * store & shift to temporary;
1269 * ld1.a r1=[r3],1
1270 * store & shift to temporary;
1271 * ld1.a r1=[r3]
1272 * store & shift to temporary;
1273 * r1=temporary
1275 * So in this case, you would get the right value is r1 but the wrong info in
1276 * the ALAT. Notice that you could do it in reverse to finish with address 3
1277 * but you would still get the size wrong. To get the size right, one needs to
1278 * execute exactly the same kind of load. You could do it from a aligned
1279 * temporary location, but you would get the address wrong.
1281 * So no matter what, it is not possible to emulate an advanced load
1282 * correctly. But is that really critical ?
1284 * We will always convert ld.a into a normal load with ALAT invalidated. This
1285 * will enable compiler to do optimization where certain code path after ld.a
1286 * is not required to have ld.c/chk.a, e.g., code path with no intervening stores.
1288 * If there is a store after the advanced load, one must either do a ld.c.* or
1289 * chk.a.* to reuse the value stored in the ALAT. Both can "fail" (meaning no
1290 * entry found in ALAT), and that's perfectly ok because:
1292 * - ld.c.*, if the entry is not present a normal load is executed
1293 * - chk.a.*, if the entry is not present, execution jumps to recovery code
1295 * In either case, the load can be potentially retried in another form.
1297 * ALAT must be invalidated for the register (so that chk.a or ld.c don't pick
1298 * up a stale entry later). The register base update MUST also be performed.
1299 */
1301 /*
1302 * when the load has the .acq completer then
1303 * use ordering fence.
1304 */
1305 if (ld.x6_op == 0x5 || ld.x6_op == 0xa)
1306 mb();
1308 /*
1309 * invalidate ALAT entry in case of advanced load
1310 */
1311 if (ld.x6_op == 0x2)
1312 invala_gr(ld.r1);
1314 return 0;
1317 static int
1318 emulate_store_int (unsigned long ifa, load_store_t ld, struct pt_regs *regs)
1320 unsigned long r2;
1321 unsigned int len = 1 << ld.x6_sz;
1323 /*
1324 * if we get to this handler, Nat bits on both r3 and r2 have already
1325 * been checked. so we don't need to do it
1327 * extract the value to be stored
1328 */
1329 getreg(ld.imm, &r2, NULL, regs);
1331 /*
1332 * we rely on the macros in unaligned.h for now i.e.,
1333 * we let the compiler figure out how to read memory gracefully.
1335 * We need this switch/case because the way the inline function
1336 * works. The code is optimized by the compiler and looks like
1337 * a single switch/case.
1338 */
1339 DPRINT("st%d [%lx]=%lx\n", len, ifa, r2);
1341 if (len != 2 && len != 4 && len != 8) {
1342 DPRINT("unknown size: x6=%d\n", ld.x6_sz);
1343 return -1;
1346 /* this assumes little-endian byte-order: */
1347 if (copy_to_user((void __user *) ifa, &r2, len))
1348 return -1;
1350 /*
1351 * stX [r3]=r2,imm(9)
1353 * NOTE:
1354 * ld.r3 can never be r0, because r0 would not generate an
1355 * unaligned access.
1356 */
1357 if (ld.op == 0x5) {
1358 unsigned long imm;
1360 /*
1361 * form imm9: [12:6] contain first 7bits
1362 */
1363 imm = ld.x << 7 | ld.r1;
1364 /*
1365 * sign extend (8bits) if m set
1366 */
1367 if (ld.m) imm |= SIGN_EXT9;
1368 /*
1369 * ifa == r3 (NaT is necessarily cleared)
1370 */
1371 ifa += imm;
1373 DPRINT("imm=%lx r3=%lx\n", imm, ifa);
1375 setreg(ld.r3, ifa, 0, regs);
1377 /*
1378 * we don't have alat_invalidate_multiple() so we need
1379 * to do the complete flush :-<<
1380 */
1381 ia64_invala();
1383 /*
1384 * stX.rel: use fence instead of release
1385 */
1386 if (ld.x6_op == 0xd)
1387 mb();
1389 return 0;
1391 #endif /* XEN */
1393 /*
1394 * floating point operations sizes in bytes
1395 */
1396 static const unsigned char float_fsz[4]={
1397 10, /* extended precision (e) */
1398 8, /* integer (8) */
1399 4, /* single precision (s) */
1400 8 /* double precision (d) */
1401 };
1403 static inline void
1404 mem2float_extended (struct ia64_fpreg *init, struct ia64_fpreg *final)
1406 ia64_ldfe(6, init);
1407 ia64_stop();
1408 ia64_stf_spill(final, 6);
1411 static inline void
1412 mem2float_integer (struct ia64_fpreg *init, struct ia64_fpreg *final)
1414 ia64_ldf8(6, init);
1415 ia64_stop();
1416 ia64_stf_spill(final, 6);
1419 static inline void
1420 mem2float_single (struct ia64_fpreg *init, struct ia64_fpreg *final)
1422 ia64_ldfs(6, init);
1423 ia64_stop();
1424 ia64_stf_spill(final, 6);
1427 static inline void
1428 mem2float_double (struct ia64_fpreg *init, struct ia64_fpreg *final)
1430 ia64_ldfd(6, init);
1431 ia64_stop();
1432 ia64_stf_spill(final, 6);
1435 static inline void
1436 float2mem_extended (struct ia64_fpreg *init, struct ia64_fpreg *final)
1438 ia64_ldf_fill(6, init);
1439 ia64_stop();
1440 ia64_stfe(final, 6);
1443 static inline void
1444 float2mem_integer (struct ia64_fpreg *init, struct ia64_fpreg *final)
1446 ia64_ldf_fill(6, init);
1447 ia64_stop();
1448 ia64_stf8(final, 6);
1451 static inline void
1452 float2mem_single (struct ia64_fpreg *init, struct ia64_fpreg *final)
1454 ia64_ldf_fill(6, init);
1455 ia64_stop();
1456 ia64_stfs(final, 6);
1459 static inline void
1460 float2mem_double (struct ia64_fpreg *init, struct ia64_fpreg *final)
1462 ia64_ldf_fill(6, init);
1463 ia64_stop();
1464 ia64_stfd(final, 6);
1467 #ifndef XEN
1468 static int
1469 emulate_load_floatpair (unsigned long ifa, load_store_t ld, struct pt_regs *regs)
1471 struct ia64_fpreg fpr_init[2];
1472 struct ia64_fpreg fpr_final[2];
1473 unsigned long len = float_fsz[ld.x6_sz];
1475 /*
1476 * fr0 & fr1 don't need to be checked because Illegal Instruction faults have
1477 * higher priority than unaligned faults.
1479 * r0 cannot be found as the base as it would never generate an unaligned
1480 * reference.
1481 */
1483 /*
1484 * make sure we get clean buffers
1485 */
1486 memset(&fpr_init, 0, sizeof(fpr_init));
1487 memset(&fpr_final, 0, sizeof(fpr_final));
1489 /*
1490 * ldfpX.a: we don't try to emulate anything but we must
1491 * invalidate the ALAT entry and execute updates, if any.
1492 */
1493 if (ld.x6_op != 0x2) {
1494 /*
1495 * This assumes little-endian byte-order. Note that there is no "ldfpe"
1496 * instruction:
1497 */
1498 if (copy_from_user(&fpr_init[0], (void __user *) ifa, len)
1499 || copy_from_user(&fpr_init[1], (void __user *) (ifa + len), len))
1500 return -1;
1502 DPRINT("ld.r1=%d ld.imm=%d x6_sz=%d\n", ld.r1, ld.imm, ld.x6_sz);
1503 DDUMP("frp_init =", &fpr_init, 2*len);
1504 /*
1505 * XXX fixme
1506 * Could optimize inlines by using ldfpX & 2 spills
1507 */
1508 switch( ld.x6_sz ) {
1509 case 0:
1510 mem2float_extended(&fpr_init[0], &fpr_final[0]);
1511 mem2float_extended(&fpr_init[1], &fpr_final[1]);
1512 break;
1513 case 1:
1514 mem2float_integer(&fpr_init[0], &fpr_final[0]);
1515 mem2float_integer(&fpr_init[1], &fpr_final[1]);
1516 break;
1517 case 2:
1518 mem2float_single(&fpr_init[0], &fpr_final[0]);
1519 mem2float_single(&fpr_init[1], &fpr_final[1]);
1520 break;
1521 case 3:
1522 mem2float_double(&fpr_init[0], &fpr_final[0]);
1523 mem2float_double(&fpr_init[1], &fpr_final[1]);
1524 break;
1526 DDUMP("fpr_final =", &fpr_final, 2*len);
1527 /*
1528 * XXX fixme
1530 * A possible optimization would be to drop fpr_final and directly
1531 * use the storage from the saved context i.e., the actual final
1532 * destination (pt_regs, switch_stack or thread structure).
1533 */
1534 setfpreg(ld.r1, &fpr_final[0], regs);
1535 setfpreg(ld.imm, &fpr_final[1], regs);
1538 /*
1539 * Check for updates: only immediate updates are available for this
1540 * instruction.
1541 */
1542 if (ld.m) {
1543 /*
1544 * the immediate is implicit given the ldsz of the operation:
1545 * single: 8 (2x4) and for all others it's 16 (2x8)
1546 */
1547 ifa += len<<1;
1549 /*
1550 * IMPORTANT:
1551 * the fact that we force the NaT of r3 to zero is ONLY valid
1552 * as long as we don't come here with a ldfpX.s.
1553 * For this reason we keep this sanity check
1554 */
1555 if (ld.x6_op == 1 || ld.x6_op == 3)
1556 printk(KERN_ERR "%s: register update on speculative load pair, error\n",
1557 __FUNCTION__);
1559 setreg(ld.r3, ifa, 0, regs);
1562 /*
1563 * Invalidate ALAT entries, if any, for both registers.
1564 */
1565 if (ld.x6_op == 0x2) {
1566 invala_fr(ld.r1);
1567 invala_fr(ld.imm);
1569 return 0;
1573 static int
1574 emulate_load_float (unsigned long ifa, load_store_t ld, struct pt_regs *regs)
1576 struct ia64_fpreg fpr_init;
1577 struct ia64_fpreg fpr_final;
1578 unsigned long len = float_fsz[ld.x6_sz];
1580 /*
1581 * fr0 & fr1 don't need to be checked because Illegal Instruction
1582 * faults have higher priority than unaligned faults.
1584 * r0 cannot be found as the base as it would never generate an
1585 * unaligned reference.
1586 */
1588 /*
1589 * make sure we get clean buffers
1590 */
1591 memset(&fpr_init,0, sizeof(fpr_init));
1592 memset(&fpr_final,0, sizeof(fpr_final));
1594 /*
1595 * ldfX.a we don't try to emulate anything but we must
1596 * invalidate the ALAT entry.
1597 * See comments in ldX for descriptions on how the various loads are handled.
1598 */
1599 if (ld.x6_op != 0x2) {
1600 if (copy_from_user(&fpr_init, (void __user *) ifa, len))
1601 return -1;
1603 DPRINT("ld.r1=%d x6_sz=%d\n", ld.r1, ld.x6_sz);
1604 DDUMP("fpr_init =", &fpr_init, len);
1605 /*
1606 * we only do something for x6_op={0,8,9}
1607 */
1608 switch( ld.x6_sz ) {
1609 case 0:
1610 mem2float_extended(&fpr_init, &fpr_final);
1611 break;
1612 case 1:
1613 mem2float_integer(&fpr_init, &fpr_final);
1614 break;
1615 case 2:
1616 mem2float_single(&fpr_init, &fpr_final);
1617 break;
1618 case 3:
1619 mem2float_double(&fpr_init, &fpr_final);
1620 break;
1622 DDUMP("fpr_final =", &fpr_final, len);
1623 /*
1624 * XXX fixme
1626 * A possible optimization would be to drop fpr_final and directly
1627 * use the storage from the saved context i.e., the actual final
1628 * destination (pt_regs, switch_stack or thread structure).
1629 */
1630 setfpreg(ld.r1, &fpr_final, regs);
1633 /*
1634 * check for updates on any loads
1635 */
1636 if (ld.op == 0x7 || ld.m)
1637 emulate_load_updates(ld.op == 0x7 ? UPD_IMMEDIATE: UPD_REG, ld, regs, ifa);
1639 /*
1640 * invalidate ALAT entry in case of advanced floating point loads
1641 */
1642 if (ld.x6_op == 0x2)
1643 invala_fr(ld.r1);
1645 return 0;
1649 static int
1650 emulate_store_float (unsigned long ifa, load_store_t ld, struct pt_regs *regs)
1652 struct ia64_fpreg fpr_init;
1653 struct ia64_fpreg fpr_final;
1654 unsigned long len = float_fsz[ld.x6_sz];
1656 /*
1657 * make sure we get clean buffers
1658 */
1659 memset(&fpr_init,0, sizeof(fpr_init));
1660 memset(&fpr_final,0, sizeof(fpr_final));
1662 /*
1663 * if we get to this handler, Nat bits on both r3 and r2 have already
1664 * been checked. so we don't need to do it
1666 * extract the value to be stored
1667 */
1668 getfpreg(ld.imm, &fpr_init, regs);
1669 /*
1670 * during this step, we extract the spilled registers from the saved
1671 * context i.e., we refill. Then we store (no spill) to temporary
1672 * aligned location
1673 */
1674 switch( ld.x6_sz ) {
1675 case 0:
1676 float2mem_extended(&fpr_init, &fpr_final);
1677 break;
1678 case 1:
1679 float2mem_integer(&fpr_init, &fpr_final);
1680 break;
1681 case 2:
1682 float2mem_single(&fpr_init, &fpr_final);
1683 break;
1684 case 3:
1685 float2mem_double(&fpr_init, &fpr_final);
1686 break;
1688 DPRINT("ld.r1=%d x6_sz=%d\n", ld.r1, ld.x6_sz);
1689 DDUMP("fpr_init =", &fpr_init, len);
1690 DDUMP("fpr_final =", &fpr_final, len);
1692 if (copy_to_user((void __user *) ifa, &fpr_final, len))
1693 return -1;
1695 /*
1696 * stfX [r3]=r2,imm(9)
1698 * NOTE:
1699 * ld.r3 can never be r0, because r0 would not generate an
1700 * unaligned access.
1701 */
1702 if (ld.op == 0x7) {
1703 unsigned long imm;
1705 /*
1706 * form imm9: [12:6] contain first 7bits
1707 */
1708 imm = ld.x << 7 | ld.r1;
1709 /*
1710 * sign extend (8bits) if m set
1711 */
1712 if (ld.m)
1713 imm |= SIGN_EXT9;
1714 /*
1715 * ifa == r3 (NaT is necessarily cleared)
1716 */
1717 ifa += imm;
1719 DPRINT("imm=%lx r3=%lx\n", imm, ifa);
1721 setreg(ld.r3, ifa, 0, regs);
1723 /*
1724 * we don't have alat_invalidate_multiple() so we need
1725 * to do the complete flush :-<<
1726 */
1727 ia64_invala();
1729 return 0;
1732 /*
1733 * Make sure we log the unaligned access, so that user/sysadmin can notice it and
1734 * eventually fix the program. However, we don't want to do that for every access so we
1735 * pace it with jiffies. This isn't really MP-safe, but it doesn't really have to be
1736 * either...
1737 */
1738 static int
1739 within_logging_rate_limit (void)
1741 static unsigned long count, last_time;
1743 if (jiffies - last_time > 5*HZ)
1744 count = 0;
1745 if (++count < 5) {
1746 last_time = jiffies;
1747 return 1;
1749 return 0;
1752 #endif /* XEN */
1754 void
1755 ia64_handle_unaligned (unsigned long ifa, struct pt_regs *regs)
1757 #ifdef XEN
1758 printk("ia64_handle_unaligned: called, not working yet\n");
1759 #else
1760 struct ia64_psr *ipsr = ia64_psr(regs);
1761 mm_segment_t old_fs = get_fs();
1762 unsigned long bundle[2];
1763 unsigned long opcode;
1764 struct siginfo si;
1765 const struct exception_table_entry *eh = NULL;
1766 union {
1767 unsigned long l;
1768 load_store_t insn;
1769 } u;
1770 int ret = -1;
1772 if (ia64_psr(regs)->be) {
1773 /* we don't support big-endian accesses */
1774 die_if_kernel("big-endian unaligned accesses are not supported", regs, 0);
1775 goto force_sigbus;
1778 /*
1779 * Treat kernel accesses for which there is an exception handler entry the same as
1780 * user-level unaligned accesses. Otherwise, a clever program could trick this
1781 * handler into reading an arbitrary kernel addresses...
1782 */
1783 if (!user_mode(regs))
1784 eh = search_exception_tables(regs->cr_iip + ia64_psr(regs)->ri);
1785 if (user_mode(regs) || eh) {
1786 if ((current->thread.flags & IA64_THREAD_UAC_SIGBUS) != 0)
1787 goto force_sigbus;
1789 if (!(current->thread.flags & IA64_THREAD_UAC_NOPRINT)
1790 && within_logging_rate_limit())
1792 char buf[200]; /* comm[] is at most 16 bytes... */
1793 size_t len;
1795 len = sprintf(buf, "%s(%d): unaligned access to 0x%016lx, "
1796 "ip=0x%016lx\n\r", current->comm, current->pid,
1797 ifa, regs->cr_iip + ipsr->ri);
1798 /*
1799 * Don't call tty_write_message() if we're in the kernel; we might
1800 * be holding locks...
1801 */
1802 if (user_mode(regs))
1803 tty_write_message(current->signal->tty, buf);
1804 buf[len-1] = '\0'; /* drop '\r' */
1805 printk(KERN_WARNING "%s", buf); /* watch for command names containing %s */
1807 } else {
1808 if (within_logging_rate_limit())
1809 printk(KERN_WARNING "kernel unaligned access to 0x%016lx, ip=0x%016lx\n",
1810 ifa, regs->cr_iip + ipsr->ri);
1811 set_fs(KERNEL_DS);
1814 DPRINT("iip=%lx ifa=%lx isr=%lx (ei=%d, sp=%d)\n",
1815 regs->cr_iip, ifa, regs->cr_ipsr, ipsr->ri, ipsr->it);
1817 if (__copy_from_user(bundle, (void __user *) regs->cr_iip, 16))
1818 goto failure;
1820 /*
1821 * extract the instruction from the bundle given the slot number
1822 */
1823 switch (ipsr->ri) {
1824 case 0: u.l = (bundle[0] >> 5); break;
1825 case 1: u.l = (bundle[0] >> 46) | (bundle[1] << 18); break;
1826 case 2: u.l = (bundle[1] >> 23); break;
1828 opcode = (u.l >> IA64_OPCODE_SHIFT) & IA64_OPCODE_MASK;
1830 DPRINT("opcode=%lx ld.qp=%d ld.r1=%d ld.imm=%d ld.r3=%d ld.x=%d ld.hint=%d "
1831 "ld.x6=0x%x ld.m=%d ld.op=%d\n", opcode, u.insn.qp, u.insn.r1, u.insn.imm,
1832 u.insn.r3, u.insn.x, u.insn.hint, u.insn.x6_sz, u.insn.m, u.insn.op);
1834 /*
1835 * IMPORTANT:
1836 * Notice that the switch statement DOES not cover all possible instructions
1837 * that DO generate unaligned references. This is made on purpose because for some
1838 * instructions it DOES NOT make sense to try and emulate the access. Sometimes it
1839 * is WRONG to try and emulate. Here is a list of instruction we don't emulate i.e.,
1840 * the program will get a signal and die:
1842 * load/store:
1843 * - ldX.spill
1844 * - stX.spill
1845 * Reason: RNATs are based on addresses
1846 * - ld16
1847 * - st16
1848 * Reason: ld16 and st16 are supposed to occur in a single
1849 * memory op
1851 * synchronization:
1852 * - cmpxchg
1853 * - fetchadd
1854 * - xchg
1855 * Reason: ATOMIC operations cannot be emulated properly using multiple
1856 * instructions.
1858 * speculative loads:
1859 * - ldX.sZ
1860 * Reason: side effects, code must be ready to deal with failure so simpler
1861 * to let the load fail.
1862 * ---------------------------------------------------------------------------------
1863 * XXX fixme
1865 * I would like to get rid of this switch case and do something
1866 * more elegant.
1867 */
1868 switch (opcode) {
1869 case LDS_OP:
1870 case LDSA_OP:
1871 if (u.insn.x)
1872 /* oops, really a semaphore op (cmpxchg, etc) */
1873 goto failure;
1874 /* no break */
1875 case LDS_IMM_OP:
1876 case LDSA_IMM_OP:
1877 case LDFS_OP:
1878 case LDFSA_OP:
1879 case LDFS_IMM_OP:
1880 /*
1881 * The instruction will be retried with deferred exceptions turned on, and
1882 * we should get Nat bit installed
1884 * IMPORTANT: When PSR_ED is set, the register & immediate update forms
1885 * are actually executed even though the operation failed. So we don't
1886 * need to take care of this.
1887 */
1888 DPRINT("forcing PSR_ED\n");
1889 regs->cr_ipsr |= IA64_PSR_ED;
1890 goto done;
1892 case LD_OP:
1893 case LDA_OP:
1894 case LDBIAS_OP:
1895 case LDACQ_OP:
1896 case LDCCLR_OP:
1897 case LDCNC_OP:
1898 case LDCCLRACQ_OP:
1899 if (u.insn.x)
1900 /* oops, really a semaphore op (cmpxchg, etc) */
1901 goto failure;
1902 /* no break */
1903 case LD_IMM_OP:
1904 case LDA_IMM_OP:
1905 case LDBIAS_IMM_OP:
1906 case LDACQ_IMM_OP:
1907 case LDCCLR_IMM_OP:
1908 case LDCNC_IMM_OP:
1909 case LDCCLRACQ_IMM_OP:
1910 ret = emulate_load_int(ifa, u.insn, regs);
1911 break;
1913 case ST_OP:
1914 case STREL_OP:
1915 if (u.insn.x)
1916 /* oops, really a semaphore op (cmpxchg, etc) */
1917 goto failure;
1918 /* no break */
1919 case ST_IMM_OP:
1920 case STREL_IMM_OP:
1921 ret = emulate_store_int(ifa, u.insn, regs);
1922 break;
1924 case LDF_OP:
1925 case LDFA_OP:
1926 case LDFCCLR_OP:
1927 case LDFCNC_OP:
1928 case LDF_IMM_OP:
1929 case LDFA_IMM_OP:
1930 case LDFCCLR_IMM_OP:
1931 case LDFCNC_IMM_OP:
1932 if (u.insn.x)
1933 ret = emulate_load_floatpair(ifa, u.insn, regs);
1934 else
1935 ret = emulate_load_float(ifa, u.insn, regs);
1936 break;
1938 case STF_OP:
1939 case STF_IMM_OP:
1940 ret = emulate_store_float(ifa, u.insn, regs);
1941 break;
1943 default:
1944 goto failure;
1946 DPRINT("ret=%d\n", ret);
1947 if (ret)
1948 goto failure;
1950 if (ipsr->ri == 2)
1951 /*
1952 * given today's architecture this case is not likely to happen because a
1953 * memory access instruction (M) can never be in the last slot of a
1954 * bundle. But let's keep it for now.
1955 */
1956 regs->cr_iip += 16;
1957 ipsr->ri = (ipsr->ri + 1) & 0x3;
1959 DPRINT("ipsr->ri=%d iip=%lx\n", ipsr->ri, regs->cr_iip);
1960 done:
1961 set_fs(old_fs); /* restore original address limit */
1962 return;
1964 failure:
1965 /* something went wrong... */
1966 if (!user_mode(regs)) {
1967 if (eh) {
1968 ia64_handle_exception(regs, eh);
1969 goto done;
1971 die_if_kernel("error during unaligned kernel access\n", regs, ret);
1972 /* NOT_REACHED */
1974 force_sigbus:
1975 si.si_signo = SIGBUS;
1976 si.si_errno = 0;
1977 si.si_code = BUS_ADRALN;
1978 si.si_addr = (void __user *) ifa;
1979 si.si_flags = 0;
1980 si.si_isr = 0;
1981 si.si_imm = 0;
1982 force_sig_info(SIGBUS, &si, current);
1983 goto done;
1984 #endif