ia64/xen-unstable

view xen/include/asm-x86/msr.h @ 11798:f14a67a35bec

[HVM][SVM] Use proper name for the K8 VM_CR MSR.
Signed-off-by: Keir Fraser <keir@xensource.com>
author kfraser@localhost.localdomain
date Thu Oct 12 17:53:51 2006 +0100 (2006-10-12)
parents 0f917d63e960
children 9a839ead4870
line source
1 #ifndef __ASM_MSR_H
2 #define __ASM_MSR_H
4 #ifndef __ASSEMBLY__
6 #define rdmsr(msr,val1,val2) \
7 __asm__ __volatile__("rdmsr" \
8 : "=a" (val1), "=d" (val2) \
9 : "c" (msr))
11 #define rdmsrl(msr,val) do { unsigned long a__,b__; \
12 __asm__ __volatile__("rdmsr" \
13 : "=a" (a__), "=d" (b__) \
14 : "c" (msr)); \
15 val = a__ | ((u64)b__<<32); \
16 } while(0);
18 #define wrmsr(msr,val1,val2) \
19 __asm__ __volatile__("wrmsr" \
20 : /* no outputs */ \
21 : "c" (msr), "a" (val1), "d" (val2))
23 static inline void wrmsrl(unsigned int msr, __u64 val)
24 {
25 __u32 lo, hi;
26 lo = (__u32)val;
27 hi = (__u32)(val >> 32);
28 wrmsr(msr, lo, hi);
29 }
31 /* rdmsr with exception handling */
32 #define rdmsr_safe(msr,val1,val2) ({\
33 int _rc; \
34 __asm__ __volatile__( \
35 "1: rdmsr\n2:\n" \
36 ".section .fixup,\"ax\"\n" \
37 "3: movl %5,%2\n; jmp 2b\n" \
38 ".previous\n" \
39 ".section __ex_table,\"a\"\n" \
40 " "__FIXUP_ALIGN"\n" \
41 " "__FIXUP_WORD" 1b,3b\n" \
42 ".previous\n" \
43 : "=a" (val1), "=d" (val2), "=&r" (_rc) \
44 : "c" (msr), "2" (0), "i" (-EFAULT)); \
45 _rc; })
47 /* wrmsr with exception handling */
48 #define wrmsr_safe(msr,val1,val2) ({\
49 int _rc; \
50 __asm__ __volatile__( \
51 "1: wrmsr\n2:\n" \
52 ".section .fixup,\"ax\"\n" \
53 "3: movl %5,%0\n; jmp 2b\n" \
54 ".previous\n" \
55 ".section __ex_table,\"a\"\n" \
56 " "__FIXUP_ALIGN"\n" \
57 " "__FIXUP_WORD" 1b,3b\n" \
58 ".previous\n" \
59 : "=&r" (_rc) \
60 : "c" (msr), "a" (val1), "d" (val2), "0" (0), "i" (-EFAULT)); \
61 _rc; })
63 #define rdtsc(low,high) \
64 __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
66 #define rdtscl(low) \
67 __asm__ __volatile__("rdtsc" : "=a" (low) : : "edx")
69 #if defined(__i386__)
70 #define rdtscll(val) \
71 __asm__ __volatile__("rdtsc" : "=A" (val))
72 #elif defined(__x86_64__)
73 #define rdtscll(val) do { \
74 unsigned int a,d; \
75 asm volatile("rdtsc" : "=a" (a), "=d" (d)); \
76 (val) = ((unsigned long)a) | (((unsigned long)d)<<32); \
77 } while(0)
78 #endif
80 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
82 #define rdpmc(counter,low,high) \
83 __asm__ __volatile__("rdpmc" \
84 : "=a" (low), "=d" (high) \
85 : "c" (counter))
87 #endif /* !__ASSEMBLY__ */
89 /* symbolic names for some interesting MSRs */
90 /* Intel defined MSRs. */
91 #define MSR_IA32_P5_MC_ADDR 0
92 #define MSR_IA32_P5_MC_TYPE 1
93 #define MSR_IA32_TIME_STAMP_COUNTER 0x10
94 #define MSR_IA32_PLATFORM_ID 0x17
95 #define MSR_IA32_EBL_CR_POWERON 0x2a
97 #define MSR_IA32_APICBASE 0x1b
98 #define MSR_IA32_APICBASE_BSP (1<<8)
99 #define MSR_IA32_APICBASE_ENABLE (1<<11)
100 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
102 #define MSR_IA32_UCODE_WRITE 0x79
103 #define MSR_IA32_UCODE_REV 0x8b
105 #define MSR_P6_PERFCTR0 0xc1
106 #define MSR_P6_PERFCTR1 0xc2
108 /* MSRs & bits used for VMX enabling */
109 #define MSR_IA32_VMX_BASIC_MSR 0x480
110 #define MSR_IA32_VMX_PINBASED_CTLS_MSR 0x481
111 #define MSR_IA32_VMX_PROCBASED_CTLS_MSR 0x482
112 #define MSR_IA32_VMX_EXIT_CTLS_MSR 0x483
113 #define MSR_IA32_VMX_ENTRY_CTLS_MSR 0x484
114 #define MSR_IA32_VMX_MISC_MSR 0x485
115 #define MSR_IA32_VMX_CR0_FIXED0 0x486
116 #define MSR_IA32_VMX_CR0_FIXED1 0x487
117 #define MSR_IA32_VMX_CR4_FIXED0 0x488
118 #define MSR_IA32_VMX_CR4_FIXED1 0x489
119 #define IA32_FEATURE_CONTROL_MSR 0x3a
120 #define IA32_FEATURE_CONTROL_MSR_LOCK 0x1
121 #define IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON 0x4
123 /* AMD/K8 specific MSRs */
124 #define MSR_EFER 0xc0000080 /* extended feature register */
125 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
126 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
127 #define MSR_CSTAR 0xc0000083 /* compatibility mode SYSCALL target */
128 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
129 #define MSR_FS_BASE 0xc0000100 /* 64bit GS base */
130 #define MSR_GS_BASE 0xc0000101 /* 64bit FS base */
131 #define MSR_SHADOW_GS_BASE 0xc0000102 /* SwapGS GS shadow */
132 /* EFER bits: */
133 #define _EFER_SCE 0 /* SYSCALL/SYSRET */
134 #define _EFER_LME 8 /* Long mode enable */
135 #define _EFER_LMA 10 /* Long mode active (read-only) */
136 #define _EFER_NX 11 /* No execute enable */
137 #define _EFER_SVME 12
139 #define EFER_SCE (1<<_EFER_SCE)
140 #define EFER_LME (1<<_EFER_LME)
141 #define EFER_LMA (1<<_EFER_LMA)
142 #define EFER_NX (1<<_EFER_NX)
143 #define EFER_SVME (1<<_EFER_SVME)
145 /* Intel MSRs. Some also available on other CPUs */
146 #define MSR_IA32_PLATFORM_ID 0x17
148 #define MSR_MTRRcap 0x0fe
149 #define MSR_IA32_BBL_CR_CTL 0x119
151 #define MSR_IA32_SYSENTER_CS 0x174
152 #define MSR_IA32_SYSENTER_ESP 0x175
153 #define MSR_IA32_SYSENTER_EIP 0x176
155 #define MSR_IA32_MCG_CAP 0x179
156 #define MSR_IA32_MCG_STATUS 0x17a
157 #define MSR_IA32_MCG_CTL 0x17b
159 /* P4/Xeon+ specific */
160 #define MSR_IA32_MCG_EAX 0x180
161 #define MSR_IA32_MCG_EBX 0x181
162 #define MSR_IA32_MCG_ECX 0x182
163 #define MSR_IA32_MCG_EDX 0x183
164 #define MSR_IA32_MCG_ESI 0x184
165 #define MSR_IA32_MCG_EDI 0x185
166 #define MSR_IA32_MCG_EBP 0x186
167 #define MSR_IA32_MCG_ESP 0x187
168 #define MSR_IA32_MCG_EFLAGS 0x188
169 #define MSR_IA32_MCG_EIP 0x189
170 #define MSR_IA32_MCG_RESERVED 0x18A
172 #define MSR_P6_EVNTSEL0 0x186
173 #define MSR_P6_EVNTSEL1 0x187
175 #define MSR_IA32_PERF_STATUS 0x198
176 #define MSR_IA32_PERF_CTL 0x199
178 #define MSR_IA32_THERM_CONTROL 0x19a
179 #define MSR_IA32_THERM_INTERRUPT 0x19b
180 #define MSR_IA32_THERM_STATUS 0x19c
181 #define MSR_IA32_MISC_ENABLE 0x1a0
183 #define MSR_IA32_MISC_ENABLE_PERF_AVAIL (1<<7)
184 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1<<11)
185 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
187 #define MSR_IA32_DEBUGCTLMSR 0x1d9
188 #define MSR_IA32_LASTBRANCHFROMIP 0x1db
189 #define MSR_IA32_LASTBRANCHTOIP 0x1dc
190 #define MSR_IA32_LASTINTFROMIP 0x1dd
191 #define MSR_IA32_LASTINTTOIP 0x1de
193 #define MSR_IA32_MC0_CTL 0x400
194 #define MSR_IA32_MC0_STATUS 0x401
195 #define MSR_IA32_MC0_ADDR 0x402
196 #define MSR_IA32_MC0_MISC 0x403
198 /* Pentium IV performance counter MSRs */
199 #define MSR_P4_BPU_PERFCTR0 0x300
200 #define MSR_P4_BPU_PERFCTR1 0x301
201 #define MSR_P4_BPU_PERFCTR2 0x302
202 #define MSR_P4_BPU_PERFCTR3 0x303
203 #define MSR_P4_MS_PERFCTR0 0x304
204 #define MSR_P4_MS_PERFCTR1 0x305
205 #define MSR_P4_MS_PERFCTR2 0x306
206 #define MSR_P4_MS_PERFCTR3 0x307
207 #define MSR_P4_FLAME_PERFCTR0 0x308
208 #define MSR_P4_FLAME_PERFCTR1 0x309
209 #define MSR_P4_FLAME_PERFCTR2 0x30a
210 #define MSR_P4_FLAME_PERFCTR3 0x30b
211 #define MSR_P4_IQ_PERFCTR0 0x30c
212 #define MSR_P4_IQ_PERFCTR1 0x30d
213 #define MSR_P4_IQ_PERFCTR2 0x30e
214 #define MSR_P4_IQ_PERFCTR3 0x30f
215 #define MSR_P4_IQ_PERFCTR4 0x310
216 #define MSR_P4_IQ_PERFCTR5 0x311
217 #define MSR_P4_BPU_CCCR0 0x360
218 #define MSR_P4_BPU_CCCR1 0x361
219 #define MSR_P4_BPU_CCCR2 0x362
220 #define MSR_P4_BPU_CCCR3 0x363
221 #define MSR_P4_MS_CCCR0 0x364
222 #define MSR_P4_MS_CCCR1 0x365
223 #define MSR_P4_MS_CCCR2 0x366
224 #define MSR_P4_MS_CCCR3 0x367
225 #define MSR_P4_FLAME_CCCR0 0x368
226 #define MSR_P4_FLAME_CCCR1 0x369
227 #define MSR_P4_FLAME_CCCR2 0x36a
228 #define MSR_P4_FLAME_CCCR3 0x36b
229 #define MSR_P4_IQ_CCCR0 0x36c
230 #define MSR_P4_IQ_CCCR1 0x36d
231 #define MSR_P4_IQ_CCCR2 0x36e
232 #define MSR_P4_IQ_CCCR3 0x36f
233 #define MSR_P4_IQ_CCCR4 0x370
234 #define MSR_P4_IQ_CCCR5 0x371
235 #define MSR_P4_ALF_ESCR0 0x3ca
236 #define MSR_P4_ALF_ESCR1 0x3cb
237 #define MSR_P4_BPU_ESCR0 0x3b2
238 #define MSR_P4_BPU_ESCR1 0x3b3
239 #define MSR_P4_BSU_ESCR0 0x3a0
240 #define MSR_P4_BSU_ESCR1 0x3a1
241 #define MSR_P4_CRU_ESCR0 0x3b8
242 #define MSR_P4_CRU_ESCR1 0x3b9
243 #define MSR_P4_CRU_ESCR2 0x3cc
244 #define MSR_P4_CRU_ESCR3 0x3cd
245 #define MSR_P4_CRU_ESCR4 0x3e0
246 #define MSR_P4_CRU_ESCR5 0x3e1
247 #define MSR_P4_DAC_ESCR0 0x3a8
248 #define MSR_P4_DAC_ESCR1 0x3a9
249 #define MSR_P4_FIRM_ESCR0 0x3a4
250 #define MSR_P4_FIRM_ESCR1 0x3a5
251 #define MSR_P4_FLAME_ESCR0 0x3a6
252 #define MSR_P4_FLAME_ESCR1 0x3a7
253 #define MSR_P4_FSB_ESCR0 0x3a2
254 #define MSR_P4_FSB_ESCR1 0x3a3
255 #define MSR_P4_IQ_ESCR0 0x3ba
256 #define MSR_P4_IQ_ESCR1 0x3bb
257 #define MSR_P4_IS_ESCR0 0x3b4
258 #define MSR_P4_IS_ESCR1 0x3b5
259 #define MSR_P4_ITLB_ESCR0 0x3b6
260 #define MSR_P4_ITLB_ESCR1 0x3b7
261 #define MSR_P4_IX_ESCR0 0x3c8
262 #define MSR_P4_IX_ESCR1 0x3c9
263 #define MSR_P4_MOB_ESCR0 0x3aa
264 #define MSR_P4_MOB_ESCR1 0x3ab
265 #define MSR_P4_MS_ESCR0 0x3c0
266 #define MSR_P4_MS_ESCR1 0x3c1
267 #define MSR_P4_PMH_ESCR0 0x3ac
268 #define MSR_P4_PMH_ESCR1 0x3ad
269 #define MSR_P4_RAT_ESCR0 0x3bc
270 #define MSR_P4_RAT_ESCR1 0x3bd
271 #define MSR_P4_SAAT_ESCR0 0x3ae
272 #define MSR_P4_SAAT_ESCR1 0x3af
273 #define MSR_P4_SSU_ESCR0 0x3be
274 #define MSR_P4_SSU_ESCR1 0x3bf /* guess: not defined in manual */
275 #define MSR_P4_TBPU_ESCR0 0x3c2
276 #define MSR_P4_TBPU_ESCR1 0x3c3
277 #define MSR_P4_TC_ESCR0 0x3c4
278 #define MSR_P4_TC_ESCR1 0x3c5
279 #define MSR_P4_U2L_ESCR0 0x3b0
280 #define MSR_P4_U2L_ESCR1 0x3b1
282 #define MSR_K6_EFER 0xC0000080
283 #define MSR_K6_STAR 0xC0000081
284 #define MSR_K6_WHCR 0xC0000082
285 #define MSR_K6_UWCCR 0xC0000085
286 #define MSR_K6_EPMR 0xC0000086
287 #define MSR_K6_PSOR 0xC0000087
288 #define MSR_K6_PFIR 0xC0000088
290 #define MSR_K7_EVNTSEL0 0xC0010000
291 #define MSR_K7_EVNTSEL1 0xC0010001
292 #define MSR_K7_EVNTSEL2 0xC0010002
293 #define MSR_K7_EVNTSEL3 0xC0010003
294 #define MSR_K7_PERFCTR0 0xC0010004
295 #define MSR_K7_PERFCTR1 0xC0010005
296 #define MSR_K7_PERFCTR2 0xC0010006
297 #define MSR_K7_PERFCTR3 0xC0010007
298 #define MSR_K7_HWCR 0xC0010015
299 #define MSR_K7_CLK_CTL 0xC001001b
300 #define MSR_K7_FID_VID_CTL 0xC0010041
301 #define MSR_K7_FID_VID_STATUS 0xC0010042
303 #define MSR_K8_TOP_MEM1 0xC001001A
304 #define MSR_K8_TOP_MEM2 0xC001001D
305 #define MSR_K8_SYSCFG 0xC0010010
306 #define MSR_K8_HWCR 0xC0010015
307 #define MSR_K8_VM_CR 0xC0010114
308 #define MSR_K8_VM_HSAVE_PA 0xC0010117
310 /* MSR_K8_VM_CR bits: */
311 #define _K8_VMCR_SVME_DISABLE 4
312 #define K8_VMCR_SVME_DISABLE (1 << _K8_VMCR_SVME_DISABLE)
314 /* Centaur-Hauls/IDT defined MSRs. */
315 #define MSR_IDT_FCR1 0x107
316 #define MSR_IDT_FCR2 0x108
317 #define MSR_IDT_FCR3 0x109
318 #define MSR_IDT_FCR4 0x10a
320 #define MSR_IDT_MCR0 0x110
321 #define MSR_IDT_MCR1 0x111
322 #define MSR_IDT_MCR2 0x112
323 #define MSR_IDT_MCR3 0x113
324 #define MSR_IDT_MCR4 0x114
325 #define MSR_IDT_MCR5 0x115
326 #define MSR_IDT_MCR6 0x116
327 #define MSR_IDT_MCR7 0x117
328 #define MSR_IDT_MCR_CTRL 0x120
330 /* VIA Cyrix defined MSRs*/
331 #define MSR_VIA_FCR 0x1107
332 #define MSR_VIA_LONGHAUL 0x110a
333 #define MSR_VIA_RNG 0x110b
334 #define MSR_VIA_BCR2 0x1147
336 /* Transmeta defined MSRs */
337 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
338 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
339 #define MSR_TMTA_LRTI_READOUT 0x80868018
340 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
342 #endif /* __ASM_MSR_H */