ia64/xen-unstable

view xen/arch/x86/i8259.c @ 19835:edfdeb150f27

Fix buildsystem to detect udev > version 124

udev removed the udevinfo symlink from versions higher than 123 and
xen's build-system could not detect if udev is in place and has the
required version.

Signed-off-by: Marc-A. Dahlhaus <mad@wol.de>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Jun 25 13:02:37 2009 +0100 (2009-06-25)
parents 6705898f768d
children
line source
1 /******************************************************************************
2 * i8259.c
3 *
4 * Well, this is required for SMP systems as well, as it build interrupt
5 * tables for IO APICS as well as uniprocessor 8259-alikes.
6 */
8 #include <xen/config.h>
9 #include <xen/init.h>
10 #include <xen/types.h>
11 #include <asm/regs.h>
12 #include <xen/errno.h>
13 #include <xen/sched.h>
14 #include <xen/irq.h>
15 #include <asm/atomic.h>
16 #include <asm/system.h>
17 #include <asm/io.h>
18 #include <asm/desc.h>
19 #include <asm/bitops.h>
20 #include <xen/delay.h>
21 #include <asm/apic.h>
22 #include <asm/asm_defns.h>
23 #include <io_ports.h>
25 /*
26 * Common place to define all x86 IRQ vectors
27 *
28 * This builds up the IRQ handler stubs using some ugly macros in irq.h
29 *
30 * These macros create the low-level assembly IRQ routines that save
31 * register context and call do_IRQ(). do_IRQ() then does all the
32 * operations that are needed to keep the AT (or SMP IOAPIC)
33 * interrupt-controller happy.
34 */
36 BUILD_COMMON_IRQ()
38 #define BI(x,y) \
39 BUILD_IRQ(x##y)
41 #define BUILD_16_IRQS(x) \
42 BI(x,0) BI(x,1) BI(x,2) BI(x,3) \
43 BI(x,4) BI(x,5) BI(x,6) BI(x,7) \
44 BI(x,8) BI(x,9) BI(x,a) BI(x,b) \
45 BI(x,c) BI(x,d) BI(x,e) BI(x,f)
47 BUILD_16_IRQS(0x0) BUILD_16_IRQS(0x1) BUILD_16_IRQS(0x2) BUILD_16_IRQS(0x3)
48 BUILD_16_IRQS(0x4) BUILD_16_IRQS(0x5) BUILD_16_IRQS(0x6) BUILD_16_IRQS(0x7)
49 BUILD_16_IRQS(0x8) BUILD_16_IRQS(0x9) BUILD_16_IRQS(0xa) BUILD_16_IRQS(0xb)
50 BUILD_16_IRQS(0xc) BUILD_16_IRQS(0xd) BUILD_16_IRQS(0xe) BUILD_16_IRQS(0xf)
52 #undef BUILD_16_IRQS
53 #undef BI
56 /*
57 * The following vectors are part of the Linux architecture, there
58 * is no hardware IRQ pin equivalent for them, they are triggered
59 * through the ICC by us (IPIs)
60 */
61 BUILD_SMP_INTERRUPT(event_check_interrupt,EVENT_CHECK_VECTOR)
62 BUILD_SMP_INTERRUPT(invalidate_interrupt,INVALIDATE_TLB_VECTOR)
63 BUILD_SMP_INTERRUPT(call_function_interrupt,CALL_FUNCTION_VECTOR)
65 /*
66 * Every pentium local APIC has two 'local interrupts', with a
67 * soft-definable vector attached to both interrupts, one of
68 * which is a timer interrupt, the other one is error counter
69 * overflow. Linux uses the local APIC timer interrupt to get
70 * a much simpler SMP time architecture:
71 */
72 BUILD_SMP_INTERRUPT(apic_timer_interrupt,LOCAL_TIMER_VECTOR)
73 BUILD_SMP_INTERRUPT(error_interrupt,ERROR_APIC_VECTOR)
74 BUILD_SMP_INTERRUPT(spurious_interrupt,SPURIOUS_APIC_VECTOR)
75 BUILD_SMP_INTERRUPT(pmu_apic_interrupt,PMU_APIC_VECTOR)
76 BUILD_SMP_INTERRUPT(thermal_interrupt,THERMAL_APIC_VECTOR)
77 BUILD_SMP_INTERRUPT(cmci_interrupt, CMCI_APIC_VECTOR)
79 #define IRQ(x,y) \
80 IRQ##x##y##_interrupt
82 #define IRQLIST_16(x) \
83 IRQ(x,0), IRQ(x,1), IRQ(x,2), IRQ(x,3), \
84 IRQ(x,4), IRQ(x,5), IRQ(x,6), IRQ(x,7), \
85 IRQ(x,8), IRQ(x,9), IRQ(x,a), IRQ(x,b), \
86 IRQ(x,c), IRQ(x,d), IRQ(x,e), IRQ(x,f)
88 static void (*interrupt[])(void) = {
89 IRQLIST_16(0x0), IRQLIST_16(0x1), IRQLIST_16(0x2), IRQLIST_16(0x3),
90 IRQLIST_16(0x4), IRQLIST_16(0x5), IRQLIST_16(0x6), IRQLIST_16(0x7),
91 IRQLIST_16(0x8), IRQLIST_16(0x9), IRQLIST_16(0xa), IRQLIST_16(0xb),
92 IRQLIST_16(0xc), IRQLIST_16(0xd), IRQLIST_16(0xe), IRQLIST_16(0xf)
93 };
95 #undef IRQ
96 #undef IRQLIST_16
98 /*
99 * This is the 'legacy' 8259A Programmable Interrupt Controller,
100 * present in the majority of PC/AT boxes.
101 * plus some generic x86 specific things if generic specifics makes
102 * any sense at all.
103 * this file should become arch/i386/kernel/irq.c when the old irq.c
104 * moves to arch independent land
105 */
107 static DEFINE_SPINLOCK(i8259A_lock);
109 static void disable_8259A_vector(unsigned int vector)
110 {
111 disable_8259A_irq(LEGACY_IRQ_FROM_VECTOR(vector));
112 }
114 static void enable_8259A_vector(unsigned int vector)
115 {
116 enable_8259A_irq(LEGACY_IRQ_FROM_VECTOR(vector));
117 }
119 static void mask_and_ack_8259A_vector(unsigned int);
121 static void end_8259A_vector(unsigned int vector)
122 {
123 if (!(irq_desc[vector].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
124 enable_8259A_vector(vector);
125 }
127 static unsigned int startup_8259A_vector(unsigned int vector)
128 {
129 enable_8259A_vector(vector);
130 return 0; /* never anything pending */
131 }
133 static struct hw_interrupt_type i8259A_irq_type = {
134 .typename = "XT-PIC",
135 .startup = startup_8259A_vector,
136 .shutdown = disable_8259A_vector,
137 .enable = enable_8259A_vector,
138 .disable = disable_8259A_vector,
139 .ack = mask_and_ack_8259A_vector,
140 .end = end_8259A_vector
141 };
143 /*
144 * 8259A PIC functions to handle ISA devices:
145 */
147 /*
148 * This contains the irq mask for both 8259A irq controllers,
149 */
150 static unsigned int cached_irq_mask = 0xffff;
152 #define __byte(x,y) (((unsigned char *)&(y))[x])
153 #define cached_21 (__byte(0,cached_irq_mask))
154 #define cached_A1 (__byte(1,cached_irq_mask))
156 /*
157 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
158 * boards the timer interrupt is not really connected to any IO-APIC pin,
159 * it's fed to the master 8259A's IR0 line only.
160 *
161 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
162 * this 'mixed mode' IRQ handling costs nothing because it's only used
163 * at IRQ setup time.
164 */
165 unsigned long io_apic_irqs;
167 void disable_8259A_irq(unsigned int irq)
168 {
169 unsigned int mask = 1 << irq;
170 unsigned long flags;
172 spin_lock_irqsave(&i8259A_lock, flags);
173 cached_irq_mask |= mask;
174 if (irq & 8)
175 outb(cached_A1,0xA1);
176 else
177 outb(cached_21,0x21);
178 spin_unlock_irqrestore(&i8259A_lock, flags);
179 }
181 void enable_8259A_irq(unsigned int irq)
182 {
183 unsigned int mask = ~(1 << irq);
184 unsigned long flags;
186 spin_lock_irqsave(&i8259A_lock, flags);
187 cached_irq_mask &= mask;
188 if (irq & 8)
189 outb(cached_A1,0xA1);
190 else
191 outb(cached_21,0x21);
192 spin_unlock_irqrestore(&i8259A_lock, flags);
193 }
195 int i8259A_irq_pending(unsigned int irq)
196 {
197 unsigned int mask = 1<<irq;
198 unsigned long flags;
199 int ret;
201 spin_lock_irqsave(&i8259A_lock, flags);
202 if (irq < 8)
203 ret = inb(0x20) & mask;
204 else
205 ret = inb(0xA0) & (mask >> 8);
206 spin_unlock_irqrestore(&i8259A_lock, flags);
208 return ret;
209 }
211 /*
212 * This function assumes to be called rarely. Switching between
213 * 8259A registers is slow.
214 * This has to be protected by the irq controller spinlock
215 * before being called.
216 */
217 static inline int i8259A_irq_real(unsigned int irq)
218 {
219 int value;
220 int irqmask = 1<<irq;
222 if (irq < 8) {
223 outb(0x0B,0x20); /* ISR register */
224 value = inb(0x20) & irqmask;
225 outb(0x0A,0x20); /* back to the IRR register */
226 return value;
227 }
228 outb(0x0B,0xA0); /* ISR register */
229 value = inb(0xA0) & (irqmask >> 8);
230 outb(0x0A,0xA0); /* back to the IRR register */
231 return value;
232 }
234 /*
235 * Careful! The 8259A is a fragile beast, it pretty
236 * much _has_ to be done exactly like this (mask it
237 * first, _then_ send the EOI, and the order of EOI
238 * to the two 8259s is important!
239 */
240 static void mask_and_ack_8259A_vector(unsigned int vector)
241 {
242 unsigned int irq = LEGACY_IRQ_FROM_VECTOR(vector);
243 unsigned int irqmask = 1 << irq;
244 unsigned long flags;
246 spin_lock_irqsave(&i8259A_lock, flags);
247 /*
248 * Lightweight spurious IRQ detection. We do not want
249 * to overdo spurious IRQ handling - it's usually a sign
250 * of hardware problems, so we only do the checks we can
251 * do without slowing down good hardware unnecesserily.
252 *
253 * Note that IRQ7 and IRQ15 (the two spurious IRQs
254 * usually resulting from the 8259A-1|2 PICs) occur
255 * even if the IRQ is masked in the 8259A. Thus we
256 * can check spurious 8259A IRQs without doing the
257 * quite slow i8259A_irq_real() call for every IRQ.
258 * This does not cover 100% of spurious interrupts,
259 * but should be enough to warn the user that there
260 * is something bad going on ...
261 */
262 if (cached_irq_mask & irqmask)
263 goto spurious_8259A_irq;
264 cached_irq_mask |= irqmask;
266 handle_real_irq:
267 if (irq & 8) {
268 inb(0xA1); /* DUMMY - (do we need this?) */
269 outb(cached_A1,0xA1);
270 outb(0x60+(irq&7),0xA0);/* 'Specific EOI' to slave */
271 outb(0x62,0x20); /* 'Specific EOI' to master-IRQ2 */
272 } else {
273 inb(0x21); /* DUMMY - (do we need this?) */
274 outb(cached_21,0x21);
275 outb(0x60+irq,0x20); /* 'Specific EOI' to master */
276 }
277 spin_unlock_irqrestore(&i8259A_lock, flags);
278 return;
280 spurious_8259A_irq:
281 /*
282 * this is the slow path - should happen rarely.
283 */
284 if (i8259A_irq_real(irq))
285 /*
286 * oops, the IRQ _is_ in service according to the
287 * 8259A - not spurious, go handle it.
288 */
289 goto handle_real_irq;
291 {
292 static int spurious_irq_mask;
293 /*
294 * At this point we can be sure the IRQ is spurious,
295 * lets ACK and report it. [once per IRQ]
296 */
297 if (!(spurious_irq_mask & irqmask)) {
298 printk("spurious 8259A interrupt: IRQ%d.\n", irq);
299 spurious_irq_mask |= irqmask;
300 }
301 atomic_inc(&irq_err_count);
302 /*
303 * Theoretically we do not have to handle this IRQ,
304 * but in Linux this does not cause problems and is
305 * simpler for us.
306 */
307 goto handle_real_irq;
308 }
309 }
311 static char irq_trigger[2];
312 /**
313 * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
314 */
315 static void restore_ELCR(char *trigger)
316 {
317 outb(trigger[0], 0x4d0);
318 outb(trigger[1], 0x4d1);
319 }
321 static void save_ELCR(char *trigger)
322 {
323 /* IRQ 0,1,2,8,13 are marked as reserved */
324 trigger[0] = inb(0x4d0) & 0xF8;
325 trigger[1] = inb(0x4d1) & 0xDE;
326 }
328 int i8259A_resume(void)
329 {
330 init_8259A(0);
331 restore_ELCR(irq_trigger);
332 return 0;
333 }
335 int i8259A_suspend(void)
336 {
337 save_ELCR(irq_trigger);
338 return 0;
339 }
341 void __devinit init_8259A(int auto_eoi)
342 {
343 unsigned long flags;
345 spin_lock_irqsave(&i8259A_lock, flags);
347 outb(0xff, 0x21); /* mask all of 8259A-1 */
348 outb(0xff, 0xA1); /* mask all of 8259A-2 */
350 /*
351 * outb_p - this has to work on a wide range of PC hardware.
352 */
353 outb_p(0x11, 0x20); /* ICW1: select 8259A-1 init */
354 outb_p(FIRST_LEGACY_VECTOR + 0, 0x21); /* ICW2: 8259A-1 IR0-7 */
355 outb_p(0x04, 0x21); /* 8259A-1 (the master) has a slave on IR2 */
356 if (auto_eoi)
357 outb_p(0x03, 0x21); /* master does Auto EOI */
358 else
359 outb_p(0x01, 0x21); /* master expects normal EOI */
361 outb_p(0x11, 0xA0); /* ICW1: select 8259A-2 init */
362 outb_p(FIRST_LEGACY_VECTOR + 8, 0xA1); /* ICW2: 8259A-2 IR0-7 */
363 outb_p(0x02, 0xA1); /* 8259A-2 is a slave on master's IR2 */
364 outb_p(0x01, 0xA1); /* (slave's support for AEOI in flat mode
365 is to be investigated) */
367 if (auto_eoi)
368 /*
369 * in AEOI mode we just have to mask the interrupt
370 * when acking.
371 */
372 i8259A_irq_type.ack = disable_8259A_vector;
373 else
374 i8259A_irq_type.ack = mask_and_ack_8259A_vector;
376 udelay(100); /* wait for 8259A to initialize */
378 outb(cached_21, 0x21); /* restore master IRQ mask */
379 outb(cached_A1, 0xA1); /* restore slave IRQ mask */
381 spin_unlock_irqrestore(&i8259A_lock, flags);
382 }
384 static struct irqaction cascade = { no_action, "cascade", NULL};
386 void __init init_IRQ(void)
387 {
388 int i;
390 init_bsp_APIC();
392 init_8259A(0);
394 for ( i = 0; i < NR_VECTORS; i++ )
395 {
396 irq_desc[i].status = IRQ_DISABLED;
397 irq_desc[i].handler = &no_irq_type;
398 irq_desc[i].action = NULL;
399 irq_desc[i].depth = 1;
400 spin_lock_init(&irq_desc[i].lock);
401 cpus_setall(irq_desc[i].affinity);
402 if ( i >= 0x20 )
403 set_intr_gate(i, interrupt[i]);
404 }
406 irq_vector = xmalloc_array(u8, nr_irqs);
407 memset(irq_vector, 0, nr_irqs * sizeof(*irq_vector));
409 for ( i = 0; i < 16; i++ )
410 {
411 vector_irq[LEGACY_VECTOR(i)] = i;
412 irq_desc[LEGACY_VECTOR(i)].handler = &i8259A_irq_type;
413 }
415 /* Never allocate the hypercall vector or Linux/BSD fast-trap vector. */
416 vector_irq[HYPERCALL_VECTOR] = NEVER_ASSIGN_IRQ;
417 vector_irq[0x80] = NEVER_ASSIGN_IRQ;
419 apic_intr_init();
421 /* Set the clock to HZ Hz */
422 #define CLOCK_TICK_RATE 1193182 /* crystal freq (Hz) */
423 #define LATCH (((CLOCK_TICK_RATE)+(HZ/2))/HZ)
424 outb_p(0x34, PIT_MODE); /* binary, mode 2, LSB/MSB, ch 0 */
425 outb_p(LATCH & 0xff, PIT_CH0); /* LSB */
426 outb(LATCH >> 8, PIT_CH0); /* MSB */
428 setup_irq(2, &cascade);
429 }