ia64/xen-unstable

view xen/arch/x86/cpu/intel.c @ 19835:edfdeb150f27

Fix buildsystem to detect udev > version 124

udev removed the udevinfo symlink from versions higher than 123 and
xen's build-system could not detect if udev is in place and has the
required version.

Signed-off-by: Marc-A. Dahlhaus <mad@wol.de>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Jun 25 13:02:37 2009 +0100 (2009-06-25)
parents b44db970f6b7
children
line source
1 #include <xen/config.h>
2 #include <xen/init.h>
3 #include <xen/kernel.h>
4 #include <xen/string.h>
5 #include <xen/bitops.h>
6 #include <xen/smp.h>
7 #include <asm/processor.h>
8 #include <asm/msr.h>
9 #include <asm/uaccess.h>
10 #include <asm/mpspec.h>
11 #include <asm/apic.h>
12 #include <mach_apic.h>
13 #include <asm/hvm/support.h>
15 #include "cpu.h"
17 #define select_idle_routine(x) ((void)0)
19 extern int trap_init_f00f_bug(void);
21 /*
22 * opt_cpuid_mask_ecx/edx: cpuid.1[ecx, edx] feature mask.
23 * For example, E8400[Intel Core 2 Duo Processor series] ecx = 0x0008E3FD,
24 * edx = 0xBFEBFBFF when executing CPUID.EAX = 1 normally. If you want to
25 * 'rev down' to E8400, you can set these values in these Xen boot parameters.
26 */
27 static unsigned int opt_cpuid_mask_ecx, opt_cpuid_mask_edx;
28 integer_param("cpuid_mask_ecx", opt_cpuid_mask_ecx);
29 integer_param("cpuid_mask_edx", opt_cpuid_mask_edx);
31 #ifdef CONFIG_X86_INTEL_USERCOPY
32 /*
33 * Alignment at which movsl is preferred for bulk memory copies.
34 */
35 struct movsl_mask movsl_mask __read_mostly;
36 #endif
38 static void __devinit set_cpuidmask(void)
39 {
40 unsigned int eax, ebx, ecx, edx, model;
42 if (!(opt_cpuid_mask_ecx | opt_cpuid_mask_edx))
43 return;
45 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
46 model = ((eax & 0xf0000) >> 12) | ((eax & 0xf0) >> 4);
47 if (!((model == 0x1d) || ((model == 0x17) && ((eax & 0xf) >= 4)))) {
48 printk(XENLOG_ERR "Cannot set CPU feature mask on CPU#%d\n",
49 smp_processor_id());
50 return;
51 }
53 wrmsr(MSR_IA32_CPUID_FEATURE_MASK1,
54 opt_cpuid_mask_ecx ? : ~0u,
55 opt_cpuid_mask_edx ? : ~0u);
56 }
58 void __devinit early_intel_workaround(struct cpuinfo_x86 *c)
59 {
60 if (c->x86_vendor != X86_VENDOR_INTEL)
61 return;
62 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
63 if (c->x86 == 15 && c->x86_cache_alignment == 64)
64 c->x86_cache_alignment = 128;
65 }
67 /*
68 * Early probe support logic for ppro memory erratum #50
69 *
70 * This is called before we do cpu ident work
71 */
73 int __devinit ppro_with_ram_bug(void)
74 {
75 /* Uses data from early_cpu_detect now */
76 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
77 boot_cpu_data.x86 == 6 &&
78 boot_cpu_data.x86_model == 1 &&
79 boot_cpu_data.x86_mask < 8) {
80 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
81 return 1;
82 }
83 return 0;
84 }
87 /*
88 * P4 Xeon errata 037 workaround.
89 * Hardware prefetcher may cause stale data to be loaded into the cache.
90 */
91 static void __devinit Intel_errata_workarounds(struct cpuinfo_x86 *c)
92 {
93 unsigned long lo, hi;
95 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
96 rdmsr (MSR_IA32_MISC_ENABLE, lo, hi);
97 if ((lo & (1<<9)) == 0) {
98 printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
99 printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
100 lo |= (1<<9); /* Disable hw prefetching */
101 wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
102 }
103 }
104 }
107 /*
108 * find out the number of processor cores on the die
109 */
110 static int __devinit num_cpu_cores(struct cpuinfo_x86 *c)
111 {
112 unsigned int eax, ebx, ecx, edx;
114 if (c->cpuid_level < 4)
115 return 1;
117 /* Intel has a non-standard dependency on %ecx for this CPUID level. */
118 cpuid_count(4, 0, &eax, &ebx, &ecx, &edx);
119 if (eax & 0x1f)
120 return ((eax >> 26) + 1);
121 else
122 return 1;
123 }
125 static void __devinit init_intel(struct cpuinfo_x86 *c)
126 {
127 unsigned int l2 = 0;
128 char *p = NULL;
130 #ifdef CONFIG_X86_F00F_BUG
131 /*
132 * All current models of Pentium and Pentium with MMX technology CPUs
133 * have the F0 0F bug, which lets nonprivileged users lock up the system.
134 * Note that the workaround only should be initialized once...
135 */
136 c->f00f_bug = 0;
137 if ( c->x86 == 5 ) {
138 static int f00f_workaround_enabled = 0;
140 c->f00f_bug = 1;
141 if ( !f00f_workaround_enabled ) {
142 trap_init_f00f_bug();
143 printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
144 f00f_workaround_enabled = 1;
145 }
146 }
147 #endif
149 select_idle_routine(c);
150 l2 = init_intel_cacheinfo(c);
152 /* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
153 if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
154 clear_bit(X86_FEATURE_SEP, c->x86_capability);
156 /* Names for the Pentium II/Celeron processors
157 detectable only by also checking the cache size.
158 Dixon is NOT a Celeron. */
159 if (c->x86 == 6) {
160 switch (c->x86_model) {
161 case 5:
162 if (c->x86_mask == 0) {
163 if (l2 == 0)
164 p = "Celeron (Covington)";
165 else if (l2 == 256)
166 p = "Mobile Pentium II (Dixon)";
167 }
168 break;
170 case 6:
171 if (l2 == 128)
172 p = "Celeron (Mendocino)";
173 else if (c->x86_mask == 0 || c->x86_mask == 5)
174 p = "Celeron-A";
175 break;
177 case 8:
178 if (l2 == 128)
179 p = "Celeron (Coppermine)";
180 break;
181 }
182 }
184 if ( p )
185 safe_strcpy(c->x86_model_id, p);
187 c->x86_max_cores = num_cpu_cores(c);
189 detect_ht(c);
191 set_cpuidmask();
193 /* Work around errata */
194 Intel_errata_workarounds(c);
196 #ifdef CONFIG_X86_INTEL_USERCOPY
197 /*
198 * Set up the preferred alignment for movsl bulk memory moves
199 */
200 switch (c->x86) {
201 case 4: /* 486: untested */
202 break;
203 case 5: /* Old Pentia: untested */
204 break;
205 case 6: /* PII/PIII only like movsl with 8-byte alignment */
206 movsl_mask.mask = 7;
207 break;
208 case 15: /* P4 is OK down to 8-byte alignment */
209 movsl_mask.mask = 7;
210 break;
211 }
212 #endif
214 if (c->x86 == 15)
215 set_bit(X86_FEATURE_P4, c->x86_capability);
216 if (c->x86 == 6)
217 set_bit(X86_FEATURE_P3, c->x86_capability);
218 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
219 (c->x86 == 0x6 && c->x86_model >= 0x0e))
220 set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
221 if (cpuid_edx(0x80000007) & (1u<<8)) {
222 set_bit(X86_FEATURE_CONSTANT_TSC, c->x86_capability);
223 set_bit(X86_FEATURE_NOSTOP_TSC, c->x86_capability);
224 }
225 if ((c->cpuid_level >= 0x00000006) &&
226 (cpuid_eax(0x00000006) & (1u<<2)))
227 set_bit(X86_FEATURE_ARAT, c->x86_capability);
229 start_vmx();
230 }
233 static unsigned int intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)
234 {
235 /* Intel PIII Tualatin. This comes in two flavours.
236 * One has 256kb of cache, the other 512. We have no way
237 * to determine which, so we use a boottime override
238 * for the 512kb model, and assume 256 otherwise.
239 */
240 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
241 size = 256;
242 return size;
243 }
245 static struct cpu_dev intel_cpu_dev __devinitdata = {
246 .c_vendor = "Intel",
247 .c_ident = { "GenuineIntel" },
248 .c_models = {
249 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
250 {
251 [0] = "486 DX-25/33",
252 [1] = "486 DX-50",
253 [2] = "486 SX",
254 [3] = "486 DX/2",
255 [4] = "486 SL",
256 [5] = "486 SX/2",
257 [7] = "486 DX/2-WB",
258 [8] = "486 DX/4",
259 [9] = "486 DX/4-WB"
260 }
261 },
262 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
263 {
264 [0] = "Pentium 60/66 A-step",
265 [1] = "Pentium 60/66",
266 [2] = "Pentium 75 - 200",
267 [3] = "OverDrive PODP5V83",
268 [4] = "Pentium MMX",
269 [7] = "Mobile Pentium 75 - 200",
270 [8] = "Mobile Pentium MMX"
271 }
272 },
273 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
274 {
275 [0] = "Pentium Pro A-step",
276 [1] = "Pentium Pro",
277 [3] = "Pentium II (Klamath)",
278 [4] = "Pentium II (Deschutes)",
279 [5] = "Pentium II (Deschutes)",
280 [6] = "Mobile Pentium II",
281 [7] = "Pentium III (Katmai)",
282 [8] = "Pentium III (Coppermine)",
283 [10] = "Pentium III (Cascades)",
284 [11] = "Pentium III (Tualatin)",
285 }
286 },
287 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
288 {
289 [0] = "Pentium 4 (Unknown)",
290 [1] = "Pentium 4 (Willamette)",
291 [2] = "Pentium 4 (Northwood)",
292 [4] = "Pentium 4 (Foster)",
293 [5] = "Pentium 4 (Foster)",
294 }
295 },
296 },
297 .c_init = init_intel,
298 .c_identify = generic_identify,
299 .c_size_cache = intel_size_cache,
300 };
302 __init int intel_cpu_init(void)
303 {
304 cpu_devs[X86_VENDOR_INTEL] = &intel_cpu_dev;
305 return 0;
306 }
308 // arch_initcall(intel_cpu_init);