ia64/xen-unstable

view xen/arch/x86/cpu/common.c @ 19835:edfdeb150f27

Fix buildsystem to detect udev > version 124

udev removed the udevinfo symlink from versions higher than 123 and
xen's build-system could not detect if udev is in place and has the
required version.

Signed-off-by: Marc-A. Dahlhaus <mad@wol.de>
author Keir Fraser <keir.fraser@citrix.com>
date Thu Jun 25 13:02:37 2009 +0100 (2009-06-25)
parents e1562a36094e
children
line source
1 #include <xen/config.h>
2 #include <xen/init.h>
3 #include <xen/string.h>
4 #include <xen/delay.h>
5 #include <xen/smp.h>
6 #include <asm/current.h>
7 #include <asm/processor.h>
8 #include <asm/i387.h>
9 #include <asm/msr.h>
10 #include <asm/io.h>
11 #include <asm/mpspec.h>
12 #include <asm/apic.h>
13 #include <mach_apic.h>
15 #include "cpu.h"
17 #define tsc_disable 0
18 #define disable_pse 0
20 static int cachesize_override __cpuinitdata = -1;
21 static int disable_x86_fxsr __cpuinitdata;
22 static int disable_x86_serial_nr __cpuinitdata;
24 struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {};
26 /*
27 * Default host IA32_CR_PAT value to cover all memory types.
28 * BIOS usually sets it to 0x07040600070406.
29 */
30 u64 host_pat = 0x050100070406;
32 static unsigned int __cpuinitdata cleared_caps[NCAPINTS];
34 void __init setup_clear_cpu_cap(unsigned int cap)
35 {
36 __clear_bit(cap, boot_cpu_data.x86_capability);
37 __set_bit(cap, cleared_caps);
38 }
40 static void default_init(struct cpuinfo_x86 * c)
41 {
42 /* Not much we can do here... */
43 /* Check if at least it has cpuid */
44 if (c->cpuid_level == -1) {
45 /* No cpuid. It must be an ancient CPU */
46 if (c->x86 == 4)
47 safe_strcpy(c->x86_model_id, "486");
48 else if (c->x86 == 3)
49 safe_strcpy(c->x86_model_id, "386");
50 }
51 }
53 static struct cpu_dev default_cpu = {
54 .c_init = default_init,
55 .c_vendor = "Unknown",
56 };
57 static struct cpu_dev * this_cpu = &default_cpu;
59 integer_param("cachesize", cachesize_override);
61 int __cpuinit get_model_name(struct cpuinfo_x86 *c)
62 {
63 unsigned int *v;
64 char *p, *q;
66 if (cpuid_eax(0x80000000) < 0x80000004)
67 return 0;
69 v = (unsigned int *) c->x86_model_id;
70 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
71 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
72 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
73 c->x86_model_id[48] = 0;
75 /* Intel chips right-justify this string for some dumb reason;
76 undo that brain damage */
77 p = q = &c->x86_model_id[0];
78 while ( *p == ' ' )
79 p++;
80 if ( p != q ) {
81 while ( *p )
82 *q++ = *p++;
83 while ( q <= &c->x86_model_id[48] )
84 *q++ = '\0'; /* Zero-pad the rest */
85 }
87 return 1;
88 }
91 void __cpuinit display_cacheinfo(struct cpuinfo_x86 *c)
92 {
93 unsigned int n, dummy, ecx, edx, l2size;
95 n = cpuid_eax(0x80000000);
97 if (n >= 0x80000005) {
98 cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
99 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
100 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
101 c->x86_cache_size=(ecx>>24)+(edx>>24);
102 }
104 if (n < 0x80000006) /* Some chips just has a large L1. */
105 return;
107 ecx = cpuid_ecx(0x80000006);
108 l2size = ecx >> 16;
110 /* do processor-specific cache resizing */
111 if (this_cpu->c_size_cache)
112 l2size = this_cpu->c_size_cache(c,l2size);
114 /* Allow user to override all this if necessary. */
115 if (cachesize_override != -1)
116 l2size = cachesize_override;
118 if ( l2size == 0 )
119 return; /* Again, no L2 cache is possible */
121 c->x86_cache_size = l2size;
123 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
124 l2size, ecx & 0xFF);
125 }
127 /* Naming convention should be: <Name> [(<Codename>)] */
128 /* This table only is used unless init_<vendor>() below doesn't set it; */
129 /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
131 /* Look up CPU names by table lookup. */
132 static char __cpuinit *table_lookup_model(struct cpuinfo_x86 *c)
133 {
134 struct cpu_model_info *info;
136 if ( c->x86_model >= 16 )
137 return NULL; /* Range check */
139 if (!this_cpu)
140 return NULL;
142 info = this_cpu->c_models;
144 while (info && info->family) {
145 if (info->family == c->x86)
146 return info->model_names[c->x86_model];
147 info++;
148 }
149 return NULL; /* Not found */
150 }
153 static void __cpuinit get_cpu_vendor(struct cpuinfo_x86 *c, int early)
154 {
155 char *v = c->x86_vendor_id;
156 int i;
157 static int printed;
159 for (i = 0; i < X86_VENDOR_NUM; i++) {
160 if (cpu_devs[i]) {
161 if (!strcmp(v,cpu_devs[i]->c_ident[0]) ||
162 (cpu_devs[i]->c_ident[1] &&
163 !strcmp(v,cpu_devs[i]->c_ident[1]))) {
164 c->x86_vendor = i;
165 if (!early)
166 this_cpu = cpu_devs[i];
167 return;
168 }
169 }
170 }
171 if (!printed) {
172 printed++;
173 printk(KERN_ERR "CPU: Vendor unknown, using generic init.\n");
174 printk(KERN_ERR "CPU: Your system may be unstable.\n");
175 }
176 c->x86_vendor = X86_VENDOR_UNKNOWN;
177 this_cpu = &default_cpu;
178 }
181 boolean_param("nofxsr", disable_x86_fxsr);
184 /* Standard macro to see if a specific flag is changeable */
185 static inline int flag_is_changeable_p(unsigned long flag)
186 {
187 unsigned long f1, f2;
189 asm("pushf\n\t"
190 "pushf\n\t"
191 "pop %0\n\t"
192 "mov %0,%1\n\t"
193 "xor %2,%0\n\t"
194 "push %0\n\t"
195 "popf\n\t"
196 "pushf\n\t"
197 "pop %0\n\t"
198 "popf\n\t"
199 : "=&r" (f1), "=&r" (f2)
200 : "ir" (flag));
202 return ((f1^f2) & flag) != 0;
203 }
206 /* Probe for the CPUID instruction */
207 static int __cpuinit have_cpuid_p(void)
208 {
209 return flag_is_changeable_p(X86_EFLAGS_ID);
210 }
212 /* Do minimum CPU detection early.
213 Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
214 The others are not touched to avoid unwanted side effects.
216 WARNING: this function is only called on the BP. Don't add code here
217 that is supposed to run on all CPUs. */
218 static void __init early_cpu_detect(void)
219 {
220 struct cpuinfo_x86 *c = &boot_cpu_data;
222 c->x86_cache_alignment = 32;
224 if (!have_cpuid_p())
225 return;
227 /* Get vendor name */
228 cpuid(0x00000000, &c->cpuid_level,
229 (int *)&c->x86_vendor_id[0],
230 (int *)&c->x86_vendor_id[8],
231 (int *)&c->x86_vendor_id[4]);
233 get_cpu_vendor(c, 1);
235 c->x86 = 4;
236 if (c->cpuid_level >= 0x00000001) {
237 u32 junk, tfms, cap0, misc;
238 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
239 c->x86 = (tfms >> 8) & 15;
240 c->x86_model = (tfms >> 4) & 15;
241 if (c->x86 == 0xf)
242 c->x86 += (tfms >> 20) & 0xff;
243 if (c->x86 >= 0x6)
244 c->x86_model += ((tfms >> 16) & 0xF) << 4;
245 c->x86_mask = tfms & 15;
246 cap0 &= ~cleared_caps[0];
247 if (cap0 & (1<<19))
248 c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
249 c->x86_capability[0] = cap0; /* Added for Xen bootstrap */
250 }
251 }
253 void __cpuinit generic_identify(struct cpuinfo_x86 * c)
254 {
255 u32 tfms, xlvl;
257 if (have_cpuid_p()) {
258 /* Get vendor name */
259 cpuid(0x00000000, &c->cpuid_level,
260 (int *)&c->x86_vendor_id[0],
261 (int *)&c->x86_vendor_id[8],
262 (int *)&c->x86_vendor_id[4]);
264 get_cpu_vendor(c, 0);
265 /* Initialize the standard set of capabilities */
266 /* Note that the vendor-specific code below might override */
268 /* Intel-defined flags: level 0x00000001 */
269 if ( c->cpuid_level >= 0x00000001 ) {
270 u32 capability, excap, ebx;
271 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
272 c->x86_capability[0] = capability;
273 c->x86_capability[4] = excap;
274 c->x86 = (tfms >> 8) & 15;
275 c->x86_model = (tfms >> 4) & 15;
276 if (c->x86 == 0xf)
277 c->x86 += (tfms >> 20) & 0xff;
278 if (c->x86 >= 0x6)
279 c->x86_model += ((tfms >> 16) & 0xF) << 4;
280 c->x86_mask = tfms & 15;
281 if ( cpu_has(c, X86_FEATURE_CLFLSH) )
282 c->x86_clflush_size = ((ebx >> 8) & 0xff) * 8;
283 } else {
284 /* Have CPUID level 0 only - unheard of */
285 c->x86 = 4;
286 }
288 /* AMD-defined flags: level 0x80000001 */
289 xlvl = cpuid_eax(0x80000000);
290 if ( (xlvl & 0xffff0000) == 0x80000000 ) {
291 if ( xlvl >= 0x80000001 ) {
292 c->x86_capability[1] = cpuid_edx(0x80000001);
293 c->x86_capability[6] = cpuid_ecx(0x80000001);
294 }
295 if ( xlvl >= 0x80000004 )
296 get_model_name(c); /* Default name */
297 }
298 }
300 early_intel_workaround(c);
302 #ifdef CONFIG_X86_HT
303 phys_proc_id[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff;
304 #endif
305 }
307 static void __cpuinit squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
308 {
309 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) {
310 /* Disable processor serial number */
311 unsigned long lo,hi;
312 rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
313 lo |= 0x200000;
314 wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
315 printk(KERN_NOTICE "CPU serial number disabled.\n");
316 clear_bit(X86_FEATURE_PN, c->x86_capability);
318 /* Disabling the serial number may affect the cpuid level */
319 c->cpuid_level = cpuid_eax(0);
320 }
321 }
323 boolean_param("noserialnumber", disable_x86_serial_nr);
327 /*
328 * This does the hard work of actually picking apart the CPU stuff...
329 */
330 void __cpuinit identify_cpu(struct cpuinfo_x86 *c)
331 {
332 int i;
334 c->x86_cache_size = -1;
335 c->x86_vendor = X86_VENDOR_UNKNOWN;
336 c->cpuid_level = -1; /* CPUID not detected */
337 c->x86_model = c->x86_mask = 0; /* So far unknown... */
338 c->x86_vendor_id[0] = '\0'; /* Unset */
339 c->x86_model_id[0] = '\0'; /* Unset */
340 c->x86_max_cores = 1;
341 c->x86_num_siblings = 1;
342 c->x86_clflush_size = 0;
343 memset(&c->x86_capability, 0, sizeof c->x86_capability);
345 if (!have_cpuid_p()) {
346 /* First of all, decide if this is a 486 or higher */
347 /* It's a 486 if we can modify the AC flag */
348 if ( flag_is_changeable_p(X86_EFLAGS_AC) )
349 c->x86 = 4;
350 else
351 c->x86 = 3;
352 }
354 generic_identify(c);
356 #ifdef NOISY_CAPS
357 printk(KERN_DEBUG "CPU: After generic identify, caps:");
358 for (i = 0; i < NCAPINTS; i++)
359 printk(" %08x", c->x86_capability[i]);
360 printk("\n");
361 #endif
363 if (this_cpu->c_identify) {
364 this_cpu->c_identify(c);
366 #ifdef NOISY_CAPS
367 printk(KERN_DEBUG "CPU: After vendor identify, caps:");
368 for (i = 0; i < NCAPINTS; i++)
369 printk(" %08x", c->x86_capability[i]);
370 printk("\n");
371 #endif
372 }
374 /*
375 * Vendor-specific initialization. In this section we
376 * canonicalize the feature flags, meaning if there are
377 * features a certain CPU supports which CPUID doesn't
378 * tell us, CPUID claiming incorrect flags, or other bugs,
379 * we handle them here.
380 *
381 * At the end of this section, c->x86_capability better
382 * indicate the features this CPU genuinely supports!
383 */
384 if (this_cpu->c_init)
385 this_cpu->c_init(c);
387 /* Disable the PN if appropriate */
388 squash_the_stupid_serial_number(c);
390 /*
391 * The vendor-specific functions might have changed features. Now
392 * we do "generic changes."
393 */
395 /* TSC disabled? */
396 if ( tsc_disable )
397 clear_bit(X86_FEATURE_TSC, c->x86_capability);
399 /* FXSR disabled? */
400 if (disable_x86_fxsr) {
401 clear_bit(X86_FEATURE_FXSR, c->x86_capability);
402 clear_bit(X86_FEATURE_XMM, c->x86_capability);
403 }
405 if (disable_pse)
406 clear_bit(X86_FEATURE_PSE, c->x86_capability);
408 for (i = 0 ; i < NCAPINTS ; ++i)
409 c->x86_capability[i] &= ~cleared_caps[i];
411 /* If the model name is still unset, do table lookup. */
412 if ( !c->x86_model_id[0] ) {
413 char *p;
414 p = table_lookup_model(c);
415 if ( p )
416 safe_strcpy(c->x86_model_id, p);
417 else
418 /* Last resort... */
419 snprintf(c->x86_model_id, sizeof(c->x86_model_id),
420 "%02x/%02x", c->x86_vendor, c->x86_model);
421 }
423 /* Now the feature flags better reflect actual CPU features! */
425 #ifdef NOISY_CAPS
426 printk(KERN_DEBUG "CPU: After all inits, caps:");
427 for (i = 0; i < NCAPINTS; i++)
428 printk(" %08x", c->x86_capability[i]);
429 printk("\n");
430 #endif
432 /*
433 * On SMP, boot_cpu_data holds the common feature set between
434 * all CPUs; so make sure that we indicate which features are
435 * common between the CPUs. The first time this routine gets
436 * executed, c == &boot_cpu_data.
437 */
438 if ( c != &boot_cpu_data ) {
439 /* AND the already accumulated flags with these */
440 for ( i = 0 ; i < NCAPINTS ; i++ )
441 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
442 }
444 /* Init Machine Check Exception if available. */
445 mcheck_init(c);
447 #if 0
448 if (c == &boot_cpu_data)
449 sysenter_setup();
450 enable_sep_cpu();
451 #endif
453 if (c == &boot_cpu_data)
454 mtrr_bp_init();
455 else
456 mtrr_ap_init();
457 }
459 #ifdef CONFIG_X86_HT
460 /* cpuid returns the value latched in the HW at reset, not the APIC ID
461 * register's value. For any box whose BIOS changes APIC IDs, like
462 * clustered APIC systems, we must use hard_smp_processor_id.
463 *
464 * See Intel's IA-32 SW Dev's Manual Vol2 under CPUID.
465 */
466 static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
467 {
468 return hard_smp_processor_id() >> index_msb;
469 }
471 void __cpuinit detect_ht(struct cpuinfo_x86 *c)
472 {
473 u32 eax, ebx, ecx, edx;
474 int index_msb, core_bits;
475 int cpu = smp_processor_id();
477 cpuid(1, &eax, &ebx, &ecx, &edx);
479 c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0);
481 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
482 return;
484 c->x86_num_siblings = (ebx & 0xff0000) >> 16;
486 if (c->x86_num_siblings == 1) {
487 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
488 } else if (c->x86_num_siblings > 1 ) {
490 if (c->x86_num_siblings > NR_CPUS) {
491 printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", c->x86_num_siblings);
492 c->x86_num_siblings = 1;
493 return;
494 }
496 index_msb = get_count_order(c->x86_num_siblings);
497 phys_proc_id[cpu] = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
499 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
500 phys_proc_id[cpu]);
502 c->x86_num_siblings = c->x86_num_siblings / c->x86_max_cores;
504 index_msb = get_count_order(c->x86_num_siblings) ;
506 core_bits = get_count_order(c->x86_max_cores);
508 cpu_core_id[cpu] = phys_pkg_id((ebx >> 24) & 0xFF, index_msb) &
509 ((1 << core_bits) - 1);
511 if (c->x86_max_cores > 1)
512 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
513 cpu_core_id[cpu]);
514 }
515 }
516 #endif
518 void __cpuinit print_cpu_info(struct cpuinfo_x86 *c)
519 {
520 char *vendor = NULL;
522 if (c->x86_vendor < X86_VENDOR_NUM)
523 vendor = this_cpu->c_vendor;
524 else if (c->cpuid_level >= 0)
525 vendor = c->x86_vendor_id;
527 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
528 printk("%s ", vendor);
530 if (!c->x86_model_id[0])
531 printk("%d86", c->x86);
532 else
533 printk("%s", c->x86_model_id);
535 if (c->x86_mask || c->cpuid_level >= 0)
536 printk(" stepping %02x\n", c->x86_mask);
537 else
538 printk("\n");
539 }
541 cpumask_t cpu_initialized __cpuinitdata = CPU_MASK_NONE;
543 /* This is hacky. :)
544 * We're emulating future behavior.
545 * In the future, the cpu-specific init functions will be called implicitly
546 * via the magic of initcalls.
547 * They will insert themselves into the cpu_devs structure.
548 * Then, when cpu_init() is called, we can just iterate over that array.
549 */
551 extern int intel_cpu_init(void);
552 extern int cyrix_init_cpu(void);
553 extern int nsc_init_cpu(void);
554 extern int amd_init_cpu(void);
555 extern int centaur_init_cpu(void);
556 extern int transmeta_init_cpu(void);
558 void __init early_cpu_init(void)
559 {
560 intel_cpu_init();
561 amd_init_cpu();
562 #ifdef CONFIG_X86_32
563 cyrix_init_cpu();
564 nsc_init_cpu();
565 centaur_init_cpu();
566 transmeta_init_cpu();
567 #endif
568 early_cpu_detect();
569 }
570 /*
571 * cpu_init() initializes state that is per-CPU. Some data is already
572 * initialized (naturally) in the bootstrap process, such as the GDT
573 * and IDT. We reload them nevertheless, this function acts as a
574 * 'CPU state barrier', nothing should get across.
575 */
576 void __cpuinit cpu_init(void)
577 {
578 int cpu = smp_processor_id();
579 struct tss_struct *t = &init_tss[cpu];
580 struct desc_ptr gdt_desc = {
581 .base = (unsigned long)(this_cpu(gdt_table) - FIRST_RESERVED_GDT_ENTRY),
582 .limit = LAST_RESERVED_GDT_BYTE
583 };
585 if (cpu_test_and_set(cpu, cpu_initialized)) {
586 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
587 for (;;) local_irq_enable();
588 }
589 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
591 if (cpu_has_pat)
592 wrmsrl(MSR_IA32_CR_PAT, host_pat);
594 /* Install correct page table. */
595 write_ptbase(current);
597 asm volatile ( "lgdt %0" : : "m" (gdt_desc) );
599 /* No nested task. */
600 asm volatile ("pushf ; andw $0xbfff,(%"__OP"sp) ; popf" );
602 /* Ensure FPU gets initialised for each domain. */
603 stts();
605 /* Set up and load the per-CPU TSS and LDT. */
606 t->bitmap = IOBMP_INVALID_OFFSET;
607 #if defined(CONFIG_X86_32)
608 t->ss0 = __HYPERVISOR_DS;
609 t->esp0 = get_stack_bottom();
610 if ( supervisor_mode_kernel && cpu_has_sep )
611 wrmsr(MSR_IA32_SYSENTER_ESP, &t->esp1, 0);
612 #elif defined(CONFIG_X86_64)
613 /* Bottom-of-stack must be 16-byte aligned! */
614 BUG_ON((get_stack_bottom() & 15) != 0);
615 t->rsp0 = get_stack_bottom();
616 #endif
617 load_TR();
618 asm volatile ( "lldt %%ax" : : "a" (0) );
620 /* Clear all 6 debug registers: */
621 #define CD(register) asm volatile ( "mov %0,%%db" #register : : "r"(0UL) );
622 CD(0); CD(1); CD(2); CD(3); /* no db4 and db5 */; CD(6); CD(7);
623 #undef CD
624 }
626 #ifdef CONFIG_HOTPLUG_CPU
627 void __cpuinit cpu_uninit(void)
628 {
629 int cpu = raw_smp_processor_id();
630 cpu_clear(cpu, cpu_initialized);
631 }
632 #endif