ia64/xen-unstable

view xen/arch/x86/apic.c @ 18806:ed8524f4a044

x86: Re-initialise HPET on resume from S3

Signed-off-by: Guanqun Lu <guanqun.lu@intel.com>
Signed-off-by: Kevin Tian <kevin.tian@intel.com>
Signed-off-by: Keir Fraser <keir.fraser@citrix.com>
author Keir Fraser <keir.fraser@citrix.com>
date Tue Nov 18 15:55:14 2008 +0000 (2008-11-18)
parents 9fd00ff95068
children 4d5203f95498
line source
1 /*
2 * based on linux-2.6.17.13/arch/i386/kernel/apic.c
3 *
4 * Local APIC handling, local APIC timers
5 *
6 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
10 * thanks to Eric Gilmore
11 * and Rolf G. Tews
12 * for testing these extensively.
13 * Maciej W. Rozycki : Various updates and fixes.
14 * Mikael Pettersson : Power Management for UP-APIC.
15 * Pavel Machek and
16 * Mikael Pettersson : PM converted to driver model.
17 */
19 #include <xen/config.h>
20 #include <xen/perfc.h>
21 #include <xen/errno.h>
22 #include <xen/init.h>
23 #include <xen/mm.h>
24 #include <xen/sched.h>
25 #include <xen/irq.h>
26 #include <xen/delay.h>
27 #include <xen/smp.h>
28 #include <xen/softirq.h>
29 #include <asm/mc146818rtc.h>
30 #include <asm/msr.h>
31 #include <asm/atomic.h>
32 #include <asm/mpspec.h>
33 #include <asm/flushtlb.h>
34 #include <asm/hardirq.h>
35 #include <asm/apic.h>
36 #include <asm/io_apic.h>
37 #include <mach_apic.h>
38 #include <io_ports.h>
40 /*
41 * Knob to control our willingness to enable the local APIC.
42 */
43 int enable_local_apic __initdata = 0; /* -1=force-disable, +1=force-enable */
45 /*
46 * Debug level
47 */
48 int apic_verbosity;
50 int x2apic_enabled __read_mostly = 0;
53 static void apic_pm_activate(void);
55 int modern_apic(void)
56 {
57 unsigned int lvr, version;
58 /* AMD systems use old APIC versions, so check the CPU */
59 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
60 boot_cpu_data.x86 >= 0xf)
61 return 1;
62 lvr = apic_read(APIC_LVR);
63 version = GET_APIC_VERSION(lvr);
64 return version >= 0x14;
65 }
67 /*
68 * 'what should we do if we get a hw irq event on an illegal vector'.
69 * each architecture has to answer this themselves.
70 */
71 void ack_bad_irq(unsigned int irq)
72 {
73 printk("unexpected IRQ trap at vector %02x\n", irq);
74 /*
75 * Currently unexpected vectors happen only on SMP and APIC.
76 * We _must_ ack these because every local APIC has only N
77 * irq slots per priority level, and a 'hanging, unacked' IRQ
78 * holds up an irq slot - in excessive cases (when multiple
79 * unexpected vectors occur) that might lock up the APIC
80 * completely.
81 * But only ack when the APIC is enabled -AK
82 */
83 if (cpu_has_apic)
84 ack_APIC_irq();
85 }
87 void __init apic_intr_init(void)
88 {
89 #ifdef CONFIG_SMP
90 smp_intr_init();
91 #endif
92 /* self generated IPI for local APIC timer */
93 set_intr_gate(LOCAL_TIMER_VECTOR, apic_timer_interrupt);
95 /* IPI vectors for APIC spurious and error interrupts */
96 set_intr_gate(SPURIOUS_APIC_VECTOR, spurious_interrupt);
97 set_intr_gate(ERROR_APIC_VECTOR, error_interrupt);
99 /* Performance Counters Interrupt */
100 set_intr_gate(PMU_APIC_VECTOR, pmu_apic_interrupt);
102 /* thermal monitor LVT interrupt */
103 #ifdef CONFIG_X86_MCE_P4THERMAL
104 set_intr_gate(THERMAL_APIC_VECTOR, thermal_interrupt);
105 #endif
106 }
108 /* Using APIC to generate smp_local_timer_interrupt? */
109 int using_apic_timer = 0;
111 static int enabled_via_apicbase;
113 void enable_NMI_through_LVT0 (void * dummy)
114 {
115 unsigned int v, ver;
117 ver = apic_read(APIC_LVR);
118 ver = GET_APIC_VERSION(ver);
119 v = APIC_DM_NMI; /* unmask and set to NMI */
120 if (!APIC_INTEGRATED(ver)) /* 82489DX */
121 v |= APIC_LVT_LEVEL_TRIGGER;
122 apic_write_around(APIC_LVT0, v);
123 }
125 int get_physical_broadcast(void)
126 {
127 if (modern_apic())
128 return 0xff;
129 else
130 return 0xf;
131 }
133 int get_maxlvt(void)
134 {
135 unsigned int v, ver, maxlvt;
137 v = apic_read(APIC_LVR);
138 ver = GET_APIC_VERSION(v);
139 /* 82489DXs do not report # of LVT entries. */
140 maxlvt = APIC_INTEGRATED(ver) ? GET_APIC_MAXLVT(v) : 2;
141 return maxlvt;
142 }
144 void clear_local_APIC(void)
145 {
146 int maxlvt;
147 unsigned long v;
149 maxlvt = get_maxlvt();
151 /*
152 * Masking an LVT entry on a P6 can trigger a local APIC error
153 * if the vector is zero. Mask LVTERR first to prevent this.
154 */
155 if (maxlvt >= 3) {
156 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
157 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
158 }
159 /*
160 * Careful: we have to set masks only first to deassert
161 * any level-triggered sources.
162 */
163 v = apic_read(APIC_LVTT);
164 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
165 v = apic_read(APIC_LVT0);
166 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
167 v = apic_read(APIC_LVT1);
168 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
169 if (maxlvt >= 4) {
170 v = apic_read(APIC_LVTPC);
171 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
172 }
174 /* lets not touch this if we didn't frob it */
175 #ifdef CONFIG_X86_MCE_P4THERMAL
176 if (maxlvt >= 5) {
177 v = apic_read(APIC_LVTTHMR);
178 apic_write_around(APIC_LVTTHMR, v | APIC_LVT_MASKED);
179 }
180 #endif
181 /*
182 * Clean APIC state for other OSs:
183 */
184 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
185 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
186 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
187 if (maxlvt >= 3)
188 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
189 if (maxlvt >= 4)
190 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
192 #ifdef CONFIG_X86_MCE_P4THERMAL
193 if (maxlvt >= 5)
194 apic_write_around(APIC_LVTTHMR, APIC_LVT_MASKED);
195 #endif
196 v = GET_APIC_VERSION(apic_read(APIC_LVR));
197 if (APIC_INTEGRATED(v)) { /* !82489DX */
198 if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
199 apic_write(APIC_ESR, 0);
200 apic_read(APIC_ESR);
201 }
202 }
204 void __init connect_bsp_APIC(void)
205 {
206 if (pic_mode) {
207 /*
208 * Do not trust the local APIC being empty at bootup.
209 */
210 clear_local_APIC();
211 /*
212 * PIC mode, enable APIC mode in the IMCR, i.e.
213 * connect BSP's local APIC to INT and NMI lines.
214 */
215 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
216 "enabling APIC mode.\n");
217 outb(0x70, 0x22);
218 outb(0x01, 0x23);
219 }
220 enable_apic_mode();
221 }
223 void disconnect_bsp_APIC(int virt_wire_setup)
224 {
225 if (pic_mode) {
226 /*
227 * Put the board back into PIC mode (has an effect
228 * only on certain older boards). Note that APIC
229 * interrupts, including IPIs, won't work beyond
230 * this point! The only exception are INIT IPIs.
231 */
232 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
233 "entering PIC mode.\n");
234 outb(0x70, 0x22);
235 outb(0x00, 0x23);
236 }
237 else {
238 /* Go back to Virtual Wire compatibility mode */
239 unsigned long value;
241 /* For the spurious interrupt use vector F, and enable it */
242 value = apic_read(APIC_SPIV);
243 value &= ~APIC_VECTOR_MASK;
244 value |= APIC_SPIV_APIC_ENABLED;
245 value |= 0xf;
246 apic_write_around(APIC_SPIV, value);
248 if (!virt_wire_setup) {
249 /* For LVT0 make it edge triggered, active high, external and enabled */
250 value = apic_read(APIC_LVT0);
251 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
252 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
253 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED );
254 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
255 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
256 apic_write_around(APIC_LVT0, value);
257 }
258 else {
259 /* Disable LVT0 */
260 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
261 }
263 /* For LVT1 make it edge triggered, active high, nmi and enabled */
264 value = apic_read(APIC_LVT1);
265 value &= ~(
266 APIC_MODE_MASK | APIC_SEND_PENDING |
267 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
268 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
269 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
270 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
271 apic_write_around(APIC_LVT1, value);
272 }
273 }
275 void disable_local_APIC(void)
276 {
277 unsigned long value;
279 clear_local_APIC();
281 /*
282 * Disable APIC (implies clearing of registers
283 * for 82489DX!).
284 */
285 value = apic_read(APIC_SPIV);
286 value &= ~APIC_SPIV_APIC_ENABLED;
287 apic_write_around(APIC_SPIV, value);
289 if (enabled_via_apicbase) {
290 unsigned int l, h;
291 rdmsr(MSR_IA32_APICBASE, l, h);
292 l &= ~MSR_IA32_APICBASE_ENABLE;
293 wrmsr(MSR_IA32_APICBASE, l, h);
294 }
295 }
297 /*
298 * This is to verify that we're looking at a real local APIC.
299 * Check these against your board if the CPUs aren't getting
300 * started for no apparent reason.
301 */
302 int __init verify_local_APIC(void)
303 {
304 unsigned int reg0, reg1;
306 /*
307 * The version register is read-only in a real APIC.
308 */
309 reg0 = apic_read(APIC_LVR);
310 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
312 /* We don't try writing LVR in x2APIC mode since that incurs #GP. */
313 if ( !x2apic_enabled )
314 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
315 reg1 = apic_read(APIC_LVR);
316 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
318 /*
319 * The two version reads above should print the same
320 * numbers. If the second one is different, then we
321 * poke at a non-APIC.
322 */
323 if (reg1 != reg0)
324 return 0;
326 /*
327 * Check if the version looks reasonably.
328 */
329 reg1 = GET_APIC_VERSION(reg0);
330 if (reg1 == 0x00 || reg1 == 0xff)
331 return 0;
332 reg1 = get_maxlvt();
333 if (reg1 < 0x02 || reg1 == 0xff)
334 return 0;
336 /*
337 * The ID register is read/write in a real APIC.
338 */
339 reg0 = apic_read(APIC_ID);
340 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
342 /*
343 * The next two are just to see if we have sane values.
344 * They're only really relevant if we're in Virtual Wire
345 * compatibility mode, but most boxes are anymore.
346 */
347 reg0 = apic_read(APIC_LVT0);
348 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
349 reg1 = apic_read(APIC_LVT1);
350 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
352 return 1;
353 }
355 void __init sync_Arb_IDs(void)
356 {
357 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1
358 And not needed on AMD */
359 if (modern_apic())
360 return;
361 /*
362 * Wait for idle.
363 */
364 apic_wait_icr_idle();
366 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
367 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
368 | APIC_DM_INIT);
369 }
371 extern void __error_in_apic_c (void);
373 /*
374 * An initial setup of the virtual wire mode.
375 */
376 void __init init_bsp_APIC(void)
377 {
378 unsigned long value, ver;
380 /*
381 * Don't do the setup now if we have a SMP BIOS as the
382 * through-I/O-APIC virtual wire mode might be active.
383 */
384 if (smp_found_config || !cpu_has_apic)
385 return;
387 value = apic_read(APIC_LVR);
388 ver = GET_APIC_VERSION(value);
390 /*
391 * Do not trust the local APIC being empty at bootup.
392 */
393 clear_local_APIC();
395 /*
396 * Enable APIC.
397 */
398 value = apic_read(APIC_SPIV);
399 value &= ~APIC_VECTOR_MASK;
400 value |= APIC_SPIV_APIC_ENABLED;
402 /* This bit is reserved on P4/Xeon and should be cleared */
403 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 15))
404 value &= ~APIC_SPIV_FOCUS_DISABLED;
405 else
406 value |= APIC_SPIV_FOCUS_DISABLED;
407 value |= SPURIOUS_APIC_VECTOR;
408 apic_write_around(APIC_SPIV, value);
410 /*
411 * Set up the virtual wire mode.
412 */
413 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
414 value = APIC_DM_NMI;
415 if (!APIC_INTEGRATED(ver)) /* 82489DX */
416 value |= APIC_LVT_LEVEL_TRIGGER;
417 apic_write_around(APIC_LVT1, value);
418 }
420 void __devinit setup_local_APIC(void)
421 {
422 unsigned long oldvalue, value, ver, maxlvt;
423 int i, j;
425 /* Pound the ESR really hard over the head with a big hammer - mbligh */
426 if (esr_disable) {
427 apic_write(APIC_ESR, 0);
428 apic_write(APIC_ESR, 0);
429 apic_write(APIC_ESR, 0);
430 apic_write(APIC_ESR, 0);
431 }
433 value = apic_read(APIC_LVR);
434 ver = GET_APIC_VERSION(value);
436 if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
437 __error_in_apic_c();
439 /*
440 * Double-check whether this APIC is really registered.
441 */
442 if (!apic_id_registered())
443 BUG();
445 /*
446 * Intel recommends to set DFR, LDR and TPR before enabling
447 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
448 * document number 292116). So here it goes...
449 */
450 init_apic_ldr();
452 /*
453 * Set Task Priority to 'accept all'. We never change this
454 * later on.
455 */
456 value = apic_read(APIC_TASKPRI);
457 value &= ~APIC_TPRI_MASK;
458 apic_write_around(APIC_TASKPRI, value);
460 /*
461 * After a crash, we no longer service the interrupts and a pending
462 * interrupt from previous kernel might still have ISR bit set.
463 *
464 * Most probably by now CPU has serviced that pending interrupt and
465 * it might not have done the ack_APIC_irq() because it thought,
466 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
467 * does not clear the ISR bit and cpu thinks it has already serivced
468 * the interrupt. Hence a vector might get locked. It was noticed
469 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
470 */
471 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
472 value = apic_read(APIC_ISR + i*0x10);
473 for (j = 31; j >= 0; j--) {
474 if (value & (1<<j))
475 ack_APIC_irq();
476 }
477 }
479 /*
480 * Now that we are all set up, enable the APIC
481 */
482 value = apic_read(APIC_SPIV);
483 value &= ~APIC_VECTOR_MASK;
484 /*
485 * Enable APIC
486 */
487 value |= APIC_SPIV_APIC_ENABLED;
489 /*
490 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
491 * certain networking cards. If high frequency interrupts are
492 * happening on a particular IOAPIC pin, plus the IOAPIC routing
493 * entry is masked/unmasked at a high rate as well then sooner or
494 * later IOAPIC line gets 'stuck', no more interrupts are received
495 * from the device. If focus CPU is disabled then the hang goes
496 * away, oh well :-(
497 *
498 * [ This bug can be reproduced easily with a level-triggered
499 * PCI Ne2000 networking cards and PII/PIII processors, dual
500 * BX chipset. ]
501 */
502 /*
503 * Actually disabling the focus CPU check just makes the hang less
504 * frequent as it makes the interrupt distributon model be more
505 * like LRU than MRU (the short-term load is more even across CPUs).
506 * See also the comment in end_level_ioapic_irq(). --macro
507 */
508 #if 1
509 /* Enable focus processor (bit==0) */
510 value &= ~APIC_SPIV_FOCUS_DISABLED;
511 #else
512 /* Disable focus processor (bit==1) */
513 value |= APIC_SPIV_FOCUS_DISABLED;
514 #endif
515 /*
516 * Set spurious IRQ vector
517 */
518 value |= SPURIOUS_APIC_VECTOR;
519 apic_write_around(APIC_SPIV, value);
521 /*
522 * Set up LVT0, LVT1:
523 *
524 * set up through-local-APIC on the BP's LINT0. This is not
525 * strictly necessery in pure symmetric-IO mode, but sometimes
526 * we delegate interrupts to the 8259A.
527 */
528 /*
529 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
530 */
531 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
532 if (!smp_processor_id() && (pic_mode || !value)) {
533 value = APIC_DM_EXTINT;
534 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
535 smp_processor_id());
536 } else {
537 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
538 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
539 smp_processor_id());
540 }
541 apic_write_around(APIC_LVT0, value);
543 /*
544 * only the BP should see the LINT1 NMI signal, obviously.
545 */
546 if (!smp_processor_id())
547 value = APIC_DM_NMI;
548 else
549 value = APIC_DM_NMI | APIC_LVT_MASKED;
550 if (!APIC_INTEGRATED(ver)) /* 82489DX */
551 value |= APIC_LVT_LEVEL_TRIGGER;
552 apic_write_around(APIC_LVT1, value);
554 if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */
555 maxlvt = get_maxlvt();
556 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
557 apic_write(APIC_ESR, 0);
558 oldvalue = apic_read(APIC_ESR);
560 value = ERROR_APIC_VECTOR; // enables sending errors
561 apic_write_around(APIC_LVTERR, value);
562 /*
563 * spec says clear errors after enabling vector.
564 */
565 if (maxlvt > 3)
566 apic_write(APIC_ESR, 0);
567 value = apic_read(APIC_ESR);
568 if (value != oldvalue)
569 apic_printk(APIC_VERBOSE, "ESR value before enabling "
570 "vector: 0x%08lx after: 0x%08lx\n",
571 oldvalue, value);
572 } else {
573 if (esr_disable)
574 /*
575 * Something untraceble is creating bad interrupts on
576 * secondary quads ... for the moment, just leave the
577 * ESR disabled - we can't do anything useful with the
578 * errors anyway - mbligh
579 */
580 printk("Leaving ESR disabled.\n");
581 else
582 printk("No ESR for 82489DX.\n");
583 }
585 if (nmi_watchdog == NMI_LOCAL_APIC)
586 setup_apic_nmi_watchdog();
587 apic_pm_activate();
588 }
590 static struct {
591 int active;
592 /* r/w apic fields */
593 unsigned int apic_id;
594 unsigned int apic_taskpri;
595 unsigned int apic_ldr;
596 unsigned int apic_dfr;
597 unsigned int apic_spiv;
598 unsigned int apic_lvtt;
599 unsigned int apic_lvtpc;
600 unsigned int apic_lvt0;
601 unsigned int apic_lvt1;
602 unsigned int apic_lvterr;
603 unsigned int apic_tmict;
604 unsigned int apic_tdcr;
605 unsigned int apic_thmr;
606 } apic_pm_state;
608 int lapic_suspend(void)
609 {
610 unsigned long flags;
612 if (!apic_pm_state.active)
613 return 0;
615 apic_pm_state.apic_id = apic_read(APIC_ID);
616 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
617 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
618 if ( !x2apic_enabled )
619 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
620 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
621 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
622 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
623 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
624 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
625 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
626 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
627 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
628 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
630 local_irq_save(flags);
631 disable_local_APIC();
632 local_irq_restore(flags);
633 return 0;
634 }
636 int lapic_resume(void)
637 {
638 unsigned int l, h;
639 unsigned long flags;
641 if (!apic_pm_state.active)
642 return 0;
644 local_irq_save(flags);
646 /*
647 * Make sure the APICBASE points to the right address
648 *
649 * FIXME! This will be wrong if we ever support suspend on
650 * SMP! We'll need to do this as part of the CPU restore!
651 */
652 if ( !x2apic_enabled )
653 {
654 rdmsr(MSR_IA32_APICBASE, l, h);
655 l &= ~MSR_IA32_APICBASE_BASE;
656 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
657 wrmsr(MSR_IA32_APICBASE, l, h);
658 }
659 else
660 enable_x2apic();
662 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
663 apic_write(APIC_ID, apic_pm_state.apic_id);
664 if ( !x2apic_enabled )
665 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
666 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
667 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
668 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
669 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
670 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
671 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
672 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
673 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
674 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
675 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
676 apic_write(APIC_ESR, 0);
677 apic_read(APIC_ESR);
678 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
679 apic_write(APIC_ESR, 0);
680 apic_read(APIC_ESR);
681 local_irq_restore(flags);
682 return 0;
683 }
686 /*
687 * If Linux enabled the LAPIC against the BIOS default
688 * disable it down before re-entering the BIOS on shutdown.
689 * Otherwise the BIOS may get confused and not power-off.
690 * Additionally clear all LVT entries before disable_local_APIC
691 * for the case where Linux didn't enable the LAPIC.
692 */
693 void lapic_shutdown(void)
694 {
695 unsigned long flags;
697 if (!cpu_has_apic)
698 return;
700 local_irq_save(flags);
701 clear_local_APIC();
703 if (enabled_via_apicbase)
704 disable_local_APIC();
706 local_irq_restore(flags);
707 }
709 static void apic_pm_activate(void)
710 {
711 apic_pm_state.active = 1;
712 }
714 /*
715 * Detect and enable local APICs on non-SMP boards.
716 * Original code written by Keir Fraser.
717 */
719 static void __init lapic_disable(char *str)
720 {
721 enable_local_apic = -1;
722 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
723 }
724 custom_param("nolapic", lapic_disable);
726 static void __init lapic_enable(char *str)
727 {
728 enable_local_apic = 1;
729 }
730 custom_param("lapic", lapic_enable);
732 static void __init apic_set_verbosity(char *str)
733 {
734 if (strcmp("debug", str) == 0)
735 apic_verbosity = APIC_DEBUG;
736 else if (strcmp("verbose", str) == 0)
737 apic_verbosity = APIC_VERBOSE;
738 else
739 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
740 " use apic_verbosity=verbose or apic_verbosity=debug", str);
741 }
742 custom_param("apic_verbosity", apic_set_verbosity);
744 static int __init detect_init_APIC (void)
745 {
746 u32 h, l, features;
748 /* Disabled by kernel option? */
749 if (enable_local_apic < 0)
750 return -1;
752 switch (boot_cpu_data.x86_vendor) {
753 case X86_VENDOR_AMD:
754 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
755 (boot_cpu_data.x86 >= 15 && boot_cpu_data.x86 <= 17))
756 break;
757 goto no_apic;
758 case X86_VENDOR_INTEL:
759 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
760 (boot_cpu_data.x86 == 5 && cpu_has_apic))
761 break;
762 goto no_apic;
763 default:
764 goto no_apic;
765 }
767 if (!cpu_has_apic) {
768 /*
769 * Over-ride BIOS and try to enable the local
770 * APIC only if "lapic" specified.
771 */
772 if (enable_local_apic <= 0) {
773 printk("Local APIC disabled by BIOS -- "
774 "you can enable it with \"lapic\"\n");
775 return -1;
776 }
777 /*
778 * Some BIOSes disable the local APIC in the
779 * APIC_BASE MSR. This can only be done in
780 * software for Intel P6 or later and AMD K7
781 * (Model > 1) or later.
782 */
783 rdmsr(MSR_IA32_APICBASE, l, h);
784 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
785 printk("Local APIC disabled by BIOS -- reenabling.\n");
786 l &= ~MSR_IA32_APICBASE_BASE;
787 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
788 wrmsr(MSR_IA32_APICBASE, l, h);
789 enabled_via_apicbase = 1;
790 }
791 }
792 /*
793 * The APIC feature bit should now be enabled
794 * in `cpuid'
795 */
796 features = cpuid_edx(1);
797 if (!(features & (1 << X86_FEATURE_APIC))) {
798 printk("Could not enable APIC!\n");
799 return -1;
800 }
802 set_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
803 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
805 /* The BIOS may have set up the APIC at some other address */
806 rdmsr(MSR_IA32_APICBASE, l, h);
807 if (l & MSR_IA32_APICBASE_ENABLE)
808 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
810 if (nmi_watchdog != NMI_NONE)
811 nmi_watchdog = NMI_LOCAL_APIC;
813 printk("Found and enabled local APIC!\n");
815 apic_pm_activate();
817 return 0;
819 no_apic:
820 printk("No local APIC present or hardware disabled\n");
821 return -1;
822 }
824 void enable_x2apic(void)
825 {
826 u32 lo, hi;
828 rdmsr(MSR_IA32_APICBASE, lo, hi);
829 if ( !(lo & MSR_IA32_APICBASE_EXTD) )
830 {
831 lo |= MSR_IA32_APICBASE_ENABLE | MSR_IA32_APICBASE_EXTD;
832 wrmsr(MSR_IA32_APICBASE, lo, 0);
833 printk("x2APIC mode enabled.\n");
834 }
835 else
836 printk("x2APIC mode enabled by BIOS.\n");
838 x2apic_enabled = 1;
839 }
841 void __init init_apic_mappings(void)
842 {
843 unsigned long apic_phys;
845 if ( x2apic_enabled )
846 goto __next;
847 /*
848 * If no local APIC can be found then set up a fake all
849 * zeroes page to simulate the local APIC and another
850 * one for the IO-APIC.
851 */
852 if (!smp_found_config && detect_init_APIC()) {
853 apic_phys = __pa(alloc_xenheap_page());
854 clear_page(__va(apic_phys));
855 } else
856 apic_phys = mp_lapic_addr;
858 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
859 apic_printk(APIC_VERBOSE, "mapped APIC to %08lx (%08lx)\n", APIC_BASE,
860 apic_phys);
862 __next:
863 /*
864 * Fetch the APIC ID of the BSP in case we have a
865 * default configuration (or the MP table is broken).
866 */
867 if (boot_cpu_physical_apicid == -1U)
868 boot_cpu_physical_apicid = get_apic_id();
870 #ifdef CONFIG_X86_IO_APIC
871 {
872 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
873 int i;
875 for (i = 0; i < nr_ioapics; i++) {
876 if (smp_found_config) {
877 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
878 if (!ioapic_phys) {
879 printk(KERN_ERR
880 "WARNING: bogus zero IO-APIC "
881 "address found in MPTABLE, "
882 "disabling IO/APIC support!\n");
883 smp_found_config = 0;
884 skip_ioapic_setup = 1;
885 goto fake_ioapic_page;
886 }
887 } else {
888 fake_ioapic_page:
889 ioapic_phys = __pa(alloc_xenheap_page());
890 clear_page(__va(ioapic_phys));
891 }
892 set_fixmap_nocache(idx, ioapic_phys);
893 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
894 __fix_to_virt(idx), ioapic_phys);
895 idx++;
896 }
897 }
898 #endif
899 }
901 /*****************************************************************************
902 * APIC calibration
903 *
904 * The APIC is programmed in bus cycles.
905 * Timeout values should specified in real time units.
906 * The "cheapest" time source is the cyclecounter.
907 *
908 * Thus, we need a mappings from: bus cycles <- cycle counter <- system time
909 *
910 * The calibration is currently a bit shoddy since it requires the external
911 * timer chip to generate periodic timer interupts.
912 *****************************************************************************/
914 /* used for system time scaling */
915 static unsigned long bus_freq; /* KAF: pointer-size avoids compile warns. */
916 static u32 bus_cycle; /* length of one bus cycle in pico-seconds */
917 static u32 bus_scale; /* scaling factor convert ns to bus cycles */
919 /*
920 * The timer chip is already set up at HZ interrupts per second here,
921 * but we do not accept timer interrupts yet. We only allow the BP
922 * to calibrate.
923 */
924 static unsigned int __init get_8254_timer_count(void)
925 {
926 /*extern spinlock_t i8253_lock;*/
927 /*unsigned long flags;*/
929 unsigned int count;
931 /*spin_lock_irqsave(&i8253_lock, flags);*/
933 outb_p(0x00, PIT_MODE);
934 count = inb_p(PIT_CH0);
935 count |= inb_p(PIT_CH0) << 8;
937 /*spin_unlock_irqrestore(&i8253_lock, flags);*/
939 return count;
940 }
942 /* next tick in 8254 can be caught by catching timer wraparound */
943 static void __init wait_8254_wraparound(void)
944 {
945 unsigned int curr_count, prev_count;
947 curr_count = get_8254_timer_count();
948 do {
949 prev_count = curr_count;
950 curr_count = get_8254_timer_count();
952 /* workaround for broken Mercury/Neptune */
953 if (prev_count >= curr_count + 0x100)
954 curr_count = get_8254_timer_count();
956 } while (prev_count >= curr_count);
957 }
959 /*
960 * Default initialization for 8254 timers. If we use other timers like HPET,
961 * we override this later
962 */
963 void (*wait_timer_tick)(void) __initdata = wait_8254_wraparound;
965 /*
966 * This function sets up the local APIC timer, with a timeout of
967 * 'clocks' APIC bus clock. During calibration we actually call
968 * this function twice on the boot CPU, once with a bogus timeout
969 * value, second time for real. The other (noncalibrating) CPUs
970 * call this function only once, with the real, calibrated value.
971 *
972 * We do reads before writes even if unnecessary, to get around the
973 * P5 APIC double write bug.
974 */
976 #define APIC_DIVISOR 1
978 void __setup_APIC_LVTT(unsigned int clocks)
979 {
980 unsigned int lvtt_value, tmp_value, ver;
982 ver = GET_APIC_VERSION(apic_read(APIC_LVR));
983 /* NB. Xen uses local APIC timer in one-shot mode. */
984 lvtt_value = /*APIC_LVT_TIMER_PERIODIC |*/ LOCAL_TIMER_VECTOR;
985 if (!APIC_INTEGRATED(ver))
986 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
987 apic_write_around(APIC_LVTT, lvtt_value);
989 tmp_value = apic_read(APIC_TDCR);
990 apic_write_around(APIC_TDCR, (tmp_value | APIC_TDR_DIV_1));
992 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
993 }
995 static void __devinit setup_APIC_timer(unsigned int clocks)
996 {
997 unsigned long flags;
998 local_irq_save(flags);
999 __setup_APIC_LVTT(clocks);
1000 local_irq_restore(flags);
1003 /*
1004 * In this function we calibrate APIC bus clocks to the external
1005 * timer. Unfortunately we cannot use jiffies and the timer irq
1006 * to calibrate, since some later bootup code depends on getting
1007 * the first irq? Ugh.
1009 * We want to do the calibration only once since we
1010 * want to have local timer irqs syncron. CPUs connected
1011 * by the same APIC bus have the very same bus frequency.
1012 * And we want to have irqs off anyways, no accidental
1013 * APIC irq that way.
1014 */
1016 int __init calibrate_APIC_clock(void)
1018 unsigned long long t1 = 0, t2 = 0;
1019 long tt1, tt2;
1020 long result;
1021 int i;
1022 const int LOOPS = HZ/10;
1024 apic_printk(APIC_VERBOSE, "calibrating APIC timer ...\n");
1026 /*
1027 * Put whatever arbitrary (but long enough) timeout
1028 * value into the APIC clock, we just want to get the
1029 * counter running for calibration.
1030 */
1031 __setup_APIC_LVTT(1000000000);
1033 /*
1034 * The timer chip counts down to zero. Let's wait
1035 * for a wraparound to start exact measurement:
1036 * (the current tick might have been already half done)
1037 */
1038 wait_timer_tick();
1040 /*
1041 * We wrapped around just now. Let's start:
1042 */
1043 if (cpu_has_tsc)
1044 rdtscll(t1);
1045 tt1 = apic_read(APIC_TMCCT);
1047 /*
1048 * Let's wait LOOPS wraprounds:
1049 */
1050 for (i = 0; i < LOOPS; i++)
1051 wait_timer_tick();
1053 tt2 = apic_read(APIC_TMCCT);
1054 if (cpu_has_tsc)
1055 rdtscll(t2);
1057 /*
1058 * The APIC bus clock counter is 32 bits only, it
1059 * might have overflown, but note that we use signed
1060 * longs, thus no extra care needed.
1062 * underflown to be exact, as the timer counts down ;)
1063 */
1065 result = (tt1-tt2)*APIC_DIVISOR/LOOPS;
1067 if (cpu_has_tsc)
1068 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
1069 "%ld.%04ld MHz.\n",
1070 ((long)(t2-t1)/LOOPS)/(1000000/HZ),
1071 ((long)(t2-t1)/LOOPS)%(1000000/HZ));
1073 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
1074 "%ld.%04ld MHz.\n",
1075 result/(1000000/HZ),
1076 result%(1000000/HZ));
1078 /* set up multipliers for accurate timer code */
1079 bus_freq = result*HZ;
1080 bus_cycle = (u32) (1000000000000LL/bus_freq); /* in pico seconds */
1081 bus_scale = (1000*262144)/bus_cycle;
1083 apic_printk(APIC_VERBOSE, "..... bus_scale = 0x%08X\n", bus_scale);
1084 /* reset APIC to zero timeout value */
1085 __setup_APIC_LVTT(0);
1087 return result;
1090 u32 get_apic_bus_cycle(void)
1092 return bus_cycle;
1095 static unsigned int calibration_result;
1097 void __init setup_boot_APIC_clock(void)
1099 unsigned long flags;
1100 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n");
1101 using_apic_timer = 1;
1103 local_irq_save(flags);
1105 calibration_result = calibrate_APIC_clock();
1106 /*
1107 * Now set up the timer for real.
1108 */
1109 setup_APIC_timer(calibration_result);
1111 local_irq_restore(flags);
1114 void __devinit setup_secondary_APIC_clock(void)
1116 setup_APIC_timer(calibration_result);
1119 void disable_APIC_timer(void)
1121 if (using_apic_timer) {
1122 unsigned long v;
1124 v = apic_read(APIC_LVTT);
1125 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
1129 void enable_APIC_timer(void)
1131 if (using_apic_timer) {
1132 unsigned long v;
1134 v = apic_read(APIC_LVTT);
1135 apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED);
1139 #undef APIC_DIVISOR
1141 /*
1142 * reprogram the APIC timer. Timeoutvalue is in ns from start of boot
1143 * returns 1 on success
1144 * returns 0 if the timeout value is too small or in the past.
1145 */
1146 int reprogram_timer(s_time_t timeout)
1148 s_time_t now;
1149 s_time_t expire;
1150 u64 apic_tmict;
1152 /*
1153 * If we don't have local APIC then we just poll the timer list off the
1154 * PIT interrupt.
1155 */
1156 if ( !cpu_has_apic )
1157 return 1;
1159 /*
1160 * We use this value because we don't trust zero (we think it may just
1161 * cause an immediate interrupt). At least this is guaranteed to hold it
1162 * off for ages (esp. since the clock ticks on bus clock, not cpu clock!).
1163 */
1164 if ( timeout == 0 )
1166 apic_tmict = 0xffffffff;
1167 goto reprogram;
1170 now = NOW();
1171 expire = timeout - now; /* value from now */
1173 if ( expire <= 0 )
1175 Dprintk("APICT[%02d] Timeout in the past 0x%08X%08X > 0x%08X%08X\n",
1176 smp_processor_id(), (u32)(now>>32),
1177 (u32)now, (u32)(timeout>>32),(u32)timeout);
1178 return 0;
1181 /* conversion to bus units */
1182 apic_tmict = (((u64)bus_scale) * expire)>>18;
1184 if ( apic_tmict >= 0xffffffff )
1186 Dprintk("APICT[%02d] Timeout value too large\n", smp_processor_id());
1187 apic_tmict = 0xffffffff;
1190 if ( apic_tmict == 0 )
1192 Dprintk("APICT[%02d] timeout value too small\n", smp_processor_id());
1193 return 0;
1196 reprogram:
1197 /* Program the timer. */
1198 apic_write(APIC_TMICT, (unsigned long)apic_tmict);
1200 return 1;
1203 fastcall void smp_apic_timer_interrupt(struct cpu_user_regs * regs)
1205 ack_APIC_irq();
1206 perfc_incr(apic_timer);
1207 raise_softirq(TIMER_SOFTIRQ);
1210 /*
1211 * This interrupt should _never_ happen with our APIC/SMP architecture
1212 */
1213 fastcall void smp_spurious_interrupt(struct cpu_user_regs *regs)
1215 unsigned long v;
1217 irq_enter();
1218 /*
1219 * Check if this really is a spurious interrupt and ACK it
1220 * if it is a vectored one. Just in case...
1221 * Spurious interrupts should not be ACKed.
1222 */
1223 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1224 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1225 ack_APIC_irq();
1227 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1228 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, should never happen.\n",
1229 smp_processor_id());
1230 irq_exit();
1233 /*
1234 * This interrupt should never happen with our APIC/SMP architecture
1235 */
1237 fastcall void smp_error_interrupt(struct cpu_user_regs *regs)
1239 unsigned long v, v1;
1241 irq_enter();
1242 /* First tickle the hardware, only then report what went on. -- REW */
1243 v = apic_read(APIC_ESR);
1244 apic_write(APIC_ESR, 0);
1245 v1 = apic_read(APIC_ESR);
1246 ack_APIC_irq();
1247 atomic_inc(&irq_err_count);
1249 /* Here is what the APIC error bits mean:
1250 0: Send CS error
1251 1: Receive CS error
1252 2: Send accept error
1253 3: Receive accept error
1254 4: Reserved
1255 5: Send illegal vector
1256 6: Received illegal vector
1257 7: Illegal register address
1258 */
1259 printk (KERN_DEBUG "APIC error on CPU%d: %02lx(%02lx)\n",
1260 smp_processor_id(), v , v1);
1261 irq_exit();
1264 /*
1265 * This interrupt handles performance counters interrupt
1266 */
1268 fastcall void smp_pmu_apic_interrupt(struct cpu_user_regs *regs)
1270 ack_APIC_irq();
1271 hvm_do_pmu_interrupt(regs);
1274 /*
1275 * This initializes the IO-APIC and APIC hardware if this is
1276 * a UP kernel.
1277 */
1278 int __init APIC_init_uniprocessor (void)
1280 if (enable_local_apic < 0)
1281 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
1283 if (!smp_found_config && !cpu_has_apic)
1284 return -1;
1286 /*
1287 * Complain if the BIOS pretends there is one.
1288 */
1289 if (!cpu_has_apic && APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1290 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1291 boot_cpu_physical_apicid);
1292 clear_bit(X86_FEATURE_APIC, boot_cpu_data.x86_capability);
1293 return -1;
1296 verify_local_APIC();
1298 connect_bsp_APIC();
1300 /*
1301 * Hack: In case of kdump, after a crash, kernel might be booting
1302 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1303 * might be zero if read from MP tables. Get it from LAPIC.
1304 */
1305 #ifdef CONFIG_CRASH_DUMP
1306 boot_cpu_physical_apicid = get_apic_id();
1307 #endif
1308 phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
1310 setup_local_APIC();
1312 if (nmi_watchdog == NMI_LOCAL_APIC)
1313 check_nmi_watchdog();
1314 #ifdef CONFIG_X86_IO_APIC
1315 if (smp_found_config)
1316 if (!skip_ioapic_setup && nr_ioapics)
1317 setup_IO_APIC();
1318 #endif
1319 setup_boot_APIC_clock();
1321 return 0;