ia64/xen-unstable

view xen/include/asm-powerpc/processor.h @ 14237:eceb9ccd84a8

[POWERPC][XEN] Introduce "platform" abstraction to describe the IO hole.
Signed-off-by: Ryan Harper <ryanh@us.ibm.com>
Signed-off-by: Hollis Blanchard <hollisb@us.ibm.com>
author Hollis Blanchard <hollisb@us.ibm.com>
date Fri Mar 02 17:06:50 2007 -0600 (2007-03-02)
parents d1f053ff43d2
children 3867217d3155
line source
1 /*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
15 *
16 * Copyright (C) IBM Corp. 2005, 2006
17 *
18 * Authors: Hollis Blanchard <hollisb@us.ibm.com>
19 */
21 #ifndef _ASM_PROCESSOR_H_
22 #define _ASM_PROCESSOR_H_
24 #include <xen/config.h>
25 #include <asm/reg_defs.h>
26 #include <asm/msr.h>
28 #define IOBMP_BYTES 8192
29 #define IOBMP_INVALID_OFFSET 0x8000
31 /* most assembler do not know this instruction */
32 #define HRFID .long 0x4c000224
34 /* Processor Version Register (PVR) field extraction */
36 #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
37 #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
39 #define __is_processor(pv) (PVR_VER(mfspr(SPRN_PVR)) == (pv))
41 /*
42 * IBM has further subdivided the standard PowerPC 16-bit version and
43 * revision subfields of the PVR for the PowerPC 403s into the following:
44 */
46 #define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
47 #define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
48 #define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
49 #define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
50 #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
51 #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
53 /* Processor Version Numbers */
55 #define PVR_403GA 0x00200000
56 #define PVR_403GB 0x00200100
57 #define PVR_403GC 0x00200200
58 #define PVR_403GCX 0x00201400
59 #define PVR_405GP 0x40110000
60 #define PVR_STB03XXX 0x40310000
61 #define PVR_NP405H 0x41410000
62 #define PVR_NP405L 0x41610000
63 #define PVR_601 0x00010000
64 #define PVR_602 0x00050000
65 #define PVR_603 0x00030000
66 #define PVR_603e 0x00060000
67 #define PVR_603ev 0x00070000
68 #define PVR_603r 0x00071000
69 #define PVR_604 0x00040000
70 #define PVR_604e 0x00090000
71 #define PVR_604r 0x000A0000
72 #define PVR_620 0x00140000
73 #define PVR_740 0x00080000
74 #define PVR_750 PVR_740
75 #define PVR_740P 0x10080000
76 #define PVR_750P PVR_740P
77 #define PVR_7400 0x000C0000
78 #define PVR_7410 0x800C0000
79 #define PVR_7450 0x80000000
80 #define PVR_8540 0x80200000
81 #define PVR_8560 0x80200000
82 /*
83 * For the 8xx processors, all of them report the same PVR family for
84 * the PowerPC core. The various versions of these processors must be
85 * differentiated by the version number in the Communication Processor
86 * Module (CPM).
87 */
88 #define PVR_821 0x00500000
89 #define PVR_823 PVR_821
90 #define PVR_850 PVR_821
91 #define PVR_860 PVR_821
92 #define PVR_8240 0x00810100
93 #define PVR_8245 0x80811014
94 #define PVR_8260 PVR_8240
96 /* 64-bit processors */
97 /* XXX the prefix should be PVR_, we'll do a global sweep to fix it one day */
98 #define PV_NORTHSTAR 0x0033
99 #define PV_PULSAR 0x0034
100 #define PV_POWER4 0x0035
101 #define PV_ICESTAR 0x0036
102 #define PV_SSTAR 0x0037
103 #define PV_POWER4p 0x0038
104 #define PV_970 0x0039
105 #define PV_POWER5 0x003A
106 #define PV_POWER5p 0x003B
107 #define PV_970FX 0x003C
108 #define PV_630 0x0040
109 #define PV_630p 0x0041
110 #define PV_970MP 0x0044
111 #define PV_BE 0x0070
113 #ifndef __ASSEMBLY__
114 #include <xen/types.h>
116 struct domain;
117 struct vcpu;
118 struct cpu_user_regs;
119 extern int cpu_machinecheck(struct cpu_user_regs *);
120 extern void show_registers(struct cpu_user_regs *);
121 extern unsigned int cpu_extent_order(void);
122 extern unsigned int cpu_default_rma_order_pages(void);
123 extern int cpu_rma_valid(unsigned int order);
124 extern uint cpu_large_page_orders(uint *sizes, uint max);
125 extern void cpu_initialize(int cpuid);
126 extern void cpu_init_vcpu(struct vcpu *);
127 extern int cpu_threads(int cpuid);
128 extern void save_cpu_sprs(struct vcpu *);
129 extern void load_cpu_sprs(struct vcpu *);
130 extern void flush_segments(void);
131 extern void dump_segments(int valid);
133 #define ARCH_HAS_PREFETCH
134 static inline void prefetch(const void *x) {;}
136 static __inline__ void sync(void)
137 {
138 __asm__ __volatile__ ("sync");
139 }
141 static __inline__ void isync(void)
142 {
143 __asm__ __volatile__ ("isync");
144 }
146 static inline ulong mfmsr(void) {
147 ulong msr;
148 __asm__ __volatile__ ("mfmsr %0" : "=&r"(msr));
149 return msr;
150 }
152 static inline void nop(void) {
153 __asm__ __volatile__ ("nop");
154 }
155 /* will need to address thread priorities when we go SMT */
156 #define cpu_relax() barrier()
158 static inline unsigned int mfpir(void)
159 {
160 unsigned int pir;
161 __asm__ __volatile__ ("mfspr %0, %1" : "=r" (pir): "i"(SPRN_PIR));
162 return pir;
163 }
165 static inline unsigned int mftbu(void)
166 {
167 unsigned int tbu;
168 __asm__ __volatile__ ("mftbu %0" : "=r" (tbu));
169 return tbu;
170 }
172 static inline unsigned int mftbl(void)
173 {
174 unsigned int tbl;
175 __asm__ __volatile__ ("mftbl %0" : "=r" (tbl));
176 return tbl;
177 }
179 static inline unsigned int mfdec(void)
180 {
181 unsigned int tmp;
182 __asm__ __volatile__ ("mfdec %0" : "=r"(tmp));
183 return tmp;
184 }
185 static inline void mtdec(unsigned int ticks)
186 {
187 __asm__ __volatile__ ("mtdec %0" : : "r" (ticks));
188 }
190 static inline u32 mfpvr(void) {
191 u32 pvr;
192 asm volatile("mfpvr %0" : "=&r" (pvr));
193 return pvr;
194 }
196 static inline ulong mfr1(void)
197 {
198 ulong r1;
199 asm volatile("mr %0, 1" : "=&r" (r1));
200 return r1;
201 }
203 static inline void mtsprg0(ulong val)
204 {
205 __asm__ __volatile__ ("mtspr %0, %1" : : "i"(SPRN_SPRG0), "r"(val));
206 }
207 static inline ulong mfsprg0(void)
208 {
209 ulong val;
210 __asm__ __volatile__ ("mfspr %0, %1" : "=r"(val) : "i"(SPRN_SPRG0));
211 return val;
212 }
214 static inline void mtsprg1(ulong val)
215 {
216 __asm__ __volatile__ ("mtspr %0, %1" : : "i"(SPRN_SPRG1), "r"(val));
217 }
218 static inline ulong mfsprg1(void)
219 {
220 ulong val;
221 __asm__ __volatile__ ("mfspr %0, %1" : "=r"(val) : "i"(SPRN_SPRG1));
222 return val;
223 }
225 static inline void mtsprg2(ulong val)
226 {
227 __asm__ __volatile__ ("mtspr %0, %1" : : "i"(SPRN_SPRG2), "r"(val));
228 }
229 static inline ulong mfsprg2(void)
230 {
231 ulong val;
232 __asm__ __volatile__ ("mfspr %0, %1" : "=r"(val) : "i"(SPRN_SPRG2));
233 return val;
234 }
236 static inline void mtsprg3(ulong val)
237 {
238 __asm__ __volatile__ ("mtspr %0, %1" : : "i"(SPRN_SPRG3), "r"(val));
239 }
240 static inline ulong mfsprg3(void)
241 {
242 ulong val;
243 __asm__ __volatile__ ("mfspr %0, %1" : "=r"(val) : "i"(SPRN_SPRG3));
244 return val;
245 }
247 static inline void mtsdr1(ulong val)
248 {
249 __asm__ __volatile__ ("mtsdr1 %0" : : "r"(val));
250 }
251 static inline ulong mfsdr1(void)
252 {
253 ulong val;
254 __asm__ __volatile__ ("mfsdr1 %0" : "=r"(val));
255 return val;
256 }
258 static inline void mtdar(ulong val)
259 {
260 __asm__ __volatile__ ("mtspr %0, %1" : : "i"(SPRN_DAR), "r"(val));
261 }
262 static inline ulong mfdar(void)
263 {
264 ulong val;
265 __asm__ __volatile__ ("mfspr %0, %1" : "=r"(val) : "i"(SPRN_DAR));
266 return val;
267 }
269 static inline void mtdsisr(ulong val)
270 {
271 __asm__ __volatile__ ("mtspr %0, %1" : : "i"(SPRN_DSISR), "r"(val));
272 }
273 static inline unsigned mfdsisr(void)
274 {
275 unsigned val;
276 __asm__ __volatile__ ("mfspr %0, %1" : "=r"(val) : "i"(SPRN_DSISR));
277 return val;
278 }
280 #ifdef CONFIG_SYSTEMSIM
281 static inline int on_systemsim(void)
282 {
283 return !!(mfmsr() & MSR_SYSTEMSIM);
284 }
285 #else /* CONFIG_SYSTEMSIM */
286 static inline int on_systemsim(void) { return 0; }
287 #endif
289 #endif /* __ASSEMBLY__ */
291 #include <asm/powerpc64/processor.h>
293 #endif