ia64/xen-unstable

view tools/ioemu/hw/serial.c @ 16554:ec61ca6cd55b

Fix ioemu compile: serial.c was including a Linux-specific header.
Signed-off-by: John Levon <john.levon@sun.com>
author Keir Fraser <keir.fraser@citrix.com>
date Fri Dec 07 00:41:54 2007 +0000 (2007-12-07)
parents 90f02ca76244
children c0f7ba3aa9b2
line source
1 /*
2 * QEMU 16550A UART emulation
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
25 #include "vl.h"
26 #include <sys/time.h>
27 #include <time.h>
28 #include <assert.h>
30 //#define DEBUG_SERIAL
32 #define TIOCM_DTR 0x002
33 #define TIOCM_RTS 0x004
34 #define TIOCM_CTS 0x020
35 #define TIOCM_CAR 0x040
36 #define TIOCM_RI 0x080
37 #define TIOCM_DSR 0x100
39 #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
41 #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
42 #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
43 #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
44 #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
46 #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
47 #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
49 #define UART_IIR_MSI 0x00 /* Modem status interrupt */
50 #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
51 #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
52 #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
53 #define UART_IIR_CTI 0x0C /* Character Timeout Indication */
55 #define UART_IIR_FENF 0x80 /* Fifo enabled, but not functionning */
56 #define UART_IIR_FE 0xC0 /* Fifo enabled */
58 /*
59 * These are the definitions for the Modem Control Register
60 */
61 #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
62 #define UART_MCR_OUT2 0x08 /* Out2 complement */
63 #define UART_MCR_OUT1 0x04 /* Out1 complement */
64 #define UART_MCR_RTS 0x02 /* RTS complement */
65 #define UART_MCR_DTR 0x01 /* DTR complement */
67 /*
68 * These are the definitions for the Modem Status Register
69 */
70 #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
71 #define UART_MSR_RI 0x40 /* Ring Indicator */
72 #define UART_MSR_DSR 0x20 /* Data Set Ready */
73 #define UART_MSR_CTS 0x10 /* Clear to Send */
74 #define UART_MSR_DDCD 0x08 /* Delta DCD */
75 #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
76 #define UART_MSR_DDSR 0x02 /* Delta DSR */
77 #define UART_MSR_DCTS 0x01 /* Delta CTS */
78 #define UART_MSR_ANY_DELTA 0x0F /* Any of the msr delta bits */
80 #define UART_LSR_TEMT 0x40 /* Transmitter empty */
81 #define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
82 #define UART_LSR_BI 0x10 /* Break interrupt indicator */
83 #define UART_LSR_FE 0x08 /* Frame error indicator */
84 #define UART_LSR_PE 0x04 /* Parity error indicator */
85 #define UART_LSR_OE 0x02 /* Overrun error indicator */
86 #define UART_LSR_DR 0x01 /* Receiver data ready */
87 #define UART_LSR_INT_ANY 0x1E /* Any of the lsr-interrupt-triggering status bits */
89 /* Interrupt trigger levels. The byte-counts are for 16550A - in newer UARTs the byte-count for each ITL is higher. */
91 #define UART_FCR_ITL_1 0x00 /* 1 byte ITL */
92 #define UART_FCR_ITL_2 0x40 /* 4 bytes ITL */
93 #define UART_FCR_ITL_3 0x80 /* 8 bytes ITL */
94 #define UART_FCR_ITL_4 0xC0 /* 14 bytes ITL */
96 #define UART_FCR_DMS 0x08 /* DMA Mode Select */
97 #define UART_FCR_XFR 0x04 /* XMIT Fifo Reset */
98 #define UART_FCR_RFR 0x02 /* RCVR Fifo Reset */
99 #define UART_FCR_FE 0x01 /* FIFO Enable */
101 #define UART_FIFO_LENGTH 16 /* 16550A Fifo Length */
103 #define XMIT_FIFO 0
104 #define RECV_FIFO 1
105 #define MAX_XMIT_RETRY 4
107 struct SerialFIFO {
108 uint8_t data[UART_FIFO_LENGTH];
109 uint8_t count;
110 uint8_t itl; /* Interrupt Trigger Level */
111 uint8_t tail;
112 uint8_t head;
113 } typedef SerialFIFO;
115 struct SerialState {
116 uint16_t divider;
117 uint8_t rbr; /* receive register */
118 uint8_t thr; /* transmit holding register */
119 uint8_t tsr; /* transmit shift register */
120 uint8_t ier;
121 uint8_t iir; /* read only */
122 uint8_t lcr;
123 uint8_t mcr;
124 uint8_t lsr; /* read only */
125 uint8_t msr; /* read only */
126 uint8_t scr;
127 uint8_t fcr;
128 /* NOTE: this hidden state is necessary for tx irq generation as
129 it can be reset while reading iir */
130 int thr_ipending;
131 SetIRQFunc *set_irq;
132 void *irq_opaque;
133 int irq;
134 CharDriverState *chr;
135 int last_break_enable;
136 target_ulong base;
137 int it_shift;
138 int tsr_retry;
140 uint64_t last_xmit_ts; /* Time when the last byte was successfully sent out of the tsr */
141 SerialFIFO recv_fifo;
142 SerialFIFO xmit_fifo;
144 struct QEMUTimer *fifo_timeout_timer;
145 int timeout_ipending; /* timeout interrupt pending state */
146 struct QEMUTimer *transmit_timer;
149 uint64_t char_transmit_time; /* time to transmit a char in ticks*/
150 int poll_msl;
152 struct QEMUTimer *modem_status_poll;
153 };
155 /* Rate limit serial requests so that e.g. grub on a serial console
156 doesn't kill dom0. Simple token bucket. If we get some actual
157 data from the user, instantly refil the bucket. */
159 /* How long it takes to generate a token, in microseconds. */
160 #define TOKEN_PERIOD 1000
161 /* Maximum and initial size of token bucket */
162 #define TOKENS_MAX 100000
164 static int tokens_avail;
166 static void fifo_clear(SerialState *s, int fifo) {
167 SerialFIFO *f = ( fifo ) ? &s->recv_fifo : &s->xmit_fifo;
168 memset(f->data, 0, UART_FIFO_LENGTH);
169 f->count = 0;
170 f->head = 0;
171 f->tail = 0;
172 }
174 static int fifo_put(SerialState *s, int fifo, uint8_t chr) {
175 SerialFIFO *f = ( fifo ) ? &s->recv_fifo : &s->xmit_fifo;
177 f->data[f->head++] = chr;
179 if (f->head == UART_FIFO_LENGTH)
180 f->head = 0;
181 f->count++;
183 tokens_avail = TOKENS_MAX;
185 return 1;
186 }
188 uint8_t fifo_get(SerialState *s, int fifo) {
189 SerialFIFO *f = ( fifo ) ? &s->recv_fifo : &s->xmit_fifo;
190 uint8_t c;
192 if( f->count == 0 )
193 return 0;
195 c = f->data[f->tail++];
196 if (f->tail == UART_FIFO_LENGTH)
197 f->tail = 0;
198 f->count--;
200 tokens_avail = TOKENS_MAX;
202 return c;
203 }
205 static void serial_update_irq(SerialState *s)
206 {
207 uint8_t tmp_iir = UART_IIR_NO_INT;
209 if (!s->ier) {
210 s->set_irq(s->irq_opaque, s->irq, 0);
211 return;
212 }
214 if ( ( s->ier & UART_IER_RLSI ) && (s->lsr & UART_LSR_INT_ANY ) ) {
215 tmp_iir = UART_IIR_RLSI;
216 } else if ( s->timeout_ipending ) {
217 tmp_iir = UART_IIR_CTI;
218 } else if ( ( s->ier & UART_IER_RDI ) && (s->lsr & UART_LSR_DR ) ) {
219 if ( !(s->iir & UART_FCR_FE) ) {
220 tmp_iir = UART_IIR_RDI;
221 } else if ( s->recv_fifo.count >= s->recv_fifo.itl ) {
222 tmp_iir = UART_IIR_RDI;
223 }
224 } else if ( (s->ier & UART_IER_THRI) && s->thr_ipending ) {
225 tmp_iir = UART_IIR_THRI;
226 } else if ( (s->ier & UART_IER_MSI) && (s->msr & UART_MSR_ANY_DELTA) ) {
227 tmp_iir = UART_IIR_MSI;
228 }
230 s->iir = tmp_iir | ( s->iir & 0xF0 );
232 if ( tmp_iir != UART_IIR_NO_INT ) {
233 s->set_irq(s->irq_opaque, s->irq, 1);
234 } else {
235 s->set_irq(s->irq_opaque, s->irq, 0);
236 }
237 }
239 static void serial_update_parameters(SerialState *s)
240 {
241 int speed, parity, data_bits, stop_bits, frame_size;
242 QEMUSerialSetParams ssp;
244 if (s->divider == 0)
245 return;
247 frame_size = 1;
248 if (s->lcr & 0x08) {
249 if (s->lcr & 0x10)
250 parity = 'E';
251 else
252 parity = 'O';
253 } else {
254 parity = 'N';
255 frame_size = 0;
256 }
257 if (s->lcr & 0x04)
258 stop_bits = 2;
259 else
260 stop_bits = 1;
262 data_bits = (s->lcr & 0x03) + 5;
263 frame_size += data_bits + stop_bits;
265 speed = 115200 / s->divider;
266 ssp.speed = speed;
267 ssp.parity = parity;
268 ssp.data_bits = data_bits;
269 ssp.stop_bits = stop_bits;
270 s->char_transmit_time = ( ticks_per_sec / speed ) * frame_size;
271 qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
272 #if 0
273 printf("speed=%d parity=%c data=%d stop=%d\n",
274 speed, parity, data_bits, stop_bits);
275 #endif
276 }
278 static void serial_get_token(void)
279 {
280 static struct timeval last_refil_time;
281 static int started;
283 assert(tokens_avail >= 0);
284 if (!tokens_avail) {
285 struct timeval delta, now;
286 int generated;
288 if (!started) {
289 gettimeofday(&last_refil_time, NULL);
290 tokens_avail = TOKENS_MAX;
291 started = 1;
292 return;
293 }
294 retry:
295 gettimeofday(&now, NULL);
296 delta.tv_sec = now.tv_sec - last_refil_time.tv_sec;
297 delta.tv_usec = now.tv_usec - last_refil_time.tv_usec;
298 if (delta.tv_usec < 0) {
299 delta.tv_usec += 1000000;
300 delta.tv_sec--;
301 }
302 assert(delta.tv_usec >= 0 && delta.tv_sec >= 0);
303 if (delta.tv_usec < TOKEN_PERIOD) {
304 struct timespec ts;
305 /* Wait until at least one token is available. */
306 ts.tv_sec = TOKEN_PERIOD / 1000000;
307 ts.tv_nsec = (TOKEN_PERIOD % 1000000) * 1000;
308 while (nanosleep(&ts, &ts) < 0 && errno == EINTR)
309 ;
310 goto retry;
311 }
312 generated = (delta.tv_sec * 1000000) / TOKEN_PERIOD;
313 generated +=
314 ((delta.tv_sec * 1000000) % TOKEN_PERIOD + delta.tv_usec) / TOKEN_PERIOD;
315 assert(generated > 0);
317 last_refil_time.tv_usec += (generated * TOKEN_PERIOD) % 1000000;
318 last_refil_time.tv_sec += last_refil_time.tv_usec / 1000000;
319 last_refil_time.tv_usec %= 1000000;
320 last_refil_time.tv_sec += (generated * TOKEN_PERIOD) / 1000000;
321 if (generated > TOKENS_MAX)
322 generated = TOKENS_MAX;
323 tokens_avail = generated;
324 }
325 tokens_avail--;
326 }
328 static void serial_update_msl( SerialState *s )
329 {
330 uint8_t omsr;
331 int flags;
333 qemu_del_timer(s->modem_status_poll);
335 if ( qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags) == -ENOTSUP ) {
336 s->poll_msl = -1;
337 return;
338 }
340 omsr = s->msr;
342 s->msr = ( flags & TIOCM_CTS ) ? s->msr | UART_MSR_CTS : s->msr & ~UART_MSR_CTS;
343 s->msr = ( flags & TIOCM_DSR ) ? s->msr | UART_MSR_DSR : s->msr & ~UART_MSR_DSR;
344 s->msr = ( flags & TIOCM_CAR ) ? s->msr | UART_MSR_DCD : s->msr & ~UART_MSR_DCD;
345 s->msr = ( flags & TIOCM_RI ) ? s->msr | UART_MSR_RI : s->msr & ~UART_MSR_RI;
347 if ( s->msr != omsr ) {
348 /* Set delta bits */
349 s->msr = s->msr | ( ( s->msr >> 4 ) ^ ( omsr >> 4 ) );
350 /* UART_MSR_TERI only if change was from 1 -> 0 */
351 if ( ( s->msr & UART_MSR_TERI ) && !( omsr & UART_MSR_RI ) )
352 s->msr &= ~UART_MSR_TERI;
353 serial_update_irq(s);
354 }
356 /* The real 16550A apparently has a 250ns response latency to line status changes.
357 We'll be lazy and poll only every 10ms, and only poll it at all if MSI interrupts are turned on */
359 if ( s->poll_msl )
360 qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + ticks_per_sec / 100);
361 }
363 static void serial_xmit(void *opaque) {
364 SerialState *s = opaque;
365 uint64_t new_xmit_ts = qemu_get_clock(vm_clock);
367 if ( s->tsr_retry == 0 ) {
368 if (s->fcr & UART_FCR_FE) {
369 s->tsr = fifo_get(s,XMIT_FIFO);
370 if ( !s->xmit_fifo.count )
371 s->lsr |= UART_LSR_THRE;
372 } else {
373 s->tsr = s->thr;
374 s->lsr |= UART_LSR_THRE;
375 }
376 }
378 if ( qemu_chr_write(s->chr, &s->tsr, 1) != 1 ) {
379 s->tsr_retry++;
380 if ( s->tsr_retry <= MAX_XMIT_RETRY ) {
381 qemu_mod_timer(s->transmit_timer, new_xmit_ts + s->char_transmit_time );
382 return;
383 }
384 }
386 s->tsr_retry = 0;
387 s->last_xmit_ts = qemu_get_clock(vm_clock);
389 if ( !(s->lsr & UART_LSR_THRE) )
390 qemu_mod_timer(s->transmit_timer, s->last_xmit_ts + s->char_transmit_time );
392 if ( s->lsr & UART_LSR_THRE ) {
393 s->lsr |= UART_LSR_TEMT;
394 s->thr_ipending = 1;
395 serial_update_irq(s);
396 }
397 }
400 static void serial_ioport_write(void *opaque, uint32_t addr, uint32_t val)
401 {
402 SerialState *s = opaque;
404 addr &= 7;
405 #ifdef DEBUG_SERIAL
406 printf("serial: write addr=0x%02x val=0x%02x\n", addr, val);
407 #endif
408 switch(addr) {
409 default:
410 case 0:
411 if (s->lcr & UART_LCR_DLAB) {
412 s->divider = (s->divider & 0xff00) | val;
413 serial_update_parameters(s);
414 } else {
415 s->thr = (uint8_t) val;
416 if(s->fcr & UART_FCR_FE) {
417 fifo_put(s, XMIT_FIFO, s->thr);
418 s->thr_ipending = 0;
419 s->lsr &= ~UART_LSR_TEMT;
420 s->lsr &= ~UART_LSR_THRE;
421 serial_update_irq(s);
422 } else {
423 s->thr_ipending = 0;
424 s->lsr &= ~UART_LSR_THRE;
425 serial_update_irq(s);
426 }
427 serial_xmit(s);
428 }
429 break;
430 case 1:
431 if (s->lcr & UART_LCR_DLAB) {
432 s->divider = (s->divider & 0x00ff) | (val << 8);
433 serial_update_parameters(s);
434 } else {
435 s->ier = val & 0x0f;
436 /* If the backend device is a real serial port, turn polling of the modem
437 status lines on physical port on or off depending on UART_IER_MSI state */
438 if ( s->poll_msl >= 0 ) {
439 if ( s->ier & UART_IER_MSI ) {
440 s->poll_msl = 1;
441 serial_update_msl(s);
442 } else {
443 qemu_del_timer(s->modem_status_poll);
444 s->poll_msl = 0;
445 }
446 }
447 if (s->lsr & UART_LSR_THRE) {
448 s->thr_ipending = 1;
449 serial_update_irq(s);
450 }
451 }
452 break;
453 case 2:
454 val = val & 0xFF;
456 if ( s->fcr == val)
457 break;
459 /* Did the enable/disable flag change? If so, make sure FIFOs get flushed */
460 if ( (val ^ s->fcr) & UART_FCR_FE )
461 val |= UART_FCR_XFR | UART_FCR_RFR;
463 /* FIFO clear */
465 if ( val & UART_FCR_RFR ) {
466 qemu_del_timer(s->fifo_timeout_timer);
467 s->timeout_ipending=0;
468 fifo_clear(s,RECV_FIFO);
469 }
471 if ( val & UART_FCR_XFR ) {
472 fifo_clear(s,XMIT_FIFO);
473 }
475 if ( val & UART_FCR_FE ) {
476 s->iir |= UART_IIR_FE;
477 /* Set RECV_FIFO trigger Level */
478 switch ( val & 0xC0 ) {
479 case UART_FCR_ITL_1:
480 s->recv_fifo.itl = 1;
481 break;
482 case UART_FCR_ITL_2:
483 s->recv_fifo.itl = 4;
484 break;
485 case UART_FCR_ITL_3:
486 s->recv_fifo.itl = 8;
487 break;
488 case UART_FCR_ITL_4:
489 s->recv_fifo.itl = 14;
490 break;
491 }
492 } else
493 s->iir &= ~UART_IIR_FE;
495 /* Set fcr - or at least the bits in it that are supposed to "stick" */
496 s->fcr = val & 0xC9;
497 serial_update_irq(s);
498 break;
499 case 3:
500 {
501 int break_enable;
502 s->lcr = val;
503 serial_update_parameters(s);
504 break_enable = (val >> 6) & 1;
505 if (break_enable != s->last_break_enable) {
506 s->last_break_enable = break_enable;
507 qemu_chr_ioctl(s->chr, CHR_IOCTL_SERIAL_SET_BREAK,
508 &break_enable);
509 }
510 }
511 break;
512 case 4:
513 {
514 int flags;
515 int old_mcr = s->mcr;
516 s->mcr = val & 0x1f;
517 if ( val & UART_MCR_LOOP )
518 break;
520 if ( s->poll_msl >= 0 && old_mcr != s->mcr ) {
522 qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_GET_TIOCM, &flags);
524 flags &= ~( TIOCM_RTS | TIOCM_DTR );
526 if ( val & UART_MCR_RTS )
527 flags |= TIOCM_RTS;
528 if ( val & UART_MCR_DTR )
529 flags |= TIOCM_DTR;
531 qemu_chr_ioctl(s->chr,CHR_IOCTL_SERIAL_SET_TIOCM, &flags);
532 /* Update the modem status after a one-character-send wait-time, since there may be a response
533 from the device/computer at the other end of the serial line */
534 qemu_mod_timer(s->modem_status_poll, qemu_get_clock(vm_clock) + s->char_transmit_time );
535 }
536 }
537 break;
538 case 5:
539 break;
540 case 6:
541 break;
542 case 7:
543 s->scr = val;
544 break;
545 }
546 }
548 static uint32_t serial_ioport_read(void *opaque, uint32_t addr)
549 {
550 SerialState *s = opaque;
551 uint32_t ret;
553 addr &= 7;
554 switch(addr) {
555 default:
556 case 0:
557 if (s->lcr & UART_LCR_DLAB) {
558 ret = s->divider & 0xff;
559 } else {
560 if(s->fcr & UART_FCR_FE) {
561 ret = fifo_get(s,RECV_FIFO);
562 if ( s->recv_fifo.count == 0 )
563 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
564 else
565 qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4 );
566 s->timeout_ipending = 0;
567 } else {
568 ret = s->rbr;
569 s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
570 }
571 serial_update_irq(s);
572 }
573 break;
574 case 1:
575 if (s->lcr & UART_LCR_DLAB) {
576 ret = (s->divider >> 8) & 0xff;
577 } else {
578 ret = s->ier;
579 }
580 break;
581 case 2:
582 ret = s->iir;
583 s->thr_ipending = 0;
584 serial_update_irq(s);
585 break;
586 case 3:
587 ret = s->lcr;
588 break;
589 case 4:
590 ret = s->mcr;
591 break;
592 case 5:
593 serial_get_token();
594 ret = s->lsr;
595 /* Clear break interrupt */
596 if ( s->lsr & UART_LSR_BI ) {
597 s->lsr &= ~UART_LSR_BI;
598 serial_update_irq(s);
599 }
600 break;
601 case 6:
602 serial_get_token();
603 if (s->mcr & UART_MCR_LOOP) {
604 /* in loopback, the modem output pins are connected to the
605 inputs */
606 ret = (s->mcr & 0x0c) << 4;
607 ret |= (s->mcr & 0x02) << 3;
608 ret |= (s->mcr & 0x01) << 5;
609 } else {
610 if ( s->poll_msl >= 0 )
611 serial_update_msl(s);
612 ret = s->msr;
613 /* Clear delta bits & msr int after read, if they were set */
614 if ( s->msr & UART_MSR_ANY_DELTA ) {
615 s->msr &= 0xF0;
616 serial_update_irq(s);
617 }
618 }
619 break;
620 case 7:
621 ret = s->scr;
622 break;
623 }
624 #ifdef DEBUG_SERIAL
625 printf("serial: read addr=0x%02x val=0x%02x\n", addr, ret);
626 #endif
627 return ret;
628 }
630 static int serial_can_receive(SerialState *s)
631 {
632 if(s->fcr & UART_FCR_FE) {
633 if(s->recv_fifo.count < UART_FIFO_LENGTH)
634 /* Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1 if above. If UART_FIFO_LENGTH - fifo.count is
635 advertised the effect will be to almost always fill the fifo completely before the guest has a chance to respond,
636 effectively overriding the ITL that the guest has set. */
637 return ( s->recv_fifo.count <= s->recv_fifo.itl ) ? s->recv_fifo.itl - s->recv_fifo.count : 1;
638 else
639 return 0;
640 } else {
641 return !(s->lsr & UART_LSR_DR);
642 }
643 }
645 static void serial_receive_break(SerialState *s)
646 {
647 s->rbr = 0;
648 s->lsr |= UART_LSR_BI | UART_LSR_DR;
649 serial_update_irq(s);
650 }
652 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
653 static void fifo_timeout_int (void *opaque) {
654 SerialState *s = opaque;
655 if ( s->recv_fifo.count ) {
656 s->timeout_ipending = 1;
657 serial_update_irq(s);
658 }
659 }
661 static int serial_can_receive1(void *opaque)
662 {
663 SerialState *s = opaque;
664 return serial_can_receive(s);
665 }
667 static void serial_receive1(void *opaque, const uint8_t *buf, int size)
668 {
669 SerialState *s = opaque;
670 tokens_avail = TOKENS_MAX;
671 if(s->fcr & UART_FCR_FE) {
672 int i;
673 for (i = 0; i < size; i++) {
674 fifo_put(s, RECV_FIFO, buf[i]);
675 }
676 s->lsr |= UART_LSR_DR;
677 /* call the timeout receive callback in 4 char transmit time */
678 qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock (vm_clock) + s->char_transmit_time * 4);
679 } else {
680 s->rbr = buf[0];
681 s->lsr |= UART_LSR_DR;
682 }
683 serial_update_irq(s);
684 }
686 static void serial_event(void *opaque, int event)
687 {
688 SerialState *s = opaque;
689 tokens_avail = TOKENS_MAX;
690 if (event == CHR_EVENT_BREAK)
691 serial_receive_break(s);
692 }
694 static void serial_save(QEMUFile *f, void *opaque)
695 {
696 SerialState *s = opaque;
698 qemu_put_be16s(f,&s->divider);
699 qemu_put_8s(f,&s->rbr);
700 qemu_put_8s(f,&s->ier);
701 qemu_put_8s(f,&s->iir);
702 qemu_put_8s(f,&s->lcr);
703 qemu_put_8s(f,&s->mcr);
704 qemu_put_8s(f,&s->lsr);
705 qemu_put_8s(f,&s->msr);
706 qemu_put_8s(f,&s->scr);
707 qemu_get_8s(f,&s->fcr);
708 }
710 static int serial_load(QEMUFile *f, void *opaque, int version_id)
711 {
712 SerialState *s = opaque;
714 if(version_id > 2)
715 return -EINVAL;
717 if (version_id >= 2)
718 qemu_get_be16s(f, &s->divider);
719 else
720 s->divider = qemu_get_byte(f);
721 qemu_get_8s(f,&s->rbr);
722 qemu_get_8s(f,&s->ier);
723 qemu_get_8s(f,&s->iir);
724 qemu_get_8s(f,&s->lcr);
725 qemu_get_8s(f,&s->mcr);
726 qemu_get_8s(f,&s->lsr);
727 qemu_get_8s(f,&s->msr);
728 qemu_get_8s(f,&s->scr);
729 qemu_get_8s(f,&s->fcr);
731 return 0;
732 }
734 /* If fd is zero, it means that the serial device uses the console */
735 SerialState *serial_init(SetIRQFunc *set_irq, void *opaque,
736 int base, int irq, CharDriverState *chr)
737 {
738 SerialState *s;
740 s = qemu_mallocz(sizeof(SerialState));
741 if (!s)
742 return NULL;
743 s->set_irq = set_irq;
744 s->irq_opaque = opaque;
745 s->irq = irq;
746 s->ier = 0;
747 s->lsr = UART_LSR_TEMT | UART_LSR_THRE;
748 s->iir = UART_IIR_NO_INT;
749 s->mcr = UART_MCR_OUT2;
750 s->msr = UART_MSR_DCD | UART_MSR_DSR | UART_MSR_CTS;
751 /* Default to 9600 baud, no parity, one stop bit */
752 s->divider = 0x0C;
753 s->tsr_retry = 0;
754 s->char_transmit_time = ( ticks_per_sec / 9600 ) * 9;
756 s->modem_status_poll = qemu_new_timer(vm_clock, ( QEMUTimerCB *) serial_update_msl, s);
758 s->poll_msl = 0;
760 fifo_clear(s,RECV_FIFO);
761 fifo_clear(s,XMIT_FIFO);
762 s->last_xmit_ts = qemu_get_clock(vm_clock);
763 s->fifo_timeout_timer = qemu_new_timer(vm_clock, ( QEMUTimerCB *) fifo_timeout_int, s);
764 s->transmit_timer = qemu_new_timer(vm_clock, ( QEMUTimerCB *) serial_xmit, s);
766 register_savevm("serial", base, 2, serial_save, serial_load, s);
768 register_ioport_write(base, 8, 1, serial_ioport_write, s);
769 register_ioport_read(base, 8, 1, serial_ioport_read, s);
770 s->chr = chr;
771 qemu_chr_add_handlers(chr, serial_can_receive1, serial_receive1,
772 serial_event, s);
773 serial_update_msl(s);
774 return s;
775 }