ia64/xen-unstable

view tools/ioemu/hw/tcx.c @ 6946:e703abaf6e3d

Add behaviour to the remove methods to remove the transaction's path itself. This allows us to write Remove(path) to remove the specified path rather than having to slice the path ourselves.
author emellor@ewan
date Sun Sep 18 14:42:13 2005 +0100 (2005-09-18)
parents 8e5fc5fe636c
children f7b43e5c42b9
line source
1 /*
2 * QEMU Sun4m System Emulator
3 *
4 * Copyright (c) 2003-2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "vl.h"
26 #define MAXX 1024
27 #define MAXY 768
28 #define XSZ (8*80)
29 #define YSZ (24*11)
30 #define XOFF (MAXX-XSZ)
31 #define YOFF (MAXY-YSZ)
33 typedef struct TCXState {
34 uint32_t addr;
35 DisplayState *ds;
36 uint8_t *vram;
37 } TCXState;
39 static TCXState *ts;
41 void vga_update_display()
42 {
43 dpy_update(ts->ds, 0, 0, XSZ, YSZ);
44 }
46 void vga_invalidate_display() {}
48 static uint32_t tcx_mem_readb(void *opaque, target_phys_addr_t addr)
49 {
50 TCXState *s = opaque;
51 uint32_t saddr;
52 unsigned int x, y;
54 saddr = addr - s->addr - YOFF*MAXX - XOFF;
55 y = saddr / MAXX;
56 x = saddr - y * MAXX;
57 if (x < XSZ && y < YSZ) {
58 return s->vram[y * XSZ + x];
59 }
60 return 0;
61 }
63 static uint32_t tcx_mem_readw(void *opaque, target_phys_addr_t addr)
64 {
65 uint32_t v;
66 #ifdef TARGET_WORDS_BIGENDIAN
67 v = tcx_mem_readb(opaque, addr) << 8;
68 v |= tcx_mem_readb(opaque, addr + 1);
69 #else
70 v = tcx_mem_readb(opaque, addr);
71 v |= tcx_mem_readb(opaque, addr + 1) << 8;
72 #endif
73 return v;
74 }
76 static uint32_t tcx_mem_readl(void *opaque, target_phys_addr_t addr)
77 {
78 uint32_t v;
79 #ifdef TARGET_WORDS_BIGENDIAN
80 v = tcx_mem_readb(opaque, addr) << 24;
81 v |= tcx_mem_readb(opaque, addr + 1) << 16;
82 v |= tcx_mem_readb(opaque, addr + 2) << 8;
83 v |= tcx_mem_readb(opaque, addr + 3);
84 #else
85 v = tcx_mem_readb(opaque, addr);
86 v |= tcx_mem_readb(opaque, addr + 1) << 8;
87 v |= tcx_mem_readb(opaque, addr + 2) << 16;
88 v |= tcx_mem_readb(opaque, addr + 3) << 24;
89 #endif
90 return v;
91 }
93 static void tcx_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
94 {
95 TCXState *s = opaque;
96 uint32_t saddr;
97 unsigned int x, y;
98 char *sptr;
100 saddr = addr - s->addr - YOFF*MAXX - XOFF;
101 y = saddr / MAXX;
102 x = saddr - y * MAXX;
103 if (x < XSZ && y < YSZ) {
104 sptr = s->ds->data;
105 if (sptr) {
106 if (s->ds->depth == 24 || s->ds->depth == 32) {
107 /* XXX need to do CLUT translation */
108 sptr[y * s->ds->linesize + x*4] = val & 0xff;
109 sptr[y * s->ds->linesize + x*4+1] = val & 0xff;
110 sptr[y * s->ds->linesize + x*4+2] = val & 0xff;
111 }
112 else if (s->ds->depth == 8) {
113 sptr[y * s->ds->linesize + x] = val & 0xff;
114 }
115 }
116 cpu_physical_memory_set_dirty(addr);
117 s->vram[y * XSZ + x] = val & 0xff;
118 }
119 }
121 static void tcx_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
122 {
123 #ifdef TARGET_WORDS_BIGENDIAN
124 tcx_mem_writeb(opaque, addr, (val >> 8) & 0xff);
125 tcx_mem_writeb(opaque, addr + 1, val & 0xff);
126 #else
127 tcx_mem_writeb(opaque, addr, val & 0xff);
128 tcx_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
129 #endif
130 }
132 static void tcx_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
133 {
134 #ifdef TARGET_WORDS_BIGENDIAN
135 tcx_mem_writeb(opaque, addr, (val >> 24) & 0xff);
136 tcx_mem_writeb(opaque, addr + 1, (val >> 16) & 0xff);
137 tcx_mem_writeb(opaque, addr + 2, (val >> 8) & 0xff);
138 tcx_mem_writeb(opaque, addr + 3, val & 0xff);
139 #else
140 tcx_mem_writeb(opaque, addr, val & 0xff);
141 tcx_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff);
142 tcx_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff);
143 tcx_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff);
144 #endif
145 }
147 static CPUReadMemoryFunc *tcx_mem_read[3] = {
148 tcx_mem_readb,
149 tcx_mem_readw,
150 tcx_mem_readl,
151 };
153 static CPUWriteMemoryFunc *tcx_mem_write[3] = {
154 tcx_mem_writeb,
155 tcx_mem_writew,
156 tcx_mem_writel,
157 };
159 void tcx_init(DisplayState *ds, uint32_t addr)
160 {
161 TCXState *s;
162 int tcx_io_memory;
164 s = qemu_mallocz(sizeof(TCXState));
165 if (!s)
166 return;
167 s->ds = ds;
168 s->addr = addr;
169 ts = s;
170 tcx_io_memory = cpu_register_io_memory(0, tcx_mem_read, tcx_mem_write, s);
171 cpu_register_physical_memory(addr, 0x100000,
172 tcx_io_memory);
173 s->vram = qemu_mallocz(XSZ*YSZ);
174 dpy_resize(s->ds, XSZ, YSZ);
175 }
177 void vga_screen_dump(const char *filename)
178 {
179 TCXState *s = ts;
180 FILE *f;
181 uint8_t *d, *d1;
182 unsigned int v;
183 int y, x;
185 f = fopen(filename, "wb");
186 if (!f)
187 return -1;
188 fprintf(f, "P6\n%d %d\n%d\n",
189 XSZ, YSZ, 255);
190 d1 = s->vram;
191 for(y = 0; y < YSZ; y++) {
192 d = d1;
193 for(x = 0; x < XSZ; x++) {
194 v = *d;
195 fputc((v) & 0xff, f);
196 fputc((v) & 0xff, f);
197 fputc((v) & 0xff, f);
198 d++;
199 }
200 d1 += XSZ;
201 }
202 fclose(f);
203 return;
204 }