ia64/xen-unstable

view tools/ioemu/hw/pci.c @ 6946:e703abaf6e3d

Add behaviour to the remove methods to remove the transaction's path itself. This allows us to write Remove(path) to remove the specified path rather than having to slice the path ourselves.
author emellor@ewan
date Sun Sep 18 14:42:13 2005 +0100 (2005-09-18)
parents 4669354bba9a
children 588e1aef89e8
line source
1 /*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "vl.h"
26 //#define DEBUG_PCI
28 #define PCI_VENDOR_ID 0x00 /* 16 bits */
29 #define PCI_DEVICE_ID 0x02 /* 16 bits */
30 #define PCI_COMMAND 0x04 /* 16 bits */
31 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
32 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
33 #define PCI_CLASS_DEVICE 0x0a /* Device class */
34 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
35 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
36 #define PCI_MIN_GNT 0x3e /* 8 bits */
37 #define PCI_MAX_LAT 0x3f /* 8 bits */
39 /* just used for simpler irq handling. */
40 #define PCI_DEVICES_MAX 64
41 #define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32)
43 struct PCIBus {
44 int bus_num;
45 int devfn_min;
46 void (*set_irq)(PCIDevice *pci_dev, int irq_num, int level);
47 uint32_t config_reg; /* XXX: suppress */
48 openpic_t *openpic; /* XXX: suppress */
49 PCIDevice *devices[256];
50 };
52 target_phys_addr_t pci_mem_base;
53 static int pci_irq_index;
54 static uint32_t pci_irq_levels[4][PCI_IRQ_WORDS];
55 static PCIBus *first_bus;
56 extern FILE *logfile;
58 static PCIBus *pci_register_bus(void)
59 {
60 PCIBus *bus;
61 bus = qemu_mallocz(sizeof(PCIBus));
62 first_bus = bus;
63 return bus;
64 }
66 void generic_pci_save(QEMUFile* f, void *opaque)
67 {
68 PCIDevice* s=(PCIDevice*)opaque;
70 qemu_put_buffer(f, s->config, 256);
71 }
73 int generic_pci_load(QEMUFile* f, void *opaque, int version_id)
74 {
75 PCIDevice* s=(PCIDevice*)opaque;
77 if (version_id != 1)
78 return -EINVAL;
80 qemu_get_buffer(f, s->config, 256);
81 return 0;
82 }
84 /* -1 for devfn means auto assign */
85 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
86 int instance_size, int devfn,
87 PCIConfigReadFunc *config_read,
88 PCIConfigWriteFunc *config_write)
89 {
90 PCIDevice *pci_dev;
92 if (pci_irq_index >= PCI_DEVICES_MAX)
93 return NULL;
95 if (devfn < 0) {
96 for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
97 if (!bus->devices[devfn])
98 goto found;
99 }
100 return NULL;
101 found: ;
102 }
103 pci_dev = qemu_mallocz(instance_size);
104 if (!pci_dev)
105 return NULL;
106 pci_dev->bus = bus;
107 pci_dev->devfn = devfn;
108 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
110 if (!config_read)
111 config_read = pci_default_read_config;
112 if (!config_write)
113 config_write = pci_default_write_config;
114 pci_dev->config_read = config_read;
115 pci_dev->config_write = config_write;
116 pci_dev->irq_index = pci_irq_index++;
117 bus->devices[devfn] = pci_dev;
118 return pci_dev;
119 }
121 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
122 uint32_t size, int type,
123 PCIMapIORegionFunc *map_func)
124 {
125 PCIIORegion *r;
127 if ((unsigned int)region_num >= PCI_NUM_REGIONS)
128 return;
129 r = &pci_dev->io_regions[region_num];
130 r->addr = -1;
131 r->size = size;
132 r->type = type;
133 r->map_func = map_func;
134 }
136 static void pci_addr_writel(void* opaque, uint32_t addr, uint32_t val)
137 {
138 PCIBus *s = opaque;
139 s->config_reg = val;
140 }
142 static uint32_t pci_addr_readl(void* opaque, uint32_t addr)
143 {
144 PCIBus *s = opaque;
145 return s->config_reg;
146 }
148 static void pci_update_mappings(PCIDevice *d)
149 {
150 PCIIORegion *r;
151 int cmd, i;
152 uint32_t last_addr, new_addr, config_ofs;
154 cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
155 for(i = 0; i < PCI_NUM_REGIONS; i++) {
156 r = &d->io_regions[i];
157 if (i == PCI_ROM_SLOT) {
158 config_ofs = 0x30;
159 } else {
160 config_ofs = 0x10 + i * 4;
161 }
162 if (r->size != 0) {
163 if (r->type & PCI_ADDRESS_SPACE_IO) {
164 if (cmd & PCI_COMMAND_IO) {
165 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
166 config_ofs));
167 new_addr = new_addr & ~(r->size - 1);
168 last_addr = new_addr + r->size - 1;
169 /* NOTE: we have only 64K ioports on PC */
170 if (last_addr <= new_addr || new_addr == 0 ||
171 last_addr >= 0x10000) {
172 new_addr = -1;
173 }
174 } else {
175 new_addr = -1;
176 }
177 } else {
178 if (cmd & PCI_COMMAND_MEMORY) {
179 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
180 config_ofs));
181 /* the ROM slot has a specific enable bit */
182 if (i == PCI_ROM_SLOT && !(new_addr & 1))
183 goto no_mem_map;
184 new_addr = new_addr & ~(r->size - 1);
185 last_addr = new_addr + r->size - 1;
186 /* NOTE: we do not support wrapping */
187 /* XXX: as we cannot support really dynamic
188 mappings, we handle specific values as invalid
189 mappings. */
190 if (last_addr <= new_addr || new_addr == 0 ||
191 last_addr == -1) {
192 new_addr = -1;
193 }
194 } else {
195 no_mem_map:
196 new_addr = -1;
197 }
198 }
199 /* now do the real mapping */
200 if (new_addr != r->addr) {
201 if (r->addr != -1) {
202 if (r->type & PCI_ADDRESS_SPACE_IO) {
203 int class;
204 /* NOTE: specific hack for IDE in PC case:
205 only one byte must be mapped. */
206 class = d->config[0x0a] | (d->config[0x0b] << 8);
207 if (class == 0x0101 && r->size == 4) {
208 isa_unassign_ioport(r->addr + 2, 1);
209 } else {
210 isa_unassign_ioport(r->addr, r->size);
211 }
212 } else {
213 cpu_register_physical_memory(r->addr + pci_mem_base,
214 r->size,
215 IO_MEM_UNASSIGNED);
216 }
217 }
218 r->addr = new_addr;
219 if (r->addr != -1) {
220 r->map_func(d, i, r->addr, r->size, r->type);
221 }
222 }
223 }
224 }
225 }
227 uint32_t pci_default_read_config(PCIDevice *d,
228 uint32_t address, int len)
229 {
230 uint32_t val;
231 switch(len) {
232 case 1:
233 val = d->config[address];
234 break;
235 case 2:
236 val = le16_to_cpu(*(uint16_t *)(d->config + address));
237 break;
238 default:
239 case 4:
240 val = le32_to_cpu(*(uint32_t *)(d->config + address));
241 break;
242 }
243 return val;
244 }
246 void pci_default_write_config(PCIDevice *d,
247 uint32_t address, uint32_t val, int len)
248 {
249 int can_write, i;
250 uint32_t end, addr;
252 if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
253 (address >= 0x30 && address < 0x34))) {
254 PCIIORegion *r;
255 int reg;
257 if ( address >= 0x30 ) {
258 reg = PCI_ROM_SLOT;
259 }else{
260 reg = (address - 0x10) >> 2;
261 }
262 r = &d->io_regions[reg];
263 if (r->size == 0)
264 goto default_config;
265 /* compute the stored value */
266 if (reg == PCI_ROM_SLOT) {
267 /* keep ROM enable bit */
268 val &= (~(r->size - 1)) | 1;
269 } else {
270 val &= ~(r->size - 1);
271 val |= r->type;
272 }
273 *(uint32_t *)(d->config + address) = cpu_to_le32(val);
274 pci_update_mappings(d);
275 return;
276 }
277 default_config:
278 /* not efficient, but simple */
279 addr = address;
280 for(i = 0; i < len; i++) {
281 /* default read/write accesses */
282 switch(d->config[0x0e]) {
283 case 0x00:
284 case 0x80:
285 switch(addr) {
286 case 0x00:
287 case 0x01:
288 case 0x02:
289 case 0x03:
290 case 0x08:
291 case 0x09:
292 case 0x0a:
293 case 0x0b:
294 case 0x0e:
295 case 0x10 ... 0x27: /* base */
296 case 0x30 ... 0x33: /* rom */
297 case 0x3d:
298 can_write = 0;
299 break;
300 default:
301 can_write = 1;
302 break;
303 }
304 break;
305 default:
306 case 0x01:
307 switch(addr) {
308 case 0x00:
309 case 0x01:
310 case 0x02:
311 case 0x03:
312 case 0x08:
313 case 0x09:
314 case 0x0a:
315 case 0x0b:
316 case 0x0e:
317 case 0x38 ... 0x3b: /* rom */
318 case 0x3d:
319 can_write = 0;
320 break;
321 default:
322 can_write = 1;
323 break;
324 }
325 break;
326 }
327 if (can_write) {
328 d->config[addr] = val;
329 }
330 addr++;
331 val >>= 8;
332 }
334 end = address + len;
335 if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
336 /* if the command register is modified, we must modify the mappings */
337 pci_update_mappings(d);
338 }
339 }
341 static void pci_data_write(void *opaque, uint32_t addr,
342 uint32_t val, int len)
343 {
344 PCIBus *s = opaque;
345 PCIDevice *pci_dev;
346 int config_addr, bus_num;
348 #if defined(DEBUG_PCI) && 0
349 printf("pci_data_write: addr=%08x val=%08x len=%d\n",
350 s->config_reg, val, len);
351 #endif
352 if (!(s->config_reg & (1 << 31))) {
353 return;
354 }
355 if ((s->config_reg & 0x3) != 0) {
356 return;
357 }
358 bus_num = (s->config_reg >> 16) & 0xff;
359 if (bus_num != 0)
360 return;
361 pci_dev = s->devices[(s->config_reg >> 8) & 0xff];
362 if (!pci_dev)
363 return;
364 config_addr = (s->config_reg & 0xfc) | (addr & 3);
365 #if defined(DEBUG_PCI)
366 printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
367 pci_dev->name, config_addr, val, len);
368 #endif
369 pci_dev->config_write(pci_dev, config_addr, val, len);
370 }
372 static uint32_t pci_data_read(void *opaque, uint32_t addr,
373 int len)
374 {
375 PCIBus *s = opaque;
376 PCIDevice *pci_dev;
377 int config_addr, bus_num;
378 uint32_t val;
380 if (!(s->config_reg & (1 << 31)))
381 goto fail;
382 if ((s->config_reg & 0x3) != 0)
383 goto fail;
384 bus_num = (s->config_reg >> 16) & 0xff;
385 if (bus_num != 0)
386 goto fail;
387 pci_dev = s->devices[(s->config_reg >> 8) & 0xff];
388 if (!pci_dev) {
389 fail:
390 switch(len) {
391 case 1:
392 val = 0xff;
393 break;
394 case 2:
395 val = 0xffff;
396 break;
397 default:
398 case 4:
399 val = 0xffffffff;
400 break;
401 }
402 goto the_end;
403 }
404 config_addr = (s->config_reg & 0xfc) | (addr & 3);
405 val = pci_dev->config_read(pci_dev, config_addr, len);
406 #if defined(DEBUG_PCI)
407 printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
408 pci_dev->name, config_addr, val, len);
409 #endif
410 the_end:
411 #if defined(DEBUG_PCI) && 0
412 printf("pci_data_read: addr=%08x val=%08x len=%d\n",
413 s->config_reg, val, len);
414 #endif
415 return val;
416 }
418 static void pci_data_writeb(void* opaque, uint32_t addr, uint32_t val)
419 {
420 pci_data_write(opaque, addr, val, 1);
421 }
423 static void pci_data_writew(void* opaque, uint32_t addr, uint32_t val)
424 {
425 pci_data_write(opaque, addr, val, 2);
426 }
428 static void pci_data_writel(void* opaque, uint32_t addr, uint32_t val)
429 {
430 pci_data_write(opaque, addr, val, 4);
431 }
433 static uint32_t pci_data_readb(void* opaque, uint32_t addr)
434 {
435 return pci_data_read(opaque, addr, 1);
436 }
438 static uint32_t pci_data_readw(void* opaque, uint32_t addr)
439 {
440 return pci_data_read(opaque, addr, 2);
441 }
443 static uint32_t pci_data_readl(void* opaque, uint32_t addr)
444 {
445 return pci_data_read(opaque, addr, 4);
446 }
448 /* i440FX PCI bridge */
450 static void piix3_set_irq(PCIDevice *pci_dev, int irq_num, int level);
452 PCIBus *i440fx_init(void)
453 {
454 PCIBus *s;
455 PCIDevice *d;
457 s = pci_register_bus();
458 s->set_irq = piix3_set_irq;
460 register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s);
461 register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s);
463 register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s);
464 register_ioport_write(0xcfc, 4, 2, pci_data_writew, s);
465 register_ioport_write(0xcfc, 4, 4, pci_data_writel, s);
466 register_ioport_read(0xcfc, 4, 1, pci_data_readb, s);
467 register_ioport_read(0xcfc, 4, 2, pci_data_readw, s);
468 register_ioport_read(0xcfc, 4, 4, pci_data_readl, s);
470 d = pci_register_device(s, "i440FX", sizeof(PCIDevice), 0,
471 NULL, NULL);
473 d->config[0x00] = 0x86; // vendor_id
474 d->config[0x01] = 0x80;
475 d->config[0x02] = 0x37; // device_id
476 d->config[0x03] = 0x12;
477 d->config[0x08] = 0x02; // revision
478 d->config[0x0a] = 0x00; // class_sub = host2pci
479 d->config[0x0b] = 0x06; // class_base = PCI_bridge
480 d->config[0x0e] = 0x00; // header_type
481 return s;
482 }
484 /* PIIX3 PCI to ISA bridge */
486 typedef struct PIIX3State {
487 PCIDevice dev;
488 } PIIX3State;
490 PIIX3State *piix3_state;
492 /* return the global irq number corresponding to a given device irq
493 pin. We could also use the bus number to have a more precise
494 mapping. */
495 static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
496 {
497 int slot_addend;
498 slot_addend = (pci_dev->devfn >> 3);
499 return (irq_num + slot_addend) & 3;
500 }
502 static void piix3_set_irq(PCIDevice *pci_dev, int irq_num, int level)
503 {
504 int irq_index, shift, pic_irq, pic_level;
505 uint32_t *p;
507 irq_num = pci_slot_get_pirq(pci_dev, irq_num);
508 irq_index = pci_dev->irq_index;
509 p = &pci_irq_levels[irq_num][irq_index >> 5];
510 shift = (irq_index & 0x1f);
511 *p = (*p & ~(1 << shift)) | (level << shift);
513 /* now we change the pic irq level according to the piix irq mappings */
514 pic_irq = piix3_state->dev.config[0x60 + irq_num];
515 if (pic_irq < 16) {
516 /* the pic level is the logical OR of all the PCI irqs mapped
517 to it */
518 pic_level = 0;
519 #if (PCI_IRQ_WORDS == 2)
520 pic_level = ((pci_irq_levels[irq_num][0] |
521 pci_irq_levels[irq_num][1]) != 0);
522 #else
523 {
524 int i;
525 pic_level = 0;
526 for(i = 0; i < PCI_IRQ_WORDS; i++) {
527 if (pci_irq_levels[irq_num][i]) {
528 pic_level = 1;
529 break;
530 }
531 }
532 }
533 #endif
534 pic_set_irq(pic_irq, pic_level);
535 }
536 }
538 static void piix3_reset(PIIX3State *d)
539 {
540 uint8_t *pci_conf = d->dev.config;
542 pci_conf[0x04] = 0x07; // master, memory and I/O
543 pci_conf[0x05] = 0x00;
544 pci_conf[0x06] = 0x00;
545 pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
546 pci_conf[0x4c] = 0x4d;
547 pci_conf[0x4e] = 0x03;
548 pci_conf[0x4f] = 0x00;
549 pci_conf[0x60] = 0x80;
550 pci_conf[0x69] = 0x02;
551 pci_conf[0x70] = 0x80;
552 pci_conf[0x76] = 0x0c;
553 pci_conf[0x77] = 0x0c;
554 pci_conf[0x78] = 0x02;
555 pci_conf[0x79] = 0x00;
556 pci_conf[0x80] = 0x00;
557 pci_conf[0x82] = 0x00;
558 pci_conf[0xa0] = 0x08;
559 pci_conf[0xa0] = 0x08;
560 pci_conf[0xa2] = 0x00;
561 pci_conf[0xa3] = 0x00;
562 pci_conf[0xa4] = 0x00;
563 pci_conf[0xa5] = 0x00;
564 pci_conf[0xa6] = 0x00;
565 pci_conf[0xa7] = 0x00;
566 pci_conf[0xa8] = 0x0f;
567 pci_conf[0xaa] = 0x00;
568 pci_conf[0xab] = 0x00;
569 pci_conf[0xac] = 0x00;
570 pci_conf[0xae] = 0x00;
571 }
573 #define PIIX_CONFIG_XBCS 0x4f
574 void piix3_write_config(PCIDevice *d,
575 uint32_t address, uint32_t val, int len)
576 {
577 if ((PIIX3State *)d != piix3_state){
578 fprintf(logfile, "piix3_write_config: error PCIDevice\n");
579 return;
580 }
582 pci_default_write_config(d, address, val, len);
583 }
586 void piix3_init(PCIBus *bus)
587 {
588 PIIX3State *d;
589 uint8_t *pci_conf;
591 d = (PIIX3State *)pci_register_device(bus, "PIIX3", sizeof(PIIX3State),
592 -1, NULL, piix3_write_config);
593 register_savevm("PIIX3", 0, 1, generic_pci_save, generic_pci_load, d);
595 piix3_state = d;
596 pci_conf = d->dev.config;
598 pci_conf[0x00] = 0x86; // Intel
599 pci_conf[0x01] = 0x80;
600 pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
601 pci_conf[0x03] = 0x70;
602 pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
603 pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
604 pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
606 piix3_reset(d);
607 }
609 /* PREP pci init */
611 static inline void set_config(PCIBus *s, target_phys_addr_t addr)
612 {
613 int devfn, i;
615 for(i = 0; i < 11; i++) {
616 if ((addr & (1 << (11 + i))) != 0)
617 break;
618 }
619 devfn = ((addr >> 8) & 7) | (i << 3);
620 s->config_reg = 0x80000000 | (addr & 0xfc) | (devfn << 8);
621 }
623 static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
624 {
625 PCIBus *s = opaque;
626 set_config(s, addr);
627 pci_data_write(s, addr, val, 1);
628 }
630 static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
631 {
632 PCIBus *s = opaque;
633 set_config(s, addr);
634 #ifdef TARGET_WORDS_BIGENDIAN
635 val = bswap16(val);
636 #endif
637 pci_data_write(s, addr, val, 2);
638 }
640 static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
641 {
642 PCIBus *s = opaque;
643 set_config(s, addr);
644 #ifdef TARGET_WORDS_BIGENDIAN
645 val = bswap32(val);
646 #endif
647 pci_data_write(s, addr, val, 4);
648 }
650 static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
651 {
652 PCIBus *s = opaque;
653 uint32_t val;
654 set_config(s, addr);
655 val = pci_data_read(s, addr, 1);
656 return val;
657 }
659 static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
660 {
661 PCIBus *s = opaque;
662 uint32_t val;
663 set_config(s, addr);
664 val = pci_data_read(s, addr, 2);
665 #ifdef TARGET_WORDS_BIGENDIAN
666 val = bswap16(val);
667 #endif
668 return val;
669 }
671 static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
672 {
673 PCIBus *s = opaque;
674 uint32_t val;
675 set_config(s, addr);
676 val = pci_data_read(s, addr, 4);
677 #ifdef TARGET_WORDS_BIGENDIAN
678 val = bswap32(val);
679 #endif
680 return val;
681 }
683 static CPUWriteMemoryFunc *PPC_PCIIO_write[] = {
684 &PPC_PCIIO_writeb,
685 &PPC_PCIIO_writew,
686 &PPC_PCIIO_writel,
687 };
689 static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
690 &PPC_PCIIO_readb,
691 &PPC_PCIIO_readw,
692 &PPC_PCIIO_readl,
693 };
695 static void prep_set_irq(PCIDevice *d, int irq_num, int level)
696 {
697 /* XXX: we do not simulate the hardware - we rely on the BIOS to
698 set correctly for irq line field */
699 pic_set_irq(d->config[PCI_INTERRUPT_LINE], level);
700 }
702 PCIBus *pci_prep_init(void)
703 {
704 PCIBus *s;
705 PCIDevice *d;
706 int PPC_io_memory;
708 s = pci_register_bus();
709 s->set_irq = prep_set_irq;
711 PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read,
712 PPC_PCIIO_write, s);
713 cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
715 d = pci_register_device(s, "PREP PCI Bridge", sizeof(PCIDevice), 0,
716 NULL, NULL);
718 /* XXX: put correct IDs */
719 d->config[0x00] = 0x11; // vendor_id
720 d->config[0x01] = 0x10;
721 d->config[0x02] = 0x26; // device_id
722 d->config[0x03] = 0x00;
723 d->config[0x08] = 0x02; // revision
724 d->config[0x0a] = 0x04; // class_sub = pci2pci
725 d->config[0x0b] = 0x06; // class_base = PCI_bridge
726 d->config[0x0e] = 0x01; // header_type
727 return s;
728 }
731 /* pmac pci init */
733 #if 0
734 /* Grackle PCI host */
735 static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
736 uint32_t val)
737 {
738 PCIBus *s = opaque;
739 #ifdef TARGET_WORDS_BIGENDIAN
740 val = bswap32(val);
741 #endif
742 s->config_reg = val;
743 }
745 static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr)
746 {
747 PCIBus *s = opaque;
748 uint32_t val;
750 val = s->config_reg;
751 #ifdef TARGET_WORDS_BIGENDIAN
752 val = bswap32(val);
753 #endif
754 return val;
755 }
757 static CPUWriteMemoryFunc *pci_grackle_config_write[] = {
758 &pci_grackle_config_writel,
759 &pci_grackle_config_writel,
760 &pci_grackle_config_writel,
761 };
763 static CPUReadMemoryFunc *pci_grackle_config_read[] = {
764 &pci_grackle_config_readl,
765 &pci_grackle_config_readl,
766 &pci_grackle_config_readl,
767 };
769 static void pci_grackle_writeb (void *opaque, target_phys_addr_t addr,
770 uint32_t val)
771 {
772 PCIBus *s = opaque;
773 pci_data_write(s, addr, val, 1);
774 }
776 static void pci_grackle_writew (void *opaque, target_phys_addr_t addr,
777 uint32_t val)
778 {
779 PCIBus *s = opaque;
780 #ifdef TARGET_WORDS_BIGENDIAN
781 val = bswap16(val);
782 #endif
783 pci_data_write(s, addr, val, 2);
784 }
786 static void pci_grackle_writel (void *opaque, target_phys_addr_t addr,
787 uint32_t val)
788 {
789 PCIBus *s = opaque;
790 #ifdef TARGET_WORDS_BIGENDIAN
791 val = bswap32(val);
792 #endif
793 pci_data_write(s, addr, val, 4);
794 }
796 static uint32_t pci_grackle_readb (void *opaque, target_phys_addr_t addr)
797 {
798 PCIBus *s = opaque;
799 uint32_t val;
800 val = pci_data_read(s, addr, 1);
801 return val;
802 }
804 static uint32_t pci_grackle_readw (void *opaque, target_phys_addr_t addr)
805 {
806 PCIBus *s = opaque;
807 uint32_t val;
808 val = pci_data_read(s, addr, 2);
809 #ifdef TARGET_WORDS_BIGENDIAN
810 val = bswap16(val);
811 #endif
812 return val;
813 }
815 static uint32_t pci_grackle_readl (void *opaque, target_phys_addr_t addr)
816 {
817 PCIBus *s = opaque;
818 uint32_t val;
820 val = pci_data_read(s, addr, 4);
821 #ifdef TARGET_WORDS_BIGENDIAN
822 val = bswap32(val);
823 #endif
824 return val;
825 }
827 static CPUWriteMemoryFunc *pci_grackle_write[] = {
828 &pci_grackle_writeb,
829 &pci_grackle_writew,
830 &pci_grackle_writel,
831 };
833 static CPUReadMemoryFunc *pci_grackle_read[] = {
834 &pci_grackle_readb,
835 &pci_grackle_readw,
836 &pci_grackle_readl,
837 };
838 #endif
840 /* Uninorth PCI host (for all Mac99 and newer machines */
841 static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr,
842 uint32_t val)
843 {
844 PCIBus *s = opaque;
845 int i;
847 #ifdef TARGET_WORDS_BIGENDIAN
848 val = bswap32(val);
849 #endif
851 for (i = 11; i < 32; i++) {
852 if ((val & (1 << i)) != 0)
853 break;
854 }
855 #if 0
856 s->config_reg = 0x80000000 | (1 << 16) | (val & 0x7FC) | (i << 11);
857 #else
858 s->config_reg = 0x80000000 | (0 << 16) | (val & 0x7FC) | (i << 11);
859 #endif
860 }
862 static uint32_t pci_unin_main_config_readl (void *opaque,
863 target_phys_addr_t addr)
864 {
865 PCIBus *s = opaque;
866 uint32_t val;
867 int devfn;
869 devfn = (s->config_reg >> 8) & 0xFF;
870 val = (1 << (devfn >> 3)) | ((devfn & 0x07) << 8) | (s->config_reg & 0xFC);
871 #ifdef TARGET_WORDS_BIGENDIAN
872 val = bswap32(val);
873 #endif
875 return val;
876 }
878 static CPUWriteMemoryFunc *pci_unin_main_config_write[] = {
879 &pci_unin_main_config_writel,
880 &pci_unin_main_config_writel,
881 &pci_unin_main_config_writel,
882 };
884 static CPUReadMemoryFunc *pci_unin_main_config_read[] = {
885 &pci_unin_main_config_readl,
886 &pci_unin_main_config_readl,
887 &pci_unin_main_config_readl,
888 };
890 static void pci_unin_main_writeb (void *opaque, target_phys_addr_t addr,
891 uint32_t val)
892 {
893 PCIBus *s = opaque;
894 pci_data_write(s, addr & 7, val, 1);
895 }
897 static void pci_unin_main_writew (void *opaque, target_phys_addr_t addr,
898 uint32_t val)
899 {
900 PCIBus *s = opaque;
901 #ifdef TARGET_WORDS_BIGENDIAN
902 val = bswap16(val);
903 #endif
904 pci_data_write(s, addr & 7, val, 2);
905 }
907 static void pci_unin_main_writel (void *opaque, target_phys_addr_t addr,
908 uint32_t val)
909 {
910 PCIBus *s = opaque;
911 #ifdef TARGET_WORDS_BIGENDIAN
912 val = bswap32(val);
913 #endif
914 pci_data_write(s, addr & 7, val, 4);
915 }
917 static uint32_t pci_unin_main_readb (void *opaque, target_phys_addr_t addr)
918 {
919 PCIBus *s = opaque;
920 uint32_t val;
922 val = pci_data_read(s, addr & 7, 1);
924 return val;
925 }
927 static uint32_t pci_unin_main_readw (void *opaque, target_phys_addr_t addr)
928 {
929 PCIBus *s = opaque;
930 uint32_t val;
932 val = pci_data_read(s, addr & 7, 2);
933 #ifdef TARGET_WORDS_BIGENDIAN
934 val = bswap16(val);
935 #endif
937 return val;
938 }
940 static uint32_t pci_unin_main_readl (void *opaque, target_phys_addr_t addr)
941 {
942 PCIBus *s = opaque;
943 uint32_t val;
945 val = pci_data_read(s, addr, 4);
946 #ifdef TARGET_WORDS_BIGENDIAN
947 val = bswap32(val);
948 #endif
950 return val;
951 }
953 static CPUWriteMemoryFunc *pci_unin_main_write[] = {
954 &pci_unin_main_writeb,
955 &pci_unin_main_writew,
956 &pci_unin_main_writel,
957 };
959 static CPUReadMemoryFunc *pci_unin_main_read[] = {
960 &pci_unin_main_readb,
961 &pci_unin_main_readw,
962 &pci_unin_main_readl,
963 };
965 #if 0
967 static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr,
968 uint32_t val)
969 {
970 PCIBus *s = opaque;
972 #ifdef TARGET_WORDS_BIGENDIAN
973 val = bswap32(val);
974 #endif
975 s->config_reg = 0x80000000 | (val & ~0x00000001);
976 }
978 static uint32_t pci_unin_config_readl (void *opaque,
979 target_phys_addr_t addr)
980 {
981 PCIBus *s = opaque;
982 uint32_t val;
984 val = (s->config_reg | 0x00000001) & ~0x80000000;
985 #ifdef TARGET_WORDS_BIGENDIAN
986 val = bswap32(val);
987 #endif
989 return val;
990 }
992 static CPUWriteMemoryFunc *pci_unin_config_write[] = {
993 &pci_unin_config_writel,
994 &pci_unin_config_writel,
995 &pci_unin_config_writel,
996 };
998 static CPUReadMemoryFunc *pci_unin_config_read[] = {
999 &pci_unin_config_readl,
1000 &pci_unin_config_readl,
1001 &pci_unin_config_readl,
1002 };
1004 static void pci_unin_writeb (void *opaque, target_phys_addr_t addr,
1005 uint32_t val)
1007 PCIBus *s = opaque;
1008 pci_data_write(s, addr & 3, val, 1);
1011 static void pci_unin_writew (void *opaque, target_phys_addr_t addr,
1012 uint32_t val)
1014 PCIBus *s = opaque;
1015 #ifdef TARGET_WORDS_BIGENDIAN
1016 val = bswap16(val);
1017 #endif
1018 pci_data_write(s, addr & 3, val, 2);
1021 static void pci_unin_writel (void *opaque, target_phys_addr_t addr,
1022 uint32_t val)
1024 PCIBus *s = opaque;
1025 #ifdef TARGET_WORDS_BIGENDIAN
1026 val = bswap32(val);
1027 #endif
1028 pci_data_write(s, addr & 3, val, 4);
1031 static uint32_t pci_unin_readb (void *opaque, target_phys_addr_t addr)
1033 PCIBus *s = opaque;
1034 uint32_t val;
1036 val = pci_data_read(s, addr & 3, 1);
1038 return val;
1041 static uint32_t pci_unin_readw (void *opaque, target_phys_addr_t addr)
1043 PCIBus *s = opaque;
1044 uint32_t val;
1046 val = pci_data_read(s, addr & 3, 2);
1047 #ifdef TARGET_WORDS_BIGENDIAN
1048 val = bswap16(val);
1049 #endif
1051 return val;
1054 static uint32_t pci_unin_readl (void *opaque, target_phys_addr_t addr)
1056 PCIBus *s = opaque;
1057 uint32_t val;
1059 val = pci_data_read(s, addr & 3, 4);
1060 #ifdef TARGET_WORDS_BIGENDIAN
1061 val = bswap32(val);
1062 #endif
1064 return val;
1067 static CPUWriteMemoryFunc *pci_unin_write[] = {
1068 &pci_unin_writeb,
1069 &pci_unin_writew,
1070 &pci_unin_writel,
1071 };
1073 static CPUReadMemoryFunc *pci_unin_read[] = {
1074 &pci_unin_readb,
1075 &pci_unin_readw,
1076 &pci_unin_readl,
1077 };
1078 #endif
1080 static void pmac_set_irq(PCIDevice *d, int irq_num, int level)
1082 openpic_t *openpic;
1083 /* XXX: we do not simulate the hardware - we rely on the BIOS to
1084 set correctly for irq line field */
1085 openpic = d->bus->openpic;
1086 #ifdef TARGET_PPC
1087 if (openpic)
1088 openpic_set_irq(openpic, d->config[PCI_INTERRUPT_LINE], level);
1089 #endif
1092 void pci_pmac_set_openpic(PCIBus *bus, openpic_t *openpic)
1094 bus->openpic = openpic;
1097 PCIBus *pci_pmac_init(void)
1099 PCIBus *s;
1100 PCIDevice *d;
1101 int pci_mem_config, pci_mem_data;
1103 /* Use values found on a real PowerMac */
1104 /* Uninorth main bus */
1105 s = pci_register_bus();
1106 s->set_irq = pmac_set_irq;
1108 pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read,
1109 pci_unin_main_config_write, s);
1110 pci_mem_data = cpu_register_io_memory(0, pci_unin_main_read,
1111 pci_unin_main_write, s);
1112 cpu_register_physical_memory(0xf2800000, 0x1000, pci_mem_config);
1113 cpu_register_physical_memory(0xf2c00000, 0x1000, pci_mem_data);
1114 s->devfn_min = 11 << 3;
1115 d = pci_register_device(s, "Uni-north main", sizeof(PCIDevice),
1116 11 << 3, NULL, NULL);
1117 d->config[0x00] = 0x6b; // vendor_id : Apple
1118 d->config[0x01] = 0x10;
1119 d->config[0x02] = 0x1F; // device_id
1120 d->config[0x03] = 0x00;
1121 d->config[0x08] = 0x00; // revision
1122 d->config[0x0A] = 0x00; // class_sub = pci host
1123 d->config[0x0B] = 0x06; // class_base = PCI_bridge
1124 d->config[0x0C] = 0x08; // cache_line_size
1125 d->config[0x0D] = 0x10; // latency_timer
1126 d->config[0x0E] = 0x00; // header_type
1127 d->config[0x34] = 0x00; // capabilities_pointer
1129 #if 0 // XXX: not activated as PPC BIOS doesn't handle mutiple buses properly
1130 /* pci-to-pci bridge */
1131 d = pci_register_device("Uni-north bridge", sizeof(PCIDevice), 0, 13 << 3,
1132 NULL, NULL);
1133 d->config[0x00] = 0x11; // vendor_id : TI
1134 d->config[0x01] = 0x10;
1135 d->config[0x02] = 0x26; // device_id
1136 d->config[0x03] = 0x00;
1137 d->config[0x08] = 0x05; // revision
1138 d->config[0x0A] = 0x04; // class_sub = pci2pci
1139 d->config[0x0B] = 0x06; // class_base = PCI_bridge
1140 d->config[0x0C] = 0x08; // cache_line_size
1141 d->config[0x0D] = 0x20; // latency_timer
1142 d->config[0x0E] = 0x01; // header_type
1144 d->config[0x18] = 0x01; // primary_bus
1145 d->config[0x19] = 0x02; // secondary_bus
1146 d->config[0x1A] = 0x02; // subordinate_bus
1147 d->config[0x1B] = 0x20; // secondary_latency_timer
1148 d->config[0x1C] = 0x11; // io_base
1149 d->config[0x1D] = 0x01; // io_limit
1150 d->config[0x20] = 0x00; // memory_base
1151 d->config[0x21] = 0x80;
1152 d->config[0x22] = 0x00; // memory_limit
1153 d->config[0x23] = 0x80;
1154 d->config[0x24] = 0x01; // prefetchable_memory_base
1155 d->config[0x25] = 0x80;
1156 d->config[0x26] = 0xF1; // prefectchable_memory_limit
1157 d->config[0x27] = 0x7F;
1158 // d->config[0x34] = 0xdc // capabilities_pointer
1159 #endif
1160 #if 0 // XXX: not needed for now
1161 /* Uninorth AGP bus */
1162 s = &pci_bridge[1];
1163 pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
1164 pci_unin_config_write, s);
1165 pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
1166 pci_unin_write, s);
1167 cpu_register_physical_memory(0xf0800000, 0x1000, pci_mem_config);
1168 cpu_register_physical_memory(0xf0c00000, 0x1000, pci_mem_data);
1170 d = pci_register_device("Uni-north AGP", sizeof(PCIDevice), 0, 11 << 3,
1171 NULL, NULL);
1172 d->config[0x00] = 0x6b; // vendor_id : Apple
1173 d->config[0x01] = 0x10;
1174 d->config[0x02] = 0x20; // device_id
1175 d->config[0x03] = 0x00;
1176 d->config[0x08] = 0x00; // revision
1177 d->config[0x0A] = 0x00; // class_sub = pci host
1178 d->config[0x0B] = 0x06; // class_base = PCI_bridge
1179 d->config[0x0C] = 0x08; // cache_line_size
1180 d->config[0x0D] = 0x10; // latency_timer
1181 d->config[0x0E] = 0x00; // header_type
1182 // d->config[0x34] = 0x80; // capabilities_pointer
1183 #endif
1185 #if 0 // XXX: not needed for now
1186 /* Uninorth internal bus */
1187 s = &pci_bridge[2];
1188 pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
1189 pci_unin_config_write, s);
1190 pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
1191 pci_unin_write, s);
1192 cpu_register_physical_memory(0xf4800000, 0x1000, pci_mem_config);
1193 cpu_register_physical_memory(0xf4c00000, 0x1000, pci_mem_data);
1195 d = pci_register_device("Uni-north internal", sizeof(PCIDevice),
1196 3, 11 << 3, NULL, NULL);
1197 d->config[0x00] = 0x6b; // vendor_id : Apple
1198 d->config[0x01] = 0x10;
1199 d->config[0x02] = 0x1E; // device_id
1200 d->config[0x03] = 0x00;
1201 d->config[0x08] = 0x00; // revision
1202 d->config[0x0A] = 0x00; // class_sub = pci host
1203 d->config[0x0B] = 0x06; // class_base = PCI_bridge
1204 d->config[0x0C] = 0x08; // cache_line_size
1205 d->config[0x0D] = 0x10; // latency_timer
1206 d->config[0x0E] = 0x00; // header_type
1207 d->config[0x34] = 0x00; // capabilities_pointer
1208 #endif
1210 #if 0 // Grackle ?
1211 /* same values as PearPC - check this */
1212 d->config[0x00] = 0x11; // vendor_id
1213 d->config[0x01] = 0x10;
1214 d->config[0x02] = 0x26; // device_id
1215 d->config[0x03] = 0x00;
1216 d->config[0x08] = 0x02; // revision
1217 d->config[0x0a] = 0x04; // class_sub = pci2pci
1218 d->config[0x0b] = 0x06; // class_base = PCI_bridge
1219 d->config[0x0e] = 0x01; // header_type
1221 d->config[0x18] = 0x0; // primary_bus
1222 d->config[0x19] = 0x1; // secondary_bus
1223 d->config[0x1a] = 0x1; // subordinate_bus
1224 d->config[0x1c] = 0x10; // io_base
1225 d->config[0x1d] = 0x20; // io_limit
1227 d->config[0x20] = 0x80; // memory_base
1228 d->config[0x21] = 0x80;
1229 d->config[0x22] = 0x90; // memory_limit
1230 d->config[0x23] = 0x80;
1232 d->config[0x24] = 0x00; // prefetchable_memory_base
1233 d->config[0x25] = 0x84;
1234 d->config[0x26] = 0x00; // prefetchable_memory_limit
1235 d->config[0x27] = 0x85;
1236 #endif
1237 return s;
1240 /***********************************************************/
1241 /* generic PCI irq support */
1243 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1244 void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
1246 PCIBus *bus = pci_dev->bus;
1247 bus->set_irq(pci_dev, irq_num, level);
1250 /***********************************************************/
1251 /* monitor info on PCI */
1253 static void pci_info_device(PCIDevice *d)
1255 int i, class;
1256 PCIIORegion *r;
1258 term_printf(" Bus %2d, device %3d, function %d:\n",
1259 d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
1260 class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
1261 term_printf(" ");
1262 switch(class) {
1263 case 0x0101:
1264 term_printf("IDE controller");
1265 break;
1266 case 0x0200:
1267 term_printf("Ethernet controller");
1268 break;
1269 case 0x0300:
1270 term_printf("VGA controller");
1271 break;
1272 default:
1273 term_printf("Class %04x", class);
1274 break;
1276 term_printf(": PCI device %04x:%04x\n",
1277 le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
1278 le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
1280 if (d->config[PCI_INTERRUPT_PIN] != 0) {
1281 term_printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
1283 for(i = 0;i < PCI_NUM_REGIONS; i++) {
1284 r = &d->io_regions[i];
1285 if (r->size != 0) {
1286 term_printf(" BAR%d: ", i);
1287 if (r->type & PCI_ADDRESS_SPACE_IO) {
1288 term_printf("I/O at 0x%04x [0x%04x].\n",
1289 r->addr, r->addr + r->size - 1);
1290 } else {
1291 term_printf("32 bit memory at 0x%08x [0x%08x].\n",
1292 r->addr, r->addr + r->size - 1);
1298 void pci_info(void)
1300 PCIBus *bus = first_bus;
1301 PCIDevice *d;
1302 int devfn;
1304 if (bus) {
1305 for(devfn = 0; devfn < 256; devfn++) {
1306 d = bus->devices[devfn];
1307 if (d)
1308 pci_info_device(d);
1313 /***********************************************************/
1314 /* XXX: the following should be moved to the PC BIOS */
1316 static __attribute__((unused)) uint32_t isa_inb(uint32_t addr)
1318 return cpu_inb(cpu_single_env, addr);
1321 static void isa_outb(uint32_t val, uint32_t addr)
1323 cpu_outb(cpu_single_env, addr, val);
1326 static __attribute__((unused)) uint32_t isa_inw(uint32_t addr)
1328 return cpu_inw(cpu_single_env, addr);
1331 static __attribute__((unused)) void isa_outw(uint32_t val, uint32_t addr)
1333 cpu_outw(cpu_single_env, addr, val);
1336 static __attribute__((unused)) uint32_t isa_inl(uint32_t addr)
1338 return cpu_inl(cpu_single_env, addr);
1341 static __attribute__((unused)) void isa_outl(uint32_t val, uint32_t addr)
1343 cpu_outl(cpu_single_env, addr, val);
1346 static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
1348 PCIBus *s = d->bus;
1349 s->config_reg = 0x80000000 | (s->bus_num << 16) |
1350 (d->devfn << 8) | addr;
1351 pci_data_write(s, 0, val, 4);
1354 static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
1356 PCIBus *s = d->bus;
1357 s->config_reg = 0x80000000 | (s->bus_num << 16) |
1358 (d->devfn << 8) | (addr & ~3);
1359 pci_data_write(s, addr & 3, val, 2);
1362 static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
1364 PCIBus *s = d->bus;
1365 s->config_reg = 0x80000000 | (s->bus_num << 16) |
1366 (d->devfn << 8) | (addr & ~3);
1367 pci_data_write(s, addr & 3, val, 1);
1370 static __attribute__((unused)) uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
1372 PCIBus *s = d->bus;
1373 s->config_reg = 0x80000000 | (s->bus_num << 16) |
1374 (d->devfn << 8) | addr;
1375 return pci_data_read(s, 0, 4);
1378 static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
1380 PCIBus *s = d->bus;
1381 s->config_reg = 0x80000000 | (s->bus_num << 16) |
1382 (d->devfn << 8) | (addr & ~3);
1383 return pci_data_read(s, addr & 3, 2);
1386 static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
1388 PCIBus *s = d->bus;
1389 s->config_reg = 0x80000000 | (s->bus_num << 16) |
1390 (d->devfn << 8) | (addr & ~3);
1391 return pci_data_read(s, addr & 3, 1);
1394 static uint32_t pci_bios_io_addr;
1395 static uint32_t pci_bios_mem_addr;
1396 /* host irqs corresponding to PCI irqs A-D */
1397 static uint8_t pci_irqs[4] = { 11, 9, 11, 9 };
1399 static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
1401 PCIIORegion *r;
1402 uint16_t cmd;
1403 uint32_t ofs;
1405 if ( region_num == PCI_ROM_SLOT ) {
1406 ofs = 0x30;
1407 }else{
1408 ofs = 0x10 + region_num * 4;
1411 pci_config_writel(d, ofs, addr);
1412 r = &d->io_regions[region_num];
1414 /* enable memory mappings */
1415 cmd = pci_config_readw(d, PCI_COMMAND);
1416 if ( region_num == PCI_ROM_SLOT )
1417 cmd |= 2;
1418 else if (r->type & PCI_ADDRESS_SPACE_IO)
1419 cmd |= 1;
1420 else
1421 cmd |= 2;
1422 pci_config_writew(d, PCI_COMMAND, cmd);
1425 static void pci_bios_init_device(PCIDevice *d)
1427 int class;
1428 PCIIORegion *r;
1429 uint32_t *paddr;
1430 int i, pin, pic_irq, vendor_id, device_id;
1432 class = pci_config_readw(d, PCI_CLASS_DEVICE);
1433 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
1434 device_id = pci_config_readw(d, PCI_DEVICE_ID);
1435 switch(class) {
1436 case 0x0101:
1437 if (vendor_id == 0x8086 && device_id == 0x7010) {
1438 /* PIIX3 IDE */
1439 pci_config_writew(d, 0x40, 0x8000); // enable IDE0
1440 pci_config_writew(d, 0x42, 0x8000); // enable IDE1
1441 goto default_map;
1442 } else {
1443 /* IDE: we map it as in ISA mode */
1444 pci_set_io_region_addr(d, 0, 0x1f0);
1445 pci_set_io_region_addr(d, 1, 0x3f4);
1446 pci_set_io_region_addr(d, 2, 0x170);
1447 pci_set_io_region_addr(d, 3, 0x374);
1449 break;
1450 case 0x0300:
1451 if (vendor_id != 0x1234)
1452 goto default_map;
1453 /* VGA: map frame buffer to default Bochs VBE address */
1454 pci_set_io_region_addr(d, 0, 0xE0000000);
1455 break;
1456 case 0x0800:
1457 /* PIC */
1458 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
1459 device_id = pci_config_readw(d, PCI_DEVICE_ID);
1460 if (vendor_id == 0x1014) {
1461 /* IBM */
1462 if (device_id == 0x0046 || device_id == 0xFFFF) {
1463 /* MPIC & MPIC2 */
1464 pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
1467 break;
1468 case 0xff00:
1469 if (vendor_id == 0x0106b &&
1470 (device_id == 0x0017 || device_id == 0x0022)) {
1471 /* macio bridge */
1472 pci_set_io_region_addr(d, 0, 0x80800000);
1474 break;
1475 default:
1476 default_map:
1477 /* default memory mappings */
1478 for(i = 0; i < PCI_NUM_REGIONS; i++) {
1479 r = &d->io_regions[i];
1480 if (r->size) {
1481 if (r->type & PCI_ADDRESS_SPACE_IO)
1482 paddr = &pci_bios_io_addr;
1483 else
1484 paddr = &pci_bios_mem_addr;
1485 *paddr = (*paddr + r->size - 1) & ~(r->size - 1);
1486 pci_set_io_region_addr(d, i, *paddr);
1487 *paddr += r->size;
1490 break;
1493 /* map the interrupt */
1494 pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
1495 if (pin != 0) {
1496 pin = pci_slot_get_pirq(d, pin - 1);
1497 pic_irq = pci_irqs[pin];
1498 pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
1502 /*
1503 * This function initializes the PCI devices as a normal PCI BIOS
1504 * would do. It is provided just in case the BIOS has no support for
1505 * PCI.
1506 */
1507 void pci_bios_init(void)
1509 PCIBus *bus;
1510 PCIDevice *d;
1511 int devfn, i, irq;
1512 uint8_t elcr[2];
1514 pci_bios_io_addr = 0xc000;
1515 pci_bios_mem_addr = 0xf0000000;
1517 /* activate IRQ mappings */
1518 elcr[0] = 0x00;
1519 elcr[1] = 0x00;
1520 for(i = 0; i < 4; i++) {
1521 irq = pci_irqs[i];
1522 /* set to trigger level */
1523 elcr[irq >> 3] |= (1 << (irq & 7));
1524 /* activate irq remapping in PIIX */
1525 pci_config_writeb((PCIDevice *)piix3_state, 0x60 + i, irq);
1527 isa_outb(elcr[0], 0x4d0);
1528 isa_outb(elcr[1], 0x4d1);
1530 bus = first_bus;
1531 if (bus) {
1532 for(devfn = 0; devfn < 256; devfn++) {
1533 d = bus->devices[devfn];
1534 if (d)
1535 pci_bios_init_device(d);