ia64/xen-unstable

view xen/arch/x86/cpu/mcheck/x86_mca.h @ 19829:e6c7d6398d38

x86 mca: Fix typo of MCA recovery flags

The following patch fixes typo of MCA recovery flags.
It should be '<<' instead of '<'.

Signed-off-by: Kazuhiro Suzuki <kaz@jp.fujitsu.com>
author Keir Fraser <keir.fraser@citrix.com>
date Wed Jun 24 11:16:08 2009 +0100 (2009-06-24)
parents c23aeb37b17f
children
line source
1 /*
2 * MCA implementation for AMD K7/K8 CPUs
3 * Copyright (c) 2007 Advanced Micro Devices, Inc.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
20 #ifndef X86_MCA_H
21 #define X86_MCA_H
23 #include <public/arch-x86/xen-mca.h>
25 /* The MCA/MCE MSRs should not be used anywhere else.
26 * They are cpu family/model specific and are only for use
27 * in terms of machine check handling.
28 * So we define them here rather in <asm/msr.h>.
29 */
32 /* Bitfield of the MSR_IA32_MCG_CAP register */
33 #define MCG_SER_P (1UL<<24)
34 #define MCG_CAP_COUNT 0x00000000000000ffULL
35 #define MCG_CTL_P 0x0000000000000100ULL
36 #define MCG_EXT_P (1UL<<9)
37 #define MCG_EXT_CNT (16)
38 #define MCG_CMCI_P (1UL<<10)
39 /* Other bits are reserved */
41 /* Bitfield of the MSR_IA32_MCG_STATUS register */
42 #define MCG_STATUS_RIPV 0x0000000000000001ULL
43 #define MCG_STATUS_EIPV 0x0000000000000002ULL
44 #define MCG_STATUS_MCIP 0x0000000000000004ULL
45 /* Bits 3-63 are reserved */
47 /* Bitfield of MSR_K8_MCi_STATUS registers */
48 /* MCA error code */
49 #define MCi_STATUS_MCA 0x000000000000ffffULL
50 /* model-specific error code */
51 #define MCi_STATUS_MSEC 0x00000000ffff0000ULL
52 /* Other information */
53 #define MCi_STATUS_OTHER 0x01ffffff00000000ULL
54 /* Action Required flag */
55 #define MCi_STATUS_AR 0x0080000000000000ULL
56 /* Signaling flag */
57 #define MCi_STATUS_S 0x0100000000000000ULL
58 /* processor context corrupt */
59 #define MCi_STATUS_PCC 0x0200000000000000ULL
60 /* MSR_K8_MCi_ADDR register valid */
61 #define MCi_STATUS_ADDRV 0x0400000000000000ULL
62 /* MSR_K8_MCi_MISC register valid */
63 #define MCi_STATUS_MISCV 0x0800000000000000ULL
64 /* error condition enabled */
65 #define MCi_STATUS_EN 0x1000000000000000ULL
66 /* uncorrected error */
67 #define MCi_STATUS_UC 0x2000000000000000ULL
68 /* status register overflow */
69 #define MCi_STATUS_OVER 0x4000000000000000ULL
70 /* valid */
71 #define MCi_STATUS_VAL 0x8000000000000000ULL
73 /* Bitfield of MSi_STATUS_OTHER field */
74 /* reserved bits */
75 #define MCi_STATUS_OTHER_RESERVED1 0x00001fff00000000ULL
76 /* uncorrectable ECC error */
77 #define MCi_STATUS_OTEHR_UC_ECC 0x0000200000000000ULL
78 /* correctable ECC error */
79 #define MCi_STATUS_OTHER_C_ECC 0x0000400000000000ULL
80 /* ECC syndrome of an ECC error */
81 #define MCi_STATUS_OTHER_ECC_SYNDROME 0x007f800000000000ULL
82 /* reserved bits */
83 #define MCi_STATUS_OTHER_RESERVED2 0x0180000000000000ULL
85 /* Bitfield of MSR_K8_HWCR register */
86 #define K8_HWCR_MCi_STATUS_WREN (1ULL << 18)
88 /*Intel Specific bitfield*/
89 #define CMCI_THRESHOLD 0x2
91 #include <asm/domain.h>
92 typedef DECLARE_BITMAP(cpu_banks_t, MAX_NR_BANKS);
93 DECLARE_PER_CPU(cpu_banks_t, mce_banks_owned);
95 /* Below interfaces are defined for MCA internal processing:
96 * a. pre_handler will be called early in MCA ISR context, mainly for early
97 * need_reset detection for avoiding log missing. Also, it is used to judge
98 * impacted DOMAIN if possible.
99 * b. mca_error_handler is actually a (error_action_index,
100 * recovery_hanlder pointer) pair. The defined recovery_handler
101 * performs the actual recovery operations such as page_offline, cpu_offline
102 * in softIRQ context when the per_bank MCA error matching the corresponding
103 * mca_code index. If pre_handler can't judge the impacted domain,
104 * recovery_handler must figure it out.
105 */
107 /* MCA error has been recovered successfully by the recovery action*/
108 #define MCA_RECOVERED (0x1 << 0)
109 /* MCA error impact the specified DOMAIN in owner field below */
110 #define MCA_OWNER (0x1 << 1)
111 /* MCA error can't be recovered and need reset */
112 #define MCA_NEED_RESET (0x1 << 2)
113 /* MCA error did not have any action yet */
114 #define MCA_NO_ACTION (0x1 << 3)
116 struct mca_handle_result
117 {
118 uint32_t result;
119 /* Used one result & MCA_OWNER */
120 domid_t owner;
121 /* Used by mca_error_handler, result & MCA_RECOVRED */
122 struct recovery_action *action;
123 };
125 extern void (*mca_prehandler)( struct cpu_user_regs *regs,
126 struct mca_handle_result *result);
128 struct mca_error_handler
129 {
130 /* Assume corresponding recovery action could be uniquely
131 * identified by mca_code. Otherwise, we might need to have
132 * a seperate function to decode the corresponding actions
133 * for the particular mca error later.
134 */
135 uint16_t mca_code;
136 void (*recovery_handler)( struct mcinfo_bank *bank,
137 struct mcinfo_global *global,
138 struct mcinfo_extended *extension,
139 struct mca_handle_result *result);
140 };
142 /* Global variables */
143 extern int mce_disabled;
144 extern unsigned int nr_mce_banks;
146 #endif /* X86_MCA_H */