ia64/xen-unstable

view linux-2.6-xen-sparse/arch/ia64/kernel/setup.c @ 15143:e54da168363a

[IA64] Trivial warning fix

contiguous_bitmap_init has implicit declaration

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
author Alex Williamson <alex.williamson@hp.com>
date Fri May 25 09:40:43 2007 -0600 (2007-05-25)
parents 3ecf1cea58b1
children
line source
1 /*
2 * Architecture-specific setup.
3 *
4 * Copyright (C) 1998-2001, 2003-2004 Hewlett-Packard Co
5 * David Mosberger-Tang <davidm@hpl.hp.com>
6 * Stephane Eranian <eranian@hpl.hp.com>
7 * Copyright (C) 2000, 2004 Intel Corp
8 * Rohit Seth <rohit.seth@intel.com>
9 * Suresh Siddha <suresh.b.siddha@intel.com>
10 * Gordon Jin <gordon.jin@intel.com>
11 * Copyright (C) 1999 VA Linux Systems
12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
13 *
14 * 12/26/04 S.Siddha, G.Jin, R.Seth
15 * Add multi-threading and multi-core detection
16 * 11/12/01 D.Mosberger Convert get_cpuinfo() to seq_file based show_cpuinfo().
17 * 04/04/00 D.Mosberger renamed cpu_initialized to cpu_online_map
18 * 03/31/00 R.Seth cpu_initialized and current->processor fixes
19 * 02/04/00 D.Mosberger some more get_cpuinfo fixes...
20 * 02/01/00 R.Seth fixed get_cpuinfo for SMP
21 * 01/07/99 S.Eranian added the support for command line argument
22 * 06/24/99 W.Drummond added boot_cpu_data.
23 * 05/28/05 Z. Menyhart Dynamic stride size for "flush_icache_range()"
24 */
25 #include <linux/module.h>
26 #include <linux/init.h>
28 #include <linux/acpi.h>
29 #include <linux/bootmem.h>
30 #include <linux/console.h>
31 #include <linux/delay.h>
32 #include <linux/kernel.h>
33 #include <linux/reboot.h>
34 #include <linux/sched.h>
35 #include <linux/seq_file.h>
36 #include <linux/string.h>
37 #include <linux/threads.h>
38 #include <linux/screen_info.h>
39 #include <linux/dmi.h>
40 #include <linux/serial.h>
41 #include <linux/serial_core.h>
42 #include <linux/efi.h>
43 #include <linux/initrd.h>
44 #include <linux/pm.h>
45 #include <linux/cpufreq.h>
47 #include <asm/ia32.h>
48 #include <asm/machvec.h>
49 #include <asm/mca.h>
50 #include <asm/meminit.h>
51 #include <asm/page.h>
52 #include <asm/patch.h>
53 #include <asm/pgtable.h>
54 #include <asm/processor.h>
55 #include <asm/sal.h>
56 #include <asm/sections.h>
57 #include <asm/serial.h>
58 #include <asm/setup.h>
59 #include <asm/smp.h>
60 #include <asm/system.h>
61 #include <asm/unistd.h>
62 #include <asm/system.h>
63 #ifdef CONFIG_XEN
64 #include <asm/hypervisor.h>
65 #include <asm/xen/xencomm.h>
66 #include <xen/xencons.h>
67 #endif
68 #include <linux/dma-mapping.h>
70 #if defined(CONFIG_SMP) && (IA64_CPU_SIZE > PAGE_SIZE)
71 # error "struct cpuinfo_ia64 too big!"
72 #endif
74 #ifdef CONFIG_SMP
75 unsigned long __per_cpu_offset[NR_CPUS];
76 EXPORT_SYMBOL(__per_cpu_offset);
77 #endif
79 #ifdef CONFIG_XEN
80 static void
81 xen_panic_hypercall(struct unw_frame_info *info, void *arg)
82 {
83 current->thread.ksp = (__u64)info->sw - 16;
84 HYPERVISOR_shutdown(SHUTDOWN_crash);
85 /* we're never actually going to get here... */
86 }
88 static int
89 xen_panic_event(struct notifier_block *this, unsigned long event, void *ptr)
90 {
91 unw_init_running(xen_panic_hypercall, NULL);
92 /* we're never actually going to get here... */
93 return NOTIFY_DONE;
94 }
96 static struct notifier_block xen_panic_block = {
97 xen_panic_event, NULL, 0 /* try to go last */
98 };
100 void xen_pm_power_off(void)
101 {
102 local_irq_disable();
103 HYPERVISOR_shutdown(SHUTDOWN_poweroff);
104 }
105 #endif
107 extern void ia64_setup_printk_clock(void);
109 DEFINE_PER_CPU(struct cpuinfo_ia64, cpu_info);
110 DEFINE_PER_CPU(unsigned long, local_per_cpu_offset);
111 DEFINE_PER_CPU(unsigned long, ia64_phys_stacked_size_p8);
112 unsigned long ia64_cycles_per_usec;
113 struct ia64_boot_param *ia64_boot_param;
114 struct screen_info screen_info;
115 unsigned long vga_console_iobase;
116 unsigned long vga_console_membase;
118 static struct resource data_resource = {
119 .name = "Kernel data",
120 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
121 };
123 static struct resource code_resource = {
124 .name = "Kernel code",
125 .flags = IORESOURCE_BUSY | IORESOURCE_MEM
126 };
127 extern void efi_initialize_iomem_resources(struct resource *,
128 struct resource *);
129 extern char _text[], _end[], _etext[];
131 unsigned long ia64_max_cacheline_size;
133 int dma_get_cache_alignment(void)
134 {
135 return ia64_max_cacheline_size;
136 }
137 EXPORT_SYMBOL(dma_get_cache_alignment);
139 unsigned long ia64_iobase; /* virtual address for I/O accesses */
140 EXPORT_SYMBOL(ia64_iobase);
141 struct io_space io_space[MAX_IO_SPACES];
142 EXPORT_SYMBOL(io_space);
143 unsigned int num_io_spaces;
145 /*
146 * "flush_icache_range()" needs to know what processor dependent stride size to use
147 * when it makes i-cache(s) coherent with d-caches.
148 */
149 #define I_CACHE_STRIDE_SHIFT 5 /* Safest way to go: 32 bytes by 32 bytes */
150 unsigned long ia64_i_cache_stride_shift = ~0;
152 /*
153 * The merge_mask variable needs to be set to (max(iommu_page_size(iommu)) - 1). This
154 * mask specifies a mask of address bits that must be 0 in order for two buffers to be
155 * mergeable by the I/O MMU (i.e., the end address of the first buffer and the start
156 * address of the second buffer must be aligned to (merge_mask+1) in order to be
157 * mergeable). By default, we assume there is no I/O MMU which can merge physically
158 * discontiguous buffers, so we set the merge_mask to ~0UL, which corresponds to a iommu
159 * page-size of 2^64.
160 */
161 unsigned long ia64_max_iommu_merge_mask = ~0UL;
162 EXPORT_SYMBOL(ia64_max_iommu_merge_mask);
164 /*
165 * We use a special marker for the end of memory and it uses the extra (+1) slot
166 */
167 struct rsvd_region rsvd_region[IA64_MAX_RSVD_REGIONS + 1] __initdata;
168 int num_rsvd_regions __initdata;
171 /*
172 * Filter incoming memory segments based on the primitive map created from the boot
173 * parameters. Segments contained in the map are removed from the memory ranges. A
174 * caller-specified function is called with the memory ranges that remain after filtering.
175 * This routine does not assume the incoming segments are sorted.
176 */
177 int __init
178 filter_rsvd_memory (unsigned long start, unsigned long end, void *arg)
179 {
180 unsigned long range_start, range_end, prev_start;
181 void (*func)(unsigned long, unsigned long, int);
182 int i;
184 #if IGNORE_PFN0
185 if (start == PAGE_OFFSET) {
186 printk(KERN_WARNING "warning: skipping physical page 0\n");
187 start += PAGE_SIZE;
188 if (start >= end) return 0;
189 }
190 #endif
191 /*
192 * lowest possible address(walker uses virtual)
193 */
194 prev_start = PAGE_OFFSET;
195 func = arg;
197 for (i = 0; i < num_rsvd_regions; ++i) {
198 range_start = max(start, prev_start);
199 range_end = min(end, rsvd_region[i].start);
201 if (range_start < range_end)
202 call_pernode_memory(__pa(range_start), range_end - range_start, func);
204 /* nothing more available in this segment */
205 if (range_end == end) return 0;
207 prev_start = rsvd_region[i].end;
208 }
209 /* end of memory marker allows full processing inside loop body */
210 return 0;
211 }
213 static void __init
214 sort_regions (struct rsvd_region *rsvd_region, int max)
215 {
216 int j;
218 /* simple bubble sorting */
219 while (max--) {
220 for (j = 0; j < max; ++j) {
221 if (rsvd_region[j].start > rsvd_region[j+1].start) {
222 struct rsvd_region tmp;
223 tmp = rsvd_region[j];
224 rsvd_region[j] = rsvd_region[j + 1];
225 rsvd_region[j + 1] = tmp;
226 }
227 }
228 }
229 }
231 /*
232 * Request address space for all standard resources
233 */
234 static int __init register_memory(void)
235 {
236 code_resource.start = ia64_tpa(_text);
237 code_resource.end = ia64_tpa(_etext) - 1;
238 data_resource.start = ia64_tpa(_etext);
239 data_resource.end = ia64_tpa(_end) - 1;
240 efi_initialize_iomem_resources(&code_resource, &data_resource);
242 return 0;
243 }
245 __initcall(register_memory);
247 /**
248 * reserve_memory - setup reserved memory areas
249 *
250 * Setup the reserved memory areas set aside for the boot parameters,
251 * initrd, etc. There are currently %IA64_MAX_RSVD_REGIONS defined,
252 * see include/asm-ia64/meminit.h if you need to define more.
253 */
254 void __init
255 reserve_memory (void)
256 {
257 int n = 0;
259 /*
260 * none of the entries in this table overlap
261 */
262 rsvd_region[n].start = (unsigned long) ia64_boot_param;
263 rsvd_region[n].end = rsvd_region[n].start + sizeof(*ia64_boot_param);
264 n++;
266 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->efi_memmap);
267 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->efi_memmap_size;
268 n++;
270 rsvd_region[n].start = (unsigned long) __va(ia64_boot_param->command_line);
271 rsvd_region[n].end = (rsvd_region[n].start
272 + strlen(__va(ia64_boot_param->command_line)) + 1);
273 n++;
275 rsvd_region[n].start = (unsigned long) ia64_imva((void *)KERNEL_START);
276 rsvd_region[n].end = (unsigned long) ia64_imva(_end);
277 n++;
279 #ifdef CONFIG_XEN
280 if (is_running_on_xen()) {
281 rsvd_region[n].start = (unsigned long)__va((HYPERVISOR_shared_info->arch.start_info_pfn << PAGE_SHIFT));
282 rsvd_region[n].end = rsvd_region[n].start + PAGE_SIZE;
283 n++;
284 }
285 #endif
287 #ifdef CONFIG_BLK_DEV_INITRD
288 if (ia64_boot_param->initrd_start) {
289 rsvd_region[n].start = (unsigned long)__va(ia64_boot_param->initrd_start);
290 rsvd_region[n].end = rsvd_region[n].start + ia64_boot_param->initrd_size;
291 n++;
292 }
293 #endif
295 efi_memmap_init(&rsvd_region[n].start, &rsvd_region[n].end);
296 n++;
298 /* end of memory marker */
299 rsvd_region[n].start = ~0UL;
300 rsvd_region[n].end = ~0UL;
301 n++;
303 num_rsvd_regions = n;
304 BUG_ON(IA64_MAX_RSVD_REGIONS + 1 < n);
306 sort_regions(rsvd_region, num_rsvd_regions);
307 }
309 /**
310 * find_initrd - get initrd parameters from the boot parameter structure
311 *
312 * Grab the initrd start and end from the boot parameter struct given us by
313 * the boot loader.
314 */
315 void __init
316 find_initrd (void)
317 {
318 #ifdef CONFIG_BLK_DEV_INITRD
319 if (ia64_boot_param->initrd_start) {
320 initrd_start = (unsigned long)__va(ia64_boot_param->initrd_start);
321 initrd_end = initrd_start+ia64_boot_param->initrd_size;
323 printk(KERN_INFO "Initial ramdisk at: 0x%lx (%lu bytes)\n",
324 initrd_start, ia64_boot_param->initrd_size);
325 }
326 #endif
327 }
329 static void __init
330 io_port_init (void)
331 {
332 unsigned long phys_iobase;
334 /*
335 * Set `iobase' based on the EFI memory map or, failing that, the
336 * value firmware left in ar.k0.
337 *
338 * Note that in ia32 mode, IN/OUT instructions use ar.k0 to compute
339 * the port's virtual address, so ia32_load_state() loads it with a
340 * user virtual address. But in ia64 mode, glibc uses the
341 * *physical* address in ar.k0 to mmap the appropriate area from
342 * /dev/mem, and the inX()/outX() interfaces use MMIO. In both
343 * cases, user-mode can only use the legacy 0-64K I/O port space.
344 *
345 * ar.k0 is not involved in kernel I/O port accesses, which can use
346 * any of the I/O port spaces and are done via MMIO using the
347 * virtual mmio_base from the appropriate io_space[].
348 */
349 phys_iobase = efi_get_iobase();
350 if (!phys_iobase) {
351 phys_iobase = ia64_get_kr(IA64_KR_IO_BASE);
352 printk(KERN_INFO "No I/O port range found in EFI memory map, "
353 "falling back to AR.KR0 (0x%lx)\n", phys_iobase);
354 }
355 ia64_iobase = (unsigned long) ioremap(phys_iobase, 0);
356 ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
358 /* setup legacy IO port space */
359 io_space[0].mmio_base = ia64_iobase;
360 io_space[0].sparse = 1;
361 num_io_spaces = 1;
362 }
364 /**
365 * early_console_setup - setup debugging console
366 *
367 * Consoles started here require little enough setup that we can start using
368 * them very early in the boot process, either right after the machine
369 * vector initialization, or even before if the drivers can detect their hw.
370 *
371 * Returns non-zero if a console couldn't be setup.
372 */
373 static inline int __init
374 early_console_setup (char *cmdline)
375 {
376 int earlycons = 0;
378 #ifdef CONFIG_SERIAL_SGI_L1_CONSOLE
379 {
380 extern int sn_serial_console_early_setup(void);
381 if (!sn_serial_console_early_setup())
382 earlycons++;
383 }
384 #endif
385 #ifdef CONFIG_EFI_PCDP
386 if (!efi_setup_pcdp_console(cmdline))
387 earlycons++;
388 #endif
389 #ifdef CONFIG_SERIAL_8250_CONSOLE
390 if (!early_serial_console_init(cmdline))
391 earlycons++;
392 #endif
394 return (earlycons) ? 0 : -1;
395 }
397 static inline void
398 mark_bsp_online (void)
399 {
400 #ifdef CONFIG_SMP
401 /* If we register an early console, allow CPU 0 to printk */
402 cpu_set(smp_processor_id(), cpu_online_map);
403 #endif
404 }
406 #ifdef CONFIG_SMP
407 static void __init
408 check_for_logical_procs (void)
409 {
410 pal_logical_to_physical_t info;
411 s64 status;
413 status = ia64_pal_logical_to_phys(0, &info);
414 if (status == -1) {
415 printk(KERN_INFO "No logical to physical processor mapping "
416 "available\n");
417 return;
418 }
419 if (status) {
420 printk(KERN_ERR "ia64_pal_logical_to_phys failed with %ld\n",
421 status);
422 return;
423 }
424 /*
425 * Total number of siblings that BSP has. Though not all of them
426 * may have booted successfully. The correct number of siblings
427 * booted is in info.overview_num_log.
428 */
429 smp_num_siblings = info.overview_tpc;
430 smp_num_cpucores = info.overview_cpp;
431 }
432 #endif
434 static __initdata int nomca;
435 static __init int setup_nomca(char *s)
436 {
437 nomca = 1;
438 return 0;
439 }
440 early_param("nomca", setup_nomca);
442 void __init
443 setup_arch (char **cmdline_p)
444 {
445 unw_init();
447 #ifdef CONFIG_XEN
448 if (is_running_on_xen()) {
449 /* Must be done before any hypercall. */
450 xencomm_init();
452 setup_xen_features();
453 /* Register a call for panic conditions. */
454 atomic_notifier_chain_register(&panic_notifier_list,
455 &xen_panic_block);
456 pm_power_off = xen_pm_power_off;
457 }
458 #endif
460 ia64_patch_vtop((u64) __start___vtop_patchlist, (u64) __end___vtop_patchlist);
462 *cmdline_p = __va(ia64_boot_param->command_line);
463 strlcpy(saved_command_line, *cmdline_p, COMMAND_LINE_SIZE);
465 efi_init();
466 io_port_init();
468 parse_early_param();
470 #ifdef CONFIG_IA64_GENERIC
471 machvec_init(NULL);
472 #endif
474 if (early_console_setup(*cmdline_p) == 0)
475 mark_bsp_online();
477 #ifdef CONFIG_ACPI
478 /* Initialize the ACPI boot-time table parser */
479 acpi_table_init();
480 # ifdef CONFIG_ACPI_NUMA
481 acpi_numa_init();
482 # endif
483 #else
484 # ifdef CONFIG_SMP
485 smp_build_cpu_map(); /* happens, e.g., with the Ski simulator */
486 # endif
487 #endif /* CONFIG_APCI_BOOT */
489 find_memory();
491 /* process SAL system table: */
492 ia64_sal_init(__va(efi.sal_systab));
494 ia64_setup_printk_clock();
496 #ifdef CONFIG_SMP
497 cpu_physical_id(0) = hard_smp_processor_id();
499 cpu_set(0, cpu_sibling_map[0]);
500 cpu_set(0, cpu_core_map[0]);
502 check_for_logical_procs();
503 if (smp_num_cpucores > 1)
504 printk(KERN_INFO
505 "cpu package is Multi-Core capable: number of cores=%d\n",
506 smp_num_cpucores);
507 if (smp_num_siblings > 1)
508 printk(KERN_INFO
509 "cpu package is Multi-Threading capable: number of siblings=%d\n",
510 smp_num_siblings);
511 #endif
513 cpu_init(); /* initialize the bootstrap CPU */
514 mmu_context_init(); /* initialize context_id bitmap */
516 #ifdef CONFIG_ACPI
517 acpi_boot_init();
518 #endif
520 #ifdef CONFIG_VT
521 if (!conswitchp) {
522 # if defined(CONFIG_DUMMY_CONSOLE)
523 conswitchp = &dummy_con;
524 # endif
525 # if defined(CONFIG_VGA_CONSOLE)
526 /*
527 * Non-legacy systems may route legacy VGA MMIO range to system
528 * memory. vga_con probes the MMIO hole, so memory looks like
529 * a VGA device to it. The EFI memory map can tell us if it's
530 * memory so we can avoid this problem.
531 */
532 if (efi_mem_type(0xA0000) != EFI_CONVENTIONAL_MEMORY)
533 conswitchp = &vga_con;
534 # endif
535 }
536 #ifdef CONFIG_XEN
537 if (is_running_on_xen()) {
538 shared_info_t *s = HYPERVISOR_shared_info;
540 xen_start_info = __va(s->arch.start_info_pfn << PAGE_SHIFT);
542 printk("Running on Xen! start_info_pfn=0x%lx nr_pages=%ld "
543 "flags=0x%x\n", s->arch.start_info_pfn,
544 xen_start_info->nr_pages, xen_start_info->flags);
546 if (!is_initial_xendomain()) {
547 #if !defined(CONFIG_VT) || !defined(CONFIG_DUMMY_CONSOLE)
548 conswitchp = NULL;
549 #endif
550 }
552 /*
553 * If a console= is NOT specified, we assume using the
554 * xencons console is desired. By default, this is ttyS0
555 * for dom0 and tty0 for domU.
556 */
557 if (!strstr(*cmdline_p, "console=")) {
558 char *p, *q, name[5];
559 int offset = 0;
561 if (is_initial_xendomain())
562 strncpy(name, "ttyS", 4);
563 else
564 strncpy(name, "tty", 3);
566 p = strstr(*cmdline_p, "xencons=");
568 if (p) {
569 p += 8;
570 if (!strncmp(p, "ttyS", 4)) {
571 strncpy(name, p, 4);
572 p += 4;
573 offset = simple_strtol(p, &q, 10);
574 if (p == q)
575 offset = 0;
576 } else if (!strncmp(p, "tty", 3) ||
577 !strncmp(p, "xvc", 3)) {
578 strncpy(name, p, 3);
579 p += 3;
580 offset = simple_strtol(p, &q, 10);
581 if (p == q)
582 offset = 0;
583 } else if (!strncmp(p, "off", 3))
584 offset = -1;
585 }
587 if (offset >= 0)
588 add_preferred_console(name, offset, NULL);
589 }
590 }
591 xencons_early_setup();
592 #endif
593 #endif
596 /* enable IA-64 Machine Check Abort Handling unless disabled */
597 #ifdef CONFIG_XEN
598 if (is_running_on_xen() && !is_initial_xendomain())
599 nomca = 1;
600 #endif
601 if (!nomca)
602 ia64_mca_init();
604 platform_setup(cmdline_p);
605 #ifdef CONFIG_XEN
606 if (!is_running_on_xen() && !ia64_platform_is("xen")) {
607 extern ia64_mv_setup_t xen_setup;
608 xen_setup(cmdline_p);
609 }
610 #endif
611 paging_init();
612 #ifdef CONFIG_XEN
613 xen_contiguous_bitmap_init(max_pfn);
614 #endif
615 }
617 /*
618 * Display cpu info for all cpu's.
619 */
620 static int
621 show_cpuinfo (struct seq_file *m, void *v)
622 {
623 #ifdef CONFIG_SMP
624 # define lpj c->loops_per_jiffy
625 # define cpunum c->cpu
626 #else
627 # define lpj loops_per_jiffy
628 # define cpunum 0
629 #endif
630 static struct {
631 unsigned long mask;
632 const char *feature_name;
633 } feature_bits[] = {
634 { 1UL << 0, "branchlong" },
635 { 1UL << 1, "spontaneous deferral"},
636 { 1UL << 2, "16-byte atomic ops" }
637 };
638 char family[32], features[128], *cp, sep;
639 struct cpuinfo_ia64 *c = v;
640 unsigned long mask;
641 unsigned long proc_freq;
642 int i;
644 mask = c->features;
646 switch (c->family) {
647 case 0x07: memcpy(family, "Itanium", 8); break;
648 case 0x1f: memcpy(family, "Itanium 2", 10); break;
649 default: sprintf(family, "%u", c->family); break;
650 }
652 /* build the feature string: */
653 memcpy(features, " standard", 10);
654 cp = features;
655 sep = 0;
656 for (i = 0; i < (int) ARRAY_SIZE(feature_bits); ++i) {
657 if (mask & feature_bits[i].mask) {
658 if (sep)
659 *cp++ = sep;
660 sep = ',';
661 *cp++ = ' ';
662 strcpy(cp, feature_bits[i].feature_name);
663 cp += strlen(feature_bits[i].feature_name);
664 mask &= ~feature_bits[i].mask;
665 }
666 }
667 if (mask) {
668 /* print unknown features as a hex value: */
669 if (sep)
670 *cp++ = sep;
671 sprintf(cp, " 0x%lx", mask);
672 }
674 proc_freq = cpufreq_quick_get(cpunum);
675 if (!proc_freq)
676 proc_freq = c->proc_freq / 1000;
678 seq_printf(m,
679 "processor : %d\n"
680 "vendor : %s\n"
681 "arch : IA-64\n"
682 "family : %s\n"
683 "model : %u\n"
684 "revision : %u\n"
685 "archrev : %u\n"
686 "features :%s\n" /* don't change this---it _is_ right! */
687 "cpu number : %lu\n"
688 "cpu regs : %u\n"
689 "cpu MHz : %lu.%06lu\n"
690 "itc MHz : %lu.%06lu\n"
691 "BogoMIPS : %lu.%02lu\n",
692 cpunum, c->vendor, family, c->model, c->revision, c->archrev,
693 features, c->ppn, c->number,
694 proc_freq / 1000, proc_freq % 1000,
695 c->itc_freq / 1000000, c->itc_freq % 1000000,
696 lpj*HZ/500000, (lpj*HZ/5000) % 100);
697 #ifdef CONFIG_SMP
698 seq_printf(m, "siblings : %u\n", cpus_weight(cpu_core_map[cpunum]));
699 if (c->threads_per_core > 1 || c->cores_per_socket > 1)
700 seq_printf(m,
701 "physical id: %u\n"
702 "core id : %u\n"
703 "thread id : %u\n",
704 c->socket_id, c->core_id, c->thread_id);
705 #endif
706 seq_printf(m,"\n");
708 return 0;
709 }
711 static void *
712 c_start (struct seq_file *m, loff_t *pos)
713 {
714 #ifdef CONFIG_SMP
715 while (*pos < NR_CPUS && !cpu_isset(*pos, cpu_online_map))
716 ++*pos;
717 #endif
718 return *pos < NR_CPUS ? cpu_data(*pos) : NULL;
719 }
721 static void *
722 c_next (struct seq_file *m, void *v, loff_t *pos)
723 {
724 ++*pos;
725 return c_start(m, pos);
726 }
728 static void
729 c_stop (struct seq_file *m, void *v)
730 {
731 }
733 struct seq_operations cpuinfo_op = {
734 .start = c_start,
735 .next = c_next,
736 .stop = c_stop,
737 .show = show_cpuinfo
738 };
740 static void __cpuinit
741 identify_cpu (struct cpuinfo_ia64 *c)
742 {
743 union {
744 unsigned long bits[5];
745 struct {
746 /* id 0 & 1: */
747 char vendor[16];
749 /* id 2 */
750 u64 ppn; /* processor serial number */
752 /* id 3: */
753 unsigned number : 8;
754 unsigned revision : 8;
755 unsigned model : 8;
756 unsigned family : 8;
757 unsigned archrev : 8;
758 unsigned reserved : 24;
760 /* id 4: */
761 u64 features;
762 } field;
763 } cpuid;
764 pal_vm_info_1_u_t vm1;
765 pal_vm_info_2_u_t vm2;
766 pal_status_t status;
767 unsigned long impl_va_msb = 50, phys_addr_size = 44; /* Itanium defaults */
768 int i;
770 for (i = 0; i < 5; ++i)
771 cpuid.bits[i] = ia64_get_cpuid(i);
773 memcpy(c->vendor, cpuid.field.vendor, 16);
774 #ifdef CONFIG_SMP
775 c->cpu = smp_processor_id();
777 /* below default values will be overwritten by identify_siblings()
778 * for Multi-Threading/Multi-Core capable cpu's
779 */
780 c->threads_per_core = c->cores_per_socket = c->num_log = 1;
781 c->socket_id = -1;
783 identify_siblings(c);
784 #endif
785 c->ppn = cpuid.field.ppn;
786 c->number = cpuid.field.number;
787 c->revision = cpuid.field.revision;
788 c->model = cpuid.field.model;
789 c->family = cpuid.field.family;
790 c->archrev = cpuid.field.archrev;
791 c->features = cpuid.field.features;
793 status = ia64_pal_vm_summary(&vm1, &vm2);
794 if (status == PAL_STATUS_SUCCESS) {
795 impl_va_msb = vm2.pal_vm_info_2_s.impl_va_msb;
796 phys_addr_size = vm1.pal_vm_info_1_s.phys_add_size;
797 }
798 c->unimpl_va_mask = ~((7L<<61) | ((1L << (impl_va_msb + 1)) - 1));
799 c->unimpl_pa_mask = ~((1L<<63) | ((1L << phys_addr_size) - 1));
800 }
802 void
803 setup_per_cpu_areas (void)
804 {
805 /* start_kernel() requires this... */
806 #ifdef CONFIG_ACPI_HOTPLUG_CPU
807 prefill_possible_map();
808 #endif
809 }
811 /*
812 * Calculate the max. cache line size.
813 *
814 * In addition, the minimum of the i-cache stride sizes is calculated for
815 * "flush_icache_range()".
816 */
817 static void __cpuinit
818 get_max_cacheline_size (void)
819 {
820 unsigned long line_size, max = 1;
821 unsigned int cache_size = 0;
822 u64 l, levels, unique_caches;
823 pal_cache_config_info_t cci;
824 s64 status;
826 status = ia64_pal_cache_summary(&levels, &unique_caches);
827 if (status != 0) {
828 printk(KERN_ERR "%s: ia64_pal_cache_summary() failed (status=%ld)\n",
829 __FUNCTION__, status);
830 max = SMP_CACHE_BYTES;
831 /* Safest setup for "flush_icache_range()" */
832 ia64_i_cache_stride_shift = I_CACHE_STRIDE_SHIFT;
833 goto out;
834 }
836 for (l = 0; l < levels; ++l) {
837 status = ia64_pal_cache_config_info(l, /* cache_type (data_or_unified)= */ 2,
838 &cci);
839 if (status != 0) {
840 printk(KERN_ERR
841 "%s: ia64_pal_cache_config_info(l=%lu, 2) failed (status=%ld)\n",
842 __FUNCTION__, l, status);
843 max = SMP_CACHE_BYTES;
844 /* The safest setup for "flush_icache_range()" */
845 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
846 cci.pcci_unified = 1;
847 }
848 line_size = 1 << cci.pcci_line_size;
849 if (line_size > max)
850 max = line_size;
851 if (cache_size < cci.pcci_cache_size)
852 cache_size = cci.pcci_cache_size;
853 if (!cci.pcci_unified) {
854 status = ia64_pal_cache_config_info(l,
855 /* cache_type (instruction)= */ 1,
856 &cci);
857 if (status != 0) {
858 printk(KERN_ERR
859 "%s: ia64_pal_cache_config_info(l=%lu, 1) failed (status=%ld)\n",
860 __FUNCTION__, l, status);
861 /* The safest setup for "flush_icache_range()" */
862 cci.pcci_stride = I_CACHE_STRIDE_SHIFT;
863 }
864 }
865 if (cci.pcci_stride < ia64_i_cache_stride_shift)
866 ia64_i_cache_stride_shift = cci.pcci_stride;
867 }
868 out:
869 #ifdef CONFIG_SMP
870 max_cache_size = max(max_cache_size, cache_size);
871 #endif
872 if (max > ia64_max_cacheline_size)
873 ia64_max_cacheline_size = max;
874 }
876 /*
877 * cpu_init() initializes state that is per-CPU. This function acts
878 * as a 'CPU state barrier', nothing should get across.
879 */
880 void __cpuinit
881 cpu_init (void)
882 {
883 extern void __cpuinit ia64_mmu_init (void *);
884 unsigned long num_phys_stacked;
885 pal_vm_info_2_u_t vmi;
886 unsigned int max_ctx;
887 struct cpuinfo_ia64 *cpu_info;
888 void *cpu_data;
890 cpu_data = per_cpu_init();
892 /*
893 * We set ar.k3 so that assembly code in MCA handler can compute
894 * physical addresses of per cpu variables with a simple:
895 * phys = ar.k3 + &per_cpu_var
896 */
897 ia64_set_kr(IA64_KR_PER_CPU_DATA,
898 ia64_tpa(cpu_data) - (long) __per_cpu_start);
900 get_max_cacheline_size();
902 /*
903 * We can't pass "local_cpu_data" to identify_cpu() because we haven't called
904 * ia64_mmu_init() yet. And we can't call ia64_mmu_init() first because it
905 * depends on the data returned by identify_cpu(). We break the dependency by
906 * accessing cpu_data() through the canonical per-CPU address.
907 */
908 cpu_info = cpu_data + ((char *) &__ia64_per_cpu_var(cpu_info) - __per_cpu_start);
909 identify_cpu(cpu_info);
911 #ifdef CONFIG_MCKINLEY
912 {
913 # define FEATURE_SET 16
914 struct ia64_pal_retval iprv;
916 if (cpu_info->family == 0x1f) {
917 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, FEATURE_SET, 0);
918 if ((iprv.status == 0) && (iprv.v0 & 0x80) && (iprv.v2 & 0x80))
919 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES,
920 (iprv.v1 | 0x80), FEATURE_SET, 0);
921 }
922 }
923 #endif
925 /* Clear the stack memory reserved for pt_regs: */
926 memset(task_pt_regs(current), 0, sizeof(struct pt_regs));
928 ia64_set_kr(IA64_KR_FPU_OWNER, 0);
930 /*
931 * Initialize the page-table base register to a global
932 * directory with all zeroes. This ensure that we can handle
933 * TLB-misses to user address-space even before we created the
934 * first user address-space. This may happen, e.g., due to
935 * aggressive use of lfetch.fault.
936 */
937 ia64_set_kr(IA64_KR_PT_BASE, __pa(ia64_imva(empty_zero_page)));
939 /*
940 * Initialize default control register to defer speculative faults except
941 * for those arising from TLB misses, which are not deferred. The
942 * kernel MUST NOT depend on a particular setting of these bits (in other words,
943 * the kernel must have recovery code for all speculative accesses). Turn on
944 * dcr.lc as per recommendation by the architecture team. Most IA-32 apps
945 * shouldn't be affected by this (moral: keep your ia32 locks aligned and you'll
946 * be fine).
947 */
948 ia64_setreg(_IA64_REG_CR_DCR, ( IA64_DCR_DP | IA64_DCR_DK | IA64_DCR_DX | IA64_DCR_DR
949 | IA64_DCR_DA | IA64_DCR_DD | IA64_DCR_LC));
950 atomic_inc(&init_mm.mm_count);
951 current->active_mm = &init_mm;
952 if (current->mm)
953 BUG();
955 ia64_mmu_init(ia64_imva(cpu_data));
956 ia64_mca_cpu_init(ia64_imva(cpu_data));
958 #ifdef CONFIG_IA32_SUPPORT
959 ia32_cpu_init();
960 #endif
962 /* Clear ITC to eliminiate sched_clock() overflows in human time. */
963 ia64_set_itc(0);
965 /* disable all local interrupt sources: */
966 ia64_set_itv(1 << 16);
967 ia64_set_lrr0(1 << 16);
968 ia64_set_lrr1(1 << 16);
969 ia64_setreg(_IA64_REG_CR_PMV, 1 << 16);
970 ia64_setreg(_IA64_REG_CR_CMCV, 1 << 16);
972 /* clear TPR & XTP to enable all interrupt classes: */
973 ia64_setreg(_IA64_REG_CR_TPR, 0);
974 #ifdef CONFIG_SMP
975 normal_xtp();
976 #endif
978 /* set ia64_ctx.max_rid to the maximum RID that is supported by all CPUs: */
979 if (ia64_pal_vm_summary(NULL, &vmi) == 0)
980 max_ctx = (1U << (vmi.pal_vm_info_2_s.rid_size - 3)) - 1;
981 else {
982 printk(KERN_WARNING "cpu_init: PAL VM summary failed, assuming 18 RID bits\n");
983 max_ctx = (1U << 15) - 1; /* use architected minimum */
984 }
985 while (max_ctx < ia64_ctx.max_ctx) {
986 unsigned int old = ia64_ctx.max_ctx;
987 if (cmpxchg(&ia64_ctx.max_ctx, old, max_ctx) == old)
988 break;
989 }
991 if (ia64_pal_rse_info(&num_phys_stacked, NULL) != 0) {
992 printk(KERN_WARNING "cpu_init: PAL RSE info failed; assuming 96 physical "
993 "stacked regs\n");
994 num_phys_stacked = 96;
995 }
996 /* size of physical stacked register partition plus 8 bytes: */
997 __get_cpu_var(ia64_phys_stacked_size_p8) = num_phys_stacked*8 + 8;
998 platform_cpu_init();
999 #ifdef CONFIG_XEN
1000 if (is_running_on_xen() && !ia64_platform_is("xen")) {
1001 extern ia64_mv_cpu_init_t xen_cpu_init;
1002 xen_cpu_init();
1004 #endif
1006 pm_idle = default_idle;
1009 /*
1010 * On SMP systems, when the scheduler does migration-cost autodetection,
1011 * it needs a way to flush as much of the CPU's caches as possible.
1012 */
1013 void sched_cacheflush(void)
1015 ia64_sal_cache_flush(3);
1018 void __init
1019 check_bugs (void)
1021 ia64_patch_mckinley_e9((unsigned long) __start___mckinley_e9_bundles,
1022 (unsigned long) __end___mckinley_e9_bundles);
1025 static int __init run_dmi_scan(void)
1027 dmi_scan_machine();
1028 return 0;
1030 core_initcall(run_dmi_scan);