ia64/xen-unstable

view tools/misc/cpuperf/p4perf.h @ 6422:e24fd7012ffb

merge?
author cl349@firebug.cl.cam.ac.uk
date Thu Aug 25 10:09:39 2005 +0000 (2005-08-25)
parents cfee4c4a8ed6
children
line source
1 /*
2 * P4 Performance counter stuff.
3 *
4 * P4 Xeon with Hyperthreading has counters per physical package which can
5 * count events from either logical CPU. However, in many cases more than
6 * ECSR and CCCR/counter can be used to count the same event. For instr or
7 * uops retired, use either ESCR0/IQ_CCCR0 ESCR1/IQ_CCCR2.
8 *
9 * $Id: p4perf.h,v 1.2 2003/10/13 16:51:41 jrb44 Exp $
10 *
11 * $Log: p4perf.h,v $
12 * Revision 1.2 2003/10/13 16:51:41 jrb44
13 * *** empty log message ***
14 *
15 */
17 #ifndef P4PERF_H
18 #define P4PERF_H
20 #ifdef __KERNEL__
21 #include <asm/msr.h>
22 #endif
24 /*****************************************************************************
25 * Performance counter configuration. *
26 *****************************************************************************/
28 #ifndef P6_EVNTSEL_OS
29 # define P6_EVNTSEL_OS (1 << 17)
30 # define P6_EVNTSEL_USR (1 << 16)
31 # define P6_EVNTSEL_E (1 << 18)
32 # define P6_EVNTSEL_EN (1 << 22)
33 #endif
34 #define P6_PERF_INST_RETIRED 0xc0
35 #define P6_PERF_UOPS_RETIRED 0xc2
37 #define P4_ESCR_USR (1 << 2)
38 #define P4_ESCR_OS (1 << 3)
39 #define P4_ESCR_T0_USR (1 << 2) /* First logical CPU */
40 #define P4_ESCR_T0_OS (1 << 3)
41 #define P4_ESCR_T1_USR (1 << 0) /* Second logical CPU */
42 #define P4_ESCR_T1_OS (1 << 1)
43 #define P4_ESCR_TE (1 << 4)
44 #define P4_ESCR_THREADS(t) (t)
45 #define P4_ESCR_TV(tag) (tag << 5)
46 #define P4_ESCR_EVNTSEL(e) (e << 25)
47 #define P4_ESCR_EVNTMASK(e) (e << 9)
49 #define P4_ESCR_EVNTSEL_FRONT_END 0x08
50 #define P4_ESCR_EVNTSEL_EXECUTION 0x0c
51 #define P4_ESCR_EVNTSEL_REPLAY 0x09
52 #define P4_ESCR_EVNTSEL_INSTR_RETIRED 0x02
53 #define P4_ESCR_EVNTSEL_UOPS_RETIRED 0x01
54 #define P4_ESCR_EVNTSEL_UOP_TYPE 0x02
55 #define P4_ESCR_EVNTSEL_RET_MBR_TYPE 0x05
56 //#define P4_ESCR_EVNTSEL_RET_MBR_TYPE 0x04
58 #define P4_ESCR_EVNTMASK_FE_NBOGUS 0x01
59 #define P4_ESCR_EVNTMASK_FE_BOGUS 0x02
61 #define P4_ESCR_EVNTMASK_EXEC_NBOGUS0 0x01
62 #define P4_ESCR_EVNTMASK_EXEC_NBOGUS1 0x02
63 #define P4_ESCR_EVNTMASK_EXEC_NBOGUS2 0x04
64 #define P4_ESCR_EVNTMASK_EXEC_NBOGUS3 0x08
65 #define P4_ESCR_EVNTMASK_EXEC_BOGUS0 0x10
66 #define P4_ESCR_EVNTMASK_EXEC_BOGUS1 0x20
67 #define P4_ESCR_EVNTMASK_EXEC_BOGUS2 0x40
68 #define P4_ESCR_EVNTMASK_EXEC_BOGUS3 0x80
70 #define P4_ESCR_EVNTMASK_REPLAY_NBOGUS 0x01
71 #define P4_ESCR_EVNTMASK_REPLAY_BOGUS 0x02
73 #define P4_ESCR_EVNTMASK_IRET_NB_NTAG 0x01
74 #define P4_ESCR_EVNTMASK_IRET_NB_TAG 0x02
75 #define P4_ESCR_EVNTMASK_IRET_B_NTAG 0x04
76 #define P4_ESCR_EVNTMASK_IRET_B_TAG 0x08
78 #define P4_ESCR_EVNTMASK_URET_NBOGUS 0x01
79 #define P4_ESCR_EVNTMASK_URET_BOGUS 0x02
81 #define P4_ESCR_EVNTMASK_UOP_LOADS 0x02
82 #define P4_ESCR_EVNTMASK_UOP_STORES 0x04
84 #define P4_ESCR_EVNTMASK_RMBRT_COND 0x02
85 #define P4_ESCR_EVNTMASK_RMBRT_CALL 0x04
86 #define P4_ESCR_EVNTMASK_RMBRT_RETURN 0x08
87 #define P4_ESCR_EVNTMASK_RMBRT_INDIR 0x10
89 #define P4_ESCR_EVNTMASK_RBRT_COND 0x02
90 #define P4_ESCR_EVNTMASK_RBRT_CALL 0x04
91 #define P4_ESCR_EVNTMASK_RBRT_RETURN 0x08
92 #define P4_ESCR_EVNTMASK_RBRT_INDIR 0x10
94 //#define P4_ESCR_EVNTMASK_INSTR_RETIRED 0x01 /* Non bogus, not tagged */
95 //#define P4_ESCR_EVNTMASK_UOPS_RETIRED 0x01 /* Non bogus */
97 #define P4_CCCR_OVF (1 << 31)
98 #define P4_CCCR_CASCADE (1 << 30)
99 #define P4_CCCR_FORCE_OVF (1 << 25)
100 #define P4_CCCR_EDGE (1 << 24)
101 #define P4_CCCR_COMPLEMENT (1 << 19)
102 #define P4_CCCR_COMPARE (1 << 18)
103 #define P4_CCCR_THRESHOLD(t) (t << 20)
104 #define P4_CCCR_ENABLE (1 << 12)
105 #define P4_CCCR_ESCR(escr) (escr << 13)
106 #define P4_CCCR_ACTIVE_THREAD(t) (t << 16) /* Set to 11 */
107 #define P4_CCCR_OVF_PMI_T0 (1 << 26)
108 #define P4_CCCR_OVF_PMI_T1 (1 << 27)
109 #define P4_CCCR_RESERVED (3 << 16)
110 #define P4_CCCR_OVF_PMI (1 << 26)
112 // BPU
113 #define MSR_P4_BPU_COUNTER0 0x300
114 #define MSR_P4_BPU_COUNTER1 0x301
115 #define MSR_P4_BPU_CCCR0 0x360
116 #define MSR_P4_BPU_CCCR1 0x361
118 #define MSR_P4_BPU_COUNTER2 0x302
119 #define MSR_P4_BPU_COUNTER3 0x303
120 #define MSR_P4_BPU_CCCR2 0x362
121 #define MSR_P4_BPU_CCCR3 0x363
123 #define MSR_P4_BSU_ESCR0 0x3a0
124 #define MSR_P4_FSB_ESCR0 0x3a2
125 #define MSR_P4_MOB_ESCR0 0x3aa
126 #define MSR_P4_PMH_ESCR0 0x3ac
127 #define MSR_P4_BPU_ESCR0 0x3b2
128 #define MSR_P4_IS_ESCR0 0x3b4
129 #define MSR_P4_ITLB_ESCR0 0x3b6
130 #define MSR_P4_IX_ESCR0 0x3c8
132 #define P4_BSU_ESCR0_NUMBER 7
133 #define P4_FSB_ESCR0_NUMBER 6
134 #define P4_MOB_ESCR0_NUMBER 2
135 #define P4_PMH_ESCR0_NUMBER 4
136 #define P4_BPU_ESCR0_NUMBER 0
137 #define P4_IS_ESCR0_NUMBER 1
138 #define P4_ITLB_ESCR0_NUMBER 3
139 #define P4_IX_ESCR0_NUMBER 5
141 #define MSR_P4_BSU_ESCR1 0x3a1
142 #define MSR_P4_FSB_ESCR1 0x3a3
143 #define MSR_P4_MOB_ESCR1 0x3ab
144 #define MSR_P4_PMH_ESCR1 0x3ad
145 #define MSR_P4_BPU_ESCR1 0x3b3
146 #define MSR_P4_IS_ESCR1 0x3b5
147 #define MSR_P4_ITLB_ESCR1 0x3b7
148 #define MSR_P4_IX_ESCR1 0x3c9
150 #define P4_BSU_ESCR1_NUMBER 7
151 #define P4_FSB_ESCR1_NUMBER 6
152 #define P4_MOB_ESCR1_NUMBER 2
153 #define P4_PMH_ESCR1_NUMBER 4
154 #define P4_BPU_ESCR1_NUMBER 0
155 #define P4_IS_ESCR1_NUMBER 1
156 #define P4_ITLB_ESCR1_NUMBER 3
157 #define P4_IX_ESCR1_NUMBER 5
159 // MS
160 #define MSR_P4_MS_COUNTER0 0x304
161 #define MSR_P4_MS_COUNTER1 0x305
162 #define MSR_P4_MS_CCCR0 0x364
163 #define MSR_P4_MS_CCCR1 0x365
165 #define MSR_P4_MS_COUNTER2 0x306
166 #define MSR_P4_MS_COUNTER3 0x307
167 #define MSR_P4_MS_CCCR2 0x366
168 #define MSR_P4_MS_CCCR3 0x367
170 #define MSR_P4_MS_ESCR0 0x3c0
171 #define MSR_P4_TBPU_ESCR0 0x3c2
172 #define MSR_P4_TC_ESCR0 0x3c4
174 #define P4_MS_ESCR0_NUMBER 0
175 #define P4_TBPU_ESCR0_NUMBER 2
176 #define P4_TC_ESCR0_NUMBER 1
178 #define MSR_P4_MS_ESCR1 0x3c1
179 #define MSR_P4_TBPU_ESCR1 0x3c3
180 #define MSR_P4_TC_ESCR1 0x3c5
182 #define P4_MS_ESCR1_NUMBER 0
183 #define P4_TBPU_ESCR1_NUMBER 2
184 #define P4_TC_ESCR1_NUMBER 1
186 // FLAME
187 #define MSR_P4_FLAME_COUNTER0 0x308
188 #define MSR_P4_FLAME_COUNTER1 0x309
189 #define MSR_P4_FLAME_CCCR0 0x368
190 #define MSR_P4_FLAME_CCCR1 0x369
192 #define MSR_P4_FLAME_COUNTER2 0x30a
193 #define MSR_P4_FLAME_COUNTER3 0x30b
194 #define MSR_P4_FLAME_CCCR2 0x36a
195 #define MSR_P4_FLAME_CCCR3 0x36b
197 #define MSR_P4_FIRM_ESCR0 0x3a4
198 #define MSR_P4_FLAME_ESCR0 0x3a6
199 #define MSR_P4_DAC_ESCR0 0x3a8
200 #define MSR_P4_SAAT_ESCR0 0x3ae
201 #define MSR_P4_U2L_ESCR0 0x3b0
203 #define P4_FIRM_ESCR0_NUMBER 1
204 #define P4_FLAME_ESCR0_NUMBER 0
205 #define P4_DAC_ESCR0_NUMBER 5
206 #define P4_SAAT_ESCR0_NUMBER 2
207 #define P4_U2L_ESCR0_NUMBER 3
209 #define MSR_P4_FIRM_ESCR1 0x3a5
210 #define MSR_P4_FLAME_ESCR1 0x3a7
211 #define MSR_P4_DAC_ESCR1 0x3a9
212 #define MSR_P4_SAAT_ESCR1 0x3af
213 #define MSR_P4_U2L_ESCR1 0x3b1
215 #define P4_FIRM_ESCR1_NUMBER 1
216 #define P4_FLAME_ESCR1_NUMBER 0
217 #define P4_DAC_ESCR1_NUMBER 5
218 #define P4_SAAT_ESCR1_NUMBER 2
219 #define P4_U2L_ESCR1_NUMBER 3
221 // IQ
222 #define MSR_P4_IQ_COUNTER0 0x30c
223 #define MSR_P4_IQ_COUNTER1 0x30d
224 #define MSR_P4_IQ_CCCR0 0x36c
225 #define MSR_P4_IQ_CCCR1 0x36d
227 #define MSR_P4_IQ_COUNTER2 0x30e
228 #define MSR_P4_IQ_COUNTER3 0x30f
229 #define MSR_P4_IQ_CCCR2 0x36e
230 #define MSR_P4_IQ_CCCR3 0x36f
232 #define MSR_P4_IQ_COUNTER4 0x310
233 #define MSR_P4_IQ_COUNTER5 0x311
234 #define MSR_P4_IQ_CCCR4 0x370
235 #define MSR_P4_IQ_CCCR5 0x371
237 #define MSR_P4_CRU_ESCR0 0x3b8
238 #define MSR_P4_CRU_ESCR2 0x3cc
239 #define MSR_P4_CRU_ESCR4 0x3e0
240 #define MSR_P4_IQ_ESCR0 0x3ba
241 #define MSR_P4_RAT_ESCR0 0x3bc
242 #define MSR_P4_SSU_ESCR0 0x3be
243 #define MSR_P4_ALF_ESCR0 0x3ca
245 #define P4_CRU_ESCR0_NUMBER 4
246 #define P4_CRU_ESCR2_NUMBER 5
247 #define P4_CRU_ESCR4_NUMBER 6
248 #define P4_IQ_ESCR0_NUMBER 0
249 #define P4_RAT_ESCR0_NUMBER 2
250 #define P4_SSU_ESCR0_NUMBER 3
251 #define P4_ALF_ESCR0_NUMBER 1
253 #define MSR_P4_CRU_ESCR1 0x3b9
254 #define MSR_P4_CRU_ESCR3 0x3cd
255 #define MSR_P4_CRU_ESCR5 0x3e1
256 #define MSR_P4_IQ_ESCR1 0x3bb
257 #define MSR_P4_RAT_ESCR1 0x3bd
258 #define MSR_P4_ALF_ESCR1 0x3cb
260 #define P4_CRU_ESCR1_NUMBER 4
261 #define P4_CRU_ESCR3_NUMBER 5
262 #define P4_CRU_ESCR5_NUMBER 6
263 #define P4_IQ_ESCR1_NUMBER 0
264 #define P4_RAT_ESCR1_NUMBER 2
265 #define P4_ALF_ESCR1_NUMBER 1
267 #define P4_BPU_COUNTER0_NUMBER 0
268 #define P4_BPU_COUNTER1_NUMBER 1
269 #define P4_BPU_COUNTER2_NUMBER 2
270 #define P4_BPU_COUNTER3_NUMBER 3
272 #define P4_MS_COUNTER0_NUMBER 4
273 #define P4_MS_COUNTER1_NUMBER 5
274 #define P4_MS_COUNTER2_NUMBER 6
275 #define P4_MS_COUNTER3_NUMBER 7
277 #define P4_FLAME_COUNTER0_NUMBER 8
278 #define P4_FLAME_COUNTER1_NUMBER 9
279 #define P4_FLAME_COUNTER2_NUMBER 10
280 #define P4_FLAME_COUNTER3_NUMBER 11
282 #define P4_IQ_COUNTER0_NUMBER 12
283 #define P4_IQ_COUNTER1_NUMBER 13
284 #define P4_IQ_COUNTER2_NUMBER 14
285 #define P4_IQ_COUNTER3_NUMBER 15
286 #define P4_IQ_COUNTER4_NUMBER 16
287 #define P4_IQ_COUNTER5_NUMBER 17
289 /* PEBS
290 */
291 #define MSR_P4_PEBS_ENABLE 0x3F1
292 #define MSR_P4_PEBS_MATRIX_VERT 0x3F2
294 #define P4_PEBS_ENABLE_MY_THR (1 << 25)
295 #define P4_PEBS_ENABLE_OTH_THR (1 << 26)
296 #define P4_PEBS_ENABLE (1 << 24)
297 #define P4_PEBS_BIT0 (1 << 0)
298 #define P4_PEBS_BIT1 (1 << 1)
299 #define P4_PEBS_BIT2 (1 << 2)
301 #define P4_PEBS_MATRIX_VERT_BIT0 (1 << 0)
302 #define P4_PEBS_MATRIX_VERT_BIT1 (1 << 1)
303 #define P4_PEBS_MATRIX_VERT_BIT2 (1 << 2)
305 /* Replay tagging.
306 */
307 #define P4_REPLAY_TAGGING_PEBS_L1LMR P4_PEBS_BIT0
308 #define P4_REPLAY_TAGGING_PEBS_L2LMR P4_PEBS_BIT1
309 #define P4_REPLAY_TAGGING_PEBS_DTLMR P4_PEBS_BIT2
310 #define P4_REPLAY_TAGGING_PEBS_DTSMR P4_PEBS_BIT2
311 #define P4_REPLAY_TAGGING_PEBS_DTAMR P4_PEBS_BIT2
313 #define P4_REPLAY_TAGGING_VERT_L1LMR P4_PEBS_MATRIX_VERT_BIT0
314 #define P4_REPLAY_TAGGING_VERT_L2LMR P4_PEBS_MATRIX_VERT_BIT0
315 #define P4_REPLAY_TAGGING_VERT_DTLMR P4_PEBS_MATRIX_VERT_BIT0
316 #define P4_REPLAY_TAGGING_VERT_DTSMR P4_PEBS_MATRIX_VERT_BIT1
317 #define P4_REPLAY_TAGGING_VERT_DTAMR P4_PEBS_MATRIX_VERT_BIT0 | P4_PEBS_MATRIX_VERT_BIT1
322 /*****************************************************************************
323 * *
324 *****************************************************************************/
326 // x87_FP_uop
327 #define EVENT_SEL_x87_FP_uop 0x04
328 #define EVENT_MASK_x87_FP_uop_ALL (1 << 15)
330 // execution event (at retirement)
331 #define EVENT_SEL_execution_event 0x0C
333 // scalar_SP_uop
334 #define EVENT_SEL_scalar_SP_uop 0x0a
335 #define EVENT_MASK_scalar_SP_uop_ALL (1 << 15)
337 // scalar_DP_uop
338 #define EVENT_SEL_scalar_DP_uop 0x0e
339 #define EVENT_MASK_scalar_DP_uop_ALL (1 << 15)
341 // Instruction retired
342 #define EVENT_SEL_instr_retired 0x02
343 #define EVENT_MASK_instr_retired_ALL 0x0f
345 // uOps retired
346 #define EVENT_SEL_uops_retired 0x01
347 #define EVENT_MASK_uops_retired_ALL 0x03
349 // L1 misses retired
350 #define EVENT_SEL_replay_event 0x09
351 #define EVENT_MASK_replay_event_ALL 0x03
353 // Trace cache
354 #define EVENT_SEL_BPU_fetch_request 0x03
355 #define EVENT_MASK_BPU_fetch_request_TCMISS 0x01
357 // Bus activity
358 #define EVENT_SEL_FSB_data_activity 0x17
359 #define EVENT_MASK_FSB_data_activity_DRDY_DRV 0x01
360 #define EVENT_MASK_FSB_data_activity_DRDY_OWN 0x02
361 #define EVENT_MASK_FSB_data_activity_DRDY_OOTHER 0x04
362 #define EVENT_MASK_FSB_data_activity_DBSY_DRV 0x08
363 #define EVENT_MASK_FSB_data_activity_DBSY_OWN 0x10
364 #define EVENT_MASK_FSB_data_activity_DBSY_OOTHER 0x20
366 // Cache L2
367 #define EVENT_SEL_BSQ_cache_reference 0x0c
368 #define EVENT_MASK_BSQ_cache_reference_RD_L2_HITS 0x001
369 #define EVENT_MASK_BSQ_cache_reference_RD_L2_HITE 0x002
370 #define EVENT_MASK_BSQ_cache_reference_RD_L2_HITM 0x004
372 #define EVENT_MASK_BSQ_cache_reference_RD_L3_HITS 0x008
373 #define EVENT_MASK_BSQ_cache_reference_RD_L3_HITE 0x010
374 #define EVENT_MASK_BSQ_cache_reference_RD_L3_HITM 0x020
376 #define EVENT_MASK_BSQ_cache_reference_RD_L2_MISS 0x100
377 #define EVENT_MASK_BSQ_cache_reference_RD_L3_MISS 0x200
378 #define EVENT_MASK_BSQ_cache_reference_WR_L2_MISS 0x400
380 #endif
382 /* End of $RCSfile: p4perf.h,v $ */