ia64/xen-unstable

view xen/arch/ia64/vmx/vmx_process.c @ 13900:dea561992abe

[IA64] Avoid recursively walking guest short VHPT

Signed-off-by: Anthony Xu <anthony.xu@intel.com>
author awilliam@xenbuild2.aw
date Mon Feb 12 09:54:20 2007 -0700 (2007-02-12)
parents b3ae332e6dbd
children 6c938630de54
line source
1 /* -*- Mode:C; c-basic-offset:4; tab-width:4; indent-tabs-mode:nil -*- */
2 /*
3 * vmx_process.c: handling VMX architecture-related VM exits
4 * Copyright (c) 2005, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
17 * Place - Suite 330, Boston, MA 02111-1307 USA.
18 *
19 * Xiaoyan Feng (Fleming Feng) <fleming.feng@intel.com>
20 * Xuefei Xu (Anthony Xu) (Anthony.xu@intel.com)
21 */
23 #include <xen/config.h>
24 #include <xen/lib.h>
25 #include <xen/errno.h>
26 #include <xen/sched.h>
27 #include <xen/smp.h>
28 #include <asm/ptrace.h>
29 #include <xen/delay.h>
31 #include <linux/efi.h> /* FOR EFI_UNIMPLEMENTED */
32 #include <asm/sal.h> /* FOR struct ia64_sal_retval */
34 #include <asm/system.h>
35 #include <asm/io.h>
36 #include <asm/processor.h>
37 #include <asm/desc.h>
38 #include <asm/vlsapic.h>
39 #include <xen/irq.h>
40 #include <xen/event.h>
41 #include <asm/regionreg.h>
42 #include <asm/privop.h>
43 #include <asm/ia64_int.h>
44 #include <asm/debugger.h>
45 //#include <asm/hpsim_ssc.h>
46 #include <asm/dom_fw.h>
47 #include <asm/vmx_vcpu.h>
48 #include <asm/kregs.h>
49 #include <asm/vmx.h>
50 #include <asm/vmmu.h>
51 #include <asm/vmx_mm_def.h>
52 #include <asm/vmx_phy_mode.h>
53 #include <xen/mm.h>
54 #include <asm/vmx_pal.h>
55 /* reset all PSR field to 0, except up,mfl,mfh,pk,dt,rt,mc,it */
56 #define INITIAL_PSR_VALUE_AT_INTERRUPTION 0x0000001808028034
59 extern void die_if_kernel(char *str, struct pt_regs *regs, long err);
60 extern void rnat_consumption (VCPU *vcpu);
61 extern void alt_itlb (VCPU *vcpu, u64 vadr);
62 extern void itlb_fault (VCPU *vcpu, u64 vadr);
63 extern void ivhpt_fault (VCPU *vcpu, u64 vadr);
64 extern unsigned long handle_fpu_swa (int fp_fault, struct pt_regs *regs, unsigned long isr);
66 #define DOMN_PAL_REQUEST 0x110000
67 #define DOMN_SAL_REQUEST 0x110001
69 static u64 vec2off[68] = {0x0,0x400,0x800,0xc00,0x1000,0x1400,0x1800,
70 0x1c00,0x2000,0x2400,0x2800,0x2c00,0x3000,0x3400,0x3800,0x3c00,0x4000,
71 0x4400,0x4800,0x4c00,0x5000,0x5100,0x5200,0x5300,0x5400,0x5500,0x5600,
72 0x5700,0x5800,0x5900,0x5a00,0x5b00,0x5c00,0x5d00,0x5e00,0x5f00,0x6000,
73 0x6100,0x6200,0x6300,0x6400,0x6500,0x6600,0x6700,0x6800,0x6900,0x6a00,
74 0x6b00,0x6c00,0x6d00,0x6e00,0x6f00,0x7000,0x7100,0x7200,0x7300,0x7400,
75 0x7500,0x7600,0x7700,0x7800,0x7900,0x7a00,0x7b00,0x7c00,0x7d00,0x7e00,
76 0x7f00
77 };
81 void vmx_reflect_interruption(u64 ifa, u64 isr, u64 iim,
82 u64 vec, REGS *regs)
83 {
84 u64 status, vector;
85 VCPU *vcpu = current;
86 u64 vpsr = VCPU(vcpu, vpsr);
88 vector = vec2off[vec];
89 if(!(vpsr&IA64_PSR_IC)&&(vector!=IA64_DATA_NESTED_TLB_VECTOR)){
90 panic_domain(regs, "Guest nested fault vector=%lx!\n", vector);
91 }
93 switch (vec) {
95 case 25: // IA64_DISABLED_FPREG_VECTOR
97 if (FP_PSR(vcpu) & IA64_PSR_DFH) {
98 FP_PSR(vcpu) = IA64_PSR_MFH;
99 if (__ia64_per_cpu_var(fp_owner) != vcpu)
100 __ia64_load_fpu(vcpu->arch._thread.fph);
101 }
102 if (!(VCPU(vcpu, vpsr) & IA64_PSR_DFH)) {
103 regs->cr_ipsr &= ~IA64_PSR_DFH;
104 return;
105 }
107 break;
109 case 32: // IA64_FP_FAULT_VECTOR
110 // handle fpswa emulation
111 // fp fault
112 status = handle_fpu_swa(1, regs, isr);
113 if (!status) {
114 vcpu_increment_iip(vcpu);
115 return;
116 } else if (IA64_RETRY == status)
117 return;
118 break;
120 case 33: // IA64_FP_TRAP_VECTOR
121 //fp trap
122 status = handle_fpu_swa(0, regs, isr);
123 if (!status)
124 return;
125 else if (IA64_RETRY == status) {
126 vcpu_decrement_iip(vcpu);
127 return;
128 }
129 break;
131 }
132 VCPU(vcpu,isr)=isr;
133 VCPU(vcpu,iipa) = regs->cr_iip;
134 if (vector == IA64_BREAK_VECTOR || vector == IA64_SPECULATION_VECTOR)
135 VCPU(vcpu,iim) = iim;
136 else {
137 set_ifa_itir_iha(vcpu,ifa,1,1,1);
138 }
139 inject_guest_interruption(vcpu, vector);
140 }
143 IA64FAULT
144 vmx_ia64_handle_break (unsigned long ifa, struct pt_regs *regs, unsigned long isr, unsigned long iim)
145 {
146 struct domain *d = current->domain;
147 struct vcpu *v = current;
149 perfc_incrc(vmx_ia64_handle_break);
150 #ifdef CRASH_DEBUG
151 if ((iim == 0 || iim == CDB_BREAK_NUM) && !user_mode(regs) &&
152 IS_VMM_ADDRESS(regs->cr_iip)) {
153 if (iim == 0)
154 show_registers(regs);
155 debugger_trap_fatal(0 /* don't care */, regs);
156 } else
157 #endif
158 {
159 if (iim == 0)
160 vmx_die_if_kernel("Break 0 in Hypervisor.", regs, iim);
162 if (!user_mode(regs)) {
163 /* Allow hypercalls only when cpl = 0. */
164 if (iim == d->arch.breakimm) {
165 ia64_hypercall(regs);
166 vcpu_increment_iip(v);
167 return IA64_NO_FAULT;
168 }
169 else if(iim == DOMN_PAL_REQUEST){
170 pal_emul(v);
171 vcpu_increment_iip(v);
172 return IA64_NO_FAULT;
173 }else if(iim == DOMN_SAL_REQUEST){
174 sal_emul(v);
175 vcpu_increment_iip(v);
176 return IA64_NO_FAULT;
177 }
178 }
179 vmx_reflect_interruption(ifa,isr,iim,11,regs);
180 }
181 return IA64_NO_FAULT;
182 }
185 void save_banked_regs_to_vpd(VCPU *v, REGS *regs)
186 {
187 unsigned long i=0UL, * src,* dst, *sunat, *dunat;
188 IA64_PSR vpsr;
189 src=&regs->r16;
190 sunat=&regs->eml_unat;
191 vpsr.val = VCPU(v, vpsr);
192 if(vpsr.bn){
193 dst = &VCPU(v, vgr[0]);
194 dunat =&VCPU(v, vnat);
195 __asm__ __volatile__ (";;extr.u %0 = %1,%4,16;; \
196 dep %2 = %0, %2, 0, 16;; \
197 st8 [%3] = %2;;"
198 ::"r"(i),"r"(*sunat),"r"(*dunat),"r"(dunat),"i"(IA64_PT_REGS_R16_SLOT):"memory");
200 }else{
201 dst = &VCPU(v, vbgr[0]);
202 // dunat =&VCPU(v, vbnat);
203 // __asm__ __volatile__ (";;extr.u %0 = %1,%4,16;;
204 // dep %2 = %0, %2, 16, 16;;
205 // st8 [%3] = %2;;"
206 // ::"r"(i),"r"(*sunat),"r"(*dunat),"r"(dunat),"i"(IA64_PT_REGS_R16_SLOT):"memory");
208 }
209 for(i=0; i<16; i++)
210 *dst++ = *src++;
211 }
214 // ONLY gets called from ia64_leave_kernel
215 // ONLY call with interrupts disabled?? (else might miss one?)
216 // NEVER successful if already reflecting a trap/fault because psr.i==0
217 void leave_hypervisor_tail(void)
218 {
219 struct domain *d = current->domain;
220 struct vcpu *v = current;
222 // FIXME: Will this work properly if doing an RFI???
223 if (!is_idle_domain(d) ) { // always comes from guest
224 // struct pt_regs *user_regs = vcpu_regs(current);
225 local_irq_enable();
226 do_softirq();
227 local_irq_disable();
229 if (v->vcpu_id == 0) {
230 unsigned long callback_irq =
231 d->arch.hvm_domain.params[HVM_PARAM_CALLBACK_IRQ];
232 /*
233 * val[63:56] == 1: val[55:0] is a delivery PCI INTx line:
234 * Domain = val[47:32], Bus = val[31:16],
235 * DevFn = val[15: 8], IntX = val[ 1: 0]
236 * val[63:56] == 0: val[55:0] is a delivery as GSI
237 */
238 if (callback_irq != 0 && local_events_need_delivery()) {
239 /* change level for para-device callback irq */
240 /* use level irq to send discrete event */
241 if ((uint8_t)(callback_irq >> 56) == 1) {
242 /* case of using PCI INTx line as callback irq */
243 int pdev = (callback_irq >> 11) & 0x1f;
244 int pintx = callback_irq & 3;
245 viosapic_set_pci_irq(d, pdev, pintx, 1);
246 viosapic_set_pci_irq(d, pdev, pintx, 0);
247 } else {
248 /* case of using GSI as callback irq */
249 viosapic_set_irq(d, callback_irq, 1);
250 viosapic_set_irq(d, callback_irq, 0);
251 }
252 }
253 }
255 rmb();
256 if (xchg(&v->arch.irq_new_pending, 0)) {
257 v->arch.irq_new_condition = 0;
258 vmx_check_pending_irq(v);
259 return;
260 }
262 if (v->arch.irq_new_condition) {
263 v->arch.irq_new_condition = 0;
264 vhpi_detection(v);
265 }
266 }
267 }
269 extern ia64_rr vmx_vcpu_rr(VCPU *vcpu, u64 vadr);
271 static int vmx_handle_lds(REGS* regs)
272 {
273 regs->cr_ipsr |=IA64_PSR_ED;
274 return IA64_FAULT;
275 }
277 /* We came here because the H/W VHPT walker failed to find an entry */
278 IA64FAULT
279 vmx_hpw_miss(u64 vadr , u64 vec, REGS* regs)
280 {
281 IA64_PSR vpsr;
282 int type;
283 u64 vhpt_adr, gppa, pteval, rr, itir;
284 ISR misr;
285 PTA vpta;
286 thash_data_t *data;
287 VCPU *v = current;
289 vpsr.val = VCPU(v, vpsr);
290 misr.val = VMX(v,cr_isr);
292 if (vec == 1)
293 type = ISIDE_TLB;
294 else if (vec == 2)
295 type = DSIDE_TLB;
296 else
297 panic_domain(regs, "wrong vec:%lx\n", vec);
299 if(is_physical_mode(v)&&(!(vadr<<1>>62))){
300 if(vec==2){
301 if (v->domain != dom0
302 && __gpfn_is_io(v->domain, (vadr << 1) >> (PAGE_SHIFT + 1))) {
303 emulate_io_inst(v,((vadr<<1)>>1),4); // UC
304 return IA64_FAULT;
305 }
306 }
307 physical_tlb_miss(v, vadr, type);
308 return IA64_FAULT;
309 }
311 if((data=vtlb_lookup(v, vadr,type))!=0){
312 if (v->domain != dom0 && type == DSIDE_TLB) {
313 gppa = (vadr & ((1UL << data->ps) - 1)) +
314 (data->ppn >> (data->ps - 12) << data->ps);
315 if (__gpfn_is_io(v->domain, gppa >> PAGE_SHIFT)) {
316 if (data->pl >= ((regs->cr_ipsr >> IA64_PSR_CPL0_BIT) & 3))
317 emulate_io_inst(v, gppa, data->ma);
318 else {
319 vcpu_set_isr(v, misr.val);
320 data_access_rights(v, vadr);
321 }
322 return IA64_FAULT;
323 }
324 }
325 thash_vhpt_insert(v, data->page_flags, data->itir, vadr, type);
327 }else if(type == DSIDE_TLB){
329 if (misr.sp)
330 return vmx_handle_lds(regs);
332 if(!vhpt_enabled(v, vadr, misr.rs?RSE_REF:DATA_REF)){
333 if(vpsr.ic){
334 vcpu_set_isr(v, misr.val);
335 alt_dtlb(v, vadr);
336 return IA64_FAULT;
337 } else{
338 nested_dtlb(v);
339 return IA64_FAULT;
340 }
341 }
343 vmx_vcpu_get_pta(v, &vpta.val);
344 if (vpta.vf) {
345 /* Long format is not yet supported. */
346 if (vpsr.ic) {
347 vcpu_set_isr(v, misr.val);
348 dtlb_fault(v, vadr);
349 return IA64_FAULT;
350 } else {
351 nested_dtlb(v);
352 return IA64_FAULT;
353 }
354 }
356 /* avoid recursively walking (short format) VHPT */
357 if ((((vadr ^ vpta.val) << 3) >> (vpta.size + 3)) == 0) {
358 if (vpsr.ic) {
359 vcpu_set_isr(v, misr.val);
360 dtlb_fault(v, vadr);
361 return IA64_FAULT;
362 } else {
363 nested_dtlb(v);
364 return IA64_FAULT;
365 }
366 }
368 vmx_vcpu_thash(v, vadr, &vhpt_adr);
369 if (!guest_vhpt_lookup(vhpt_adr, &pteval)) {
370 /* VHPT successfully read. */
371 if (!(pteval & _PAGE_P)) {
372 if (vpsr.ic) {
373 vcpu_set_isr(v, misr.val);
374 dtlb_fault(v, vadr);
375 return IA64_FAULT;
376 } else {
377 nested_dtlb(v);
378 return IA64_FAULT;
379 }
380 } else if ((pteval & _PAGE_MA_MASK) != _PAGE_MA_ST) {
381 vcpu_get_rr(v, vadr, &rr);
382 itir = rr & (RR_RID_MASK | RR_PS_MASK);
383 thash_purge_and_insert(v, pteval, itir, vadr, DSIDE_TLB);
384 return IA64_NO_FAULT;
385 } else if (vpsr.ic) {
386 vcpu_set_isr(v, misr.val);
387 dtlb_fault(v, vadr);
388 return IA64_FAULT;
389 }else{
390 nested_dtlb(v);
391 return IA64_FAULT;
392 }
393 } else {
394 /* Can't read VHPT. */
395 if (vpsr.ic) {
396 vcpu_set_isr(v, misr.val);
397 dvhpt_fault(v, vadr);
398 return IA64_FAULT;
399 } else {
400 nested_dtlb(v);
401 return IA64_FAULT;
402 }
403 }
404 }else if(type == ISIDE_TLB){
406 if (!vpsr.ic)
407 misr.ni = 1;
408 if (!vhpt_enabled(v, vadr, INST_REF)) {
409 vcpu_set_isr(v, misr.val);
410 alt_itlb(v, vadr);
411 return IA64_FAULT;
412 }
414 vmx_vcpu_get_pta(v, &vpta.val);
415 if (vpta.vf) {
416 /* Long format is not yet supported. */
417 vcpu_set_isr(v, misr.val);
418 itlb_fault(v, vadr);
419 return IA64_FAULT;
420 }
423 vmx_vcpu_thash(v, vadr, &vhpt_adr);
424 if (!guest_vhpt_lookup(vhpt_adr, &pteval)) {
425 /* VHPT successfully read. */
426 if (pteval & _PAGE_P) {
427 vcpu_get_rr(v, vadr, &rr);
428 itir = rr & (RR_RID_MASK | RR_PS_MASK);
429 thash_purge_and_insert(v, pteval, itir, vadr, ISIDE_TLB);
430 return IA64_NO_FAULT;
431 } else {
432 vcpu_set_isr(v, misr.val);
433 inst_page_not_present(v, vadr);
434 return IA64_FAULT;
435 }
436 } else {
437 vcpu_set_isr(v, misr.val);
438 ivhpt_fault(v, vadr);
439 return IA64_FAULT;
440 }
441 }
442 return IA64_NO_FAULT;
443 }