ia64/xen-unstable

view xen/arch/x86/hvm/svm/svm.c @ 11682:dea06c7fd19d

[HVM][SVM] 64-bit Windows HVM guests require MCE/MCA CPUID bits to be present.
This SVM patch removes "masking off" of these bits for AMD-V HVM guests.
Signed-off-by: Tom Woller <thomas.woller@amd.com>=20
author kfraser@localhost.localdomain
date Fri Sep 29 11:21:02 2006 +0100 (2006-09-29)
parents 058f4a2a8642
children 82983c636549
line source
1 /*
2 * svm.c: handling SVM architecture-related VM exits
3 * Copyright (c) 2004, Intel Corporation.
4 * Copyright (c) 2005, AMD Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
17 * Place - Suite 330, Boston, MA 02111-1307 USA.
18 *
19 */
21 #include <xen/config.h>
22 #include <xen/init.h>
23 #include <xen/lib.h>
24 #include <xen/trace.h>
25 #include <xen/sched.h>
26 #include <xen/irq.h>
27 #include <xen/softirq.h>
28 #include <xen/hypercall.h>
29 #include <xen/domain_page.h>
30 #include <asm/current.h>
31 #include <asm/io.h>
32 #include <asm/shadow.h>
33 #include <asm/regs.h>
34 #include <asm/cpufeature.h>
35 #include <asm/processor.h>
36 #include <asm/types.h>
37 #include <asm/msr.h>
38 #include <asm/spinlock.h>
39 #include <asm/hvm/hvm.h>
40 #include <asm/hvm/support.h>
41 #include <asm/hvm/io.h>
42 #include <asm/hvm/svm/svm.h>
43 #include <asm/hvm/svm/vmcb.h>
44 #include <asm/hvm/svm/emulate.h>
45 #include <asm/hvm/svm/vmmcall.h>
46 #include <asm/hvm/svm/intr.h>
47 #include <asm/x86_emulate.h>
48 #include <public/sched.h>
50 #define SVM_EXTRA_DEBUG
52 #define set_segment_register(name, value) \
53 __asm__ __volatile__ ( "movw %%ax ,%%" STR(name) "" : : "a" (value) )
55 /* External functions. We should move these to some suitable header file(s) */
57 extern void do_nmi(struct cpu_user_regs *, unsigned long);
58 extern int inst_copy_from_guest(unsigned char *buf, unsigned long guest_eip,
59 int inst_len);
60 extern uint32_t vlapic_update_ppr(struct vlapic *vlapic);
61 extern asmlinkage void do_IRQ(struct cpu_user_regs *);
62 extern void send_pio_req(struct cpu_user_regs *regs, unsigned long port,
63 unsigned long count, int size, long value, int dir, int pvalid);
64 extern void svm_dump_inst(unsigned long eip);
65 extern int svm_dbg_on;
66 void svm_dump_regs(const char *from, struct cpu_user_regs *regs);
68 static void svm_relinquish_guest_resources(struct domain *d);
69 static int svm_do_vmmcall_reset_to_realmode(struct vcpu *v,
70 struct cpu_user_regs *regs);
72 /* va of hardware host save area */
73 static void *hsa[NR_CPUS] __read_mostly;
75 /* vmcb used for extended host state */
76 static void *root_vmcb[NR_CPUS] __read_mostly;
78 /* physical address of above for host VMSAVE/VMLOAD */
79 u64 root_vmcb_pa[NR_CPUS] __read_mostly;
82 /* ASID API */
83 enum {
84 ASID_AVAILABLE = 0,
85 ASID_INUSE,
86 ASID_RETIRED
87 };
88 #define INITIAL_ASID 0
89 #define ASID_MAX 64
91 struct asid_pool {
92 spinlock_t asid_lock;
93 u32 asid[ASID_MAX];
94 };
96 static DEFINE_PER_CPU(struct asid_pool, asid_pool);
99 /*
100 * Initializes the POOL of ASID used by the guests per core.
101 */
102 void asidpool_init(int core)
103 {
104 int i;
106 spin_lock_init(&per_cpu(asid_pool,core).asid_lock);
108 /* Host ASID is always in use */
109 per_cpu(asid_pool,core).asid[INITIAL_ASID] = ASID_INUSE;
110 for ( i = 1; i < ASID_MAX; i++ )
111 per_cpu(asid_pool,core).asid[i] = ASID_AVAILABLE;
112 }
115 /* internal function to get the next available ASID */
116 static int asidpool_fetch_next(struct vmcb_struct *vmcb, int core)
117 {
118 int i;
119 for ( i = 1; i < ASID_MAX; i++ )
120 {
121 if ( per_cpu(asid_pool,core).asid[i] == ASID_AVAILABLE )
122 {
123 vmcb->guest_asid = i;
124 per_cpu(asid_pool,core).asid[i] = ASID_INUSE;
125 return i;
126 }
127 }
128 return -1;
129 }
132 /*
133 * This functions assigns on the passed VMCB, the next
134 * available ASID number. If none are available, the
135 * TLB flush flag is set, and all retireds ASID
136 * are made available.
137 *
138 * Returns: 1 -- sucess;
139 * 0 -- failure -- no more ASID numbers
140 * available.
141 */
142 int asidpool_assign_next( struct vmcb_struct *vmcb, int retire_current,
143 int oldcore, int newcore )
144 {
145 int i;
146 int res = 1;
147 static unsigned long cnt=0;
149 spin_lock(&per_cpu(asid_pool,oldcore).asid_lock);
150 if( retire_current && vmcb->guest_asid ) {
151 per_cpu(asid_pool,oldcore).asid[vmcb->guest_asid & (ASID_MAX-1)] =
152 ASID_RETIRED;
153 }
154 spin_unlock(&per_cpu(asid_pool,oldcore).asid_lock);
155 spin_lock(&per_cpu(asid_pool,newcore).asid_lock);
156 if( asidpool_fetch_next( vmcb, newcore ) < 0 ) {
157 if (svm_dbg_on)
158 printk( "SVM: tlb(%ld)\n", cnt++ );
159 /* FLUSH the TLB and all retired slots are made available */
160 vmcb->tlb_control = 1;
161 for( i = 1; i < ASID_MAX; i++ ) {
162 if( per_cpu(asid_pool,newcore).asid[i] == ASID_RETIRED ) {
163 per_cpu(asid_pool,newcore).asid[i] = ASID_AVAILABLE;
164 }
165 }
166 /* Get the First slot available */
167 res = asidpool_fetch_next( vmcb, newcore ) > 0;
168 }
169 spin_unlock(&per_cpu(asid_pool,newcore).asid_lock);
170 return res;
171 }
173 void asidpool_retire( struct vmcb_struct *vmcb, int core )
174 {
175 spin_lock(&per_cpu(asid_pool,core).asid_lock);
176 if( vmcb->guest_asid ) {
177 per_cpu(asid_pool,core).asid[vmcb->guest_asid & (ASID_MAX-1)] =
178 ASID_RETIRED;
179 }
180 spin_unlock(&per_cpu(asid_pool,core).asid_lock);
181 }
183 static inline void svm_inject_exception(struct vcpu *v, int trap,
184 int ev, int error_code)
185 {
186 eventinj_t event;
187 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
189 event.bytes = 0;
190 event.fields.v = 1;
191 event.fields.type = EVENTTYPE_EXCEPTION;
192 event.fields.vector = trap;
193 event.fields.ev = ev;
194 event.fields.errorcode = error_code;
196 ASSERT(vmcb->eventinj.fields.v == 0);
198 vmcb->eventinj = event;
199 }
201 static void stop_svm(void)
202 {
203 u32 eax, edx;
204 int cpu = smp_processor_id();
206 /* We turn off the EFER_SVME bit. */
207 rdmsr(MSR_EFER, eax, edx);
208 eax &= ~EFER_SVME;
209 wrmsr(MSR_EFER, eax, edx);
211 /* release the HSA */
212 free_host_save_area(hsa[cpu]);
213 hsa[cpu] = NULL;
214 wrmsr(MSR_K8_VM_HSAVE_PA, 0, 0 );
216 /* free up the root vmcb */
217 free_vmcb(root_vmcb[cpu]);
218 root_vmcb[cpu] = NULL;
219 root_vmcb_pa[cpu] = 0;
221 printk("AMD SVM Extension is disabled.\n");
222 }
225 static void svm_store_cpu_guest_regs(
226 struct vcpu *v, struct cpu_user_regs *regs, unsigned long *crs)
227 {
228 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
230 if ( regs != NULL )
231 {
232 regs->eip = vmcb->rip;
233 regs->esp = vmcb->rsp;
234 regs->eflags = vmcb->rflags;
235 regs->cs = vmcb->cs.sel;
236 regs->ds = vmcb->ds.sel;
237 regs->es = vmcb->es.sel;
238 regs->ss = vmcb->ss.sel;
239 regs->gs = vmcb->gs.sel;
240 regs->fs = vmcb->fs.sel;
241 }
243 if ( crs != NULL )
244 {
245 /* Returning the guest's regs */
246 crs[0] = v->arch.hvm_svm.cpu_shadow_cr0;
247 crs[2] = v->arch.hvm_svm.cpu_cr2;
248 crs[3] = v->arch.hvm_svm.cpu_cr3;
249 crs[4] = v->arch.hvm_svm.cpu_shadow_cr4;
250 }
251 }
253 static int svm_paging_enabled(struct vcpu *v)
254 {
255 unsigned long cr0;
257 cr0 = v->arch.hvm_svm.cpu_shadow_cr0;
259 return (cr0 & X86_CR0_PE) && (cr0 & X86_CR0_PG);
260 }
262 static int svm_pae_enabled(struct vcpu *v)
263 {
264 unsigned long cr4;
266 if(!svm_paging_enabled(v))
267 return 0;
269 cr4 = v->arch.hvm_svm.cpu_shadow_cr4;
271 return (cr4 & X86_CR4_PAE);
272 }
274 #define IS_CANO_ADDRESS(add) 1
276 static inline int long_mode_do_msr_read(struct cpu_user_regs *regs)
277 {
278 u64 msr_content = 0;
279 struct vcpu *vc = current;
280 struct vmcb_struct *vmcb = vc->arch.hvm_svm.vmcb;
282 switch (regs->ecx)
283 {
284 case MSR_EFER:
285 msr_content = vmcb->efer;
286 msr_content &= ~EFER_SVME;
287 break;
289 case MSR_FS_BASE:
290 msr_content = vmcb->fs.base;
291 break;
293 case MSR_GS_BASE:
294 msr_content = vmcb->gs.base;
295 break;
297 case MSR_SHADOW_GS_BASE:
298 msr_content = vmcb->kerngsbase;
299 break;
301 case MSR_STAR:
302 msr_content = vmcb->star;
303 break;
305 case MSR_LSTAR:
306 msr_content = vmcb->lstar;
307 break;
309 case MSR_CSTAR:
310 msr_content = vmcb->cstar;
311 break;
313 case MSR_SYSCALL_MASK:
314 msr_content = vmcb->sfmask;
315 break;
316 default:
317 return 0;
318 }
320 HVM_DBG_LOG(DBG_LEVEL_2, "mode_do_msr_read: msr_content: %"PRIx64"\n",
321 msr_content);
323 regs->eax = (u32)(msr_content >> 0);
324 regs->edx = (u32)(msr_content >> 32);
325 return 1;
326 }
328 static inline int long_mode_do_msr_write(struct cpu_user_regs *regs)
329 {
330 u64 msr_content = (u32)regs->eax | ((u64)regs->edx << 32);
331 struct vcpu *vc = current;
332 struct vmcb_struct *vmcb = vc->arch.hvm_svm.vmcb;
334 HVM_DBG_LOG(DBG_LEVEL_1, "mode_do_msr_write msr %lx "
335 "msr_content %"PRIx64"\n",
336 (unsigned long)regs->ecx, msr_content);
338 switch (regs->ecx)
339 {
340 case MSR_EFER:
341 #ifdef __x86_64__
342 /* offending reserved bit will cause #GP */
343 if ( msr_content & ~(EFER_LME | EFER_LMA | EFER_NX | EFER_SCE) )
344 {
345 printk("Trying to set reserved bit in EFER: %"PRIx64"\n",
346 msr_content);
347 svm_inject_exception(vc, TRAP_gp_fault, 1, 0);
348 return 0;
349 }
351 /* LME: 0 -> 1 */
352 if ( msr_content & EFER_LME &&
353 !test_bit(SVM_CPU_STATE_LME_ENABLED, &vc->arch.hvm_svm.cpu_state))
354 {
355 if ( svm_paging_enabled(vc) ||
356 !test_bit(SVM_CPU_STATE_PAE_ENABLED,
357 &vc->arch.hvm_svm.cpu_state) )
358 {
359 printk("Trying to set LME bit when "
360 "in paging mode or PAE bit is not set\n");
361 svm_inject_exception(vc, TRAP_gp_fault, 1, 0);
362 return 0;
363 }
364 set_bit(SVM_CPU_STATE_LME_ENABLED, &vc->arch.hvm_svm.cpu_state);
365 }
367 /* We have already recorded that we want LME, so it will be set
368 * next time CR0 gets updated. So we clear that bit and continue.
369 */
370 if ((msr_content ^ vmcb->efer) & EFER_LME)
371 msr_content &= ~EFER_LME;
372 /* No update for LME/LMA since it have no effect */
373 #endif
374 vmcb->efer = msr_content | EFER_SVME;
375 break;
377 case MSR_FS_BASE:
378 case MSR_GS_BASE:
379 if (!(SVM_LONG_GUEST(vc)))
380 domain_crash_synchronous();
382 if (!IS_CANO_ADDRESS(msr_content))
383 {
384 HVM_DBG_LOG(DBG_LEVEL_1, "Not cano address of msr write\n");
385 svm_inject_exception(vc, TRAP_gp_fault, 1, 0);
386 }
388 if (regs->ecx == MSR_FS_BASE)
389 vmcb->fs.base = msr_content;
390 else
391 vmcb->gs.base = msr_content;
392 break;
394 case MSR_SHADOW_GS_BASE:
395 vmcb->kerngsbase = msr_content;
396 break;
398 case MSR_STAR:
399 vmcb->star = msr_content;
400 break;
402 case MSR_LSTAR:
403 vmcb->lstar = msr_content;
404 break;
406 case MSR_CSTAR:
407 vmcb->cstar = msr_content;
408 break;
410 case MSR_SYSCALL_MASK:
411 vmcb->sfmask = msr_content;
412 break;
414 default:
415 return 0;
416 }
417 return 1;
418 }
421 #define loaddebug(_v,_reg) \
422 __asm__ __volatile__ ("mov %0,%%db" #_reg : : "r" ((_v)->debugreg[_reg]))
423 #define savedebug(_v,_reg) \
424 __asm__ __volatile__ ("mov %%db" #_reg ",%0" : : "r" ((_v)->debugreg[_reg]))
427 static inline void svm_save_dr(struct vcpu *v)
428 {
429 if (v->arch.hvm_vcpu.flag_dr_dirty)
430 {
431 /* clear the DR dirty flag and re-enable intercepts for DR accesses */
432 v->arch.hvm_vcpu.flag_dr_dirty = 0;
433 v->arch.hvm_svm.vmcb->dr_intercepts = DR_INTERCEPT_ALL_WRITES;
435 savedebug(&v->arch.guest_context, 0);
436 savedebug(&v->arch.guest_context, 1);
437 savedebug(&v->arch.guest_context, 2);
438 savedebug(&v->arch.guest_context, 3);
439 }
440 }
443 static inline void __restore_debug_registers(struct vcpu *v)
444 {
445 loaddebug(&v->arch.guest_context, 0);
446 loaddebug(&v->arch.guest_context, 1);
447 loaddebug(&v->arch.guest_context, 2);
448 loaddebug(&v->arch.guest_context, 3);
449 }
452 static inline void svm_restore_dr(struct vcpu *v)
453 {
454 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
456 if (!vmcb)
457 return;
459 if (unlikely(vmcb->dr7 & 0xFF))
460 __restore_debug_registers(v);
461 }
464 static int svm_realmode(struct vcpu *v)
465 {
466 unsigned long cr0 = v->arch.hvm_svm.cpu_shadow_cr0;
467 unsigned long eflags = v->arch.hvm_svm.vmcb->rflags;
469 return (eflags & X86_EFLAGS_VM) || !(cr0 & X86_CR0_PE);
470 }
472 static int svm_guest_x86_mode(struct vcpu *v)
473 {
474 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
476 if ( vmcb->efer & EFER_LMA )
477 return (vmcb->cs.attributes.fields.l ?
478 X86EMUL_MODE_PROT64 : X86EMUL_MODE_PROT32);
480 if ( svm_realmode(v) )
481 return X86EMUL_MODE_REAL;
483 return (vmcb->cs.attributes.fields.db ?
484 X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16);
485 }
487 void svm_update_host_cr3(struct vcpu *v)
488 {
489 /* SVM doesn't have a HOST_CR3 equivalent to update. */
490 }
492 unsigned long svm_get_ctrl_reg(struct vcpu *v, unsigned int num)
493 {
494 switch ( num )
495 {
496 case 0:
497 return v->arch.hvm_svm.cpu_shadow_cr0;
498 case 2:
499 return v->arch.hvm_svm.cpu_cr2;
500 case 3:
501 return v->arch.hvm_svm.cpu_cr3;
502 case 4:
503 return v->arch.hvm_svm.cpu_shadow_cr4;
504 default:
505 BUG();
506 }
507 return 0; /* dummy */
508 }
511 /* Make sure that xen intercepts any FP accesses from current */
512 static void svm_stts(struct vcpu *v)
513 {
514 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
516 /*
517 * If the guest does not have TS enabled then we must cause and handle an
518 * exception on first use of the FPU. If the guest *does* have TS enabled
519 * then this is not necessary: no FPU activity can occur until the guest
520 * clears CR0.TS, and we will initialise the FPU when that happens.
521 */
522 if ( !(v->arch.hvm_svm.cpu_shadow_cr0 & X86_CR0_TS) )
523 {
524 v->arch.hvm_svm.vmcb->exception_intercepts |= EXCEPTION_BITMAP_NM;
525 vmcb->cr0 |= X86_CR0_TS;
526 }
527 }
530 static void svm_set_tsc_offset(struct vcpu *v, u64 offset)
531 {
532 v->arch.hvm_svm.vmcb->tsc_offset = offset;
533 }
536 /* SVM-specific intitialization code for VCPU application processors */
537 static void svm_init_ap_context(struct vcpu_guest_context *ctxt,
538 int vcpuid, int trampoline_vector)
539 {
540 int i;
541 struct vcpu *v, *bsp = current;
542 struct domain *d = bsp->domain;
543 cpu_user_regs_t *regs;;
546 if ((v = d->vcpu[vcpuid]) == NULL)
547 {
548 printk("vcpuid %d is invalid! good-bye.\n", vcpuid);
549 domain_crash_synchronous();
550 }
551 regs = &v->arch.guest_context.user_regs;
553 memset(ctxt, 0, sizeof(*ctxt));
554 for (i = 0; i < 256; ++i)
555 {
556 ctxt->trap_ctxt[i].vector = i;
557 ctxt->trap_ctxt[i].cs = FLAT_KERNEL_CS;
558 }
561 /*
562 * We execute the trampoline code in real mode. The trampoline vector
563 * passed to us is page alligned and is the physicall frame number for
564 * the code. We will execute this code in real mode.
565 */
566 ctxt->user_regs.eip = 0x0;
567 ctxt->user_regs.cs = (trampoline_vector << 8);
568 ctxt->flags = VGCF_HVM_GUEST;
569 }
571 static void svm_init_hypercall_page(struct domain *d, void *hypercall_page)
572 {
573 char *p;
574 int i;
576 memset(hypercall_page, 0, PAGE_SIZE);
578 for ( i = 0; i < (PAGE_SIZE / 32); i++ )
579 {
580 p = (char *)(hypercall_page + (i * 32));
581 *(u8 *)(p + 0) = 0xb8; /* mov imm32, %eax */
582 *(u32 *)(p + 1) = i;
583 *(u8 *)(p + 5) = 0x0f; /* vmmcall */
584 *(u8 *)(p + 6) = 0x01;
585 *(u8 *)(p + 7) = 0xd9;
586 *(u8 *)(p + 8) = 0xc3; /* ret */
587 }
589 /* Don't support HYPERVISOR_iret at the moment */
590 *(u16 *)(hypercall_page + (__HYPERVISOR_iret * 32)) = 0x0b0f; /* ud2 */
591 }
594 int svm_dbg_on = 0;
596 static inline int svm_do_debugout(unsigned long exit_code)
597 {
598 int i;
600 static unsigned long counter = 0;
601 static unsigned long works[] =
602 {
603 VMEXIT_IOIO,
604 VMEXIT_HLT,
605 VMEXIT_CPUID,
606 VMEXIT_DR0_READ,
607 VMEXIT_DR1_READ,
608 VMEXIT_DR2_READ,
609 VMEXIT_DR3_READ,
610 VMEXIT_DR6_READ,
611 VMEXIT_DR7_READ,
612 VMEXIT_DR0_WRITE,
613 VMEXIT_DR1_WRITE,
614 VMEXIT_DR2_WRITE,
615 VMEXIT_DR3_WRITE,
616 VMEXIT_CR0_READ,
617 VMEXIT_CR0_WRITE,
618 VMEXIT_CR3_READ,
619 VMEXIT_CR4_READ,
620 VMEXIT_MSR,
621 VMEXIT_CR0_WRITE,
622 VMEXIT_CR3_WRITE,
623 VMEXIT_CR4_WRITE,
624 VMEXIT_EXCEPTION_PF,
625 VMEXIT_INTR,
626 VMEXIT_INVLPG,
627 VMEXIT_EXCEPTION_NM
628 };
631 #if 0
632 if (svm_dbg_on && exit_code != 0x7B)
633 return 1;
634 #endif
636 counter++;
638 #if 0
639 if ((exit_code == 0x4E
640 || exit_code == VMEXIT_CR0_READ
641 || exit_code == VMEXIT_CR0_WRITE)
642 && counter < 200000)
643 return 0;
645 if ((exit_code == 0x4E) && counter < 500000)
646 return 0;
647 #endif
649 for (i = 0; i < sizeof(works) / sizeof(works[0]); i++)
650 if (exit_code == works[i])
651 return 0;
653 return 1;
654 }
656 static void save_svm_cpu_user_regs(struct vcpu *v, struct cpu_user_regs *ctxt)
657 {
658 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
660 ASSERT(vmcb);
662 ctxt->eax = vmcb->rax;
663 ctxt->ss = vmcb->ss.sel;
664 ctxt->esp = vmcb->rsp;
665 ctxt->eflags = vmcb->rflags;
666 ctxt->cs = vmcb->cs.sel;
667 ctxt->eip = vmcb->rip;
669 ctxt->gs = vmcb->gs.sel;
670 ctxt->fs = vmcb->fs.sel;
671 ctxt->es = vmcb->es.sel;
672 ctxt->ds = vmcb->ds.sel;
673 }
675 static void svm_store_cpu_user_regs(struct cpu_user_regs *regs, struct vcpu *v)
676 {
677 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
679 regs->eip = vmcb->rip;
680 regs->esp = vmcb->rsp;
681 regs->eflags = vmcb->rflags;
682 regs->cs = vmcb->cs.sel;
683 regs->ds = vmcb->ds.sel;
684 regs->es = vmcb->es.sel;
685 regs->ss = vmcb->ss.sel;
686 }
688 /* XXX Use svm_load_cpu_guest_regs instead */
689 static void svm_load_cpu_user_regs(struct vcpu *v, struct cpu_user_regs *regs)
690 {
691 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
692 u32 *intercepts = &v->arch.hvm_svm.vmcb->exception_intercepts;
694 /* Write the guest register value into VMCB */
695 vmcb->rax = regs->eax;
696 vmcb->ss.sel = regs->ss;
697 vmcb->rsp = regs->esp;
698 vmcb->rflags = regs->eflags;
699 vmcb->cs.sel = regs->cs;
700 vmcb->rip = regs->eip;
701 if (regs->eflags & EF_TF)
702 *intercepts |= EXCEPTION_BITMAP_DB;
703 else
704 *intercepts &= ~EXCEPTION_BITMAP_DB;
705 }
707 static void svm_load_cpu_guest_regs(
708 struct vcpu *v, struct cpu_user_regs *regs)
709 {
710 svm_load_cpu_user_regs(v, regs);
711 }
713 int svm_long_mode_enabled(struct vcpu *v)
714 {
715 return SVM_LONG_GUEST(v);
716 }
720 static void arch_svm_do_launch(struct vcpu *v)
721 {
722 cpu_user_regs_t *regs = &current->arch.guest_context.user_regs;
723 int error;
725 #if 0
726 if (svm_dbg_on)
727 printk("Do launch\n");
728 #endif
729 error = construct_vmcb(&v->arch.hvm_svm, regs);
730 if ( error < 0 )
731 {
732 if (v->vcpu_id == 0) {
733 printk("Failed to construct a new VMCB for BSP.\n");
734 } else {
735 printk("Failed to construct a new VMCB for AP %d\n", v->vcpu_id);
736 }
737 domain_crash_synchronous();
738 }
740 svm_do_launch(v);
741 #if 0
742 if (svm_dbg_on)
743 svm_dump_host_regs(__func__);
744 #endif
745 if (v->vcpu_id != 0)
746 {
747 u16 cs_sel = regs->cs;
748 /*
749 * This is the launch of an AP; set state so that we begin executing
750 * the trampoline code in real-mode.
751 */
752 svm_do_vmmcall_reset_to_realmode(v, regs);
753 /* Adjust the state to execute the trampoline code.*/
754 v->arch.hvm_svm.vmcb->rip = 0;
755 v->arch.hvm_svm.vmcb->cs.sel= cs_sel;
756 v->arch.hvm_svm.vmcb->cs.base = (cs_sel << 4);
757 }
759 reset_stack_and_jump(svm_asm_do_launch);
760 }
762 static void svm_freeze_time(struct vcpu *v)
763 {
764 struct periodic_time *pt=&v->domain->arch.hvm_domain.pl_time.periodic_tm;
766 if ( pt->enabled && pt->first_injected && !v->arch.hvm_vcpu.guest_time ) {
767 v->arch.hvm_vcpu.guest_time = hvm_get_guest_time(v);
768 stop_timer(&(pt->timer));
769 }
770 }
773 static void svm_ctxt_switch_from(struct vcpu *v)
774 {
775 svm_freeze_time(v);
776 svm_save_dr(v);
777 }
779 static void svm_ctxt_switch_to(struct vcpu *v)
780 {
781 #ifdef __x86_64__
782 /*
783 * This is required, because VMRUN does consistency check
784 * and some of the DOM0 selectors are pointing to
785 * invalid GDT locations, and cause AMD processors
786 * to shutdown.
787 */
788 set_segment_register(ds, 0);
789 set_segment_register(es, 0);
790 set_segment_register(ss, 0);
791 #endif
792 svm_restore_dr(v);
793 }
796 static void svm_final_setup_guest(struct vcpu *v)
797 {
798 struct domain *d = v->domain;
800 v->arch.schedule_tail = arch_svm_do_launch;
801 v->arch.ctxt_switch_from = svm_ctxt_switch_from;
802 v->arch.ctxt_switch_to = svm_ctxt_switch_to;
804 if ( v != d->vcpu[0] )
805 return;
807 if ( !shadow_mode_external(d) )
808 {
809 DPRINTK("Can't init HVM for dom %u vcpu %u: "
810 "not in shadow external mode\n", d->domain_id, v->vcpu_id);
811 domain_crash(d);
812 }
814 /*
815 * Required to do this once per domain
816 * TODO: add a seperate function to do these.
817 */
818 memset(&d->shared_info->evtchn_mask[0], 0xff,
819 sizeof(d->shared_info->evtchn_mask));
820 }
823 static int svm_initialize_guest_resources(struct vcpu *v)
824 {
825 svm_final_setup_guest(v);
826 return 1;
827 }
830 int start_svm(void)
831 {
832 u32 eax, ecx, edx;
833 u32 phys_hsa_lo, phys_hsa_hi;
834 u64 phys_hsa;
835 int cpu = smp_processor_id();
837 /* Xen does not fill x86_capability words except 0. */
838 ecx = cpuid_ecx(0x80000001);
839 boot_cpu_data.x86_capability[5] = ecx;
841 if (!(test_bit(X86_FEATURE_SVME, &boot_cpu_data.x86_capability)))
842 return 0;
844 if (!(hsa[cpu] = alloc_host_save_area()))
845 return 0;
847 rdmsr(MSR_EFER, eax, edx);
848 eax |= EFER_SVME;
849 wrmsr(MSR_EFER, eax, edx);
850 asidpool_init( cpu );
851 printk("AMD SVM Extension is enabled for cpu %d.\n", cpu );
853 /* Initialize the HSA for this core */
854 phys_hsa = (u64) virt_to_maddr(hsa[cpu]);
855 phys_hsa_lo = (u32) phys_hsa;
856 phys_hsa_hi = (u32) (phys_hsa >> 32);
857 wrmsr(MSR_K8_VM_HSAVE_PA, phys_hsa_lo, phys_hsa_hi);
859 if (!(root_vmcb[cpu] = alloc_vmcb()))
860 return 0;
861 root_vmcb_pa[cpu] = virt_to_maddr(root_vmcb[cpu]);
863 if (cpu == 0)
864 setup_vmcb_dump();
866 /* Setup HVM interfaces */
867 hvm_funcs.disable = stop_svm;
869 hvm_funcs.initialize_guest_resources = svm_initialize_guest_resources;
870 hvm_funcs.relinquish_guest_resources = svm_relinquish_guest_resources;
872 hvm_funcs.store_cpu_guest_regs = svm_store_cpu_guest_regs;
873 hvm_funcs.load_cpu_guest_regs = svm_load_cpu_guest_regs;
875 hvm_funcs.realmode = svm_realmode;
876 hvm_funcs.paging_enabled = svm_paging_enabled;
877 hvm_funcs.long_mode_enabled = svm_long_mode_enabled;
878 hvm_funcs.pae_enabled = svm_pae_enabled;
879 hvm_funcs.guest_x86_mode = svm_guest_x86_mode;
880 hvm_funcs.get_guest_ctrl_reg = svm_get_ctrl_reg;
882 hvm_funcs.update_host_cr3 = svm_update_host_cr3;
884 hvm_funcs.stts = svm_stts;
885 hvm_funcs.set_tsc_offset = svm_set_tsc_offset;
887 hvm_funcs.init_ap_context = svm_init_ap_context;
888 hvm_funcs.init_hypercall_page = svm_init_hypercall_page;
890 hvm_enabled = 1;
892 return 1;
893 }
896 static void svm_relinquish_guest_resources(struct domain *d)
897 {
898 struct vcpu *v;
900 for_each_vcpu ( d, v )
901 {
902 if ( !test_bit(_VCPUF_initialised, &v->vcpu_flags) )
903 continue;
905 destroy_vmcb(&v->arch.hvm_svm);
906 kill_timer(&v->arch.hvm_vcpu.hlt_timer);
907 if ( hvm_apic_support(v->domain) && (VLAPIC(v) != NULL) )
908 {
909 kill_timer( &(VLAPIC(v)->vlapic_timer) );
910 unmap_domain_page_global(VLAPIC(v)->regs);
911 free_domheap_page(VLAPIC(v)->regs_page);
912 xfree(VLAPIC(v));
913 }
914 hvm_release_assist_channel(v);
915 }
917 kill_timer(&d->arch.hvm_domain.pl_time.periodic_tm.timer);
919 if ( d->arch.hvm_domain.shared_page_va )
920 unmap_domain_page_global(
921 (void *)d->arch.hvm_domain.shared_page_va);
923 if ( d->arch.hvm_domain.buffered_io_va )
924 unmap_domain_page_global((void *)d->arch.hvm_domain.buffered_io_va);
925 }
928 static void svm_migrate_timers(struct vcpu *v)
929 {
930 struct periodic_time *pt =
931 &(v->domain->arch.hvm_domain.pl_time.periodic_tm);
933 if ( pt->enabled ) {
934 migrate_timer( &pt->timer, v->processor );
935 migrate_timer( &v->arch.hvm_vcpu.hlt_timer, v->processor );
936 }
937 if ( hvm_apic_support(v->domain) && VLAPIC( v ))
938 migrate_timer( &(VLAPIC(v)->vlapic_timer ), v->processor );
939 }
942 void arch_svm_do_resume(struct vcpu *v)
943 {
944 /* pinning VCPU to a different core? */
945 if ( v->arch.hvm_svm.launch_core == smp_processor_id()) {
946 hvm_do_resume( v );
947 reset_stack_and_jump( svm_asm_do_resume );
948 }
949 else {
950 if (svm_dbg_on)
951 printk("VCPU core pinned: %d to %d\n",
952 v->arch.hvm_svm.launch_core, smp_processor_id() );
953 v->arch.hvm_svm.launch_core = smp_processor_id();
954 svm_migrate_timers( v );
955 hvm_do_resume( v );
956 reset_stack_and_jump( svm_asm_do_resume );
957 }
958 }
962 static int svm_do_page_fault(unsigned long va, struct cpu_user_regs *regs)
963 {
964 struct vcpu *v = current;
965 unsigned long eip;
966 int result;
967 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
969 ASSERT(vmcb);
971 //#if HVM_DEBUG
972 eip = vmcb->rip;
973 HVM_DBG_LOG(DBG_LEVEL_VMMU,
974 "svm_do_page_fault = 0x%lx, eip = %lx, error_code = %lx",
975 va, eip, (unsigned long)regs->error_code);
976 //#endif
978 result = shadow_fault(va, regs);
980 if( result ) {
981 /* Let's make sure that the Guest TLB is flushed */
982 set_bit(ARCH_SVM_VMCB_ASSIGN_ASID, &v->arch.hvm_svm.flags);
983 }
985 return result;
986 }
989 static void svm_do_no_device_fault(struct vmcb_struct *vmcb)
990 {
991 struct vcpu *v = current;
993 setup_fpu(v);
994 vmcb->exception_intercepts &= ~EXCEPTION_BITMAP_NM;
996 if ( !(v->arch.hvm_svm.cpu_shadow_cr0 & X86_CR0_TS) )
997 vmcb->cr0 &= ~X86_CR0_TS;
998 }
1001 static void svm_do_general_protection_fault(struct vcpu *v,
1002 struct cpu_user_regs *regs)
1004 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1005 unsigned long eip, error_code;
1007 ASSERT(vmcb);
1009 eip = vmcb->rip;
1010 error_code = vmcb->exitinfo1;
1012 if (vmcb->idtr.limit == 0) {
1013 printf("Huh? We got a GP Fault with an invalid IDTR!\n");
1014 svm_dump_vmcb(__func__, vmcb);
1015 svm_dump_regs(__func__, regs);
1016 svm_dump_inst(vmcb->rip);
1017 __hvm_bug(regs);
1020 HVM_DBG_LOG(DBG_LEVEL_1,
1021 "svm_general_protection_fault: eip = %lx, erro_code = %lx",
1022 eip, error_code);
1024 HVM_DBG_LOG(DBG_LEVEL_1,
1025 "eax=%lx, ebx=%lx, ecx=%lx, edx=%lx, esi=%lx, edi=%lx",
1026 (unsigned long)regs->eax, (unsigned long)regs->ebx,
1027 (unsigned long)regs->ecx, (unsigned long)regs->edx,
1028 (unsigned long)regs->esi, (unsigned long)regs->edi);
1030 /* Reflect it back into the guest */
1031 svm_inject_exception(v, TRAP_gp_fault, 1, error_code);
1034 /* Reserved bits ECX: [31:14], [12:4], [2:1]*/
1035 #define SVM_VCPU_CPUID_L1_ECX_RESERVED 0xffffdff6
1036 /* Reserved bits EDX: [31:29], [27], [22:20], [18], [10] */
1037 #define SVM_VCPU_CPUID_L1_EDX_RESERVED 0xe8740400
1039 static void svm_vmexit_do_cpuid(struct vmcb_struct *vmcb, unsigned long input,
1040 struct cpu_user_regs *regs)
1042 unsigned int eax, ebx, ecx, edx;
1043 unsigned long eip;
1044 struct vcpu *v = current;
1045 int inst_len;
1047 ASSERT(vmcb);
1049 eip = vmcb->rip;
1051 HVM_DBG_LOG(DBG_LEVEL_1,
1052 "do_cpuid: (eax) %lx, (ebx) %lx, (ecx) %lx, (edx) %lx,"
1053 " (esi) %lx, (edi) %lx",
1054 (unsigned long)regs->eax, (unsigned long)regs->ebx,
1055 (unsigned long)regs->ecx, (unsigned long)regs->edx,
1056 (unsigned long)regs->esi, (unsigned long)regs->edi);
1058 if ( !cpuid_hypervisor_leaves(input, &eax, &ebx, &ecx, &edx) )
1060 cpuid(input, &eax, &ebx, &ecx, &edx);
1061 if (input == 0x00000001 || input == 0x80000001 )
1063 if ( !hvm_apic_support(v->domain) ||
1064 !vlapic_global_enabled((VLAPIC(v))) )
1066 /* Since the apic is disabled, avoid any confusion
1067 about SMP cpus being available */
1068 clear_bit(X86_FEATURE_APIC, &edx);
1070 #if CONFIG_PAGING_LEVELS >= 3
1071 if ( !v->domain->arch.hvm_domain.params[HVM_PARAM_PAE_ENABLED] )
1072 #endif
1074 clear_bit(X86_FEATURE_PAE, &edx);
1075 if (input == 0x80000001 )
1076 clear_bit(X86_FEATURE_NX & 31, &edx);
1078 clear_bit(X86_FEATURE_PSE36, &edx);
1079 if (input == 0x00000001 )
1081 /* Clear out reserved bits. */
1082 ecx &= ~SVM_VCPU_CPUID_L1_ECX_RESERVED;
1083 edx &= ~SVM_VCPU_CPUID_L1_EDX_RESERVED;
1085 clear_bit(X86_FEATURE_MWAIT & 31, &ecx);
1087 /* Guest should only see one logical processor.
1088 * See details on page 23 of AMD CPUID Specification.
1089 */
1090 clear_bit(X86_FEATURE_HT, &edx); /* clear the hyperthread bit */
1091 ebx &= 0xFF00FFFF; /* clear the logical processor count when HTT=0 */
1092 ebx |= 0x00010000; /* set to 1 just for precaution */
1094 else
1096 /* Clear the Cmp_Legacy bit
1097 * This bit is supposed to be zero when HTT = 0.
1098 * See details on page 23 of AMD CPUID Specification.
1099 */
1100 clear_bit(X86_FEATURE_CMP_LEGACY & 31, &ecx);
1101 /* Make SVM feature invisible to the guest. */
1102 clear_bit(X86_FEATURE_SVME & 31, &ecx);
1103 #ifdef __i386__
1104 /* Mask feature for Intel ia32e or AMD long mode. */
1105 clear_bit(X86_FEATURE_LAHF_LM & 31, &ecx);
1107 clear_bit(X86_FEATURE_LM & 31, &edx);
1108 clear_bit(X86_FEATURE_SYSCALL & 31, &edx);
1109 #endif
1110 /* So far, we do not support 3DNow for the guest. */
1111 clear_bit(X86_FEATURE_3DNOW & 31, &edx);
1112 clear_bit(X86_FEATURE_3DNOWEXT & 31, &edx);
1115 else if ( ( input == 0x80000007 ) || ( input == 0x8000000A ) )
1117 /* Mask out features of power management and SVM extension. */
1118 eax = ebx = ecx = edx = 0;
1120 else if ( input == 0x80000008 )
1122 /* Make sure Number of CPU core is 1 when HTT=0 */
1123 ecx &= 0xFFFFFF00;
1127 regs->eax = (unsigned long)eax;
1128 regs->ebx = (unsigned long)ebx;
1129 regs->ecx = (unsigned long)ecx;
1130 regs->edx = (unsigned long)edx;
1132 HVM_DBG_LOG(DBG_LEVEL_1,
1133 "svm_vmexit_do_cpuid: eip: %lx, input: %lx, out:eax=%x, "
1134 "ebx=%x, ecx=%x, edx=%x",
1135 eip, input, eax, ebx, ecx, edx);
1137 inst_len = __get_instruction_length(vmcb, INSTR_CPUID, NULL);
1138 ASSERT(inst_len > 0);
1139 __update_guest_eip(vmcb, inst_len);
1143 static inline unsigned long *get_reg_p(unsigned int gpreg,
1144 struct cpu_user_regs *regs, struct vmcb_struct *vmcb)
1146 unsigned long *reg_p = NULL;
1147 switch (gpreg)
1149 case SVM_REG_EAX:
1150 reg_p = (unsigned long *)&regs->eax;
1151 break;
1152 case SVM_REG_EBX:
1153 reg_p = (unsigned long *)&regs->ebx;
1154 break;
1155 case SVM_REG_ECX:
1156 reg_p = (unsigned long *)&regs->ecx;
1157 break;
1158 case SVM_REG_EDX:
1159 reg_p = (unsigned long *)&regs->edx;
1160 break;
1161 case SVM_REG_EDI:
1162 reg_p = (unsigned long *)&regs->edi;
1163 break;
1164 case SVM_REG_ESI:
1165 reg_p = (unsigned long *)&regs->esi;
1166 break;
1167 case SVM_REG_EBP:
1168 reg_p = (unsigned long *)&regs->ebp;
1169 break;
1170 case SVM_REG_ESP:
1171 reg_p = (unsigned long *)&vmcb->rsp;
1172 break;
1173 #ifdef __x86_64__
1174 case SVM_REG_R8:
1175 reg_p = (unsigned long *)&regs->r8;
1176 break;
1177 case SVM_REG_R9:
1178 reg_p = (unsigned long *)&regs->r9;
1179 break;
1180 case SVM_REG_R10:
1181 reg_p = (unsigned long *)&regs->r10;
1182 break;
1183 case SVM_REG_R11:
1184 reg_p = (unsigned long *)&regs->r11;
1185 break;
1186 case SVM_REG_R12:
1187 reg_p = (unsigned long *)&regs->r12;
1188 break;
1189 case SVM_REG_R13:
1190 reg_p = (unsigned long *)&regs->r13;
1191 break;
1192 case SVM_REG_R14:
1193 reg_p = (unsigned long *)&regs->r14;
1194 break;
1195 case SVM_REG_R15:
1196 reg_p = (unsigned long *)&regs->r15;
1197 break;
1198 #endif
1199 default:
1200 BUG();
1203 return reg_p;
1207 static inline unsigned long get_reg(unsigned int gpreg,
1208 struct cpu_user_regs *regs, struct vmcb_struct *vmcb)
1210 unsigned long *gp;
1211 gp = get_reg_p(gpreg, regs, vmcb);
1212 return *gp;
1216 static inline void set_reg(unsigned int gpreg, unsigned long value,
1217 struct cpu_user_regs *regs, struct vmcb_struct *vmcb)
1219 unsigned long *gp;
1220 gp = get_reg_p(gpreg, regs, vmcb);
1221 *gp = value;
1225 static void svm_dr_access(struct vcpu *v, struct cpu_user_regs *regs)
1227 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1229 v->arch.hvm_vcpu.flag_dr_dirty = 1;
1231 __restore_debug_registers(v);
1233 /* allow the guest full access to the debug registers */
1234 vmcb->dr_intercepts = 0;
1238 static void svm_get_prefix_info(
1239 struct vmcb_struct *vmcb,
1240 unsigned int dir, segment_selector_t **seg, unsigned int *asize)
1242 unsigned char inst[MAX_INST_LEN];
1243 int i;
1245 memset(inst, 0, MAX_INST_LEN);
1246 if (inst_copy_from_guest(inst, svm_rip2pointer(vmcb), sizeof(inst))
1247 != MAX_INST_LEN)
1249 printk("%s: get guest instruction failed\n", __func__);
1250 domain_crash_synchronous();
1253 for (i = 0; i < MAX_INST_LEN; i++)
1255 switch (inst[i])
1257 case 0xf3: /* REPZ */
1258 case 0xf2: /* REPNZ */
1259 case 0xf0: /* LOCK */
1260 case 0x66: /* data32 */
1261 #ifdef __x86_64__
1262 /* REX prefixes */
1263 case 0x40:
1264 case 0x41:
1265 case 0x42:
1266 case 0x43:
1267 case 0x44:
1268 case 0x45:
1269 case 0x46:
1270 case 0x47:
1272 case 0x48:
1273 case 0x49:
1274 case 0x4a:
1275 case 0x4b:
1276 case 0x4c:
1277 case 0x4d:
1278 case 0x4e:
1279 case 0x4f:
1280 #endif
1281 continue;
1282 case 0x67: /* addr32 */
1283 *asize ^= 48; /* Switch 16/32 bits */
1284 continue;
1285 case 0x2e: /* CS */
1286 *seg = &vmcb->cs;
1287 continue;
1288 case 0x36: /* SS */
1289 *seg = &vmcb->ss;
1290 continue;
1291 case 0x26: /* ES */
1292 *seg = &vmcb->es;
1293 continue;
1294 case 0x64: /* FS */
1295 *seg = &vmcb->fs;
1296 continue;
1297 case 0x65: /* GS */
1298 *seg = &vmcb->gs;
1299 continue;
1300 case 0x3e: /* DS */
1301 *seg = &vmcb->ds;
1302 continue;
1303 default:
1304 break;
1306 return;
1311 /* Get the address of INS/OUTS instruction */
1312 static inline int svm_get_io_address(
1313 struct vcpu *v,
1314 struct cpu_user_regs *regs, unsigned int dir,
1315 unsigned long *count, unsigned long *addr)
1317 unsigned long reg;
1318 unsigned int asize = 0;
1319 unsigned int isize;
1320 int long_mode;
1321 ioio_info_t info;
1322 segment_selector_t *seg = NULL;
1323 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1325 info.bytes = vmcb->exitinfo1;
1327 /* If we're in long mode, we shouldn't check the segment presence & limit */
1328 long_mode = vmcb->cs.attributes.fields.l && vmcb->efer & EFER_LMA;
1330 /* d field of cs.attributes is 1 for 32-bit, 0 for 16 or 64 bit.
1331 * l field combined with EFER_LMA -> longmode says whether it's 16 or 64 bit.
1332 */
1333 asize = (long_mode)?64:((vmcb->cs.attributes.fields.db)?32:16);
1336 /* The ins/outs instructions are single byte, so if we have got more
1337 * than one byte (+ maybe rep-prefix), we have some prefix so we need
1338 * to figure out what it is...
1339 */
1340 isize = vmcb->exitinfo2 - vmcb->rip;
1342 if (info.fields.rep)
1343 isize --;
1345 if (isize > 1)
1347 svm_get_prefix_info(vmcb, dir, &seg, &asize);
1350 ASSERT(dir == IOREQ_READ || dir == IOREQ_WRITE);
1352 if (dir == IOREQ_WRITE)
1354 reg = regs->esi;
1355 if (!seg) /* If no prefix, used DS. */
1356 seg = &vmcb->ds;
1358 else
1360 reg = regs->edi;
1361 seg = &vmcb->es; /* Note: This is ALWAYS ES. */
1364 /* If the segment isn't present, give GP fault! */
1365 if (!long_mode && !seg->attributes.fields.p)
1367 svm_inject_exception(v, TRAP_gp_fault, 1, seg->sel);
1368 return 0;
1371 if (asize == 16)
1373 *addr = (reg & 0xFFFF);
1374 *count = regs->ecx & 0xffff;
1376 else
1378 *addr = reg;
1379 *count = regs->ecx;
1382 if (!long_mode) {
1383 if (*addr > seg->limit)
1385 svm_inject_exception(v, TRAP_gp_fault, 1, seg->sel);
1386 return 0;
1388 else
1390 *addr += seg->base;
1395 return 1;
1399 static void svm_io_instruction(struct vcpu *v)
1401 struct cpu_user_regs *regs;
1402 struct hvm_io_op *pio_opp;
1403 unsigned int port;
1404 unsigned int size, dir;
1405 ioio_info_t info;
1406 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1408 ASSERT(vmcb);
1409 pio_opp = &current->arch.hvm_vcpu.io_op;
1410 pio_opp->instr = INSTR_PIO;
1411 pio_opp->flags = 0;
1413 regs = &pio_opp->io_context;
1415 /* Copy current guest state into io instruction state structure. */
1416 memcpy(regs, guest_cpu_user_regs(), HVM_CONTEXT_STACK_BYTES);
1417 hvm_store_cpu_guest_regs(v, regs, NULL);
1419 info.bytes = vmcb->exitinfo1;
1421 port = info.fields.port; /* port used to be addr */
1422 dir = info.fields.type; /* direction */
1423 if (info.fields.sz32)
1424 size = 4;
1425 else if (info.fields.sz16)
1426 size = 2;
1427 else
1428 size = 1;
1430 HVM_DBG_LOG(DBG_LEVEL_IO,
1431 "svm_io_instruction: port 0x%x eip=%x:%"PRIx64", "
1432 "exit_qualification = %"PRIx64,
1433 port, vmcb->cs.sel, vmcb->rip, info.bytes);
1435 /* string instruction */
1436 if (info.fields.str)
1438 unsigned long addr, count;
1439 int sign = regs->eflags & EF_DF ? -1 : 1;
1441 if (!svm_get_io_address(v, regs, dir, &count, &addr))
1443 /* We failed to get a valid address, so don't do the IO operation -
1444 * it would just get worse if we do! Hopefully the guest is handing
1445 * gp-faults...
1446 */
1447 return;
1450 /* "rep" prefix */
1451 if (info.fields.rep)
1453 pio_opp->flags |= REPZ;
1455 else
1457 count = 1;
1460 /*
1461 * Handle string pio instructions that cross pages or that
1462 * are unaligned. See the comments in hvm_platform.c/handle_mmio()
1463 */
1464 if ((addr & PAGE_MASK) != ((addr + size - 1) & PAGE_MASK))
1466 unsigned long value = 0;
1468 pio_opp->flags |= OVERLAP;
1470 if (dir == IOREQ_WRITE)
1471 (void)hvm_copy_from_guest_virt(&value, addr, size);
1473 send_pio_req(regs, port, 1, size, value, dir, 0);
1475 else
1477 if ((addr & PAGE_MASK) != ((addr + count * size - 1) & PAGE_MASK))
1479 if (sign > 0)
1480 count = (PAGE_SIZE - (addr & ~PAGE_MASK)) / size;
1481 else
1482 count = (addr & ~PAGE_MASK) / size;
1484 else
1485 regs->eip = vmcb->exitinfo2;
1487 send_pio_req(regs, port, count, size, addr, dir, 1);
1490 else
1492 /*
1493 * On SVM, the RIP of the intruction following the IN/OUT is saved in
1494 * ExitInfo2
1495 */
1496 regs->eip = vmcb->exitinfo2;
1498 if (port == 0xe9 && dir == IOREQ_WRITE && size == 1)
1499 hvm_print_line(v, regs->eax); /* guest debug output */
1501 send_pio_req(regs, port, 1, size, regs->eax, dir, 0);
1505 static int svm_set_cr0(unsigned long value)
1507 struct vcpu *v = current;
1508 unsigned long mfn;
1509 int paging_enabled;
1510 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1511 unsigned long old_base_mfn;
1513 ASSERT(vmcb);
1515 /* We don't want to lose PG. ET is reserved and should be always be 1*/
1516 paging_enabled = svm_paging_enabled(v);
1517 value |= X86_CR0_ET;
1518 vmcb->cr0 = value | X86_CR0_PG;
1519 v->arch.hvm_svm.cpu_shadow_cr0 = value;
1521 /* TS cleared? Then initialise FPU now. */
1522 if ( !(value & X86_CR0_TS) )
1524 setup_fpu(v);
1525 vmcb->exception_intercepts &= ~EXCEPTION_BITMAP_NM;
1528 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR0 value = %lx\n", value);
1530 if ((value & X86_CR0_PE) && (value & X86_CR0_PG) && !paging_enabled)
1532 /* The guest CR3 must be pointing to the guest physical. */
1533 if (!VALID_MFN(mfn =
1534 get_mfn_from_gpfn(v->arch.hvm_svm.cpu_cr3 >> PAGE_SHIFT))
1535 || !get_page(mfn_to_page(mfn), v->domain))
1537 printk("Invalid CR3 value = %lx\n", v->arch.hvm_svm.cpu_cr3);
1538 domain_crash_synchronous(); /* need to take a clean path */
1541 #if defined(__x86_64__)
1542 if (test_bit(SVM_CPU_STATE_LME_ENABLED, &v->arch.hvm_svm.cpu_state)
1543 && !test_bit(SVM_CPU_STATE_PAE_ENABLED,
1544 &v->arch.hvm_svm.cpu_state))
1546 HVM_DBG_LOG(DBG_LEVEL_1, "Enable paging before PAE enable\n");
1547 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
1550 if (test_bit(SVM_CPU_STATE_LME_ENABLED, &v->arch.hvm_svm.cpu_state))
1552 /* Here the PAE is should to be opened */
1553 HVM_DBG_LOG(DBG_LEVEL_1, "Enable the Long mode\n");
1554 set_bit(SVM_CPU_STATE_LMA_ENABLED,
1555 &v->arch.hvm_svm.cpu_state);
1556 vmcb->efer |= (EFER_LMA | EFER_LME);
1558 #endif /* __x86_64__ */
1560 /* Now arch.guest_table points to machine physical. */
1561 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1562 v->arch.guest_table = pagetable_from_pfn(mfn);
1563 if ( old_base_mfn )
1564 put_page(mfn_to_page(old_base_mfn));
1565 shadow_update_paging_modes(v);
1567 HVM_DBG_LOG(DBG_LEVEL_VMMU, "New arch.guest_table = %lx",
1568 (unsigned long) (mfn << PAGE_SHIFT));
1570 vmcb->cr3 = v->arch.hvm_vcpu.hw_cr3;
1571 set_bit(ARCH_SVM_VMCB_ASSIGN_ASID, &v->arch.hvm_svm.flags);
1574 if ( !((value & X86_CR0_PE) && (value & X86_CR0_PG)) && paging_enabled )
1575 if ( v->arch.hvm_svm.cpu_cr3 ) {
1576 put_page(mfn_to_page(get_mfn_from_gpfn(
1577 v->arch.hvm_svm.cpu_cr3 >> PAGE_SHIFT)));
1578 v->arch.guest_table = pagetable_null();
1581 /*
1582 * SVM implements paged real-mode and when we return to real-mode
1583 * we revert back to the physical mappings that the domain builder
1584 * created.
1585 */
1586 if ((value & X86_CR0_PE) == 0) {
1587 if (value & X86_CR0_PG) {
1588 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
1589 return 0;
1591 shadow_update_paging_modes(v);
1592 vmcb->cr3 = v->arch.hvm_vcpu.hw_cr3;
1593 set_bit(ARCH_SVM_VMCB_ASSIGN_ASID, &v->arch.hvm_svm.flags);
1595 else if ( (value & (X86_CR0_PE | X86_CR0_PG)) == X86_CR0_PE )
1597 /* we should take care of this kind of situation */
1598 shadow_update_paging_modes(v);
1599 vmcb->cr3 = v->arch.hvm_vcpu.hw_cr3;
1600 set_bit(ARCH_SVM_VMCB_ASSIGN_ASID, &v->arch.hvm_svm.flags);
1603 return 1;
1606 /*
1607 * Read from control registers. CR0 and CR4 are read from the shadow.
1608 */
1609 static void mov_from_cr(int cr, int gp, struct cpu_user_regs *regs)
1611 unsigned long value = 0;
1612 struct vcpu *v = current;
1613 struct vlapic *vlapic = VLAPIC(v);
1614 struct vmcb_struct *vmcb;
1616 vmcb = v->arch.hvm_svm.vmcb;
1617 ASSERT(vmcb);
1619 switch (cr)
1621 case 0:
1622 value = v->arch.hvm_svm.cpu_shadow_cr0;
1623 if (svm_dbg_on)
1624 printk("CR0 read =%lx \n", value );
1625 break;
1626 case 2:
1627 value = vmcb->cr2;
1628 break;
1629 case 3:
1630 value = (unsigned long) v->arch.hvm_svm.cpu_cr3;
1631 if (svm_dbg_on)
1632 printk("CR3 read =%lx \n", value );
1633 break;
1634 case 4:
1635 value = (unsigned long) v->arch.hvm_svm.cpu_shadow_cr4;
1636 if (svm_dbg_on)
1637 printk( "CR4 read=%lx\n", value );
1638 break;
1639 case 8:
1640 value = (unsigned long)vlapic_get_reg(vlapic, APIC_TASKPRI);
1641 value = (value & 0xF0) >> 4;
1642 break;
1644 default:
1645 __hvm_bug(regs);
1648 set_reg(gp, value, regs, vmcb);
1650 HVM_DBG_LOG(DBG_LEVEL_VMMU, "mov_from_cr: CR%d, value = %lx,", cr, value);
1654 static inline int svm_pgbit_test(struct vcpu *v)
1656 return v->arch.hvm_svm.cpu_shadow_cr0 & X86_CR0_PG;
1660 /*
1661 * Write to control registers
1662 */
1663 static int mov_to_cr(int gpreg, int cr, struct cpu_user_regs *regs)
1665 unsigned long value;
1666 unsigned long old_cr;
1667 struct vcpu *v = current;
1668 struct vlapic *vlapic = VLAPIC(v);
1669 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1671 ASSERT(vmcb);
1673 value = get_reg(gpreg, regs, vmcb);
1675 HVM_DBG_LOG(DBG_LEVEL_1, "mov_to_cr: CR%d, value = %lx,", cr, value);
1676 HVM_DBG_LOG(DBG_LEVEL_1, "current = %lx,", (unsigned long) current);
1678 switch (cr)
1680 case 0:
1681 if (svm_dbg_on)
1682 printk("CR0 write =%lx \n", value );
1683 return svm_set_cr0(value);
1685 case 3:
1687 unsigned long old_base_mfn, mfn;
1688 if (svm_dbg_on)
1689 printk("CR3 write =%lx \n", value );
1690 /* If paging is not enabled yet, simply copy the value to CR3. */
1691 if (!svm_paging_enabled(v)) {
1692 v->arch.hvm_svm.cpu_cr3 = value;
1693 break;
1695 set_bit(ARCH_SVM_VMCB_ASSIGN_ASID, &v->arch.hvm_svm.flags);
1697 /* We make a new one if the shadow does not exist. */
1698 if (value == v->arch.hvm_svm.cpu_cr3)
1700 /*
1701 * This is simple TLB flush, implying the guest has
1702 * removed some translation or changed page attributes.
1703 * We simply invalidate the shadow.
1704 */
1705 mfn = get_mfn_from_gpfn(value >> PAGE_SHIFT);
1706 if (mfn != pagetable_get_pfn(v->arch.guest_table))
1707 __hvm_bug(regs);
1708 shadow_update_cr3(v);
1710 else
1712 /*
1713 * If different, make a shadow. Check if the PDBR is valid
1714 * first.
1715 */
1716 HVM_DBG_LOG(DBG_LEVEL_VMMU, "CR3 value = %lx", value);
1717 if (((value >> PAGE_SHIFT) > v->domain->max_pages)
1718 || !VALID_MFN(mfn = get_mfn_from_gpfn(value >> PAGE_SHIFT))
1719 || !get_page(mfn_to_page(mfn), v->domain))
1721 printk("Invalid CR3 value=%lx\n", value);
1722 domain_crash_synchronous(); /* need to take a clean path */
1725 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1726 v->arch.guest_table = pagetable_from_pfn(mfn);
1728 if (old_base_mfn)
1729 put_page(mfn_to_page(old_base_mfn));
1731 /*
1732 * arch.shadow_table should now hold the next CR3 for shadow
1733 */
1734 v->arch.hvm_svm.cpu_cr3 = value;
1735 update_cr3(v);
1736 vmcb->cr3 = v->arch.hvm_vcpu.hw_cr3;
1737 HVM_DBG_LOG(DBG_LEVEL_VMMU, "Update CR3 value = %lx", value);
1739 break;
1742 case 4: /* CR4 */
1744 if (svm_dbg_on)
1745 printk( "write cr4=%lx, cr0=%lx\n",
1746 value, v->arch.hvm_svm.cpu_shadow_cr0 );
1747 old_cr = v->arch.hvm_svm.cpu_shadow_cr4;
1748 if ( value & X86_CR4_PAE && !(old_cr & X86_CR4_PAE) )
1750 set_bit(SVM_CPU_STATE_PAE_ENABLED, &v->arch.hvm_svm.cpu_state);
1751 if ( svm_pgbit_test(v) )
1753 /* The guest is a 32-bit PAE guest. */
1754 #if CONFIG_PAGING_LEVELS >= 3
1755 unsigned long mfn, old_base_mfn;
1757 if ( !VALID_MFN(mfn = get_mfn_from_gpfn(
1758 v->arch.hvm_svm.cpu_cr3 >> PAGE_SHIFT)) ||
1759 !get_page(mfn_to_page(mfn), v->domain) )
1761 printk("Invalid CR3 value = %lx", v->arch.hvm_svm.cpu_cr3);
1762 domain_crash_synchronous(); /* need to take a clean path */
1765 /*
1766 * Now arch.guest_table points to machine physical.
1767 */
1769 old_base_mfn = pagetable_get_pfn(v->arch.guest_table);
1770 v->arch.guest_table = pagetable_from_pfn(mfn);
1771 if ( old_base_mfn )
1772 put_page(mfn_to_page(old_base_mfn));
1773 shadow_update_paging_modes(v);
1775 HVM_DBG_LOG(DBG_LEVEL_VMMU, "New arch.guest_table = %lx",
1776 (unsigned long) (mfn << PAGE_SHIFT));
1778 vmcb->cr3 = v->arch.hvm_vcpu.hw_cr3;
1780 /*
1781 * arch->shadow_table should hold the next CR3 for shadow
1782 */
1784 HVM_DBG_LOG(DBG_LEVEL_VMMU,
1785 "Update CR3 value = %lx, mfn = %lx",
1786 v->arch.hvm_svm.cpu_cr3, mfn);
1787 #endif
1790 else if (value & X86_CR4_PAE) {
1791 set_bit(SVM_CPU_STATE_PAE_ENABLED, &v->arch.hvm_svm.cpu_state);
1792 } else {
1793 if (test_bit(SVM_CPU_STATE_LMA_ENABLED,
1794 &v->arch.hvm_svm.cpu_state)) {
1795 svm_inject_exception(v, TRAP_gp_fault, 1, 0);
1797 clear_bit(SVM_CPU_STATE_PAE_ENABLED, &v->arch.hvm_svm.cpu_state);
1800 v->arch.hvm_svm.cpu_shadow_cr4 = value;
1801 vmcb->cr4 = value | SVM_CR4_HOST_MASK;
1803 /*
1804 * Writing to CR4 to modify the PSE, PGE, or PAE flag invalidates
1805 * all TLB entries except global entries.
1806 */
1807 if ((old_cr ^ value) & (X86_CR4_PSE | X86_CR4_PGE | X86_CR4_PAE))
1809 set_bit(ARCH_SVM_VMCB_ASSIGN_ASID, &v->arch.hvm_svm.flags);
1810 shadow_update_paging_modes(v);
1812 break;
1815 case 8:
1817 vlapic_set_reg(vlapic, APIC_TASKPRI, ((value & 0x0F) << 4));
1818 vlapic_update_ppr(vlapic);
1819 break;
1822 default:
1823 printk("invalid cr: %d\n", cr);
1824 __hvm_bug(regs);
1827 return 1;
1831 #define ARR_SIZE(x) (sizeof(x) / sizeof(x[0]))
1834 static int svm_cr_access(struct vcpu *v, unsigned int cr, unsigned int type,
1835 struct cpu_user_regs *regs)
1837 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1838 int inst_len = 0;
1839 int index;
1840 unsigned int gpreg;
1841 unsigned long value;
1842 u8 buffer[MAX_INST_LEN];
1843 u8 prefix = 0;
1844 int result = 1;
1845 enum instruction_index list_a[] = {INSTR_MOV2CR, INSTR_CLTS, INSTR_LMSW};
1846 enum instruction_index list_b[] = {INSTR_MOVCR2, INSTR_SMSW};
1847 enum instruction_index match;
1849 ASSERT(vmcb);
1851 inst_copy_from_guest(buffer, svm_rip2pointer(vmcb), sizeof(buffer));
1853 /* get index to first actual instruction byte - as we will need to know
1854 where the prefix lives later on */
1855 index = skip_prefix_bytes(buffer, sizeof(buffer));
1857 if ( type == TYPE_MOV_TO_CR )
1859 inst_len = __get_instruction_length_from_list(
1860 vmcb, list_a, ARR_SIZE(list_a), &buffer[index], &match);
1862 else /* type == TYPE_MOV_FROM_CR */
1864 inst_len = __get_instruction_length_from_list(
1865 vmcb, list_b, ARR_SIZE(list_b), &buffer[index], &match);
1868 ASSERT(inst_len > 0);
1870 inst_len += index;
1872 /* Check for REX prefix - it's ALWAYS the last byte of any prefix bytes */
1873 if (index > 0 && (buffer[index-1] & 0xF0) == 0x40)
1874 prefix = buffer[index-1];
1876 HVM_DBG_LOG(DBG_LEVEL_1, "eip = %lx", (unsigned long) vmcb->rip);
1878 switch (match)
1880 case INSTR_MOV2CR:
1881 gpreg = decode_src_reg(prefix, buffer[index+2]);
1882 result = mov_to_cr(gpreg, cr, regs);
1883 break;
1885 case INSTR_MOVCR2:
1886 gpreg = decode_src_reg(prefix, buffer[index+2]);
1887 mov_from_cr(cr, gpreg, regs);
1888 break;
1890 case INSTR_CLTS:
1891 /* TS being cleared means that it's time to restore fpu state. */
1892 setup_fpu(current);
1893 vmcb->exception_intercepts &= ~EXCEPTION_BITMAP_NM;
1894 vmcb->cr0 &= ~X86_CR0_TS; /* clear TS */
1895 v->arch.hvm_svm.cpu_shadow_cr0 &= ~X86_CR0_TS; /* clear TS */
1896 break;
1898 case INSTR_LMSW:
1899 if (svm_dbg_on)
1900 svm_dump_inst(svm_rip2pointer(vmcb));
1902 gpreg = decode_src_reg(prefix, buffer[index+2]);
1903 value = get_reg(gpreg, regs, vmcb) & 0xF;
1905 if (svm_dbg_on)
1906 printk("CR0-LMSW value=%lx, reg=%d, inst_len=%d\n", value, gpreg,
1907 inst_len);
1909 value = (v->arch.hvm_svm.cpu_shadow_cr0 & ~0xF) | value;
1911 if (svm_dbg_on)
1912 printk("CR0-LMSW CR0 - New value=%lx\n", value);
1914 result = svm_set_cr0(value);
1915 break;
1917 case INSTR_SMSW:
1918 if (svm_dbg_on)
1919 svm_dump_inst(svm_rip2pointer(vmcb));
1920 value = v->arch.hvm_svm.cpu_shadow_cr0;
1921 gpreg = decode_src_reg(prefix, buffer[index+2]);
1922 set_reg(gpreg, value, regs, vmcb);
1924 if (svm_dbg_on)
1925 printk("CR0-SMSW value=%lx, reg=%d, inst_len=%d\n", value, gpreg,
1926 inst_len);
1927 break;
1929 default:
1930 __hvm_bug(regs);
1931 break;
1934 ASSERT(inst_len);
1936 __update_guest_eip(vmcb, inst_len);
1938 return result;
1941 static inline void svm_do_msr_access(
1942 struct vcpu *v, struct cpu_user_regs *regs)
1944 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
1945 int inst_len;
1946 u64 msr_content=0;
1947 u32 eax, edx;
1949 ASSERT(vmcb);
1951 HVM_DBG_LOG(DBG_LEVEL_1, "svm_do_msr_access: ecx=%lx, eax=%lx, edx=%lx, "
1952 "exitinfo = %lx", (unsigned long)regs->ecx,
1953 (unsigned long)regs->eax, (unsigned long)regs->edx,
1954 (unsigned long)vmcb->exitinfo1);
1956 /* is it a read? */
1957 if (vmcb->exitinfo1 == 0)
1959 inst_len = __get_instruction_length(vmcb, INSTR_RDMSR, NULL);
1961 regs->edx = 0;
1962 switch (regs->ecx) {
1963 case MSR_IA32_TIME_STAMP_COUNTER:
1964 msr_content = hvm_get_guest_time(v);
1965 break;
1966 case MSR_IA32_SYSENTER_CS:
1967 msr_content = vmcb->sysenter_cs;
1968 break;
1969 case MSR_IA32_SYSENTER_ESP:
1970 msr_content = vmcb->sysenter_esp;
1971 break;
1972 case MSR_IA32_SYSENTER_EIP:
1973 msr_content = vmcb->sysenter_eip;
1974 break;
1975 case MSR_IA32_APICBASE:
1976 msr_content = VLAPIC(v) ? VLAPIC(v)->apic_base_msr : 0;
1977 break;
1978 default:
1979 if (long_mode_do_msr_read(regs))
1980 goto done;
1982 if ( rdmsr_hypervisor_regs(regs->ecx, &eax, &edx) )
1984 regs->eax = eax;
1985 regs->edx = edx;
1986 goto done;
1989 rdmsr_safe(regs->ecx, regs->eax, regs->edx);
1990 break;
1992 regs->eax = msr_content & 0xFFFFFFFF;
1993 regs->edx = msr_content >> 32;
1995 else
1997 inst_len = __get_instruction_length(vmcb, INSTR_WRMSR, NULL);
1998 msr_content = (u32)regs->eax | ((u64)regs->edx << 32);
2000 switch (regs->ecx)
2002 case MSR_IA32_TIME_STAMP_COUNTER:
2003 hvm_set_guest_time(v, msr_content);
2004 break;
2005 case MSR_IA32_SYSENTER_CS:
2006 vmcb->sysenter_cs = msr_content;
2007 break;
2008 case MSR_IA32_SYSENTER_ESP:
2009 vmcb->sysenter_esp = msr_content;
2010 break;
2011 case MSR_IA32_SYSENTER_EIP:
2012 vmcb->sysenter_eip = msr_content;
2013 break;
2014 case MSR_IA32_APICBASE:
2015 vlapic_msr_set(VLAPIC(v), msr_content);
2016 break;
2017 default:
2018 if ( !long_mode_do_msr_write(regs) )
2019 wrmsr_hypervisor_regs(regs->ecx, regs->eax, regs->edx);
2020 break;
2024 done:
2026 HVM_DBG_LOG(DBG_LEVEL_1, "svm_do_msr_access returns: "
2027 "ecx=%lx, eax=%lx, edx=%lx",
2028 (unsigned long)regs->ecx, (unsigned long)regs->eax,
2029 (unsigned long)regs->edx);
2031 __update_guest_eip(vmcb, inst_len);
2035 static inline void svm_vmexit_do_hlt(struct vmcb_struct *vmcb)
2037 __update_guest_eip(vmcb, 1);
2039 /* Check for interrupt not handled or new interrupt. */
2040 if ( (vmcb->rflags & X86_EFLAGS_IF) &&
2041 (vmcb->vintr.fields.irq || cpu_has_pending_irq(current)) )
2042 return;
2044 hvm_hlt(vmcb->rflags);
2048 static void svm_vmexit_do_invd(struct vmcb_struct *vmcb)
2050 int inst_len;
2052 /* Invalidate the cache - we can't really do that safely - maybe we should
2053 * WBINVD, but I think it's just fine to completely ignore it - we should
2054 * have cache-snooping that solves it anyways. -- Mats P.
2055 */
2057 /* Tell the user that we did this - just in case someone runs some really
2058 * weird operating system and wants to know why it's not working...
2059 */
2060 printk("INVD instruction intercepted - ignored\n");
2062 inst_len = __get_instruction_length(vmcb, INSTR_INVD, NULL);
2063 __update_guest_eip(vmcb, inst_len);
2069 #ifdef XEN_DEBUGGER
2070 static void svm_debug_save_cpu_user_regs(struct vmcb_struct *vmcb,
2071 struct cpu_user_regs *regs)
2073 regs->eip = vmcb->rip;
2074 regs->esp = vmcb->rsp;
2075 regs->eflags = vmcb->rflags;
2077 regs->xcs = vmcb->cs.sel;
2078 regs->xds = vmcb->ds.sel;
2079 regs->xes = vmcb->es.sel;
2080 regs->xfs = vmcb->fs.sel;
2081 regs->xgs = vmcb->gs.sel;
2082 regs->xss = vmcb->ss.sel;
2086 static void svm_debug_restore_cpu_user_regs(struct cpu_user_regs *regs)
2088 vmcb->ss.sel = regs->xss;
2089 vmcb->rsp = regs->esp;
2090 vmcb->rflags = regs->eflags;
2091 vmcb->cs.sel = regs->xcs;
2092 vmcb->rip = regs->eip;
2094 vmcb->gs.sel = regs->xgs;
2095 vmcb->fs.sel = regs->xfs;
2096 vmcb->es.sel = regs->xes;
2097 vmcb->ds.sel = regs->xds;
2099 #endif
2102 void svm_handle_invlpg(const short invlpga, struct cpu_user_regs *regs)
2104 struct vcpu *v = current;
2105 u8 opcode[MAX_INST_LEN], prefix, length = MAX_INST_LEN;
2106 unsigned long g_vaddr;
2107 int inst_len;
2108 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
2110 ASSERT(vmcb);
2111 /*
2112 * Unknown how many bytes the invlpg instruction will take. Use the
2113 * maximum instruction length here
2114 */
2115 if (inst_copy_from_guest(opcode, svm_rip2pointer(vmcb), length) < length)
2117 printk("svm_handle_invlpg (): Error reading memory %d bytes\n",
2118 length);
2119 __hvm_bug(regs);
2122 if (invlpga)
2124 inst_len = __get_instruction_length(vmcb, INSTR_INVLPGA, opcode);
2125 ASSERT(inst_len > 0);
2126 __update_guest_eip(vmcb, inst_len);
2128 /*
2129 * The address is implicit on this instruction. At the moment, we don't
2130 * use ecx (ASID) to identify individual guests pages
2131 */
2132 g_vaddr = regs->eax;
2134 else
2136 /* What about multiple prefix codes? */
2137 prefix = (is_prefix(opcode[0])?opcode[0]:0);
2138 inst_len = __get_instruction_length(vmcb, INSTR_INVLPG, opcode);
2139 ASSERT(inst_len > 0);
2141 inst_len--;
2142 length -= inst_len;
2144 /*
2145 * Decode memory operand of the instruction including ModRM, SIB, and
2146 * displacement to get effecticve address and length in bytes. Assume
2147 * the system in either 32- or 64-bit mode.
2148 */
2149 g_vaddr = get_effective_addr_modrm64(vmcb, regs, prefix,
2150 &opcode[inst_len], &length);
2152 inst_len += length;
2153 __update_guest_eip (vmcb, inst_len);
2156 /* Overkill, we may not this */
2157 set_bit(ARCH_SVM_VMCB_ASSIGN_ASID, &v->arch.hvm_svm.flags);
2158 shadow_invlpg(v, g_vaddr);
2162 /*
2163 * Reset to realmode causes execution to start at 0xF000:0xFFF0 in
2164 * 16-bit realmode. Basically, this mimics a processor reset.
2166 * returns 0 on success, non-zero otherwise
2167 */
2168 static int svm_do_vmmcall_reset_to_realmode(struct vcpu *v,
2169 struct cpu_user_regs *regs)
2171 struct vmcb_struct *vmcb;
2173 ASSERT(v);
2174 ASSERT(regs);
2176 vmcb = v->arch.hvm_svm.vmcb;
2178 ASSERT(vmcb);
2180 /* clear the vmcb and user regs */
2181 memset(regs, 0, sizeof(struct cpu_user_regs));
2183 /* VMCB Control */
2184 vmcb->tsc_offset = 0;
2186 /* VMCB State */
2187 vmcb->cr0 = X86_CR0_ET | X86_CR0_PG;
2188 v->arch.hvm_svm.cpu_shadow_cr0 = X86_CR0_ET;
2190 vmcb->cr2 = 0;
2191 vmcb->efer = EFER_SVME;
2193 vmcb->cr4 = SVM_CR4_HOST_MASK;
2194 v->arch.hvm_svm.cpu_shadow_cr4 = 0;
2195 clear_bit(SVM_CPU_STATE_PAE_ENABLED, &v->arch.hvm_svm.cpu_state);
2197 /* This will jump to ROMBIOS */
2198 vmcb->rip = 0xFFF0;
2200 /* setup the segment registers and all their hidden states */
2201 vmcb->cs.sel = 0xF000;
2202 vmcb->cs.attributes.bytes = 0x089b;
2203 vmcb->cs.limit = 0xffff;
2204 vmcb->cs.base = 0x000F0000;
2206 vmcb->ss.sel = 0x00;
2207 vmcb->ss.attributes.bytes = 0x0893;
2208 vmcb->ss.limit = 0xffff;
2209 vmcb->ss.base = 0x00;
2211 vmcb->ds.sel = 0x00;
2212 vmcb->ds.attributes.bytes = 0x0893;
2213 vmcb->ds.limit = 0xffff;
2214 vmcb->ds.base = 0x00;
2216 vmcb->es.sel = 0x00;
2217 vmcb->es.attributes.bytes = 0x0893;
2218 vmcb->es.limit = 0xffff;
2219 vmcb->es.base = 0x00;
2221 vmcb->fs.sel = 0x00;
2222 vmcb->fs.attributes.bytes = 0x0893;
2223 vmcb->fs.limit = 0xffff;
2224 vmcb->fs.base = 0x00;
2226 vmcb->gs.sel = 0x00;
2227 vmcb->gs.attributes.bytes = 0x0893;
2228 vmcb->gs.limit = 0xffff;
2229 vmcb->gs.base = 0x00;
2231 vmcb->ldtr.sel = 0x00;
2232 vmcb->ldtr.attributes.bytes = 0x0000;
2233 vmcb->ldtr.limit = 0x0;
2234 vmcb->ldtr.base = 0x00;
2236 vmcb->gdtr.sel = 0x00;
2237 vmcb->gdtr.attributes.bytes = 0x0000;
2238 vmcb->gdtr.limit = 0x0;
2239 vmcb->gdtr.base = 0x00;
2241 vmcb->tr.sel = 0;
2242 vmcb->tr.attributes.bytes = 0;
2243 vmcb->tr.limit = 0x0;
2244 vmcb->tr.base = 0;
2246 vmcb->idtr.sel = 0x00;
2247 vmcb->idtr.attributes.bytes = 0x0000;
2248 vmcb->idtr.limit = 0x3ff;
2249 vmcb->idtr.base = 0x00;
2251 vmcb->rax = 0;
2252 vmcb->rsp = 0;
2254 return 0;
2258 /*
2259 * svm_do_vmmcall - SVM VMMCALL handler
2261 * returns 0 on success, non-zero otherwise
2262 */
2263 static int svm_do_vmmcall(struct vcpu *v, struct cpu_user_regs *regs)
2265 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
2266 int inst_len;
2268 ASSERT(vmcb);
2269 ASSERT(regs);
2271 inst_len = __get_instruction_length(vmcb, INSTR_VMCALL, NULL);
2272 ASSERT(inst_len > 0);
2274 if ( regs->eax & 0x80000000 )
2276 /* VMMCALL sanity check */
2277 if ( vmcb->cpl > get_vmmcall_cpl(regs->edi) )
2279 printf("VMMCALL CPL check failed\n");
2280 return -1;
2283 /* handle the request */
2284 switch ( regs->eax )
2286 case VMMCALL_RESET_TO_REALMODE:
2287 if ( svm_do_vmmcall_reset_to_realmode(v, regs) )
2289 printf("svm_do_vmmcall_reset_to_realmode() failed\n");
2290 return -1;
2292 /* since we just reset the VMCB, return without adjusting
2293 * the eip */
2294 return 0;
2296 case VMMCALL_DEBUG:
2297 printf("DEBUG features not implemented yet\n");
2298 break;
2299 default:
2300 break;
2303 hvm_print_line(v, regs->eax); /* provides the current domain */
2305 else
2307 hvm_do_hypercall(regs);
2310 __update_guest_eip(vmcb, inst_len);
2311 return 0;
2315 void svm_dump_inst(unsigned long eip)
2317 u8 opcode[256];
2318 unsigned long ptr;
2319 int len;
2320 int i;
2322 ptr = eip & ~0xff;
2323 len = 0;
2325 if (hvm_copy_from_guest_virt(opcode, ptr, sizeof(opcode)) == 0)
2326 len = sizeof(opcode);
2328 printf("Code bytes around(len=%d) %lx:", len, eip);
2329 for (i = 0; i < len; i++)
2331 if ((i & 0x0f) == 0)
2332 printf("\n%08lx:", ptr+i);
2334 printf("%02x ", opcode[i]);
2337 printf("\n");
2341 void svm_dump_regs(const char *from, struct cpu_user_regs *regs)
2343 struct vcpu *v = current;
2344 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
2345 unsigned long pt = pagetable_get_paddr(v->arch.shadow_table);
2347 printf("%s: guest registers from %s:\n", __func__, from);
2348 #if defined (__x86_64__)
2349 printk("rax: %016lx rbx: %016lx rcx: %016lx\n",
2350 regs->rax, regs->rbx, regs->rcx);
2351 printk("rdx: %016lx rsi: %016lx rdi: %016lx\n",
2352 regs->rdx, regs->rsi, regs->rdi);
2353 printk("rbp: %016lx rsp: %016lx r8: %016lx\n",
2354 regs->rbp, regs->rsp, regs->r8);
2355 printk("r9: %016lx r10: %016lx r11: %016lx\n",
2356 regs->r9, regs->r10, regs->r11);
2357 printk("r12: %016lx r13: %016lx r14: %016lx\n",
2358 regs->r12, regs->r13, regs->r14);
2359 printk("r15: %016lx cr0: %016lx cr3: %016lx\n",
2360 regs->r15, v->arch.hvm_svm.cpu_shadow_cr0, vmcb->cr3);
2361 #else
2362 printf("eax: %08x, ebx: %08x, ecx: %08x, edx: %08x\n",
2363 regs->eax, regs->ebx, regs->ecx, regs->edx);
2364 printf("edi: %08x, esi: %08x, ebp: %08x, esp: %08x\n",
2365 regs->edi, regs->esi, regs->ebp, regs->esp);
2366 printf("%s: guest cr0: %lx\n", __func__,
2367 v->arch.hvm_svm.cpu_shadow_cr0);
2368 printf("guest CR3 = %llx\n", vmcb->cr3);
2369 #endif
2370 printf("%s: pt = %lx\n", __func__, pt);
2374 void svm_dump_host_regs(const char *from)
2376 struct vcpu *v = current;
2377 unsigned long pt = pt = pagetable_get_paddr(v->arch.monitor_table);
2378 unsigned long cr3, cr0;
2379 printf("Host registers at %s\n", from);
2381 __asm__ __volatile__ ("\tmov %%cr0,%0\n"
2382 "\tmov %%cr3,%1\n"
2383 : "=r" (cr0), "=r"(cr3));
2384 printf("%s: pt = %lx, cr3 = %lx, cr0 = %lx\n", __func__, pt, cr3, cr0);
2387 #ifdef SVM_EXTRA_DEBUG
2388 static char *exit_reasons[] = {
2389 [VMEXIT_CR0_READ] = "CR0_READ",
2390 [VMEXIT_CR1_READ] = "CR1_READ",
2391 [VMEXIT_CR2_READ] = "CR2_READ",
2392 [VMEXIT_CR3_READ] = "CR3_READ",
2393 [VMEXIT_CR4_READ] = "CR4_READ",
2394 [VMEXIT_CR5_READ] = "CR5_READ",
2395 [VMEXIT_CR6_READ] = "CR6_READ",
2396 [VMEXIT_CR7_READ] = "CR7_READ",
2397 [VMEXIT_CR8_READ] = "CR8_READ",
2398 [VMEXIT_CR9_READ] = "CR9_READ",
2399 [VMEXIT_CR10_READ] = "CR10_READ",
2400 [VMEXIT_CR11_READ] = "CR11_READ",
2401 [VMEXIT_CR12_READ] = "CR12_READ",
2402 [VMEXIT_CR13_READ] = "CR13_READ",
2403 [VMEXIT_CR14_READ] = "CR14_READ",
2404 [VMEXIT_CR15_READ] = "CR15_READ",
2405 [VMEXIT_CR0_WRITE] = "CR0_WRITE",
2406 [VMEXIT_CR1_WRITE] = "CR1_WRITE",
2407 [VMEXIT_CR2_WRITE] = "CR2_WRITE",
2408 [VMEXIT_CR3_WRITE] = "CR3_WRITE",
2409 [VMEXIT_CR4_WRITE] = "CR4_WRITE",
2410 [VMEXIT_CR5_WRITE] = "CR5_WRITE",
2411 [VMEXIT_CR6_WRITE] = "CR6_WRITE",
2412 [VMEXIT_CR7_WRITE] = "CR7_WRITE",
2413 [VMEXIT_CR8_WRITE] = "CR8_WRITE",
2414 [VMEXIT_CR9_WRITE] = "CR9_WRITE",
2415 [VMEXIT_CR10_WRITE] = "CR10_WRITE",
2416 [VMEXIT_CR11_WRITE] = "CR11_WRITE",
2417 [VMEXIT_CR12_WRITE] = "CR12_WRITE",
2418 [VMEXIT_CR13_WRITE] = "CR13_WRITE",
2419 [VMEXIT_CR14_WRITE] = "CR14_WRITE",
2420 [VMEXIT_CR15_WRITE] = "CR15_WRITE",
2421 [VMEXIT_DR0_READ] = "DR0_READ",
2422 [VMEXIT_DR1_READ] = "DR1_READ",
2423 [VMEXIT_DR2_READ] = "DR2_READ",
2424 [VMEXIT_DR3_READ] = "DR3_READ",
2425 [VMEXIT_DR4_READ] = "DR4_READ",
2426 [VMEXIT_DR5_READ] = "DR5_READ",
2427 [VMEXIT_DR6_READ] = "DR6_READ",
2428 [VMEXIT_DR7_READ] = "DR7_READ",
2429 [VMEXIT_DR8_READ] = "DR8_READ",
2430 [VMEXIT_DR9_READ] = "DR9_READ",
2431 [VMEXIT_DR10_READ] = "DR10_READ",
2432 [VMEXIT_DR11_READ] = "DR11_READ",
2433 [VMEXIT_DR12_READ] = "DR12_READ",
2434 [VMEXIT_DR13_READ] = "DR13_READ",
2435 [VMEXIT_DR14_READ] = "DR14_READ",
2436 [VMEXIT_DR15_READ] = "DR15_READ",
2437 [VMEXIT_DR0_WRITE] = "DR0_WRITE",
2438 [VMEXIT_DR1_WRITE] = "DR1_WRITE",
2439 [VMEXIT_DR2_WRITE] = "DR2_WRITE",
2440 [VMEXIT_DR3_WRITE] = "DR3_WRITE",
2441 [VMEXIT_DR4_WRITE] = "DR4_WRITE",
2442 [VMEXIT_DR5_WRITE] = "DR5_WRITE",
2443 [VMEXIT_DR6_WRITE] = "DR6_WRITE",
2444 [VMEXIT_DR7_WRITE] = "DR7_WRITE",
2445 [VMEXIT_DR8_WRITE] = "DR8_WRITE",
2446 [VMEXIT_DR9_WRITE] = "DR9_WRITE",
2447 [VMEXIT_DR10_WRITE] = "DR10_WRITE",
2448 [VMEXIT_DR11_WRITE] = "DR11_WRITE",
2449 [VMEXIT_DR12_WRITE] = "DR12_WRITE",
2450 [VMEXIT_DR13_WRITE] = "DR13_WRITE",
2451 [VMEXIT_DR14_WRITE] = "DR14_WRITE",
2452 [VMEXIT_DR15_WRITE] = "DR15_WRITE",
2453 [VMEXIT_EXCEPTION_DE] = "EXCEPTION_DE",
2454 [VMEXIT_EXCEPTION_DB] = "EXCEPTION_DB",
2455 [VMEXIT_EXCEPTION_NMI] = "EXCEPTION_NMI",
2456 [VMEXIT_EXCEPTION_BP] = "EXCEPTION_BP",
2457 [VMEXIT_EXCEPTION_OF] = "EXCEPTION_OF",
2458 [VMEXIT_EXCEPTION_BR] = "EXCEPTION_BR",
2459 [VMEXIT_EXCEPTION_UD] = "EXCEPTION_UD",
2460 [VMEXIT_EXCEPTION_NM] = "EXCEPTION_NM",
2461 [VMEXIT_EXCEPTION_DF] = "EXCEPTION_DF",
2462 [VMEXIT_EXCEPTION_09] = "EXCEPTION_09",
2463 [VMEXIT_EXCEPTION_TS] = "EXCEPTION_TS",
2464 [VMEXIT_EXCEPTION_NP] = "EXCEPTION_NP",
2465 [VMEXIT_EXCEPTION_SS] = "EXCEPTION_SS",
2466 [VMEXIT_EXCEPTION_GP] = "EXCEPTION_GP",
2467 [VMEXIT_EXCEPTION_PF] = "EXCEPTION_PF",
2468 [VMEXIT_EXCEPTION_15] = "EXCEPTION_15",
2469 [VMEXIT_EXCEPTION_MF] = "EXCEPTION_MF",
2470 [VMEXIT_EXCEPTION_AC] = "EXCEPTION_AC",
2471 [VMEXIT_EXCEPTION_MC] = "EXCEPTION_MC",
2472 [VMEXIT_EXCEPTION_XF] = "EXCEPTION_XF",
2473 [VMEXIT_INTR] = "INTR",
2474 [VMEXIT_NMI] = "NMI",
2475 [VMEXIT_SMI] = "SMI",
2476 [VMEXIT_INIT] = "INIT",
2477 [VMEXIT_VINTR] = "VINTR",
2478 [VMEXIT_CR0_SEL_WRITE] = "CR0_SEL_WRITE",
2479 [VMEXIT_IDTR_READ] = "IDTR_READ",
2480 [VMEXIT_GDTR_READ] = "GDTR_READ",
2481 [VMEXIT_LDTR_READ] = "LDTR_READ",
2482 [VMEXIT_TR_READ] = "TR_READ",
2483 [VMEXIT_IDTR_WRITE] = "IDTR_WRITE",
2484 [VMEXIT_GDTR_WRITE] = "GDTR_WRITE",
2485 [VMEXIT_LDTR_WRITE] = "LDTR_WRITE",
2486 [VMEXIT_TR_WRITE] = "TR_WRITE",
2487 [VMEXIT_RDTSC] = "RDTSC",
2488 [VMEXIT_RDPMC] = "RDPMC",
2489 [VMEXIT_PUSHF] = "PUSHF",
2490 [VMEXIT_POPF] = "POPF",
2491 [VMEXIT_CPUID] = "CPUID",
2492 [VMEXIT_RSM] = "RSM",
2493 [VMEXIT_IRET] = "IRET",
2494 [VMEXIT_SWINT] = "SWINT",
2495 [VMEXIT_INVD] = "INVD",
2496 [VMEXIT_PAUSE] = "PAUSE",
2497 [VMEXIT_HLT] = "HLT",
2498 [VMEXIT_INVLPG] = "INVLPG",
2499 [VMEXIT_INVLPGA] = "INVLPGA",
2500 [VMEXIT_IOIO] = "IOIO",
2501 [VMEXIT_MSR] = "MSR",
2502 [VMEXIT_TASK_SWITCH] = "TASK_SWITCH",
2503 [VMEXIT_FERR_FREEZE] = "FERR_FREEZE",
2504 [VMEXIT_SHUTDOWN] = "SHUTDOWN",
2505 [VMEXIT_VMRUN] = "VMRUN",
2506 [VMEXIT_VMMCALL] = "VMMCALL",
2507 [VMEXIT_VMLOAD] = "VMLOAD",
2508 [VMEXIT_VMSAVE] = "VMSAVE",
2509 [VMEXIT_STGI] = "STGI",
2510 [VMEXIT_CLGI] = "CLGI",
2511 [VMEXIT_SKINIT] = "SKINIT",
2512 [VMEXIT_RDTSCP] = "RDTSCP",
2513 [VMEXIT_ICEBP] = "ICEBP",
2514 [VMEXIT_NPF] = "NPF"
2515 };
2516 #endif /* SVM_EXTRA_DEBUG */
2518 #ifdef SVM_WALK_GUEST_PAGES
2519 void walk_shadow_and_guest_pt(unsigned long gva)
2521 l2_pgentry_t gpde;
2522 l2_pgentry_t spde;
2523 l1_pgentry_t gpte;
2524 l1_pgentry_t spte;
2525 struct vcpu *v = current;
2526 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
2527 unsigned long gpa;
2529 gpa = shadow_gva_to_gpa(current, gva);
2530 printk( "gva = %lx, gpa=%lx, gCR3=%x\n", gva, gpa, (u32)vmcb->cr3 );
2531 if( !svm_paging_enabled(v) || mmio_space(gpa) )
2532 return;
2534 /* let's dump the guest and shadow page info */
2536 __guest_get_l2e(v, gva, &gpde);
2537 printk( "G-PDE = %x, flags=%x\n", gpde.l2, l2e_get_flags(gpde) );
2538 __shadow_get_l2e( v, gva, &spde );
2539 printk( "S-PDE = %x, flags=%x\n", spde.l2, l2e_get_flags(spde) );
2541 if ( unlikely(!(l2e_get_flags(gpde) & _PAGE_PRESENT)) )
2542 return;
2544 spte = l1e_empty();
2546 /* This is actually overkill - we only need to ensure the hl2 is in-sync.*/
2547 shadow_sync_va(v, gva);
2549 gpte.l1 = 0;
2550 __copy_from_user(&gpte, &linear_pg_table[ l1_linear_offset(gva) ],
2551 sizeof(gpte) );
2552 printk( "G-PTE = %x, flags=%x\n", gpte.l1, l1e_get_flags(gpte) );
2554 BUG(); // need to think about this, and convert usage of
2555 // phys_to_machine_mapping to use pagetable format...
2556 __copy_from_user( &spte, &phys_to_machine_mapping[ l1e_get_pfn( gpte ) ],
2557 sizeof(spte) );
2559 printk( "S-PTE = %x, flags=%x\n", spte.l1, l1e_get_flags(spte));
2561 #endif /* SVM_WALK_GUEST_PAGES */
2564 asmlinkage void svm_vmexit_handler(struct cpu_user_regs *regs)
2566 unsigned int exit_reason;
2567 unsigned long eip;
2568 struct vcpu *v = current;
2569 int error;
2570 int do_debug = 0;
2571 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
2573 ASSERT(vmcb);
2575 exit_reason = vmcb->exitcode;
2576 save_svm_cpu_user_regs(v, regs);
2578 vmcb->tlb_control = 1;
2581 if (exit_reason == VMEXIT_INVALID)
2583 svm_dump_vmcb(__func__, vmcb);
2584 domain_crash_synchronous();
2587 #ifdef SVM_EXTRA_DEBUG
2589 #if defined(__i386__)
2590 #define rip eip
2591 #endif
2593 static unsigned long intercepts_counter = 0;
2595 if (svm_dbg_on && exit_reason == VMEXIT_EXCEPTION_PF)
2597 if (svm_paging_enabled(v) &&
2598 !mmio_space(shadow_gva_to_gpa(current, vmcb->exitinfo2)))
2600 printk("I%08ld,ExC=%s(%d),IP=%x:%"PRIx64","
2601 "I1=%"PRIx64",I2=%"PRIx64",INT=%"PRIx64", "
2602 "gpa=%"PRIx64"\n", intercepts_counter,
2603 exit_reasons[exit_reason], exit_reason, regs->cs,
2604 (u64)regs->rip,
2605 (u64)vmcb->exitinfo1,
2606 (u64)vmcb->exitinfo2,
2607 (u64)vmcb->exitintinfo.bytes,
2608 (u64)shadow_gva_to_gpa(current, vmcb->exitinfo2));
2610 else
2612 printk("I%08ld,ExC=%s(%d),IP=%x:%"PRIx64","
2613 "I1=%"PRIx64",I2=%"PRIx64",INT=%"PRIx64"\n",
2614 intercepts_counter,
2615 exit_reasons[exit_reason], exit_reason, regs->cs,
2616 (u64)regs->rip,
2617 (u64)vmcb->exitinfo1,
2618 (u64)vmcb->exitinfo2,
2619 (u64)vmcb->exitintinfo.bytes );
2622 else if ( svm_dbg_on
2623 && exit_reason != VMEXIT_IOIO
2624 && exit_reason != VMEXIT_INTR)
2627 if (exit_reasons[exit_reason])
2629 printk("I%08ld,ExC=%s(%d),IP=%x:%"PRIx64","
2630 "I1=%"PRIx64",I2=%"PRIx64",INT=%"PRIx64"\n",
2631 intercepts_counter,
2632 exit_reasons[exit_reason], exit_reason, regs->cs,
2633 (u64)regs->rip,
2634 (u64)vmcb->exitinfo1,
2635 (u64)vmcb->exitinfo2,
2636 (u64)vmcb->exitintinfo.bytes);
2638 else
2640 printk("I%08ld,ExC=%d(0x%x),IP=%x:%"PRIx64","
2641 "I1=%"PRIx64",I2=%"PRIx64",INT=%"PRIx64"\n",
2642 intercepts_counter, exit_reason, exit_reason, regs->cs,
2643 (u64)regs->rip,
2644 (u64)vmcb->exitinfo1,
2645 (u64)vmcb->exitinfo2,
2646 (u64)vmcb->exitintinfo.bytes);
2650 #ifdef SVM_WALK_GUEST_PAGES
2651 if( exit_reason == VMEXIT_EXCEPTION_PF
2652 && ( ( vmcb->exitinfo2 == vmcb->rip )
2653 || vmcb->exitintinfo.bytes) )
2655 if ( svm_paging_enabled(v) &&
2656 !mmio_space(gva_to_gpa(vmcb->exitinfo2)) )
2657 walk_shadow_and_guest_pt(vmcb->exitinfo2);
2659 #endif
2661 intercepts_counter++;
2663 #if 0
2664 if (svm_dbg_on)
2665 do_debug = svm_do_debugout(exit_reason);
2666 #endif
2668 if (do_debug)
2670 printk("%s:+ guest_table = 0x%08x, monitor_table = 0x%08x, "
2671 "shadow_table = 0x%08x\n",
2672 __func__,
2673 (int) v->arch.guest_table.pfn,
2674 (int) v->arch.monitor_table.pfn,
2675 (int) v->arch.shadow_table.pfn);
2677 svm_dump_vmcb(__func__, vmcb);
2678 svm_dump_regs(__func__, regs);
2679 svm_dump_inst(svm_rip2pointer(vmcb));
2682 #if defined(__i386__)
2683 #undef rip
2684 #endif
2687 #endif /* SVM_EXTRA_DEBUG */
2690 perfc_incra(svmexits, exit_reason);
2691 eip = vmcb->rip;
2693 #ifdef SVM_EXTRA_DEBUG
2694 if (do_debug)
2696 printk("eip = %lx, exit_reason = %d (0x%x)\n",
2697 eip, exit_reason, exit_reason);
2699 #endif /* SVM_EXTRA_DEBUG */
2701 TRACE_3D(TRC_VMX_VMEXIT, v->domain->domain_id, eip, exit_reason);
2703 switch (exit_reason)
2705 case VMEXIT_EXCEPTION_DB:
2707 #ifdef XEN_DEBUGGER
2708 svm_debug_save_cpu_user_regs(regs);
2709 pdb_handle_exception(1, regs, 1);
2710 svm_debug_restore_cpu_user_regs(regs);
2711 #else
2712 svm_store_cpu_user_regs(regs, v);
2713 domain_pause_for_debugger();
2714 #endif
2716 break;
2718 case VMEXIT_NMI:
2719 do_nmi(regs, 0);
2720 break;
2722 case VMEXIT_SMI:
2723 /*
2724 * For asynchronous SMI's, we just need to allow global interrupts
2725 * so that the SMI is taken properly in the context of the host. The
2726 * standard code does a STGI after the VMEXIT which should accomplish
2727 * this task. Continue as normal and restart the guest.
2728 */
2729 break;
2731 case VMEXIT_INIT:
2732 /*
2733 * Nothing to do, in fact we should never get to this point.
2734 */
2735 break;
2737 case VMEXIT_EXCEPTION_BP:
2738 #ifdef XEN_DEBUGGER
2739 svm_debug_save_cpu_user_regs(regs);
2740 pdb_handle_exception(3, regs, 1);
2741 svm_debug_restore_cpu_user_regs(regs);
2742 #else
2743 if ( test_bit(_DOMF_debugging, &v->domain->domain_flags) )
2744 domain_pause_for_debugger();
2745 else
2746 svm_inject_exception(v, TRAP_int3, 0, 0);
2747 #endif
2748 break;
2750 case VMEXIT_EXCEPTION_NM:
2751 svm_do_no_device_fault(vmcb);
2752 break;
2754 case VMEXIT_EXCEPTION_GP:
2755 /* This should probably not be trapped in the future */
2756 regs->error_code = vmcb->exitinfo1;
2757 svm_do_general_protection_fault(v, regs);
2758 break;
2760 case VMEXIT_EXCEPTION_PF:
2762 unsigned long va;
2763 va = vmcb->exitinfo2;
2764 regs->error_code = vmcb->exitinfo1;
2765 HVM_DBG_LOG(DBG_LEVEL_VMMU,
2766 "eax=%lx, ebx=%lx, ecx=%lx, edx=%lx, esi=%lx, edi=%lx",
2767 (unsigned long)regs->eax, (unsigned long)regs->ebx,
2768 (unsigned long)regs->ecx, (unsigned long)regs->edx,
2769 (unsigned long)regs->esi, (unsigned long)regs->edi);
2771 if (!(error = svm_do_page_fault(va, regs)))
2773 /* Inject #PG using Interruption-Information Fields */
2774 svm_inject_exception(v, TRAP_page_fault, 1, regs->error_code);
2776 v->arch.hvm_svm.cpu_cr2 = va;
2777 vmcb->cr2 = va;
2778 TRACE_3D(TRC_VMX_INT, v->domain->domain_id,
2779 VMEXIT_EXCEPTION_PF, va);
2781 break;
2784 case VMEXIT_EXCEPTION_DF:
2785 /* Debug info to hopefully help debug WHY the guest double-faulted. */
2786 svm_dump_vmcb(__func__, vmcb);
2787 svm_dump_regs(__func__, regs);
2788 svm_dump_inst(svm_rip2pointer(vmcb));
2789 svm_inject_exception(v, TRAP_double_fault, 1, 0);
2790 break;
2792 case VMEXIT_INTR:
2793 break;
2795 case VMEXIT_INVD:
2796 svm_vmexit_do_invd(vmcb);
2797 break;
2799 case VMEXIT_GDTR_WRITE:
2800 printk("WRITE to GDTR\n");
2801 break;
2803 case VMEXIT_TASK_SWITCH:
2804 __hvm_bug(regs);
2805 break;
2807 case VMEXIT_CPUID:
2808 svm_vmexit_do_cpuid(vmcb, regs->eax, regs);
2809 break;
2811 case VMEXIT_HLT:
2812 svm_vmexit_do_hlt(vmcb);
2813 break;
2815 case VMEXIT_INVLPG:
2816 svm_handle_invlpg(0, regs);
2817 break;
2819 case VMEXIT_INVLPGA:
2820 svm_handle_invlpg(1, regs);
2821 break;
2823 case VMEXIT_VMMCALL:
2824 svm_do_vmmcall(v, regs);
2825 break;
2827 case VMEXIT_CR0_READ:
2828 svm_cr_access(v, 0, TYPE_MOV_FROM_CR, regs);
2829 break;
2831 case VMEXIT_CR2_READ:
2832 svm_cr_access(v, 2, TYPE_MOV_FROM_CR, regs);
2833 break;
2835 case VMEXIT_CR3_READ:
2836 svm_cr_access(v, 3, TYPE_MOV_FROM_CR, regs);
2837 break;
2839 case VMEXIT_CR4_READ:
2840 svm_cr_access(v, 4, TYPE_MOV_FROM_CR, regs);
2841 break;
2843 case VMEXIT_CR8_READ:
2844 svm_cr_access(v, 8, TYPE_MOV_FROM_CR, regs);
2845 break;
2847 case VMEXIT_CR0_WRITE:
2848 svm_cr_access(v, 0, TYPE_MOV_TO_CR, regs);
2849 break;
2851 case VMEXIT_CR2_WRITE:
2852 svm_cr_access(v, 2, TYPE_MOV_TO_CR, regs);
2853 break;
2855 case VMEXIT_CR3_WRITE:
2856 svm_cr_access(v, 3, TYPE_MOV_TO_CR, regs);
2857 local_flush_tlb();
2858 break;
2860 case VMEXIT_CR4_WRITE:
2861 svm_cr_access(v, 4, TYPE_MOV_TO_CR, regs);
2862 break;
2864 case VMEXIT_CR8_WRITE:
2865 svm_cr_access(v, 8, TYPE_MOV_TO_CR, regs);
2866 break;
2868 case VMEXIT_DR0_WRITE ... VMEXIT_DR7_WRITE:
2869 svm_dr_access(v, regs);
2870 break;
2872 case VMEXIT_IOIO:
2873 svm_io_instruction(v);
2874 break;
2876 case VMEXIT_MSR:
2877 svm_do_msr_access(v, regs);
2878 break;
2880 case VMEXIT_SHUTDOWN:
2881 printk("Guest shutdown exit\n");
2882 domain_crash_synchronous();
2883 break;
2885 default:
2886 printk("unexpected VMEXIT: exit reason = 0x%x, exitinfo1 = %"PRIx64", "
2887 "exitinfo2 = %"PRIx64"\n", exit_reason,
2888 (u64)vmcb->exitinfo1, (u64)vmcb->exitinfo2);
2889 __hvm_bug(regs); /* should not happen */
2890 break;
2893 #ifdef SVM_EXTRA_DEBUG
2894 if (do_debug)
2896 printk("%s: Done switch on vmexit_code\n", __func__);
2897 svm_dump_regs(__func__, regs);
2900 if (do_debug)
2902 printk("vmexit_handler():- guest_table = 0x%08x, "
2903 "monitor_table = 0x%08x, shadow_table = 0x%08x\n",
2904 (int)v->arch.guest_table.pfn,
2905 (int)v->arch.monitor_table.pfn,
2906 (int)v->arch.shadow_table.pfn);
2907 printk("svm_vmexit_handler: Returning\n");
2909 #endif
2911 return;
2914 asmlinkage void svm_load_cr2(void)
2916 struct vcpu *v = current;
2918 local_irq_disable();
2919 asm volatile("mov %0,%%cr2": :"r" (v->arch.hvm_svm.cpu_cr2));
2922 asmlinkage void svm_asid(void)
2924 struct vcpu *v = current;
2925 struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
2927 /*
2928 * if need to assign new asid, or if switching cores,
2929 * retire asid for the old core, and assign a new asid to the current core.
2930 */
2931 if ( test_bit( ARCH_SVM_VMCB_ASSIGN_ASID, &v->arch.hvm_svm.flags ) ||
2932 ( v->arch.hvm_svm.asid_core != v->arch.hvm_svm.launch_core )) {
2933 /* recycle asid */
2934 if ( !asidpool_assign_next(vmcb, 1,
2935 v->arch.hvm_svm.asid_core,
2936 v->arch.hvm_svm.launch_core) )
2938 /* If we get here, we have a major problem */
2939 domain_crash_synchronous();
2942 v->arch.hvm_svm.asid_core = v->arch.hvm_svm.launch_core;
2943 clear_bit( ARCH_SVM_VMCB_ASSIGN_ASID, &v->arch.hvm_svm.flags );
2947 /*
2948 * Local variables:
2949 * mode: C
2950 * c-set-style: "BSD"
2951 * c-basic-offset: 4
2952 * tab-width: 4
2953 * indent-tabs-mode: nil
2954 * End:
2955 */