ia64/xen-unstable

view linux-2.6-xen-sparse/include/asm-ia64/iosapic.h @ 9747:de2dc4e7966a

[IA64] Add support to physdev_ops

Add support to physdev ops, and thus give IOSAPIC RTEs
managed by Xen now. Dom0 now issues hypercall to r/w
RTE entry. Another change is the irq vector allocation
which is also owned by xen now.

After this change, the IOSAPIC is almost owned by xen
with only exception as IOSAPIC EOI which is still issued
by dom0 directly. But that's OK since currently dom0
owns all external physical devices. Later full event
channel mechanism will provide necessary support for
driver domain, and at that time, dom0 instead issues
physdev_op (PHYSDEVOP_IRQ_UNMASK_NOTIFY) naturally as
replace of IOSAPIC EOI.

Signed-off-by Kevin Tian <kevin.tian@intel.com>
author awilliam@xenbuild.aw
date Fri Apr 21 09:03:19 2006 -0600 (2006-04-21)
parents 19148831ab05
children
line source
1 #ifndef __ASM_IA64_IOSAPIC_H
2 #define __ASM_IA64_IOSAPIC_H
4 #define IOSAPIC_REG_SELECT 0x0
5 #define IOSAPIC_WINDOW 0x10
6 #define IOSAPIC_EOI 0x40
8 #define IOSAPIC_VERSION 0x1
10 /*
11 * Redirection table entry
12 */
13 #define IOSAPIC_RTE_LOW(i) (0x10+i*2)
14 #define IOSAPIC_RTE_HIGH(i) (0x11+i*2)
16 #define IOSAPIC_DEST_SHIFT 16
18 /*
19 * Delivery mode
20 */
21 #define IOSAPIC_DELIVERY_SHIFT 8
22 #define IOSAPIC_FIXED 0x0
23 #define IOSAPIC_LOWEST_PRIORITY 0x1
24 #define IOSAPIC_PMI 0x2
25 #define IOSAPIC_NMI 0x4
26 #define IOSAPIC_INIT 0x5
27 #define IOSAPIC_EXTINT 0x7
29 /*
30 * Interrupt polarity
31 */
32 #define IOSAPIC_POLARITY_SHIFT 13
33 #define IOSAPIC_POL_HIGH 0
34 #define IOSAPIC_POL_LOW 1
36 /*
37 * Trigger mode
38 */
39 #define IOSAPIC_TRIGGER_SHIFT 15
40 #define IOSAPIC_EDGE 0
41 #define IOSAPIC_LEVEL 1
43 /*
44 * Mask bit
45 */
47 #define IOSAPIC_MASK_SHIFT 16
48 #define IOSAPIC_MASK (1<<IOSAPIC_MASK_SHIFT)
50 #ifndef __ASSEMBLY__
52 #ifdef CONFIG_IOSAPIC
54 #define NR_IOSAPICS 256
56 #ifndef CONFIG_XEN
57 static inline unsigned int iosapic_read(char __iomem *iosapic, unsigned int reg)
58 {
59 writel(reg, iosapic + IOSAPIC_REG_SELECT);
60 return readl(iosapic + IOSAPIC_WINDOW);
61 }
63 static inline void iosapic_write(char __iomem *iosapic, unsigned int reg, u32 val)
64 {
65 writel(reg, iosapic + IOSAPIC_REG_SELECT);
66 writel(val, iosapic + IOSAPIC_WINDOW);
67 }
68 #endif
70 static inline void iosapic_eoi(char __iomem *iosapic, u32 vector)
71 {
72 writel(vector, iosapic + IOSAPIC_EOI);
73 }
75 extern void __init iosapic_system_init (int pcat_compat);
76 extern int __devinit iosapic_init (unsigned long address,
77 unsigned int gsi_base);
78 #ifdef CONFIG_HOTPLUG
79 extern int iosapic_remove (unsigned int gsi_base);
80 #else
81 #define iosapic_remove(gsi_base) (-EINVAL)
82 #endif /* CONFIG_HOTPLUG */
83 extern int gsi_to_vector (unsigned int gsi);
84 extern int gsi_to_irq (unsigned int gsi);
85 extern int iosapic_register_intr (unsigned int gsi, unsigned long polarity,
86 unsigned long trigger);
87 extern void iosapic_unregister_intr (unsigned int irq);
88 extern void __init iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
89 unsigned long polarity,
90 unsigned long trigger);
91 extern int __init iosapic_register_platform_intr (u32 int_type,
92 unsigned int gsi,
93 int pmi_vector,
94 u16 eid, u16 id,
95 unsigned long polarity,
96 unsigned long trigger);
97 extern unsigned int iosapic_version (char __iomem *addr);
99 #ifdef CONFIG_NUMA
100 extern void __devinit map_iosapic_to_node (unsigned int, int);
101 #endif
102 #else
103 #define iosapic_system_init(pcat_compat) do { } while (0)
104 #define iosapic_init(address,gsi_base) (-EINVAL)
105 #define iosapic_remove(gsi_base) (-ENODEV)
106 #define iosapic_register_intr(gsi,polarity,trigger) (gsi)
107 #define iosapic_unregister_intr(irq) do { } while (0)
108 #define iosapic_override_isa_irq(isa_irq,gsi,polarity,trigger) do { } while (0)
109 #define iosapic_register_platform_intr(type,gsi,pmi,eid,id, \
110 polarity,trigger) (gsi)
111 #endif
113 # endif /* !__ASSEMBLY__ */
114 #endif /* __ASM_IA64_IOSAPIC_H */