ia64/xen-unstable

view linux-2.6-xen-sparse/include/asm-ia64/processor.h @ 8534:da7873110bbb

Tiny bootstrap cleanup.

Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Mon Jan 09 19:46:46 2006 +0100 (2006-01-09)
parents 3b6d422fc0be
children f20c10ecef94
line source
1 #ifndef _ASM_IA64_PROCESSOR_H
2 #define _ASM_IA64_PROCESSOR_H
4 /*
5 * Copyright (C) 1998-2004 Hewlett-Packard Co
6 * David Mosberger-Tang <davidm@hpl.hp.com>
7 * Stephane Eranian <eranian@hpl.hp.com>
8 * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
9 * Copyright (C) 1999 Don Dugger <don.dugger@intel.com>
10 *
11 * 11/24/98 S.Eranian added ia64_set_iva()
12 * 12/03/99 D. Mosberger implement thread_saved_pc() via kernel unwind API
13 * 06/16/00 A. Mallick added csd/ssd/tssd for ia32 support
14 */
16 #include <linux/config.h>
18 #include <asm/intrinsics.h>
19 #include <asm/kregs.h>
20 #include <asm/ptrace.h>
21 #include <asm/ustack.h>
22 #include <asm/privop.h>
24 /* Our arch specific arch_init_sched_domain is in arch/ia64/kernel/domain.c */
25 #define ARCH_HAS_SCHED_DOMAIN
27 #define IA64_NUM_DBG_REGS 8
28 /*
29 * Limits for PMC and PMD are set to less than maximum architected values
30 * but should be sufficient for a while
31 */
32 #define IA64_NUM_PMC_REGS 32
33 #define IA64_NUM_PMD_REGS 32
35 #define DEFAULT_MAP_BASE __IA64_UL_CONST(0x2000000000000000)
36 #define DEFAULT_TASK_SIZE __IA64_UL_CONST(0xa000000000000000)
38 /*
39 * TASK_SIZE really is a mis-named. It really is the maximum user
40 * space address (plus one). On IA-64, there are five regions of 2TB
41 * each (assuming 8KB page size), for a total of 8TB of user virtual
42 * address space.
43 */
44 #define TASK_SIZE (current->thread.task_size)
46 /*
47 * This decides where the kernel will search for a free chunk of vm
48 * space during mmap's.
49 */
50 #define TASK_UNMAPPED_BASE (current->thread.map_base)
52 #define IA64_THREAD_FPH_VALID (__IA64_UL(1) << 0) /* floating-point high state valid? */
53 #define IA64_THREAD_DBG_VALID (__IA64_UL(1) << 1) /* debug registers valid? */
54 #define IA64_THREAD_PM_VALID (__IA64_UL(1) << 2) /* performance registers valid? */
55 #define IA64_THREAD_UAC_NOPRINT (__IA64_UL(1) << 3) /* don't log unaligned accesses */
56 #define IA64_THREAD_UAC_SIGBUS (__IA64_UL(1) << 4) /* generate SIGBUS on unaligned acc. */
57 /* bit 5 is currently unused */
58 #define IA64_THREAD_FPEMU_NOPRINT (__IA64_UL(1) << 6) /* don't log any fpswa faults */
59 #define IA64_THREAD_FPEMU_SIGFPE (__IA64_UL(1) << 7) /* send a SIGFPE for fpswa faults */
61 #define IA64_THREAD_UAC_SHIFT 3
62 #define IA64_THREAD_UAC_MASK (IA64_THREAD_UAC_NOPRINT | IA64_THREAD_UAC_SIGBUS)
63 #define IA64_THREAD_FPEMU_SHIFT 6
64 #define IA64_THREAD_FPEMU_MASK (IA64_THREAD_FPEMU_NOPRINT | IA64_THREAD_FPEMU_SIGFPE)
67 /*
68 * This shift should be large enough to be able to represent 1000000000/itc_freq with good
69 * accuracy while being small enough to fit 10*1000000000<<IA64_NSEC_PER_CYC_SHIFT in 64 bits
70 * (this will give enough slack to represent 10 seconds worth of time as a scaled number).
71 */
72 #define IA64_NSEC_PER_CYC_SHIFT 30
74 #ifndef __ASSEMBLY__
76 #include <linux/cache.h>
77 #include <linux/compiler.h>
78 #include <linux/threads.h>
79 #include <linux/types.h>
81 #include <asm/fpu.h>
82 #include <asm/page.h>
83 #include <asm/percpu.h>
84 #include <asm/rse.h>
85 #include <asm/unwind.h>
86 #include <asm/atomic.h>
87 #ifdef CONFIG_NUMA
88 #include <asm/nodedata.h>
89 #endif
91 /* like above but expressed as bitfields for more efficient access: */
92 struct ia64_psr {
93 __u64 reserved0 : 1;
94 __u64 be : 1;
95 __u64 up : 1;
96 __u64 ac : 1;
97 __u64 mfl : 1;
98 __u64 mfh : 1;
99 __u64 reserved1 : 7;
100 __u64 ic : 1;
101 __u64 i : 1;
102 __u64 pk : 1;
103 __u64 reserved2 : 1;
104 __u64 dt : 1;
105 __u64 dfl : 1;
106 __u64 dfh : 1;
107 __u64 sp : 1;
108 __u64 pp : 1;
109 __u64 di : 1;
110 __u64 si : 1;
111 __u64 db : 1;
112 __u64 lp : 1;
113 __u64 tb : 1;
114 __u64 rt : 1;
115 __u64 reserved3 : 4;
116 __u64 cpl : 2;
117 __u64 is : 1;
118 __u64 mc : 1;
119 __u64 it : 1;
120 __u64 id : 1;
121 __u64 da : 1;
122 __u64 dd : 1;
123 __u64 ss : 1;
124 __u64 ri : 2;
125 __u64 ed : 1;
126 __u64 bn : 1;
127 __u64 reserved4 : 19;
128 };
130 /*
131 * CPU type, hardware bug flags, and per-CPU state. Frequently used
132 * state comes earlier:
133 */
134 struct cpuinfo_ia64 {
135 __u32 softirq_pending;
136 __u64 itm_delta; /* # of clock cycles between clock ticks */
137 __u64 itm_next; /* interval timer mask value to use for next clock tick */
138 __u64 nsec_per_cyc; /* (1000000000<<IA64_NSEC_PER_CYC_SHIFT)/itc_freq */
139 __u64 unimpl_va_mask; /* mask of unimplemented virtual address bits (from PAL) */
140 __u64 unimpl_pa_mask; /* mask of unimplemented physical address bits (from PAL) */
141 __u64 itc_freq; /* frequency of ITC counter */
142 __u64 proc_freq; /* frequency of processor */
143 __u64 cyc_per_usec; /* itc_freq/1000000 */
144 __u64 ptce_base;
145 __u32 ptce_count[2];
146 __u32 ptce_stride[2];
147 struct task_struct *ksoftirqd; /* kernel softirq daemon for this CPU */
149 #ifdef CONFIG_SMP
150 __u64 loops_per_jiffy;
151 int cpu;
152 __u32 socket_id; /* physical processor socket id */
153 __u16 core_id; /* core id */
154 __u16 thread_id; /* thread id */
155 __u16 num_log; /* Total number of logical processors on
156 * this socket that were successfully booted */
157 __u8 cores_per_socket; /* Cores per processor socket */
158 __u8 threads_per_core; /* Threads per core */
159 #endif
161 /* CPUID-derived information: */
162 __u64 ppn;
163 __u64 features;
164 __u8 number;
165 __u8 revision;
166 __u8 model;
167 __u8 family;
168 __u8 archrev;
169 char vendor[16];
171 #ifdef CONFIG_NUMA
172 struct ia64_node_data *node_data;
173 #endif
174 };
176 DECLARE_PER_CPU(struct cpuinfo_ia64, cpu_info);
178 /*
179 * The "local" data variable. It refers to the per-CPU data of the currently executing
180 * CPU, much like "current" points to the per-task data of the currently executing task.
181 * Do not use the address of local_cpu_data, since it will be different from
182 * cpu_data(smp_processor_id())!
183 */
184 #define local_cpu_data (&__ia64_per_cpu_var(cpu_info))
185 #define cpu_data(cpu) (&per_cpu(cpu_info, cpu))
187 extern void identify_cpu (struct cpuinfo_ia64 *);
188 extern void print_cpu_info (struct cpuinfo_ia64 *);
190 typedef struct {
191 unsigned long seg;
192 } mm_segment_t;
194 #define SET_UNALIGN_CTL(task,value) \
195 ({ \
196 (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_UAC_MASK) \
197 | (((value) << IA64_THREAD_UAC_SHIFT) & IA64_THREAD_UAC_MASK)); \
198 0; \
199 })
200 #define GET_UNALIGN_CTL(task,addr) \
201 ({ \
202 put_user(((task)->thread.flags & IA64_THREAD_UAC_MASK) >> IA64_THREAD_UAC_SHIFT, \
203 (int __user *) (addr)); \
204 })
206 #define SET_FPEMU_CTL(task,value) \
207 ({ \
208 (task)->thread.flags = (((task)->thread.flags & ~IA64_THREAD_FPEMU_MASK) \
209 | (((value) << IA64_THREAD_FPEMU_SHIFT) & IA64_THREAD_FPEMU_MASK)); \
210 0; \
211 })
212 #define GET_FPEMU_CTL(task,addr) \
213 ({ \
214 put_user(((task)->thread.flags & IA64_THREAD_FPEMU_MASK) >> IA64_THREAD_FPEMU_SHIFT, \
215 (int __user *) (addr)); \
216 })
218 #ifdef CONFIG_IA32_SUPPORT
219 struct desc_struct {
220 unsigned int a, b;
221 };
223 #define desc_empty(desc) (!((desc)->a + (desc)->b))
224 #define desc_equal(desc1, desc2) (((desc1)->a == (desc2)->a) && ((desc1)->b == (desc2)->b))
226 #define GDT_ENTRY_TLS_ENTRIES 3
227 #define GDT_ENTRY_TLS_MIN 6
228 #define GDT_ENTRY_TLS_MAX (GDT_ENTRY_TLS_MIN + GDT_ENTRY_TLS_ENTRIES - 1)
230 #define TLS_SIZE (GDT_ENTRY_TLS_ENTRIES * 8)
232 struct partial_page_list;
233 #endif
235 struct thread_struct {
236 __u32 flags; /* various thread flags (see IA64_THREAD_*) */
237 /* writing on_ustack is performance-critical, so it's worth spending 8 bits on it... */
238 __u8 on_ustack; /* executing on user-stacks? */
239 __u8 pad[3];
240 __u64 ksp; /* kernel stack pointer */
241 __u64 map_base; /* base address for get_unmapped_area() */
242 __u64 task_size; /* limit for task size */
243 __u64 rbs_bot; /* the base address for the RBS */
244 int last_fph_cpu; /* CPU that may hold the contents of f32-f127 */
246 #ifdef CONFIG_IA32_SUPPORT
247 __u64 eflag; /* IA32 EFLAGS reg */
248 __u64 fsr; /* IA32 floating pt status reg */
249 __u64 fcr; /* IA32 floating pt control reg */
250 __u64 fir; /* IA32 fp except. instr. reg */
251 __u64 fdr; /* IA32 fp except. data reg */
252 __u64 old_k1; /* old value of ar.k1 */
253 __u64 old_iob; /* old IOBase value */
254 struct partial_page_list *ppl; /* partial page list for 4K page size issue */
255 /* cached TLS descriptors. */
256 struct desc_struct tls_array[GDT_ENTRY_TLS_ENTRIES];
258 # define INIT_THREAD_IA32 .eflag = 0, \
259 .fsr = 0, \
260 .fcr = 0x17800000037fULL, \
261 .fir = 0, \
262 .fdr = 0, \
263 .old_k1 = 0, \
264 .old_iob = 0, \
265 .ppl = NULL,
266 #else
267 # define INIT_THREAD_IA32
268 #endif /* CONFIG_IA32_SUPPORT */
269 #ifdef CONFIG_PERFMON
270 __u64 pmcs[IA64_NUM_PMC_REGS];
271 __u64 pmds[IA64_NUM_PMD_REGS];
272 void *pfm_context; /* pointer to detailed PMU context */
273 unsigned long pfm_needs_checking; /* when >0, pending perfmon work on kernel exit */
274 # define INIT_THREAD_PM .pmcs = {0UL, }, \
275 .pmds = {0UL, }, \
276 .pfm_context = NULL, \
277 .pfm_needs_checking = 0UL,
278 #else
279 # define INIT_THREAD_PM
280 #endif
281 __u64 dbr[IA64_NUM_DBG_REGS];
282 __u64 ibr[IA64_NUM_DBG_REGS];
283 struct ia64_fpreg fph[96]; /* saved/loaded on demand */
284 };
286 #define INIT_THREAD { \
287 .flags = 0, \
288 .on_ustack = 0, \
289 .ksp = 0, \
290 .map_base = DEFAULT_MAP_BASE, \
291 .rbs_bot = STACK_TOP - DEFAULT_USER_STACK_SIZE, \
292 .task_size = DEFAULT_TASK_SIZE, \
293 .last_fph_cpu = -1, \
294 INIT_THREAD_IA32 \
295 INIT_THREAD_PM \
296 .dbr = {0, }, \
297 .ibr = {0, }, \
298 .fph = {{{{0}}}, } \
299 }
301 #define start_thread(regs,new_ip,new_sp) do { \
302 set_fs(USER_DS); \
303 regs->cr_ipsr = ((regs->cr_ipsr | (IA64_PSR_BITS_TO_SET | IA64_PSR_CPL)) \
304 & ~(IA64_PSR_BITS_TO_CLEAR | IA64_PSR_RI | IA64_PSR_IS)); \
305 regs->cr_iip = new_ip; \
306 regs->ar_rsc = 0xf; /* eager mode, privilege level 3 */ \
307 regs->ar_rnat = 0; \
308 regs->ar_bspstore = current->thread.rbs_bot; \
309 regs->ar_fpsr = FPSR_DEFAULT; \
310 regs->loadrs = 0; \
311 regs->r8 = current->mm->dumpable; /* set "don't zap registers" flag */ \
312 regs->r12 = new_sp - 16; /* allocate 16 byte scratch area */ \
313 if (unlikely(!current->mm->dumpable)) { \
314 /* \
315 * Zap scratch regs to avoid leaking bits between processes with different \
316 * uid/privileges. \
317 */ \
318 regs->ar_pfs = 0; regs->b0 = 0; regs->pr = 0; \
319 regs->r1 = 0; regs->r9 = 0; regs->r11 = 0; regs->r13 = 0; regs->r15 = 0; \
320 } \
321 } while (0)
323 /* Forward declarations, a strange C thing... */
324 struct mm_struct;
325 struct task_struct;
327 /*
328 * Free all resources held by a thread. This is called after the
329 * parent of DEAD_TASK has collected the exit status of the task via
330 * wait().
331 */
332 #define release_thread(dead_task)
334 /* Prepare to copy thread state - unlazy all lazy status */
335 #define prepare_to_copy(tsk) do { } while (0)
337 /*
338 * This is the mechanism for creating a new kernel thread.
339 *
340 * NOTE 1: Only a kernel-only process (ie the swapper or direct
341 * descendants who haven't done an "execve()") should use this: it
342 * will work within a system call from a "real" process, but the
343 * process memory space will not be free'd until both the parent and
344 * the child have exited.
345 *
346 * NOTE 2: This MUST NOT be an inlined function. Otherwise, we get
347 * into trouble in init/main.c when the child thread returns to
348 * do_basic_setup() and the timing is such that free_initmem() has
349 * been called already.
350 */
351 extern pid_t kernel_thread (int (*fn)(void *), void *arg, unsigned long flags);
353 /* Get wait channel for task P. */
354 extern unsigned long get_wchan (struct task_struct *p);
356 /* Return instruction pointer of blocked task TSK. */
357 #define KSTK_EIP(tsk) \
358 ({ \
359 struct pt_regs *_regs = ia64_task_regs(tsk); \
360 _regs->cr_iip + ia64_psr(_regs)->ri; \
361 })
363 /* Return stack pointer of blocked task TSK. */
364 #define KSTK_ESP(tsk) ((tsk)->thread.ksp)
366 extern void ia64_getreg_unknown_kr (void);
367 extern void ia64_setreg_unknown_kr (void);
369 #define ia64_get_kr(regnum) \
370 ({ \
371 unsigned long r = 0; \
372 \
373 switch (regnum) { \
374 case 0: r = ia64_getreg(_IA64_REG_AR_KR0); break; \
375 case 1: r = ia64_getreg(_IA64_REG_AR_KR1); break; \
376 case 2: r = ia64_getreg(_IA64_REG_AR_KR2); break; \
377 case 3: r = ia64_getreg(_IA64_REG_AR_KR3); break; \
378 case 4: r = ia64_getreg(_IA64_REG_AR_KR4); break; \
379 case 5: r = ia64_getreg(_IA64_REG_AR_KR5); break; \
380 case 6: r = ia64_getreg(_IA64_REG_AR_KR6); break; \
381 case 7: r = ia64_getreg(_IA64_REG_AR_KR7); break; \
382 default: ia64_getreg_unknown_kr(); break; \
383 } \
384 r; \
385 })
387 #define ia64_set_kr(regnum, r) \
388 ({ \
389 switch (regnum) { \
390 case 0: ia64_setreg(_IA64_REG_AR_KR0, r); break; \
391 case 1: ia64_setreg(_IA64_REG_AR_KR1, r); break; \
392 case 2: ia64_setreg(_IA64_REG_AR_KR2, r); break; \
393 case 3: ia64_setreg(_IA64_REG_AR_KR3, r); break; \
394 case 4: ia64_setreg(_IA64_REG_AR_KR4, r); break; \
395 case 5: ia64_setreg(_IA64_REG_AR_KR5, r); break; \
396 case 6: ia64_setreg(_IA64_REG_AR_KR6, r); break; \
397 case 7: ia64_setreg(_IA64_REG_AR_KR7, r); break; \
398 default: ia64_setreg_unknown_kr(); break; \
399 } \
400 })
402 /*
403 * The following three macros can't be inline functions because we don't have struct
404 * task_struct at this point.
405 */
407 /*
408 * Return TRUE if task T owns the fph partition of the CPU we're running on.
409 * Must be called from code that has preemption disabled.
410 */
411 #define ia64_is_local_fpu_owner(t) \
412 ({ \
413 struct task_struct *__ia64_islfo_task = (t); \
414 (__ia64_islfo_task->thread.last_fph_cpu == smp_processor_id() \
415 && __ia64_islfo_task == (struct task_struct *) ia64_get_kr(IA64_KR_FPU_OWNER)); \
416 })
418 /*
419 * Mark task T as owning the fph partition of the CPU we're running on.
420 * Must be called from code that has preemption disabled.
421 */
422 #define ia64_set_local_fpu_owner(t) do { \
423 struct task_struct *__ia64_slfo_task = (t); \
424 __ia64_slfo_task->thread.last_fph_cpu = smp_processor_id(); \
425 ia64_set_kr(IA64_KR_FPU_OWNER, (unsigned long) __ia64_slfo_task); \
426 } while (0)
428 /* Mark the fph partition of task T as being invalid on all CPUs. */
429 #define ia64_drop_fpu(t) ((t)->thread.last_fph_cpu = -1)
431 extern void __ia64_init_fpu (void);
432 extern void __ia64_save_fpu (struct ia64_fpreg *fph);
433 extern void __ia64_load_fpu (struct ia64_fpreg *fph);
434 extern void ia64_save_debug_regs (unsigned long *save_area);
435 extern void ia64_load_debug_regs (unsigned long *save_area);
437 #ifdef CONFIG_IA32_SUPPORT
438 extern void ia32_save_state (struct task_struct *task);
439 extern void ia32_load_state (struct task_struct *task);
440 #endif
442 #define ia64_fph_enable() do { ia64_rsm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
443 #define ia64_fph_disable() do { ia64_ssm(IA64_PSR_DFH); ia64_srlz_d(); } while (0)
445 /* load fp 0.0 into fph */
446 static inline void
447 ia64_init_fpu (void) {
448 ia64_fph_enable();
449 __ia64_init_fpu();
450 ia64_fph_disable();
451 }
453 /* save f32-f127 at FPH */
454 static inline void
455 ia64_save_fpu (struct ia64_fpreg *fph) {
456 ia64_fph_enable();
457 __ia64_save_fpu(fph);
458 ia64_fph_disable();
459 }
461 /* load f32-f127 from FPH */
462 static inline void
463 ia64_load_fpu (struct ia64_fpreg *fph) {
464 ia64_fph_enable();
465 __ia64_load_fpu(fph);
466 ia64_fph_disable();
467 }
469 static inline __u64
470 ia64_clear_ic (void)
471 {
472 __u64 psr;
473 psr = ia64_getreg(_IA64_REG_PSR);
474 ia64_stop();
475 ia64_rsm(IA64_PSR_I | IA64_PSR_IC);
476 ia64_srlz_i();
477 return psr;
478 }
480 /*
481 * Restore the psr.
482 */
483 static inline void
484 ia64_set_psr (__u64 psr)
485 {
486 ia64_stop();
487 ia64_setreg(_IA64_REG_PSR_L, psr);
488 ia64_srlz_d();
489 }
491 /*
492 * Insert a translation into an instruction and/or data translation
493 * register.
494 */
495 static inline void
496 ia64_itr (__u64 target_mask, __u64 tr_num,
497 __u64 vmaddr, __u64 pte,
498 __u64 log_page_size)
499 {
500 ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
501 ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
502 ia64_stop();
503 if (target_mask & 0x1)
504 ia64_itri(tr_num, pte);
505 if (target_mask & 0x2)
506 ia64_itrd(tr_num, pte);
507 }
509 /*
510 * Insert a translation into the instruction and/or data translation
511 * cache.
512 */
513 static inline void
514 ia64_itc (__u64 target_mask, __u64 vmaddr, __u64 pte,
515 __u64 log_page_size)
516 {
517 ia64_setreg(_IA64_REG_CR_ITIR, (log_page_size << 2));
518 ia64_setreg(_IA64_REG_CR_IFA, vmaddr);
519 ia64_stop();
520 /* as per EAS2.6, itc must be the last instruction in an instruction group */
521 if (target_mask & 0x1)
522 ia64_itci(pte);
523 if (target_mask & 0x2)
524 ia64_itcd(pte);
525 }
527 /*
528 * Purge a range of addresses from instruction and/or data translation
529 * register(s).
530 */
531 static inline void
532 ia64_ptr (__u64 target_mask, __u64 vmaddr, __u64 log_size)
533 {
534 if (target_mask & 0x1)
535 ia64_ptri(vmaddr, (log_size << 2));
536 if (target_mask & 0x2)
537 ia64_ptrd(vmaddr, (log_size << 2));
538 }
540 /* Set the interrupt vector address. The address must be suitably aligned (32KB). */
541 static inline void
542 ia64_set_iva (void *ivt_addr)
543 {
544 ia64_setreg(_IA64_REG_CR_IVA, (__u64) ivt_addr);
545 ia64_srlz_i();
546 }
548 /* Set the page table address and control bits. */
549 static inline void
550 ia64_set_pta (__u64 pta)
551 {
552 /* Note: srlz.i implies srlz.d */
553 ia64_setreg(_IA64_REG_CR_PTA, pta);
554 ia64_srlz_i();
555 }
557 static inline void
558 ia64_eoi (void)
559 {
560 ia64_setreg(_IA64_REG_CR_EOI, 0);
561 ia64_srlz_d();
562 }
564 #define cpu_relax() ia64_hint(ia64_hint_pause)
566 static inline void
567 ia64_set_lrr0 (unsigned long val)
568 {
569 ia64_setreg(_IA64_REG_CR_LRR0, val);
570 ia64_srlz_d();
571 }
573 static inline void
574 ia64_set_lrr1 (unsigned long val)
575 {
576 ia64_setreg(_IA64_REG_CR_LRR1, val);
577 ia64_srlz_d();
578 }
581 /*
582 * Given the address to which a spill occurred, return the unat bit
583 * number that corresponds to this address.
584 */
585 static inline __u64
586 ia64_unat_pos (void *spill_addr)
587 {
588 return ((__u64) spill_addr >> 3) & 0x3f;
589 }
591 /*
592 * Set the NaT bit of an integer register which was spilled at address
593 * SPILL_ADDR. UNAT is the mask to be updated.
594 */
595 static inline void
596 ia64_set_unat (__u64 *unat, void *spill_addr, unsigned long nat)
597 {
598 __u64 bit = ia64_unat_pos(spill_addr);
599 __u64 mask = 1UL << bit;
601 *unat = (*unat & ~mask) | (nat << bit);
602 }
604 /*
605 * Return saved PC of a blocked thread.
606 * Note that the only way T can block is through a call to schedule() -> switch_to().
607 */
608 static inline unsigned long
609 thread_saved_pc (struct task_struct *t)
610 {
611 struct unw_frame_info info;
612 unsigned long ip;
614 unw_init_from_blocked_task(&info, t);
615 if (unw_unwind(&info) < 0)
616 return 0;
617 unw_get_ip(&info, &ip);
618 return ip;
619 }
621 /*
622 * Get the current instruction/program counter value.
623 */
624 #define current_text_addr() \
625 ({ void *_pc; _pc = (void *)ia64_getreg(_IA64_REG_IP); _pc; })
627 static inline __u64
628 ia64_get_ivr (void)
629 {
630 __u64 r;
631 ia64_srlz_d();
632 r = ia64_getreg(_IA64_REG_CR_IVR);
633 ia64_srlz_d();
634 return r;
635 }
637 static inline void
638 ia64_set_dbr (__u64 regnum, __u64 value)
639 {
640 __ia64_set_dbr(regnum, value);
641 #ifdef CONFIG_ITANIUM
642 ia64_srlz_d();
643 #endif
644 }
646 static inline __u64
647 ia64_get_dbr (__u64 regnum)
648 {
649 __u64 retval;
651 retval = __ia64_get_dbr(regnum);
652 #ifdef CONFIG_ITANIUM
653 ia64_srlz_d();
654 #endif
655 return retval;
656 }
658 static inline __u64
659 ia64_rotr (__u64 w, __u64 n)
660 {
661 return (w >> n) | (w << (64 - n));
662 }
664 #define ia64_rotl(w,n) ia64_rotr((w), (64) - (n))
666 /*
667 * Take a mapped kernel address and return the equivalent address
668 * in the region 7 identity mapped virtual area.
669 */
670 static inline void *
671 ia64_imva (void *addr)
672 {
673 void *result;
674 result = (void *) ia64_tpa(addr);
675 return __va(result);
676 }
678 #define ARCH_HAS_PREFETCH
679 #define ARCH_HAS_PREFETCHW
680 #define ARCH_HAS_SPINLOCK_PREFETCH
681 #define PREFETCH_STRIDE L1_CACHE_BYTES
683 static inline void
684 prefetch (const void *x)
685 {
686 ia64_lfetch(ia64_lfhint_none, x);
687 }
689 static inline void
690 prefetchw (const void *x)
691 {
692 ia64_lfetch_excl(ia64_lfhint_none, x);
693 }
695 #define spin_lock_prefetch(x) prefetchw(x)
697 extern unsigned long boot_option_idle_override;
699 #endif /* !__ASSEMBLY__ */
701 #endif /* _ASM_IA64_PROCESSOR_H */