ia64/xen-unstable

view linux-2.6-xen-sparse/include/asm-ia64/pal.h @ 8534:da7873110bbb

Tiny bootstrap cleanup.

Signed-off-by: Keir Fraser <keir@xensource.com>
author kaf24@firebug.cl.cam.ac.uk
date Mon Jan 09 19:46:46 2006 +0100 (2006-01-09)
parents 3b6d422fc0be
children f20c10ecef94
line source
1 #ifndef _ASM_IA64_PAL_H
2 #define _ASM_IA64_PAL_H
4 /*
5 * Processor Abstraction Layer definitions.
6 *
7 * This is based on Intel IA-64 Architecture Software Developer's Manual rev 1.0
8 * chapter 11 IA-64 Processor Abstraction Layer
9 *
10 * Copyright (C) 1998-2001 Hewlett-Packard Co
11 * David Mosberger-Tang <davidm@hpl.hp.com>
12 * Stephane Eranian <eranian@hpl.hp.com>
13 * Copyright (C) 1999 VA Linux Systems
14 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
15 * Copyright (C) 1999 Srinivasa Prasad Thirumalachar <sprasad@sprasad.engr.sgi.com>
16 *
17 * 99/10/01 davidm Make sure we pass zero for reserved parameters.
18 * 00/03/07 davidm Updated pal_cache_flush() to be in sync with PAL v2.6.
19 * 00/03/23 cfleck Modified processor min-state save area to match updated PAL & SAL info
20 * 00/05/24 eranian Updated to latest PAL spec, fix structures bugs, added
21 * 00/05/25 eranian Support for stack calls, and static physical calls
22 * 00/06/18 eranian Support for stacked physical calls
23 */
25 /*
26 * Note that some of these calls use a static-register only calling
27 * convention which has nothing to do with the regular calling
28 * convention.
29 */
30 #define PAL_CACHE_FLUSH 1 /* flush i/d cache */
31 #define PAL_CACHE_INFO 2 /* get detailed i/d cache info */
32 #define PAL_CACHE_INIT 3 /* initialize i/d cache */
33 #define PAL_CACHE_SUMMARY 4 /* get summary of cache heirarchy */
34 #define PAL_MEM_ATTRIB 5 /* list supported memory attributes */
35 #define PAL_PTCE_INFO 6 /* purge TLB info */
36 #define PAL_VM_INFO 7 /* return supported virtual memory features */
37 #define PAL_VM_SUMMARY 8 /* return summary on supported vm features */
38 #define PAL_BUS_GET_FEATURES 9 /* return processor bus interface features settings */
39 #define PAL_BUS_SET_FEATURES 10 /* set processor bus features */
40 #define PAL_DEBUG_INFO 11 /* get number of debug registers */
41 #define PAL_FIXED_ADDR 12 /* get fixed component of processors's directed address */
42 #define PAL_FREQ_BASE 13 /* base frequency of the platform */
43 #define PAL_FREQ_RATIOS 14 /* ratio of processor, bus and ITC frequency */
44 #define PAL_PERF_MON_INFO 15 /* return performance monitor info */
45 #define PAL_PLATFORM_ADDR 16 /* set processor interrupt block and IO port space addr */
46 #define PAL_PROC_GET_FEATURES 17 /* get configurable processor features & settings */
47 #define PAL_PROC_SET_FEATURES 18 /* enable/disable configurable processor features */
48 #define PAL_RSE_INFO 19 /* return rse information */
49 #define PAL_VERSION 20 /* return version of PAL code */
50 #define PAL_MC_CLEAR_LOG 21 /* clear all processor log info */
51 #define PAL_MC_DRAIN 22 /* drain operations which could result in an MCA */
52 #define PAL_MC_EXPECTED 23 /* set/reset expected MCA indicator */
53 #define PAL_MC_DYNAMIC_STATE 24 /* get processor dynamic state */
54 #define PAL_MC_ERROR_INFO 25 /* get processor MCA info and static state */
55 #define PAL_MC_RESUME 26 /* Return to interrupted process */
56 #define PAL_MC_REGISTER_MEM 27 /* Register memory for PAL to use during MCAs and inits */
57 #define PAL_HALT 28 /* enter the low power HALT state */
58 #define PAL_HALT_LIGHT 29 /* enter the low power light halt state*/
59 #define PAL_COPY_INFO 30 /* returns info needed to relocate PAL */
60 #define PAL_CACHE_LINE_INIT 31 /* init tags & data of cache line */
61 #define PAL_PMI_ENTRYPOINT 32 /* register PMI memory entry points with the processor */
62 #define PAL_ENTER_IA_32_ENV 33 /* enter IA-32 system environment */
63 #define PAL_VM_PAGE_SIZE 34 /* return vm TC and page walker page sizes */
65 #define PAL_MEM_FOR_TEST 37 /* get amount of memory needed for late processor test */
66 #define PAL_CACHE_PROT_INFO 38 /* get i/d cache protection info */
67 #define PAL_REGISTER_INFO 39 /* return AR and CR register information*/
68 #define PAL_SHUTDOWN 40 /* enter processor shutdown state */
69 #define PAL_PREFETCH_VISIBILITY 41 /* Make Processor Prefetches Visible */
70 #define PAL_LOGICAL_TO_PHYSICAL 42 /* returns information on logical to physical processor mapping */
72 #define PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */
73 #define PAL_HALT_INFO 257 /* return the low power capabilities of processor */
74 #define PAL_TEST_PROC 258 /* perform late processor self-test */
75 #define PAL_CACHE_READ 259 /* read tag & data of cacheline for diagnostic testing */
76 #define PAL_CACHE_WRITE 260 /* write tag & data of cacheline for diagnostic testing */
77 #define PAL_VM_TR_READ 261 /* read contents of translation register */
79 #ifndef __ASSEMBLY__
81 #include <linux/types.h>
82 #include <asm/processor.h>
83 #include <asm/fpu.h>
85 /*
86 * Data types needed to pass information into PAL procedures and
87 * interpret information returned by them.
88 */
90 /* Return status from the PAL procedure */
91 typedef s64 pal_status_t;
93 #define PAL_STATUS_SUCCESS 0 /* No error */
94 #define PAL_STATUS_UNIMPLEMENTED (-1) /* Unimplemented procedure */
95 #define PAL_STATUS_EINVAL (-2) /* Invalid argument */
96 #define PAL_STATUS_ERROR (-3) /* Error */
97 #define PAL_STATUS_CACHE_INIT_FAIL (-4) /* Could not initialize the
98 * specified level and type of
99 * cache without sideeffects
100 * and "restrict" was 1
101 */
103 /* Processor cache level in the heirarchy */
104 typedef u64 pal_cache_level_t;
105 #define PAL_CACHE_LEVEL_L0 0 /* L0 */
106 #define PAL_CACHE_LEVEL_L1 1 /* L1 */
107 #define PAL_CACHE_LEVEL_L2 2 /* L2 */
110 /* Processor cache type at a particular level in the heirarchy */
112 typedef u64 pal_cache_type_t;
113 #define PAL_CACHE_TYPE_INSTRUCTION 1 /* Instruction cache */
114 #define PAL_CACHE_TYPE_DATA 2 /* Data or unified cache */
115 #define PAL_CACHE_TYPE_INSTRUCTION_DATA 3 /* Both Data & Instruction */
118 #define PAL_CACHE_FLUSH_INVALIDATE 1 /* Invalidate clean lines */
119 #define PAL_CACHE_FLUSH_CHK_INTRS 2 /* check for interrupts/mc while flushing */
121 /* Processor cache line size in bytes */
122 typedef int pal_cache_line_size_t;
124 /* Processor cache line state */
125 typedef u64 pal_cache_line_state_t;
126 #define PAL_CACHE_LINE_STATE_INVALID 0 /* Invalid */
127 #define PAL_CACHE_LINE_STATE_SHARED 1 /* Shared */
128 #define PAL_CACHE_LINE_STATE_EXCLUSIVE 2 /* Exclusive */
129 #define PAL_CACHE_LINE_STATE_MODIFIED 3 /* Modified */
131 typedef struct pal_freq_ratio {
132 u64 den : 32, num : 32; /* numerator & denominator */
133 } itc_ratio, proc_ratio;
135 typedef union pal_cache_config_info_1_s {
136 struct {
137 u64 u : 1, /* 0 Unified cache ? */
138 at : 2, /* 2-1 Cache mem attr*/
139 reserved : 5, /* 7-3 Reserved */
140 associativity : 8, /* 16-8 Associativity*/
141 line_size : 8, /* 23-17 Line size */
142 stride : 8, /* 31-24 Stride */
143 store_latency : 8, /*39-32 Store latency*/
144 load_latency : 8, /* 47-40 Load latency*/
145 store_hints : 8, /* 55-48 Store hints*/
146 load_hints : 8; /* 63-56 Load hints */
147 } pcci1_bits;
148 u64 pcci1_data;
149 } pal_cache_config_info_1_t;
151 typedef union pal_cache_config_info_2_s {
152 struct {
153 u64 cache_size : 32, /*cache size in bytes*/
156 alias_boundary : 8, /* 39-32 aliased addr
157 * separation for max
158 * performance.
159 */
160 tag_ls_bit : 8, /* 47-40 LSb of addr*/
161 tag_ms_bit : 8, /* 55-48 MSb of addr*/
162 reserved : 8; /* 63-56 Reserved */
163 } pcci2_bits;
164 u64 pcci2_data;
165 } pal_cache_config_info_2_t;
168 typedef struct pal_cache_config_info_s {
169 pal_status_t pcci_status;
170 pal_cache_config_info_1_t pcci_info_1;
171 pal_cache_config_info_2_t pcci_info_2;
172 u64 pcci_reserved;
173 } pal_cache_config_info_t;
175 #define pcci_ld_hints pcci_info_1.pcci1_bits.load_hints
176 #define pcci_st_hints pcci_info_1.pcci1_bits.store_hints
177 #define pcci_ld_latency pcci_info_1.pcci1_bits.load_latency
178 #define pcci_st_latency pcci_info_1.pcci1_bits.store_latency
179 #define pcci_stride pcci_info_1.pcci1_bits.stride
180 #define pcci_line_size pcci_info_1.pcci1_bits.line_size
181 #define pcci_assoc pcci_info_1.pcci1_bits.associativity
182 #define pcci_cache_attr pcci_info_1.pcci1_bits.at
183 #define pcci_unified pcci_info_1.pcci1_bits.u
184 #define pcci_tag_msb pcci_info_2.pcci2_bits.tag_ms_bit
185 #define pcci_tag_lsb pcci_info_2.pcci2_bits.tag_ls_bit
186 #define pcci_alias_boundary pcci_info_2.pcci2_bits.alias_boundary
187 #define pcci_cache_size pcci_info_2.pcci2_bits.cache_size
191 /* Possible values for cache attributes */
193 #define PAL_CACHE_ATTR_WT 0 /* Write through cache */
194 #define PAL_CACHE_ATTR_WB 1 /* Write back cache */
195 #define PAL_CACHE_ATTR_WT_OR_WB 2 /* Either write thru or write
196 * back depending on TLB
197 * memory attributes
198 */
201 /* Possible values for cache hints */
203 #define PAL_CACHE_HINT_TEMP_1 0 /* Temporal level 1 */
204 #define PAL_CACHE_HINT_NTEMP_1 1 /* Non-temporal level 1 */
205 #define PAL_CACHE_HINT_NTEMP_ALL 3 /* Non-temporal all levels */
207 /* Processor cache protection information */
208 typedef union pal_cache_protection_element_u {
209 u32 pcpi_data;
210 struct {
211 u32 data_bits : 8, /* # data bits covered by
212 * each unit of protection
213 */
215 tagprot_lsb : 6, /* Least -do- */
216 tagprot_msb : 6, /* Most Sig. tag address
217 * bit that this
218 * protection covers.
219 */
220 prot_bits : 6, /* # of protection bits */
221 method : 4, /* Protection method */
222 t_d : 2; /* Indicates which part
223 * of the cache this
224 * protection encoding
225 * applies.
226 */
227 } pcp_info;
228 } pal_cache_protection_element_t;
230 #define pcpi_cache_prot_part pcp_info.t_d
231 #define pcpi_prot_method pcp_info.method
232 #define pcpi_prot_bits pcp_info.prot_bits
233 #define pcpi_tagprot_msb pcp_info.tagprot_msb
234 #define pcpi_tagprot_lsb pcp_info.tagprot_lsb
235 #define pcpi_data_bits pcp_info.data_bits
237 /* Processor cache part encodings */
238 #define PAL_CACHE_PROT_PART_DATA 0 /* Data protection */
239 #define PAL_CACHE_PROT_PART_TAG 1 /* Tag protection */
240 #define PAL_CACHE_PROT_PART_TAG_DATA 2 /* Tag+data protection (tag is
241 * more significant )
242 */
243 #define PAL_CACHE_PROT_PART_DATA_TAG 3 /* Data+tag protection (data is
244 * more significant )
245 */
246 #define PAL_CACHE_PROT_PART_MAX 6
249 typedef struct pal_cache_protection_info_s {
250 pal_status_t pcpi_status;
251 pal_cache_protection_element_t pcp_info[PAL_CACHE_PROT_PART_MAX];
252 } pal_cache_protection_info_t;
255 /* Processor cache protection method encodings */
256 #define PAL_CACHE_PROT_METHOD_NONE 0 /* No protection */
257 #define PAL_CACHE_PROT_METHOD_ODD_PARITY 1 /* Odd parity */
258 #define PAL_CACHE_PROT_METHOD_EVEN_PARITY 2 /* Even parity */
259 #define PAL_CACHE_PROT_METHOD_ECC 3 /* ECC protection */
262 /* Processor cache line identification in the heirarchy */
263 typedef union pal_cache_line_id_u {
264 u64 pclid_data;
265 struct {
266 u64 cache_type : 8, /* 7-0 cache type */
267 level : 8, /* 15-8 level of the
268 * cache in the
269 * heirarchy.
270 */
271 way : 8, /* 23-16 way in the set
272 */
273 part : 8, /* 31-24 part of the
274 * cache
275 */
276 reserved : 32; /* 63-32 is reserved*/
277 } pclid_info_read;
278 struct {
279 u64 cache_type : 8, /* 7-0 cache type */
280 level : 8, /* 15-8 level of the
281 * cache in the
282 * heirarchy.
283 */
284 way : 8, /* 23-16 way in the set
285 */
286 part : 8, /* 31-24 part of the
287 * cache
288 */
289 mesi : 8, /* 39-32 cache line
290 * state
291 */
292 start : 8, /* 47-40 lsb of data to
293 * invert
294 */
295 length : 8, /* 55-48 #bits to
296 * invert
297 */
298 trigger : 8; /* 63-56 Trigger error
299 * by doing a load
300 * after the write
301 */
303 } pclid_info_write;
304 } pal_cache_line_id_u_t;
306 #define pclid_read_part pclid_info_read.part
307 #define pclid_read_way pclid_info_read.way
308 #define pclid_read_level pclid_info_read.level
309 #define pclid_read_cache_type pclid_info_read.cache_type
311 #define pclid_write_trigger pclid_info_write.trigger
312 #define pclid_write_length pclid_info_write.length
313 #define pclid_write_start pclid_info_write.start
314 #define pclid_write_mesi pclid_info_write.mesi
315 #define pclid_write_part pclid_info_write.part
316 #define pclid_write_way pclid_info_write.way
317 #define pclid_write_level pclid_info_write.level
318 #define pclid_write_cache_type pclid_info_write.cache_type
320 /* Processor cache line part encodings */
321 #define PAL_CACHE_LINE_ID_PART_DATA 0 /* Data */
322 #define PAL_CACHE_LINE_ID_PART_TAG 1 /* Tag */
323 #define PAL_CACHE_LINE_ID_PART_DATA_PROT 2 /* Data protection */
324 #define PAL_CACHE_LINE_ID_PART_TAG_PROT 3 /* Tag protection */
325 #define PAL_CACHE_LINE_ID_PART_DATA_TAG_PROT 4 /* Data+tag
326 * protection
327 */
328 typedef struct pal_cache_line_info_s {
329 pal_status_t pcli_status; /* Return status of the read cache line
330 * info call.
331 */
332 u64 pcli_data; /* 64-bit data, tag, protection bits .. */
333 u64 pcli_data_len; /* data length in bits */
334 pal_cache_line_state_t pcli_cache_line_state; /* mesi state */
336 } pal_cache_line_info_t;
339 /* Machine Check related crap */
341 /* Pending event status bits */
342 typedef u64 pal_mc_pending_events_t;
344 #define PAL_MC_PENDING_MCA (1 << 0)
345 #define PAL_MC_PENDING_INIT (1 << 1)
347 /* Error information type */
348 typedef u64 pal_mc_info_index_t;
350 #define PAL_MC_INFO_PROCESSOR 0 /* Processor */
351 #define PAL_MC_INFO_CACHE_CHECK 1 /* Cache check */
352 #define PAL_MC_INFO_TLB_CHECK 2 /* Tlb check */
353 #define PAL_MC_INFO_BUS_CHECK 3 /* Bus check */
354 #define PAL_MC_INFO_REQ_ADDR 4 /* Requestor address */
355 #define PAL_MC_INFO_RESP_ADDR 5 /* Responder address */
356 #define PAL_MC_INFO_TARGET_ADDR 6 /* Target address */
357 #define PAL_MC_INFO_IMPL_DEP 7 /* Implementation
358 * dependent
359 */
362 typedef struct pal_process_state_info_s {
363 u64 reserved1 : 2,
364 rz : 1, /* PAL_CHECK processor
365 * rendezvous
366 * successful.
367 */
369 ra : 1, /* PAL_CHECK attempted
370 * a rendezvous.
371 */
372 me : 1, /* Distinct multiple
373 * errors occurred
374 */
376 mn : 1, /* Min. state save
377 * area has been
378 * registered with PAL
379 */
381 sy : 1, /* Storage integrity
382 * synched
383 */
386 co : 1, /* Continuable */
387 ci : 1, /* MC isolated */
388 us : 1, /* Uncontained storage
389 * damage.
390 */
393 hd : 1, /* Non-essential hw
394 * lost (no loss of
395 * functionality)
396 * causing the
397 * processor to run in
398 * degraded mode.
399 */
401 tl : 1, /* 1 => MC occurred
402 * after an instr was
403 * executed but before
404 * the trap that
405 * resulted from instr
406 * execution was
407 * generated.
408 * (Trap Lost )
409 */
410 mi : 1, /* More information available
411 * call PAL_MC_ERROR_INFO
412 */
413 pi : 1, /* Precise instruction pointer */
414 pm : 1, /* Precise min-state save area */
416 dy : 1, /* Processor dynamic
417 * state valid
418 */
421 in : 1, /* 0 = MC, 1 = INIT */
422 rs : 1, /* RSE valid */
423 cm : 1, /* MC corrected */
424 ex : 1, /* MC is expected */
425 cr : 1, /* Control regs valid*/
426 pc : 1, /* Perf cntrs valid */
427 dr : 1, /* Debug regs valid */
428 tr : 1, /* Translation regs
429 * valid
430 */
431 rr : 1, /* Region regs valid */
432 ar : 1, /* App regs valid */
433 br : 1, /* Branch regs valid */
434 pr : 1, /* Predicate registers
435 * valid
436 */
438 fp : 1, /* fp registers valid*/
439 b1 : 1, /* Preserved bank one
440 * general registers
441 * are valid
442 */
443 b0 : 1, /* Preserved bank zero
444 * general registers
445 * are valid
446 */
447 gr : 1, /* General registers
448 * are valid
449 * (excl. banked regs)
450 */
451 dsize : 16, /* size of dynamic
452 * state returned
453 * by the processor
454 */
456 reserved2 : 11,
457 cc : 1, /* Cache check */
458 tc : 1, /* TLB check */
459 bc : 1, /* Bus check */
460 rc : 1, /* Register file check */
461 uc : 1; /* Uarch check */
463 } pal_processor_state_info_t;
465 typedef struct pal_cache_check_info_s {
466 u64 op : 4, /* Type of cache
467 * operation that
468 * caused the machine
469 * check.
470 */
471 level : 2, /* Cache level */
472 reserved1 : 2,
473 dl : 1, /* Failure in data part
474 * of cache line
475 */
476 tl : 1, /* Failure in tag part
477 * of cache line
478 */
479 dc : 1, /* Failure in dcache */
480 ic : 1, /* Failure in icache */
481 mesi : 3, /* Cache line state */
482 mv : 1, /* mesi valid */
483 way : 5, /* Way in which the
484 * error occurred
485 */
486 wiv : 1, /* Way field valid */
487 reserved2 : 10,
489 index : 20, /* Cache line index */
490 reserved3 : 2,
492 is : 1, /* instruction set (1 == ia32) */
493 iv : 1, /* instruction set field valid */
494 pl : 2, /* privilege level */
495 pv : 1, /* privilege level field valid */
496 mcc : 1, /* Machine check corrected */
497 tv : 1, /* Target address
498 * structure is valid
499 */
500 rq : 1, /* Requester identifier
501 * structure is valid
502 */
503 rp : 1, /* Responder identifier
504 * structure is valid
505 */
506 pi : 1; /* Precise instruction pointer
507 * structure is valid
508 */
509 } pal_cache_check_info_t;
511 typedef struct pal_tlb_check_info_s {
513 u64 tr_slot : 8, /* Slot# of TR where
514 * error occurred
515 */
516 trv : 1, /* tr_slot field is valid */
517 reserved1 : 1,
518 level : 2, /* TLB level where failure occurred */
519 reserved2 : 4,
520 dtr : 1, /* Fail in data TR */
521 itr : 1, /* Fail in inst TR */
522 dtc : 1, /* Fail in data TC */
523 itc : 1, /* Fail in inst. TC */
524 op : 4, /* Cache operation */
525 reserved3 : 30,
527 is : 1, /* instruction set (1 == ia32) */
528 iv : 1, /* instruction set field valid */
529 pl : 2, /* privilege level */
530 pv : 1, /* privilege level field valid */
531 mcc : 1, /* Machine check corrected */
532 tv : 1, /* Target address
533 * structure is valid
534 */
535 rq : 1, /* Requester identifier
536 * structure is valid
537 */
538 rp : 1, /* Responder identifier
539 * structure is valid
540 */
541 pi : 1; /* Precise instruction pointer
542 * structure is valid
543 */
544 } pal_tlb_check_info_t;
546 typedef struct pal_bus_check_info_s {
547 u64 size : 5, /* Xaction size */
548 ib : 1, /* Internal bus error */
549 eb : 1, /* External bus error */
550 cc : 1, /* Error occurred
551 * during cache-cache
552 * transfer.
553 */
554 type : 8, /* Bus xaction type*/
555 sev : 5, /* Bus error severity*/
556 hier : 2, /* Bus hierarchy level */
557 reserved1 : 1,
558 bsi : 8, /* Bus error status
559 * info
560 */
561 reserved2 : 22,
563 is : 1, /* instruction set (1 == ia32) */
564 iv : 1, /* instruction set field valid */
565 pl : 2, /* privilege level */
566 pv : 1, /* privilege level field valid */
567 mcc : 1, /* Machine check corrected */
568 tv : 1, /* Target address
569 * structure is valid
570 */
571 rq : 1, /* Requester identifier
572 * structure is valid
573 */
574 rp : 1, /* Responder identifier
575 * structure is valid
576 */
577 pi : 1; /* Precise instruction pointer
578 * structure is valid
579 */
580 } pal_bus_check_info_t;
582 typedef struct pal_reg_file_check_info_s {
583 u64 id : 4, /* Register file identifier */
584 op : 4, /* Type of register
585 * operation that
586 * caused the machine
587 * check.
588 */
589 reg_num : 7, /* Register number */
590 rnv : 1, /* reg_num valid */
591 reserved2 : 38,
593 is : 1, /* instruction set (1 == ia32) */
594 iv : 1, /* instruction set field valid */
595 pl : 2, /* privilege level */
596 pv : 1, /* privilege level field valid */
597 mcc : 1, /* Machine check corrected */
598 reserved3 : 3,
599 pi : 1; /* Precise instruction pointer
600 * structure is valid
601 */
602 } pal_reg_file_check_info_t;
604 typedef struct pal_uarch_check_info_s {
605 u64 sid : 5, /* Structure identification */
606 level : 3, /* Level of failure */
607 array_id : 4, /* Array identification */
608 op : 4, /* Type of
609 * operation that
610 * caused the machine
611 * check.
612 */
613 way : 6, /* Way of structure */
614 wv : 1, /* way valid */
615 xv : 1, /* index valid */
616 reserved1 : 8,
617 index : 8, /* Index or set of the uarch
618 * structure that failed.
619 */
620 reserved2 : 24,
622 is : 1, /* instruction set (1 == ia32) */
623 iv : 1, /* instruction set field valid */
624 pl : 2, /* privilege level */
625 pv : 1, /* privilege level field valid */
626 mcc : 1, /* Machine check corrected */
627 tv : 1, /* Target address
628 * structure is valid
629 */
630 rq : 1, /* Requester identifier
631 * structure is valid
632 */
633 rp : 1, /* Responder identifier
634 * structure is valid
635 */
636 pi : 1; /* Precise instruction pointer
637 * structure is valid
638 */
639 } pal_uarch_check_info_t;
641 typedef union pal_mc_error_info_u {
642 u64 pmei_data;
643 pal_processor_state_info_t pme_processor;
644 pal_cache_check_info_t pme_cache;
645 pal_tlb_check_info_t pme_tlb;
646 pal_bus_check_info_t pme_bus;
647 pal_reg_file_check_info_t pme_reg_file;
648 pal_uarch_check_info_t pme_uarch;
649 } pal_mc_error_info_t;
651 #define pmci_proc_unknown_check pme_processor.uc
652 #define pmci_proc_bus_check pme_processor.bc
653 #define pmci_proc_tlb_check pme_processor.tc
654 #define pmci_proc_cache_check pme_processor.cc
655 #define pmci_proc_dynamic_state_size pme_processor.dsize
656 #define pmci_proc_gpr_valid pme_processor.gr
657 #define pmci_proc_preserved_bank0_gpr_valid pme_processor.b0
658 #define pmci_proc_preserved_bank1_gpr_valid pme_processor.b1
659 #define pmci_proc_fp_valid pme_processor.fp
660 #define pmci_proc_predicate_regs_valid pme_processor.pr
661 #define pmci_proc_branch_regs_valid pme_processor.br
662 #define pmci_proc_app_regs_valid pme_processor.ar
663 #define pmci_proc_region_regs_valid pme_processor.rr
664 #define pmci_proc_translation_regs_valid pme_processor.tr
665 #define pmci_proc_debug_regs_valid pme_processor.dr
666 #define pmci_proc_perf_counters_valid pme_processor.pc
667 #define pmci_proc_control_regs_valid pme_processor.cr
668 #define pmci_proc_machine_check_expected pme_processor.ex
669 #define pmci_proc_machine_check_corrected pme_processor.cm
670 #define pmci_proc_rse_valid pme_processor.rs
671 #define pmci_proc_machine_check_or_init pme_processor.in
672 #define pmci_proc_dynamic_state_valid pme_processor.dy
673 #define pmci_proc_operation pme_processor.op
674 #define pmci_proc_trap_lost pme_processor.tl
675 #define pmci_proc_hardware_damage pme_processor.hd
676 #define pmci_proc_uncontained_storage_damage pme_processor.us
677 #define pmci_proc_machine_check_isolated pme_processor.ci
678 #define pmci_proc_continuable pme_processor.co
679 #define pmci_proc_storage_intergrity_synced pme_processor.sy
680 #define pmci_proc_min_state_save_area_regd pme_processor.mn
681 #define pmci_proc_distinct_multiple_errors pme_processor.me
682 #define pmci_proc_pal_attempted_rendezvous pme_processor.ra
683 #define pmci_proc_pal_rendezvous_complete pme_processor.rz
686 #define pmci_cache_level pme_cache.level
687 #define pmci_cache_line_state pme_cache.mesi
688 #define pmci_cache_line_state_valid pme_cache.mv
689 #define pmci_cache_line_index pme_cache.index
690 #define pmci_cache_instr_cache_fail pme_cache.ic
691 #define pmci_cache_data_cache_fail pme_cache.dc
692 #define pmci_cache_line_tag_fail pme_cache.tl
693 #define pmci_cache_line_data_fail pme_cache.dl
694 #define pmci_cache_operation pme_cache.op
695 #define pmci_cache_way_valid pme_cache.wv
696 #define pmci_cache_target_address_valid pme_cache.tv
697 #define pmci_cache_way pme_cache.way
698 #define pmci_cache_mc pme_cache.mc
700 #define pmci_tlb_instr_translation_cache_fail pme_tlb.itc
701 #define pmci_tlb_data_translation_cache_fail pme_tlb.dtc
702 #define pmci_tlb_instr_translation_reg_fail pme_tlb.itr
703 #define pmci_tlb_data_translation_reg_fail pme_tlb.dtr
704 #define pmci_tlb_translation_reg_slot pme_tlb.tr_slot
705 #define pmci_tlb_mc pme_tlb.mc
707 #define pmci_bus_status_info pme_bus.bsi
708 #define pmci_bus_req_address_valid pme_bus.rq
709 #define pmci_bus_resp_address_valid pme_bus.rp
710 #define pmci_bus_target_address_valid pme_bus.tv
711 #define pmci_bus_error_severity pme_bus.sev
712 #define pmci_bus_transaction_type pme_bus.type
713 #define pmci_bus_cache_cache_transfer pme_bus.cc
714 #define pmci_bus_transaction_size pme_bus.size
715 #define pmci_bus_internal_error pme_bus.ib
716 #define pmci_bus_external_error pme_bus.eb
717 #define pmci_bus_mc pme_bus.mc
719 /*
720 * NOTE: this min_state_save area struct only includes the 1KB
721 * architectural state save area. The other 3 KB is scratch space
722 * for PAL.
723 */
725 typedef struct pal_min_state_area_s {
726 u64 pmsa_nat_bits; /* nat bits for saved GRs */
727 u64 pmsa_gr[15]; /* GR1 - GR15 */
728 u64 pmsa_bank0_gr[16]; /* GR16 - GR31 */
729 u64 pmsa_bank1_gr[16]; /* GR16 - GR31 */
730 u64 pmsa_pr; /* predicate registers */
731 u64 pmsa_br0; /* branch register 0 */
732 u64 pmsa_rsc; /* ar.rsc */
733 u64 pmsa_iip; /* cr.iip */
734 u64 pmsa_ipsr; /* cr.ipsr */
735 u64 pmsa_ifs; /* cr.ifs */
736 u64 pmsa_xip; /* previous iip */
737 u64 pmsa_xpsr; /* previous psr */
738 u64 pmsa_xfs; /* previous ifs */
739 u64 pmsa_br1; /* branch register 1 */
740 u64 pmsa_reserved[70]; /* pal_min_state_area should total to 1KB */
741 } pal_min_state_area_t;
744 struct ia64_pal_retval {
745 /*
746 * A zero status value indicates call completed without error.
747 * A negative status value indicates reason of call failure.
748 * A positive status value indicates success but an
749 * informational value should be printed (e.g., "reboot for
750 * change to take effect").
751 */
752 s64 status;
753 u64 v0;
754 u64 v1;
755 u64 v2;
756 };
758 /*
759 * Note: Currently unused PAL arguments are generally labeled
760 * "reserved" so the value specified in the PAL documentation
761 * (generally 0) MUST be passed. Reserved parameters are not optional
762 * parameters.
763 */
764 extern struct ia64_pal_retval ia64_pal_call_static (u64, u64, u64, u64, u64);
765 extern struct ia64_pal_retval ia64_pal_call_stacked (u64, u64, u64, u64);
766 extern struct ia64_pal_retval ia64_pal_call_phys_static (u64, u64, u64, u64);
767 extern struct ia64_pal_retval ia64_pal_call_phys_stacked (u64, u64, u64, u64);
768 extern void ia64_save_scratch_fpregs (struct ia64_fpreg *);
769 extern void ia64_load_scratch_fpregs (struct ia64_fpreg *);
771 #define PAL_CALL(iprv,a0,a1,a2,a3) do { \
772 struct ia64_fpreg fr[6]; \
773 ia64_save_scratch_fpregs(fr); \
774 iprv = ia64_pal_call_static(a0, a1, a2, a3, 0); \
775 ia64_load_scratch_fpregs(fr); \
776 } while (0)
778 #define PAL_CALL_IC_OFF(iprv,a0,a1,a2,a3) do { \
779 struct ia64_fpreg fr[6]; \
780 ia64_save_scratch_fpregs(fr); \
781 iprv = ia64_pal_call_static(a0, a1, a2, a3, 1); \
782 ia64_load_scratch_fpregs(fr); \
783 } while (0)
785 #define PAL_CALL_STK(iprv,a0,a1,a2,a3) do { \
786 struct ia64_fpreg fr[6]; \
787 ia64_save_scratch_fpregs(fr); \
788 iprv = ia64_pal_call_stacked(a0, a1, a2, a3); \
789 ia64_load_scratch_fpregs(fr); \
790 } while (0)
792 #define PAL_CALL_PHYS(iprv,a0,a1,a2,a3) do { \
793 struct ia64_fpreg fr[6]; \
794 ia64_save_scratch_fpregs(fr); \
795 iprv = ia64_pal_call_phys_static(a0, a1, a2, a3); \
796 ia64_load_scratch_fpregs(fr); \
797 } while (0)
799 #define PAL_CALL_PHYS_STK(iprv,a0,a1,a2,a3) do { \
800 struct ia64_fpreg fr[6]; \
801 ia64_save_scratch_fpregs(fr); \
802 iprv = ia64_pal_call_phys_stacked(a0, a1, a2, a3); \
803 ia64_load_scratch_fpregs(fr); \
804 } while (0)
806 typedef int (*ia64_pal_handler) (u64, ...);
807 extern ia64_pal_handler ia64_pal;
808 extern void ia64_pal_handler_init (void *);
810 extern ia64_pal_handler ia64_pal;
812 extern pal_cache_config_info_t l0d_cache_config_info;
813 extern pal_cache_config_info_t l0i_cache_config_info;
814 extern pal_cache_config_info_t l1_cache_config_info;
815 extern pal_cache_config_info_t l2_cache_config_info;
817 extern pal_cache_protection_info_t l0d_cache_protection_info;
818 extern pal_cache_protection_info_t l0i_cache_protection_info;
819 extern pal_cache_protection_info_t l1_cache_protection_info;
820 extern pal_cache_protection_info_t l2_cache_protection_info;
822 extern pal_cache_config_info_t pal_cache_config_info_get(pal_cache_level_t,
823 pal_cache_type_t);
825 extern pal_cache_protection_info_t pal_cache_protection_info_get(pal_cache_level_t,
826 pal_cache_type_t);
829 extern void pal_error(int);
832 /* Useful wrappers for the current list of pal procedures */
834 typedef union pal_bus_features_u {
835 u64 pal_bus_features_val;
836 struct {
837 u64 pbf_reserved1 : 29;
838 u64 pbf_req_bus_parking : 1;
839 u64 pbf_bus_lock_mask : 1;
840 u64 pbf_enable_half_xfer_rate : 1;
841 u64 pbf_reserved2 : 22;
842 u64 pbf_disable_xaction_queueing : 1;
843 u64 pbf_disable_resp_err_check : 1;
844 u64 pbf_disable_berr_check : 1;
845 u64 pbf_disable_bus_req_internal_err_signal : 1;
846 u64 pbf_disable_bus_req_berr_signal : 1;
847 u64 pbf_disable_bus_init_event_check : 1;
848 u64 pbf_disable_bus_init_event_signal : 1;
849 u64 pbf_disable_bus_addr_err_check : 1;
850 u64 pbf_disable_bus_addr_err_signal : 1;
851 u64 pbf_disable_bus_data_err_check : 1;
852 } pal_bus_features_s;
853 } pal_bus_features_u_t;
855 extern void pal_bus_features_print (u64);
857 /* Provide information about configurable processor bus features */
858 static inline s64
859 ia64_pal_bus_get_features (pal_bus_features_u_t *features_avail,
860 pal_bus_features_u_t *features_status,
861 pal_bus_features_u_t *features_control)
862 {
863 struct ia64_pal_retval iprv;
864 PAL_CALL_PHYS(iprv, PAL_BUS_GET_FEATURES, 0, 0, 0);
865 if (features_avail)
866 features_avail->pal_bus_features_val = iprv.v0;
867 if (features_status)
868 features_status->pal_bus_features_val = iprv.v1;
869 if (features_control)
870 features_control->pal_bus_features_val = iprv.v2;
871 return iprv.status;
872 }
874 /* Enables/disables specific processor bus features */
875 static inline s64
876 ia64_pal_bus_set_features (pal_bus_features_u_t feature_select)
877 {
878 struct ia64_pal_retval iprv;
879 PAL_CALL_PHYS(iprv, PAL_BUS_SET_FEATURES, feature_select.pal_bus_features_val, 0, 0);
880 return iprv.status;
881 }
883 /* Get detailed cache information */
884 static inline s64
885 ia64_pal_cache_config_info (u64 cache_level, u64 cache_type, pal_cache_config_info_t *conf)
886 {
887 struct ia64_pal_retval iprv;
889 PAL_CALL(iprv, PAL_CACHE_INFO, cache_level, cache_type, 0);
891 if (iprv.status == 0) {
892 conf->pcci_status = iprv.status;
893 conf->pcci_info_1.pcci1_data = iprv.v0;
894 conf->pcci_info_2.pcci2_data = iprv.v1;
895 conf->pcci_reserved = iprv.v2;
896 }
897 return iprv.status;
899 }
901 /* Get detailed cche protection information */
902 static inline s64
903 ia64_pal_cache_prot_info (u64 cache_level, u64 cache_type, pal_cache_protection_info_t *prot)
904 {
905 struct ia64_pal_retval iprv;
907 PAL_CALL(iprv, PAL_CACHE_PROT_INFO, cache_level, cache_type, 0);
909 if (iprv.status == 0) {
910 prot->pcpi_status = iprv.status;
911 prot->pcp_info[0].pcpi_data = iprv.v0 & 0xffffffff;
912 prot->pcp_info[1].pcpi_data = iprv.v0 >> 32;
913 prot->pcp_info[2].pcpi_data = iprv.v1 & 0xffffffff;
914 prot->pcp_info[3].pcpi_data = iprv.v1 >> 32;
915 prot->pcp_info[4].pcpi_data = iprv.v2 & 0xffffffff;
916 prot->pcp_info[5].pcpi_data = iprv.v2 >> 32;
917 }
918 return iprv.status;
919 }
921 /*
922 * Flush the processor instruction or data caches. *PROGRESS must be
923 * initialized to zero before calling this for the first time..
924 */
925 static inline s64
926 ia64_pal_cache_flush (u64 cache_type, u64 invalidate, u64 *progress, u64 *vector)
927 {
928 struct ia64_pal_retval iprv;
929 PAL_CALL_IC_OFF(iprv, PAL_CACHE_FLUSH, cache_type, invalidate, *progress);
930 if (vector)
931 *vector = iprv.v0;
932 *progress = iprv.v1;
933 return iprv.status;
934 }
937 /* Initialize the processor controlled caches */
938 static inline s64
939 ia64_pal_cache_init (u64 level, u64 cache_type, u64 rest)
940 {
941 struct ia64_pal_retval iprv;
942 PAL_CALL(iprv, PAL_CACHE_INIT, level, cache_type, rest);
943 return iprv.status;
944 }
946 /* Initialize the tags and data of a data or unified cache line of
947 * processor controlled cache to known values without the availability
948 * of backing memory.
949 */
950 static inline s64
951 ia64_pal_cache_line_init (u64 physical_addr, u64 data_value)
952 {
953 struct ia64_pal_retval iprv;
954 PAL_CALL(iprv, PAL_CACHE_LINE_INIT, physical_addr, data_value, 0);
955 return iprv.status;
956 }
959 /* Read the data and tag of a processor controlled cache line for diags */
960 static inline s64
961 ia64_pal_cache_read (pal_cache_line_id_u_t line_id, u64 physical_addr)
962 {
963 struct ia64_pal_retval iprv;
964 PAL_CALL(iprv, PAL_CACHE_READ, line_id.pclid_data, physical_addr, 0);
965 return iprv.status;
966 }
968 /* Return summary information about the heirarchy of caches controlled by the processor */
969 static inline s64
970 ia64_pal_cache_summary (u64 *cache_levels, u64 *unique_caches)
971 {
972 struct ia64_pal_retval iprv;
973 PAL_CALL(iprv, PAL_CACHE_SUMMARY, 0, 0, 0);
974 if (cache_levels)
975 *cache_levels = iprv.v0;
976 if (unique_caches)
977 *unique_caches = iprv.v1;
978 return iprv.status;
979 }
981 /* Write the data and tag of a processor-controlled cache line for diags */
982 static inline s64
983 ia64_pal_cache_write (pal_cache_line_id_u_t line_id, u64 physical_addr, u64 data)
984 {
985 struct ia64_pal_retval iprv;
986 PAL_CALL(iprv, PAL_CACHE_WRITE, line_id.pclid_data, physical_addr, data);
987 return iprv.status;
988 }
991 /* Return the parameters needed to copy relocatable PAL procedures from ROM to memory */
992 static inline s64
993 ia64_pal_copy_info (u64 copy_type, u64 num_procs, u64 num_iopics,
994 u64 *buffer_size, u64 *buffer_align)
995 {
996 struct ia64_pal_retval iprv;
997 PAL_CALL(iprv, PAL_COPY_INFO, copy_type, num_procs, num_iopics);
998 if (buffer_size)
999 *buffer_size = iprv.v0;
1000 if (buffer_align)
1001 *buffer_align = iprv.v1;
1002 return iprv.status;
1005 /* Copy relocatable PAL procedures from ROM to memory */
1006 static inline s64
1007 ia64_pal_copy_pal (u64 target_addr, u64 alloc_size, u64 processor, u64 *pal_proc_offset)
1009 struct ia64_pal_retval iprv;
1010 PAL_CALL(iprv, PAL_COPY_PAL, target_addr, alloc_size, processor);
1011 if (pal_proc_offset)
1012 *pal_proc_offset = iprv.v0;
1013 return iprv.status;
1016 /* Return the number of instruction and data debug register pairs */
1017 static inline s64
1018 ia64_pal_debug_info (u64 *inst_regs, u64 *data_regs)
1020 struct ia64_pal_retval iprv;
1021 PAL_CALL(iprv, PAL_DEBUG_INFO, 0, 0, 0);
1022 if (inst_regs)
1023 *inst_regs = iprv.v0;
1024 if (data_regs)
1025 *data_regs = iprv.v1;
1027 return iprv.status;
1030 #ifdef TBD
1031 /* Switch from IA64-system environment to IA-32 system environment */
1032 static inline s64
1033 ia64_pal_enter_ia32_env (ia32_env1, ia32_env2, ia32_env3)
1035 struct ia64_pal_retval iprv;
1036 PAL_CALL(iprv, PAL_ENTER_IA_32_ENV, ia32_env1, ia32_env2, ia32_env3);
1037 return iprv.status;
1039 #endif
1041 /* Get unique geographical address of this processor on its bus */
1042 static inline s64
1043 ia64_pal_fixed_addr (u64 *global_unique_addr)
1045 struct ia64_pal_retval iprv;
1046 PAL_CALL(iprv, PAL_FIXED_ADDR, 0, 0, 0);
1047 if (global_unique_addr)
1048 *global_unique_addr = iprv.v0;
1049 return iprv.status;
1052 /* Get base frequency of the platform if generated by the processor */
1053 static inline s64
1054 ia64_pal_freq_base (u64 *platform_base_freq)
1056 struct ia64_pal_retval iprv;
1057 PAL_CALL(iprv, PAL_FREQ_BASE, 0, 0, 0);
1058 if (platform_base_freq)
1059 *platform_base_freq = iprv.v0;
1060 return iprv.status;
1063 /*
1064 * Get the ratios for processor frequency, bus frequency and interval timer to
1065 * to base frequency of the platform
1066 */
1067 static inline s64
1068 ia64_pal_freq_ratios (struct pal_freq_ratio *proc_ratio, struct pal_freq_ratio *bus_ratio,
1069 struct pal_freq_ratio *itc_ratio)
1071 struct ia64_pal_retval iprv;
1072 PAL_CALL(iprv, PAL_FREQ_RATIOS, 0, 0, 0);
1073 if (proc_ratio)
1074 *(u64 *)proc_ratio = iprv.v0;
1075 if (bus_ratio)
1076 *(u64 *)bus_ratio = iprv.v1;
1077 if (itc_ratio)
1078 *(u64 *)itc_ratio = iprv.v2;
1079 return iprv.status;
1082 /* Make the processor enter HALT or one of the implementation dependent low
1083 * power states where prefetching and execution are suspended and cache and
1084 * TLB coherency is not maintained.
1085 */
1086 static inline s64
1087 ia64_pal_halt (u64 halt_state)
1089 struct ia64_pal_retval iprv;
1090 PAL_CALL(iprv, PAL_HALT, halt_state, 0, 0);
1091 return iprv.status;
1094 typedef union pal_power_mgmt_info_u {
1095 u64 ppmi_data;
1096 struct {
1097 u64 exit_latency : 16,
1098 entry_latency : 16,
1099 power_consumption : 28,
1100 im : 1,
1101 co : 1,
1102 reserved : 2;
1103 } pal_power_mgmt_info_s;
1104 } pal_power_mgmt_info_u_t;
1106 /* Return information about processor's optional power management capabilities. */
1107 static inline s64
1108 ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
1110 struct ia64_pal_retval iprv;
1111 PAL_CALL_STK(iprv, PAL_HALT_INFO, (unsigned long) power_buf, 0, 0);
1112 return iprv.status;
1115 /* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
1116 * suspended, but cache and TLB coherency is maintained.
1117 */
1118 static inline s64
1119 ia64_pal_halt_light (void)
1121 struct ia64_pal_retval iprv;
1122 PAL_CALL(iprv, PAL_HALT_LIGHT, 0, 0, 0);
1123 return iprv.status;
1126 /* Clear all the processor error logging registers and reset the indicator that allows
1127 * the error logging registers to be written. This procedure also checks the pending
1128 * machine check bit and pending INIT bit and reports their states.
1129 */
1130 static inline s64
1131 ia64_pal_mc_clear_log (u64 *pending_vector)
1133 struct ia64_pal_retval iprv;
1134 PAL_CALL(iprv, PAL_MC_CLEAR_LOG, 0, 0, 0);
1135 if (pending_vector)
1136 *pending_vector = iprv.v0;
1137 return iprv.status;
1140 /* Ensure that all outstanding transactions in a processor are completed or that any
1141 * MCA due to thes outstanding transaction is taken.
1142 */
1143 static inline s64
1144 ia64_pal_mc_drain (void)
1146 struct ia64_pal_retval iprv;
1147 PAL_CALL(iprv, PAL_MC_DRAIN, 0, 0, 0);
1148 return iprv.status;
1151 /* Return the machine check dynamic processor state */
1152 static inline s64
1153 ia64_pal_mc_dynamic_state (u64 offset, u64 *size, u64 *pds)
1155 struct ia64_pal_retval iprv;
1156 PAL_CALL(iprv, PAL_MC_DYNAMIC_STATE, offset, 0, 0);
1157 if (size)
1158 *size = iprv.v0;
1159 if (pds)
1160 *pds = iprv.v1;
1161 return iprv.status;
1164 /* Return processor machine check information */
1165 static inline s64
1166 ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_info)
1168 struct ia64_pal_retval iprv;
1169 PAL_CALL(iprv, PAL_MC_ERROR_INFO, info_index, type_index, 0);
1170 if (size)
1171 *size = iprv.v0;
1172 if (error_info)
1173 *error_info = iprv.v1;
1174 return iprv.status;
1177 /* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot
1178 * attempt to correct any expected machine checks.
1179 */
1180 static inline s64
1181 ia64_pal_mc_expected (u64 expected, u64 *previous)
1183 struct ia64_pal_retval iprv;
1184 PAL_CALL(iprv, PAL_MC_EXPECTED, expected, 0, 0);
1185 if (previous)
1186 *previous = iprv.v0;
1187 return iprv.status;
1190 /* Register a platform dependent location with PAL to which it can save
1191 * minimal processor state in the event of a machine check or initialization
1192 * event.
1193 */
1194 static inline s64
1195 ia64_pal_mc_register_mem (u64 physical_addr)
1197 struct ia64_pal_retval iprv;
1198 PAL_CALL(iprv, PAL_MC_REGISTER_MEM, physical_addr, 0, 0);
1199 return iprv.status;
1202 /* Restore minimal architectural processor state, set CMC interrupt if necessary
1203 * and resume execution
1204 */
1205 static inline s64
1206 ia64_pal_mc_resume (u64 set_cmci, u64 save_ptr)
1208 struct ia64_pal_retval iprv;
1209 PAL_CALL(iprv, PAL_MC_RESUME, set_cmci, save_ptr, 0);
1210 return iprv.status;
1213 /* Return the memory attributes implemented by the processor */
1214 static inline s64
1215 ia64_pal_mem_attrib (u64 *mem_attrib)
1217 struct ia64_pal_retval iprv;
1218 PAL_CALL(iprv, PAL_MEM_ATTRIB, 0, 0, 0);
1219 if (mem_attrib)
1220 *mem_attrib = iprv.v0 & 0xff;
1221 return iprv.status;
1224 /* Return the amount of memory needed for second phase of processor
1225 * self-test and the required alignment of memory.
1226 */
1227 static inline s64
1228 ia64_pal_mem_for_test (u64 *bytes_needed, u64 *alignment)
1230 struct ia64_pal_retval iprv;
1231 PAL_CALL(iprv, PAL_MEM_FOR_TEST, 0, 0, 0);
1232 if (bytes_needed)
1233 *bytes_needed = iprv.v0;
1234 if (alignment)
1235 *alignment = iprv.v1;
1236 return iprv.status;
1239 typedef union pal_perf_mon_info_u {
1240 u64 ppmi_data;
1241 struct {
1242 u64 generic : 8,
1243 width : 8,
1244 cycles : 8,
1245 retired : 8,
1246 reserved : 32;
1247 } pal_perf_mon_info_s;
1248 } pal_perf_mon_info_u_t;
1250 /* Return the performance monitor information about what can be counted
1251 * and how to configure the monitors to count the desired events.
1252 */
1253 static inline s64
1254 ia64_pal_perf_mon_info (u64 *pm_buffer, pal_perf_mon_info_u_t *pm_info)
1256 struct ia64_pal_retval iprv;
1257 PAL_CALL(iprv, PAL_PERF_MON_INFO, (unsigned long) pm_buffer, 0, 0);
1258 if (pm_info)
1259 pm_info->ppmi_data = iprv.v0;
1260 return iprv.status;
1263 /* Specifies the physical address of the processor interrupt block
1264 * and I/O port space.
1265 */
1266 static inline s64
1267 ia64_pal_platform_addr (u64 type, u64 physical_addr)
1269 struct ia64_pal_retval iprv;
1270 PAL_CALL(iprv, PAL_PLATFORM_ADDR, type, physical_addr, 0);
1271 return iprv.status;
1274 /* Set the SAL PMI entrypoint in memory */
1275 static inline s64
1276 ia64_pal_pmi_entrypoint (u64 sal_pmi_entry_addr)
1278 struct ia64_pal_retval iprv;
1279 PAL_CALL(iprv, PAL_PMI_ENTRYPOINT, sal_pmi_entry_addr, 0, 0);
1280 return iprv.status;
1283 struct pal_features_s;
1284 /* Provide information about configurable processor features */
1285 static inline s64
1286 ia64_pal_proc_get_features (u64 *features_avail,
1287 u64 *features_status,
1288 u64 *features_control)
1290 struct ia64_pal_retval iprv;
1291 PAL_CALL_PHYS(iprv, PAL_PROC_GET_FEATURES, 0, 0, 0);
1292 if (iprv.status == 0) {
1293 *features_avail = iprv.v0;
1294 *features_status = iprv.v1;
1295 *features_control = iprv.v2;
1297 return iprv.status;
1300 /* Enable/disable processor dependent features */
1301 static inline s64
1302 ia64_pal_proc_set_features (u64 feature_select)
1304 struct ia64_pal_retval iprv;
1305 PAL_CALL_PHYS(iprv, PAL_PROC_SET_FEATURES, feature_select, 0, 0);
1306 return iprv.status;
1309 /*
1310 * Put everything in a struct so we avoid the global offset table whenever
1311 * possible.
1312 */
1313 typedef struct ia64_ptce_info_s {
1314 u64 base;
1315 u32 count[2];
1316 u32 stride[2];
1317 } ia64_ptce_info_t;
1319 /* Return the information required for the architected loop used to purge
1320 * (initialize) the entire TC
1321 */
1322 static inline s64
1323 ia64_get_ptce (ia64_ptce_info_t *ptce)
1325 struct ia64_pal_retval iprv;
1327 if (!ptce)
1328 return -1;
1330 PAL_CALL(iprv, PAL_PTCE_INFO, 0, 0, 0);
1331 if (iprv.status == 0) {
1332 ptce->base = iprv.v0;
1333 ptce->count[0] = iprv.v1 >> 32;
1334 ptce->count[1] = iprv.v1 & 0xffffffff;
1335 ptce->stride[0] = iprv.v2 >> 32;
1336 ptce->stride[1] = iprv.v2 & 0xffffffff;
1338 return iprv.status;
1341 /* Return info about implemented application and control registers. */
1342 static inline s64
1343 ia64_pal_register_info (u64 info_request, u64 *reg_info_1, u64 *reg_info_2)
1345 struct ia64_pal_retval iprv;
1346 PAL_CALL(iprv, PAL_REGISTER_INFO, info_request, 0, 0);
1347 if (reg_info_1)
1348 *reg_info_1 = iprv.v0;
1349 if (reg_info_2)
1350 *reg_info_2 = iprv.v1;
1351 return iprv.status;
1354 typedef union pal_hints_u {
1355 u64 ph_data;
1356 struct {
1357 u64 si : 1,
1358 li : 1,
1359 reserved : 62;
1360 } pal_hints_s;
1361 } pal_hints_u_t;
1363 /* Return information about the register stack and RSE for this processor
1364 * implementation.
1365 */
1366 static inline s64
1367 ia64_pal_rse_info (u64 *num_phys_stacked, pal_hints_u_t *hints)
1369 struct ia64_pal_retval iprv;
1370 PAL_CALL(iprv, PAL_RSE_INFO, 0, 0, 0);
1371 if (num_phys_stacked)
1372 *num_phys_stacked = iprv.v0;
1373 if (hints)
1374 hints->ph_data = iprv.v1;
1375 return iprv.status;
1378 /* Cause the processor to enter SHUTDOWN state, where prefetching and execution are
1379 * suspended, but cause cache and TLB coherency to be maintained.
1380 * This is usually called in IA-32 mode.
1381 */
1382 static inline s64
1383 ia64_pal_shutdown (void)
1385 struct ia64_pal_retval iprv;
1386 PAL_CALL(iprv, PAL_SHUTDOWN, 0, 0, 0);
1387 return iprv.status;
1390 /* Perform the second phase of processor self-test. */
1391 static inline s64
1392 ia64_pal_test_proc (u64 test_addr, u64 test_size, u64 attributes, u64 *self_test_state)
1394 struct ia64_pal_retval iprv;
1395 PAL_CALL(iprv, PAL_TEST_PROC, test_addr, test_size, attributes);
1396 if (self_test_state)
1397 *self_test_state = iprv.v0;
1398 return iprv.status;
1401 typedef union pal_version_u {
1402 u64 pal_version_val;
1403 struct {
1404 u64 pv_pal_b_rev : 8;
1405 u64 pv_pal_b_model : 8;
1406 u64 pv_reserved1 : 8;
1407 u64 pv_pal_vendor : 8;
1408 u64 pv_pal_a_rev : 8;
1409 u64 pv_pal_a_model : 8;
1410 u64 pv_reserved2 : 16;
1411 } pal_version_s;
1412 } pal_version_u_t;
1415 /* Return PAL version information */
1416 static inline s64
1417 ia64_pal_version (pal_version_u_t *pal_min_version, pal_version_u_t *pal_cur_version)
1419 struct ia64_pal_retval iprv;
1420 PAL_CALL_PHYS(iprv, PAL_VERSION, 0, 0, 0);
1421 if (pal_min_version)
1422 pal_min_version->pal_version_val = iprv.v0;
1424 if (pal_cur_version)
1425 pal_cur_version->pal_version_val = iprv.v1;
1427 return iprv.status;
1430 typedef union pal_tc_info_u {
1431 u64 pti_val;
1432 struct {
1433 u64 num_sets : 8,
1434 associativity : 8,
1435 num_entries : 16,
1436 pf : 1,
1437 unified : 1,
1438 reduce_tr : 1,
1439 reserved : 29;
1440 } pal_tc_info_s;
1441 } pal_tc_info_u_t;
1443 #define tc_reduce_tr pal_tc_info_s.reduce_tr
1444 #define tc_unified pal_tc_info_s.unified
1445 #define tc_pf pal_tc_info_s.pf
1446 #define tc_num_entries pal_tc_info_s.num_entries
1447 #define tc_associativity pal_tc_info_s.associativity
1448 #define tc_num_sets pal_tc_info_s.num_sets
1451 /* Return information about the virtual memory characteristics of the processor
1452 * implementation.
1453 */
1454 static inline s64
1455 ia64_pal_vm_info (u64 tc_level, u64 tc_type, pal_tc_info_u_t *tc_info, u64 *tc_pages)
1457 struct ia64_pal_retval iprv;
1458 PAL_CALL(iprv, PAL_VM_INFO, tc_level, tc_type, 0);
1459 if (tc_info)
1460 tc_info->pti_val = iprv.v0;
1461 if (tc_pages)
1462 *tc_pages = iprv.v1;
1463 return iprv.status;
1466 /* Get page size information about the virtual memory characteristics of the processor
1467 * implementation.
1468 */
1469 static inline s64
1470 ia64_pal_vm_page_size (u64 *tr_pages, u64 *vw_pages)
1472 struct ia64_pal_retval iprv;
1473 PAL_CALL(iprv, PAL_VM_PAGE_SIZE, 0, 0, 0);
1474 if (tr_pages)
1475 *tr_pages = iprv.v0;
1476 if (vw_pages)
1477 *vw_pages = iprv.v1;
1478 return iprv.status;
1481 typedef union pal_vm_info_1_u {
1482 u64 pvi1_val;
1483 struct {
1484 u64 vw : 1,
1485 phys_add_size : 7,
1486 key_size : 8,
1487 max_pkr : 8,
1488 hash_tag_id : 8,
1489 max_dtr_entry : 8,
1490 max_itr_entry : 8,
1491 max_unique_tcs : 8,
1492 num_tc_levels : 8;
1493 } pal_vm_info_1_s;
1494 } pal_vm_info_1_u_t;
1496 typedef union pal_vm_info_2_u {
1497 u64 pvi2_val;
1498 struct {
1499 u64 impl_va_msb : 8,
1500 rid_size : 8,
1501 reserved : 48;
1502 } pal_vm_info_2_s;
1503 } pal_vm_info_2_u_t;
1505 /* Get summary information about the virtual memory characteristics of the processor
1506 * implementation.
1507 */
1508 static inline s64
1509 ia64_pal_vm_summary (pal_vm_info_1_u_t *vm_info_1, pal_vm_info_2_u_t *vm_info_2)
1511 struct ia64_pal_retval iprv;
1512 PAL_CALL(iprv, PAL_VM_SUMMARY, 0, 0, 0);
1513 if (vm_info_1)
1514 vm_info_1->pvi1_val = iprv.v0;
1515 if (vm_info_2)
1516 vm_info_2->pvi2_val = iprv.v1;
1517 return iprv.status;
1520 typedef union pal_itr_valid_u {
1521 u64 piv_val;
1522 struct {
1523 u64 access_rights_valid : 1,
1524 priv_level_valid : 1,
1525 dirty_bit_valid : 1,
1526 mem_attr_valid : 1,
1527 reserved : 60;
1528 } pal_tr_valid_s;
1529 } pal_tr_valid_u_t;
1531 /* Read a translation register */
1532 static inline s64
1533 ia64_pal_tr_read (u64 reg_num, u64 tr_type, u64 *tr_buffer, pal_tr_valid_u_t *tr_valid)
1535 struct ia64_pal_retval iprv;
1536 PAL_CALL_PHYS_STK(iprv, PAL_VM_TR_READ, reg_num, tr_type,(u64)ia64_tpa(tr_buffer));
1537 if (tr_valid)
1538 tr_valid->piv_val = iprv.v0;
1539 return iprv.status;
1542 /*
1543 * PAL_PREFETCH_VISIBILITY transaction types
1544 */
1545 #define PAL_VISIBILITY_VIRTUAL 0
1546 #define PAL_VISIBILITY_PHYSICAL 1
1548 /*
1549 * PAL_PREFETCH_VISIBILITY return codes
1550 */
1551 #define PAL_VISIBILITY_OK 1
1552 #define PAL_VISIBILITY_OK_REMOTE_NEEDED 0
1553 #define PAL_VISIBILITY_INVAL_ARG -2
1554 #define PAL_VISIBILITY_ERROR -3
1556 static inline s64
1557 ia64_pal_prefetch_visibility (s64 trans_type)
1559 struct ia64_pal_retval iprv;
1560 PAL_CALL(iprv, PAL_PREFETCH_VISIBILITY, trans_type, 0, 0);
1561 return iprv.status;
1564 /* data structure for getting information on logical to physical mappings */
1565 typedef union pal_log_overview_u {
1566 struct {
1567 u64 num_log :16, /* Total number of logical
1568 * processors on this die
1569 */
1570 tpc :8, /* Threads per core */
1571 reserved3 :8, /* Reserved */
1572 cpp :8, /* Cores per processor */
1573 reserved2 :8, /* Reserved */
1574 ppid :8, /* Physical processor ID */
1575 reserved1 :8; /* Reserved */
1576 } overview_bits;
1577 u64 overview_data;
1578 } pal_log_overview_t;
1580 typedef union pal_proc_n_log_info1_u{
1581 struct {
1582 u64 tid :16, /* Thread id */
1583 reserved2 :16, /* Reserved */
1584 cid :16, /* Core id */
1585 reserved1 :16; /* Reserved */
1586 } ppli1_bits;
1587 u64 ppli1_data;
1588 } pal_proc_n_log_info1_t;
1590 typedef union pal_proc_n_log_info2_u {
1591 struct {
1592 u64 la :16, /* Logical address */
1593 reserved :48; /* Reserved */
1594 } ppli2_bits;
1595 u64 ppli2_data;
1596 } pal_proc_n_log_info2_t;
1598 typedef struct pal_logical_to_physical_s
1600 pal_log_overview_t overview;
1601 pal_proc_n_log_info1_t ppli1;
1602 pal_proc_n_log_info2_t ppli2;
1603 } pal_logical_to_physical_t;
1605 #define overview_num_log overview.overview_bits.num_log
1606 #define overview_tpc overview.overview_bits.tpc
1607 #define overview_cpp overview.overview_bits.cpp
1608 #define overview_ppid overview.overview_bits.ppid
1609 #define log1_tid ppli1.ppli1_bits.tid
1610 #define log1_cid ppli1.ppli1_bits.cid
1611 #define log2_la ppli2.ppli2_bits.la
1613 /* Get information on logical to physical processor mappings. */
1614 static inline s64
1615 ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
1617 struct ia64_pal_retval iprv;
1619 PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);
1621 if (iprv.status == PAL_STATUS_SUCCESS)
1623 if (proc_number == 0)
1624 mapping->overview.overview_data = iprv.v0;
1625 mapping->ppli1.ppli1_data = iprv.v1;
1626 mapping->ppli2.ppli2_data = iprv.v2;
1629 return iprv.status;
1631 #endif /* __ASSEMBLY__ */
1633 #endif /* _ASM_IA64_PAL_H */