ia64/xen-unstable

view xen/include/asm-x86/msr.h @ 3959:da3bec7765d1

bitkeeper revision 1.1236.1.42 (4224bb8fOnbAClkv82bfZwfayrn5Rw)

Fix error-code generation in rdmsr_user and wrmsr_user.
Signed-off-by: Keir Fraser <keir.fraser@cl.cam.ac.uk>
author kaf24@scramble.cl.cam.ac.uk
date Tue Mar 01 18:59:27 2005 +0000 (2005-03-01)
parents f25349622916
children 24703bde489b
line source
1 #ifndef __ASM_MSR_H
2 #define __ASM_MSR_H
4 #define rdmsr(msr,val1,val2) \
5 __asm__ __volatile__("rdmsr" \
6 : "=a" (val1), "=d" (val2) \
7 : "c" (msr))
9 #define wrmsr(msr,val1,val2) \
10 __asm__ __volatile__("wrmsr" \
11 : /* no outputs */ \
12 : "c" (msr), "a" (val1), "d" (val2))
14 #define rdmsr_user(msr,val1,val2) ({\
15 int _rc; \
16 __asm__ __volatile__( \
17 "1: rdmsr\n2:\n" \
18 ".section .fixup,\"ax\"\n" \
19 "3: movl $1,%2\n; jmp 2b\n" \
20 ".previous\n" \
21 ".section __ex_table,\"a\"\n" \
22 " "__FIXUP_ALIGN"\n" \
23 " "__FIXUP_WORD" 1b,3b\n" \
24 ".previous\n" \
25 : "=a" (val1), "=d" (val2), "=&r" (_rc) \
26 : "c" (msr), "2" (0)); \
27 _rc; })
29 #define wrmsr_user(msr,val1,val2) ({\
30 int _rc; \
31 __asm__ __volatile__( \
32 "1: wrmsr\n2:\n" \
33 ".section .fixup,\"ax\"\n" \
34 "3: movl $1,%0\n; jmp 2b\n" \
35 ".previous\n" \
36 ".section __ex_table,\"a\"\n" \
37 " "__FIXUP_ALIGN"\n" \
38 " "__FIXUP_WORD" 1b,3b\n" \
39 ".previous\n" \
40 : "=&r" (_rc) \
41 : "c" (msr), "a" (val1), "d" (val2), "0" (0)); \
42 _rc; })
44 #define rdtsc(low,high) \
45 __asm__ __volatile__("rdtsc" : "=a" (low), "=d" (high))
47 #define rdtscl(low) \
48 __asm__ __volatile__("rdtsc" : "=a" (low) : : "edx")
50 #if defined(__i386__)
51 #define rdtscll(val) \
52 __asm__ __volatile__("rdtsc" : "=A" (val))
53 #elif defined(__x86_64__)
54 #define rdtscll(val) do { \
55 unsigned int a,d; \
56 asm volatile("rdtsc" : "=a" (a), "=d" (d)); \
57 (val) = ((unsigned long)a) | (((unsigned long)d)<<32); \
58 } while(0)
59 #endif
61 #define write_tsc(val1,val2) wrmsr(0x10, val1, val2)
63 #define rdpmc(counter,low,high) \
64 __asm__ __volatile__("rdpmc" \
65 : "=a" (low), "=d" (high) \
66 : "c" (counter))
68 /* symbolic names for some interesting MSRs */
69 /* Intel defined MSRs. */
70 #define MSR_IA32_P5_MC_ADDR 0
71 #define MSR_IA32_P5_MC_TYPE 1
72 #define MSR_IA32_PLATFORM_ID 0x17
73 #define MSR_IA32_EBL_CR_POWERON 0x2a
75 /* AMD/K8 specific MSRs */
76 #define MSR_EFER 0xc0000080 /* extended feature register */
77 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target */
78 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target */
79 #define MSR_CSTAR 0xc0000083 /* compatibility mode SYSCALL target */
80 #define MSR_SYSCALL_MASK 0xc0000084 /* EFLAGS mask for syscall */
81 #define MSR_FS_BASE 0xc0000100 /* 64bit GS base */
82 #define MSR_GS_BASE 0xc0000101 /* 64bit FS base */
83 #define MSR_SHADOW_GS_BASE 0xc0000102 /* SwapGS GS shadow */
84 /* EFER bits: */
85 #define _EFER_SCE 0 /* SYSCALL/SYSRET */
86 #define _EFER_LME 8 /* Long mode enable */
87 #define _EFER_LMA 10 /* Long mode active (read-only) */
88 #define _EFER_NX 11 /* No execute enable */
90 #define EFER_SCE (1<<_EFER_SCE)
91 #define EFER_LME (1<<_EFER_LME)
92 #define EFER_LMA (1<<_EFER_LMA)
93 #define EFER_NX (1<<_EFER_NX)
95 /* Intel MSRs. Some also available on other CPUs */
96 #define MSR_IA32_PLATFORM_ID 0x17
98 #define MSR_IA32_PERFCTR0 0xc1
99 #define MSR_IA32_PERFCTR1 0xc2
101 #define MSR_MTRRcap 0x0fe
102 #define MSR_IA32_BBL_CR_CTL 0x119
104 #define MSR_IA32_SYSENTER_CS 0x174
105 #define MSR_IA32_SYSENTER_ESP 0x175
106 #define MSR_IA32_SYSENTER_EIP 0x176
108 #define MSR_IA32_MCG_CAP 0x179
109 #define MSR_IA32_MCG_STATUS 0x17a
110 #define MSR_IA32_MCG_CTL 0x17b
112 #define MSR_IA32_EVNTSEL0 0x186
113 #define MSR_IA32_EVNTSEL1 0x187
115 #define MSR_MTRRfix64K_00000 0x250
116 #define MSR_MTRRfix16K_80000 0x258
117 #define MSR_MTRRfix16K_A0000 0x259
118 #define MSR_MTRRfix4K_C0000 0x268
119 #define MSR_MTRRfix4K_C8000 0x269
120 #define MSR_MTRRfix4K_D0000 0x26a
121 #define MSR_MTRRfix4K_D8000 0x26b
122 #define MSR_MTRRfix4K_E0000 0x26c
123 #define MSR_MTRRfix4K_E8000 0x26d
124 #define MSR_MTRRfix4K_F0000 0x26e
125 #define MSR_MTRRfix4K_F8000 0x26f
126 #define MSR_MTRRdefType 0x2ff
128 #define MSR_IA32_MC0_CTL 0x400
129 #define MSR_IA32_MC0_STATUS 0x401
130 #define MSR_IA32_MC0_ADDR 0x402
131 #define MSR_IA32_MC0_MISC 0x403
133 #define MSR_IA32_DS_AREA 0x600
135 #define MSR_IA32_APICBASE 0x1b
136 #define MSR_IA32_APICBASE_BSP (1<<8)
137 #define MSR_IA32_APICBASE_ENABLE (1<<11)
138 #define MSR_IA32_APICBASE_BASE (0xfffff<<12)
140 #define MSR_IA32_UCODE_WRITE 0x79
141 #define MSR_IA32_UCODE_REV 0x8b
143 #define MSR_IA32_BBL_CR_CTL 0x119
145 #define MSR_IA32_MCG_CAP 0x179
146 #define MSR_IA32_MCG_STATUS 0x17a
147 #define MSR_IA32_MCG_CTL 0x17b
149 #define MSR_IA32_THERM_CONTROL 0x19a
150 #define MSR_IA32_THERM_INTERRUPT 0x19b
151 #define MSR_IA32_THERM_STATUS 0x19c
152 #define MSR_IA32_MISC_ENABLE 0x1a0
154 #define MSR_IA32_MISC_ENABLE_PERF_AVAIL (1<<7)
155 #define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL (1<<11)
156 #define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL (1<<12)
158 #define MSR_IA32_DEBUGCTLMSR 0x1d9
159 #define MSR_IA32_DEBUGCTLMSR_LBR (1<<0)
160 #define MSR_IA32_DEBUGCTLMSR_BTF (1<<1)
161 #define MSR_IA32_DEBUGCTLMSR_TR (1<<2)
162 #define MSR_IA32_DEBUGCTLMSR_BTS (1<<3)
163 #define MSR_IA32_DEBUGCTLMSR_BTINT (1<<4)
165 #define MSR_IA32_LASTBRANCH_TOS 0x1da
166 #define MSR_IA32_LASTBRANCH_0 0x1db
167 #define MSR_IA32_LASTBRANCH_1 0x1dc
168 #define MSR_IA32_LASTBRANCH_2 0x1dd
169 #define MSR_IA32_LASTBRANCH_3 0x1de
171 #define MSR_IA32_MC0_CTL 0x400
172 #define MSR_IA32_MC0_STATUS 0x401
173 #define MSR_IA32_MC0_ADDR 0x402
174 #define MSR_IA32_MC0_MISC 0x403
176 #define MSR_P6_PERFCTR0 0xc1
177 #define MSR_P6_PERFCTR1 0xc2
178 #define MSR_P6_EVNTSEL0 0x186
179 #define MSR_P6_EVNTSEL1 0x187
182 /* K7/K8 MSRs. Not complete. See the architecture manual for a more complete list. */
183 #define MSR_K7_EVNTSEL0 0xC0010000
184 #define MSR_K7_PERFCTR0 0xC0010004
185 #define MSR_K7_EVNTSEL1 0xC0010001
186 #define MSR_K7_PERFCTR1 0xC0010005
187 #define MSR_K7_EVNTSEL2 0xC0010002
188 #define MSR_K7_PERFCTR2 0xC0010006
189 #define MSR_K7_EVNTSEL3 0xC0010003
190 #define MSR_K7_PERFCTR3 0xC0010007
191 #define MSR_K8_TOP_MEM1 0xC001001A
192 #define MSR_K8_TOP_MEM2 0xC001001D
193 #define MSR_K8_SYSCFG 0xC0000010
194 #define MSR_K7_HWCR 0xC0010015
195 #define MSR_K7_CLK_CTL 0xC001001b
196 #define MSR_K7_FID_VID_CTL 0xC0010041
197 #define MSR_K7_VID_STATUS 0xC0010042
199 /* K6 MSRs */
200 #define MSR_K6_EFER 0xC0000080
201 #define MSR_K6_STAR 0xC0000081
202 #define MSR_K6_WHCR 0xC0000082
203 #define MSR_K6_UWCCR 0xC0000085
204 #define MSR_K6_EPMR 0xC0000086
205 #define MSR_K6_PSOR 0xC0000087
206 #define MSR_K6_PFIR 0xC0000088
208 /* Centaur-Hauls/IDT defined MSRs. */
209 #define MSR_IDT_FCR1 0x107
210 #define MSR_IDT_FCR2 0x108
211 #define MSR_IDT_FCR3 0x109
212 #define MSR_IDT_FCR4 0x10a
214 #define MSR_IDT_MCR0 0x110
215 #define MSR_IDT_MCR1 0x111
216 #define MSR_IDT_MCR2 0x112
217 #define MSR_IDT_MCR3 0x113
218 #define MSR_IDT_MCR4 0x114
219 #define MSR_IDT_MCR5 0x115
220 #define MSR_IDT_MCR6 0x116
221 #define MSR_IDT_MCR7 0x117
222 #define MSR_IDT_MCR_CTRL 0x120
224 /* VIA Cyrix defined MSRs*/
225 #define MSR_VIA_FCR 0x1107
226 #define MSR_VIA_LONGHAUL 0x110a
227 #define MSR_VIA_BCR2 0x1147
229 /* Transmeta defined MSRs */
230 #define MSR_TMTA_LONGRUN_CTRL 0x80868010
231 #define MSR_TMTA_LONGRUN_FLAGS 0x80868011
232 #define MSR_TMTA_LRTI_READOUT 0x80868018
233 #define MSR_TMTA_LRTI_VOLT_MHZ 0x8086801a
235 #endif /* __ASM_MSR_H */