ia64/xen-unstable

view xen/arch/x86/x86_emulate/x86_emulate.c @ 17497:d9a74b8e9b1a

x86_emulate: BT instruction does not write to its 'destination' operand.

This fixes w2k3 guests occasionally writing back to read-only registers.

Signed-off-by: Xu Dongxiao <dongxiao.xu@intel.com>
author Keir Fraser <keir.fraser@citrix.com>
date Tue Apr 22 10:27:04 2008 +0100 (2008-04-22)
parents d178c5ee6822
children 1cc4df5c7fe8
line source
1 /******************************************************************************
2 * x86_emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005-2007 Keir Fraser
7 * Copyright (c) 2005-2007 XenSource Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
24 /* Operand sizes: 8-bit operands or specified/overridden size. */
25 #define ByteOp (1<<0) /* 8-bit operands. */
26 /* Destination operand type. */
27 #define DstBitBase (0<<1) /* Memory operand, bit string. */
28 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
29 #define DstReg (2<<1) /* Register operand. */
30 #define DstMem (3<<1) /* Memory operand. */
31 #define DstMask (3<<1)
32 /* Source operand type. */
33 #define SrcNone (0<<3) /* No source operand. */
34 #define SrcImplicit (0<<3) /* Source operand is implicit in the opcode. */
35 #define SrcReg (1<<3) /* Register operand. */
36 #define SrcMem (2<<3) /* Memory operand. */
37 #define SrcMem16 (3<<3) /* Memory operand (16-bit). */
38 #define SrcImm (4<<3) /* Immediate operand. */
39 #define SrcImmByte (5<<3) /* 8-bit sign-extended immediate operand. */
40 #define SrcMask (7<<3)
41 /* Generic ModRM decode. */
42 #define ModRM (1<<6)
43 /* Destination is only written; never read. */
44 #define Mov (1<<7)
46 static uint8_t opcode_table[256] = {
47 /* 0x00 - 0x07 */
48 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
49 ByteOp|DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
50 ByteOp|DstReg|SrcImm, DstReg|SrcImm, ImplicitOps, ImplicitOps,
51 /* 0x08 - 0x0F */
52 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
53 ByteOp|DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
54 ByteOp|DstReg|SrcImm, DstReg|SrcImm, ImplicitOps, 0,
55 /* 0x10 - 0x17 */
56 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
57 ByteOp|DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
58 ByteOp|DstReg|SrcImm, DstReg|SrcImm, ImplicitOps, ImplicitOps,
59 /* 0x18 - 0x1F */
60 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
61 ByteOp|DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
62 ByteOp|DstReg|SrcImm, DstReg|SrcImm, ImplicitOps, ImplicitOps,
63 /* 0x20 - 0x27 */
64 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
65 ByteOp|DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
66 ByteOp|DstReg|SrcImm, DstReg|SrcImm, 0, ImplicitOps,
67 /* 0x28 - 0x2F */
68 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
69 ByteOp|DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
70 ByteOp|DstReg|SrcImm, DstReg|SrcImm, 0, ImplicitOps,
71 /* 0x30 - 0x37 */
72 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
73 ByteOp|DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
74 ByteOp|DstReg|SrcImm, DstReg|SrcImm, 0, ImplicitOps,
75 /* 0x38 - 0x3F */
76 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
77 ByteOp|DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
78 ByteOp|DstReg|SrcImm, DstReg|SrcImm, 0, ImplicitOps,
79 /* 0x40 - 0x4F */
80 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
81 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
82 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
83 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
84 /* 0x50 - 0x5F */
85 ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov,
86 ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov,
87 ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov,
88 ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov,
89 /* 0x60 - 0x67 */
90 ImplicitOps, ImplicitOps, DstReg|SrcMem|ModRM, DstReg|SrcMem16|ModRM|Mov,
91 0, 0, 0, 0,
92 /* 0x68 - 0x6F */
93 ImplicitOps|Mov, DstReg|SrcImm|ModRM|Mov,
94 ImplicitOps|Mov, DstReg|SrcImmByte|ModRM|Mov,
95 ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov, ImplicitOps|Mov,
96 /* 0x70 - 0x77 */
97 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
98 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
99 /* 0x78 - 0x7F */
100 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
101 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
102 /* 0x80 - 0x87 */
103 ByteOp|DstMem|SrcImm|ModRM, DstMem|SrcImm|ModRM,
104 ByteOp|DstMem|SrcImm|ModRM, DstMem|SrcImmByte|ModRM,
105 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
106 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
107 /* 0x88 - 0x8F */
108 ByteOp|DstMem|SrcReg|ModRM|Mov, DstMem|SrcReg|ModRM|Mov,
109 ByteOp|DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
110 DstMem|SrcReg|ModRM|Mov, DstReg|SrcNone|ModRM,
111 DstReg|SrcMem|ModRM|Mov, DstMem|SrcNone|ModRM|Mov,
112 /* 0x90 - 0x97 */
113 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
114 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
115 /* 0x98 - 0x9F */
116 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
117 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
118 /* 0xA0 - 0xA7 */
119 ByteOp|ImplicitOps|Mov, ImplicitOps|Mov,
120 ByteOp|ImplicitOps|Mov, ImplicitOps|Mov,
121 ByteOp|ImplicitOps|Mov, ImplicitOps|Mov,
122 ByteOp|ImplicitOps, ImplicitOps,
123 /* 0xA8 - 0xAF */
124 ByteOp|DstReg|SrcImm, DstReg|SrcImm,
125 ByteOp|ImplicitOps|Mov, ImplicitOps|Mov,
126 ByteOp|ImplicitOps|Mov, ImplicitOps|Mov,
127 ByteOp|ImplicitOps, ImplicitOps,
128 /* 0xB0 - 0xB7 */
129 ByteOp|DstReg|SrcImm|Mov, ByteOp|DstReg|SrcImm|Mov,
130 ByteOp|DstReg|SrcImm|Mov, ByteOp|DstReg|SrcImm|Mov,
131 ByteOp|DstReg|SrcImm|Mov, ByteOp|DstReg|SrcImm|Mov,
132 ByteOp|DstReg|SrcImm|Mov, ByteOp|DstReg|SrcImm|Mov,
133 /* 0xB8 - 0xBF */
134 DstReg|SrcImm|Mov, DstReg|SrcImm|Mov, DstReg|SrcImm|Mov, DstReg|SrcImm|Mov,
135 DstReg|SrcImm|Mov, DstReg|SrcImm|Mov, DstReg|SrcImm|Mov, DstReg|SrcImm|Mov,
136 /* 0xC0 - 0xC7 */
137 ByteOp|DstMem|SrcImm|ModRM, DstMem|SrcImmByte|ModRM,
138 ImplicitOps, ImplicitOps,
139 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
140 ByteOp|DstMem|SrcImm|ModRM|Mov, DstMem|SrcImm|ModRM|Mov,
141 /* 0xC8 - 0xCF */
142 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
143 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
144 /* 0xD0 - 0xD7 */
145 ByteOp|DstMem|SrcImplicit|ModRM, DstMem|SrcImplicit|ModRM,
146 ByteOp|DstMem|SrcImplicit|ModRM, DstMem|SrcImplicit|ModRM,
147 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
148 /* 0xD8 - 0xDF */
149 0, ImplicitOps|ModRM|Mov, 0, ImplicitOps|ModRM|Mov,
150 0, ImplicitOps|ModRM|Mov, ImplicitOps|ModRM|Mov, ImplicitOps|ModRM|Mov,
151 /* 0xE0 - 0xE7 */
152 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
153 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
154 /* 0xE8 - 0xEF */
155 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
156 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
157 /* 0xF0 - 0xF7 */
158 0, ImplicitOps, 0, 0,
159 ImplicitOps, ImplicitOps,
160 ByteOp|DstMem|SrcNone|ModRM, DstMem|SrcNone|ModRM,
161 /* 0xF8 - 0xFF */
162 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
163 ImplicitOps, ImplicitOps, ByteOp|DstMem|SrcNone|ModRM, DstMem|SrcNone|ModRM
164 };
166 static uint8_t twobyte_table[256] = {
167 /* 0x00 - 0x07 */
168 0, ImplicitOps|ModRM, 0, 0, 0, 0, ImplicitOps, 0,
169 /* 0x08 - 0x0F */
170 ImplicitOps, ImplicitOps, 0, 0, 0, ImplicitOps|ModRM, 0, 0,
171 /* 0x10 - 0x17 */
172 0, 0, 0, 0, 0, 0, 0, 0,
173 /* 0x18 - 0x1F */
174 ImplicitOps|ModRM, ImplicitOps|ModRM, ImplicitOps|ModRM, ImplicitOps|ModRM,
175 ImplicitOps|ModRM, ImplicitOps|ModRM, ImplicitOps|ModRM, ImplicitOps|ModRM,
176 /* 0x20 - 0x27 */
177 ImplicitOps|ModRM, ImplicitOps|ModRM, ImplicitOps|ModRM, ImplicitOps|ModRM,
178 0, 0, 0, 0,
179 /* 0x28 - 0x2F */
180 0, 0, 0, 0, 0, 0, 0, 0,
181 /* 0x30 - 0x37 */
182 ImplicitOps, ImplicitOps, ImplicitOps, 0, 0, 0, 0, 0,
183 /* 0x38 - 0x3F */
184 0, 0, 0, 0, 0, 0, 0, 0,
185 /* 0x40 - 0x47 */
186 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
187 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
188 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
189 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
190 /* 0x48 - 0x4F */
191 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
192 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
193 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
194 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
195 /* 0x50 - 0x5F */
196 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
197 /* 0x60 - 0x6F */
198 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps|ModRM,
199 /* 0x70 - 0x7F */
200 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, ImplicitOps|ModRM,
201 /* 0x80 - 0x87 */
202 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
203 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
204 /* 0x88 - 0x8F */
205 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
206 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
207 /* 0x90 - 0x97 */
208 ByteOp|DstMem|SrcNone|ModRM|Mov, ByteOp|DstMem|SrcNone|ModRM|Mov,
209 ByteOp|DstMem|SrcNone|ModRM|Mov, ByteOp|DstMem|SrcNone|ModRM|Mov,
210 ByteOp|DstMem|SrcNone|ModRM|Mov, ByteOp|DstMem|SrcNone|ModRM|Mov,
211 ByteOp|DstMem|SrcNone|ModRM|Mov, ByteOp|DstMem|SrcNone|ModRM|Mov,
212 /* 0x98 - 0x9F */
213 ByteOp|DstMem|SrcNone|ModRM|Mov, ByteOp|DstMem|SrcNone|ModRM|Mov,
214 ByteOp|DstMem|SrcNone|ModRM|Mov, ByteOp|DstMem|SrcNone|ModRM|Mov,
215 ByteOp|DstMem|SrcNone|ModRM|Mov, ByteOp|DstMem|SrcNone|ModRM|Mov,
216 ByteOp|DstMem|SrcNone|ModRM|Mov, ByteOp|DstMem|SrcNone|ModRM|Mov,
217 /* 0xA0 - 0xA7 */
218 ImplicitOps, ImplicitOps, ImplicitOps, DstBitBase|SrcReg|ModRM,
219 DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM, 0, 0,
220 /* 0xA8 - 0xAF */
221 ImplicitOps, ImplicitOps, 0, DstBitBase|SrcReg|ModRM,
222 DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM, 0, DstReg|SrcMem|ModRM,
223 /* 0xB0 - 0xB7 */
224 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM,
225 DstReg|SrcMem|ModRM|Mov, DstBitBase|SrcReg|ModRM,
226 DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov,
227 ByteOp|DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem16|ModRM|Mov,
228 /* 0xB8 - 0xBF */
229 0, 0, DstBitBase|SrcImmByte|ModRM, DstBitBase|SrcReg|ModRM,
230 DstReg|SrcMem|ModRM, DstReg|SrcMem|ModRM,
231 ByteOp|DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem16|ModRM|Mov,
232 /* 0xC0 - 0xC7 */
233 ByteOp|DstMem|SrcReg|ModRM, DstMem|SrcReg|ModRM, 0, 0,
234 0, 0, 0, ImplicitOps|ModRM,
235 /* 0xC8 - 0xCF */
236 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
237 ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps,
238 /* 0xD0 - 0xDF */
239 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
240 /* 0xE0 - 0xEF */
241 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
242 /* 0xF0 - 0xFF */
243 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
244 };
246 /* Type, address-of, and value of an instruction's operand. */
247 struct operand {
248 enum { OP_REG, OP_MEM, OP_IMM, OP_NONE } type;
249 unsigned int bytes;
250 unsigned long val, orig_val;
251 union {
252 /* OP_REG: Pointer to register field. */
253 unsigned long *reg;
254 /* OP_MEM: Segment and offset. */
255 struct {
256 enum x86_segment seg;
257 unsigned long off;
258 } mem;
259 };
260 };
262 /* MSRs. */
263 #define MSR_TSC 0x10
265 /* Control register flags. */
266 #define CR0_PE (1<<0)
267 #define CR4_TSD (1<<2)
269 /* EFLAGS bit definitions. */
270 #define EFLG_VIP (1<<20)
271 #define EFLG_VIF (1<<19)
272 #define EFLG_AC (1<<18)
273 #define EFLG_VM (1<<17)
274 #define EFLG_RF (1<<16)
275 #define EFLG_NT (1<<14)
276 #define EFLG_IOPL (3<<12)
277 #define EFLG_OF (1<<11)
278 #define EFLG_DF (1<<10)
279 #define EFLG_IF (1<<9)
280 #define EFLG_TF (1<<8)
281 #define EFLG_SF (1<<7)
282 #define EFLG_ZF (1<<6)
283 #define EFLG_AF (1<<4)
284 #define EFLG_PF (1<<2)
285 #define EFLG_CF (1<<0)
287 /* Exception definitions. */
288 #define EXC_DE 0
289 #define EXC_DB 1
290 #define EXC_BP 3
291 #define EXC_OF 4
292 #define EXC_BR 5
293 #define EXC_UD 6
294 #define EXC_TS 10
295 #define EXC_NP 11
296 #define EXC_SS 12
297 #define EXC_GP 13
298 #define EXC_PF 14
299 #define EXC_MF 16
301 /*
302 * Instruction emulation:
303 * Most instructions are emulated directly via a fragment of inline assembly
304 * code. This allows us to save/restore EFLAGS and thus very easily pick up
305 * any modified flags.
306 */
308 #if defined(__x86_64__)
309 #define _LO32 "k" /* force 32-bit operand */
310 #define _STK "%%rsp" /* stack pointer */
311 #define _BYTES_PER_LONG "8"
312 #elif defined(__i386__)
313 #define _LO32 "" /* force 32-bit operand */
314 #define _STK "%%esp" /* stack pointer */
315 #define _BYTES_PER_LONG "4"
316 #endif
318 /*
319 * These EFLAGS bits are restored from saved value during emulation, and
320 * any changes are written back to the saved value after emulation.
321 */
322 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
324 /* Before executing instruction: restore necessary bits in EFLAGS. */
325 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
326 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
327 "movl %"_sav",%"_LO32 _tmp"; " \
328 "push %"_tmp"; " \
329 "push %"_tmp"; " \
330 "movl %"_msk",%"_LO32 _tmp"; " \
331 "andl %"_LO32 _tmp",("_STK"); " \
332 "pushf; " \
333 "notl %"_LO32 _tmp"; " \
334 "andl %"_LO32 _tmp",("_STK"); " \
335 "andl %"_LO32 _tmp",2*"_BYTES_PER_LONG"("_STK"); " \
336 "pop %"_tmp"; " \
337 "orl %"_LO32 _tmp",("_STK"); " \
338 "popf; " \
339 "pop %"_sav"; "
341 /* After executing instruction: write-back necessary bits in EFLAGS. */
342 #define _POST_EFLAGS(_sav, _msk, _tmp) \
343 /* _sav |= EFLAGS & _msk; */ \
344 "pushf; " \
345 "pop %"_tmp"; " \
346 "andl %"_msk",%"_LO32 _tmp"; " \
347 "orl %"_LO32 _tmp",%"_sav"; "
349 /* Raw emulation: instruction has two explicit operands. */
350 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy)\
351 do{ unsigned long _tmp; \
352 switch ( (_dst).bytes ) \
353 { \
354 case 2: \
355 asm volatile ( \
356 _PRE_EFLAGS("0","4","2") \
357 _op"w %"_wx"3,%1; " \
358 _POST_EFLAGS("0","4","2") \
359 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
360 : _wy ((_src).val), "i" (EFLAGS_MASK), \
361 "m" (_eflags), "m" ((_dst).val) ); \
362 break; \
363 case 4: \
364 asm volatile ( \
365 _PRE_EFLAGS("0","4","2") \
366 _op"l %"_lx"3,%1; " \
367 _POST_EFLAGS("0","4","2") \
368 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
369 : _ly ((_src).val), "i" (EFLAGS_MASK), \
370 "m" (_eflags), "m" ((_dst).val) ); \
371 break; \
372 case 8: \
373 __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy); \
374 break; \
375 } \
376 } while (0)
377 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy)\
378 do{ unsigned long _tmp; \
379 switch ( (_dst).bytes ) \
380 { \
381 case 1: \
382 asm volatile ( \
383 _PRE_EFLAGS("0","4","2") \
384 _op"b %"_bx"3,%1; " \
385 _POST_EFLAGS("0","4","2") \
386 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
387 : _by ((_src).val), "i" (EFLAGS_MASK), \
388 "m" (_eflags), "m" ((_dst).val) ); \
389 break; \
390 default: \
391 __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy);\
392 break; \
393 } \
394 } while (0)
395 /* Source operand is byte-sized and may be restricted to just %cl. */
396 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
397 __emulate_2op(_op, _src, _dst, _eflags, \
398 "b", "c", "b", "c", "b", "c", "b", "c")
399 /* Source operand is byte, word, long or quad sized. */
400 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
401 __emulate_2op(_op, _src, _dst, _eflags, \
402 "b", "q", "w", "r", _LO32, "r", "", "r")
403 /* Source operand is word, long or quad sized. */
404 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
405 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
406 "w", "r", _LO32, "r", "", "r")
408 /* Instruction has only one explicit operand (no source operand). */
409 #define emulate_1op(_op,_dst,_eflags) \
410 do{ unsigned long _tmp; \
411 switch ( (_dst).bytes ) \
412 { \
413 case 1: \
414 asm volatile ( \
415 _PRE_EFLAGS("0","3","2") \
416 _op"b %1; " \
417 _POST_EFLAGS("0","3","2") \
418 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
419 : "i" (EFLAGS_MASK), "m" (_eflags), "m" ((_dst).val) ); \
420 break; \
421 case 2: \
422 asm volatile ( \
423 _PRE_EFLAGS("0","3","2") \
424 _op"w %1; " \
425 _POST_EFLAGS("0","3","2") \
426 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
427 : "i" (EFLAGS_MASK), "m" (_eflags), "m" ((_dst).val) ); \
428 break; \
429 case 4: \
430 asm volatile ( \
431 _PRE_EFLAGS("0","3","2") \
432 _op"l %1; " \
433 _POST_EFLAGS("0","3","2") \
434 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
435 : "i" (EFLAGS_MASK), "m" (_eflags), "m" ((_dst).val) ); \
436 break; \
437 case 8: \
438 __emulate_1op_8byte(_op, _dst, _eflags); \
439 break; \
440 } \
441 } while (0)
443 /* Emulate an instruction with quadword operands (x86/64 only). */
444 #if defined(__x86_64__)
445 #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy) \
446 do{ asm volatile ( \
447 _PRE_EFLAGS("0","4","2") \
448 _op"q %"_qx"3,%1; " \
449 _POST_EFLAGS("0","4","2") \
450 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
451 : _qy ((_src).val), "i" (EFLAGS_MASK), \
452 "m" (_eflags), "m" ((_dst).val) ); \
453 } while (0)
454 #define __emulate_1op_8byte(_op, _dst, _eflags) \
455 do{ asm volatile ( \
456 _PRE_EFLAGS("0","3","2") \
457 _op"q %1; " \
458 _POST_EFLAGS("0","3","2") \
459 : "=m" (_eflags), "=m" ((_dst).val), "=&r" (_tmp) \
460 : "i" (EFLAGS_MASK), "m" (_eflags), "m" ((_dst).val) ); \
461 } while (0)
462 #elif defined(__i386__)
463 #define __emulate_2op_8byte(_op, _src, _dst, _eflags, _qx, _qy)
464 #define __emulate_1op_8byte(_op, _dst, _eflags)
465 #endif /* __i386__ */
467 /* Fetch next part of the instruction being emulated. */
468 #define insn_fetch_bytes(_size) \
469 ({ unsigned long _x, _eip = _regs.eip; \
470 if ( !mode_64bit() ) _eip = (uint32_t)_eip; /* ignore upper dword */ \
471 _regs.eip += (_size); /* real hardware doesn't truncate */ \
472 generate_exception_if((uint8_t)(_regs.eip - ctxt->regs->eip) > 15, \
473 EXC_GP, 0); \
474 rc = ops->insn_fetch(x86_seg_cs, _eip, &_x, (_size), ctxt); \
475 if ( rc ) goto done; \
476 _x; \
477 })
478 #define insn_fetch_type(_type) ((_type)insn_fetch_bytes(sizeof(_type)))
480 #define truncate_word(ea, byte_width) \
481 ({ unsigned long __ea = (ea); \
482 unsigned int _width = (byte_width); \
483 ((_width == sizeof(unsigned long)) ? __ea : \
484 (__ea & ((1UL << (_width << 3)) - 1))); \
485 })
486 #define truncate_ea(ea) truncate_word((ea), ad_bytes)
488 #define mode_64bit() (def_ad_bytes == 8)
490 #define fail_if(p) \
491 do { \
492 rc = (p) ? X86EMUL_UNHANDLEABLE : X86EMUL_OKAY; \
493 if ( rc ) goto done; \
494 } while (0)
496 #define generate_exception_if(p, e, ec) \
497 ({ if ( (p) ) { \
498 fail_if(ops->inject_hw_exception == NULL); \
499 rc = ops->inject_hw_exception(e, ec, ctxt) ? : X86EMUL_EXCEPTION; \
500 goto done; \
501 } \
502 })
504 /*
505 * Given byte has even parity (even number of 1s)? SDM Vol. 1 Sec. 3.4.3.1,
506 * "Status Flags": EFLAGS.PF reflects parity of least-sig. byte of result only.
507 */
508 static int even_parity(uint8_t v)
509 {
510 asm ( "test %b0,%b0; setp %b0" : "=a" (v) : "0" (v) );
511 return v;
512 }
514 /* Update address held in a register, based on addressing mode. */
515 #define _register_address_increment(reg, inc, byte_width) \
516 do { \
517 int _inc = (inc); /* signed type ensures sign extension to long */ \
518 unsigned int _width = (byte_width); \
519 if ( _width == sizeof(unsigned long) ) \
520 (reg) += _inc; \
521 else if ( mode_64bit() ) \
522 (reg) = ((reg) + _inc) & ((1UL << (_width << 3)) - 1); \
523 else \
524 (reg) = ((reg) & ~((1UL << (_width << 3)) - 1)) | \
525 (((reg) + _inc) & ((1UL << (_width << 3)) - 1)); \
526 } while (0)
527 #define register_address_increment(reg, inc) \
528 _register_address_increment((reg), (inc), ad_bytes)
530 #define sp_pre_dec(dec) ({ \
531 _register_address_increment(_regs.esp, -(dec), ctxt->sp_size/8); \
532 truncate_word(_regs.esp, ctxt->sp_size/8); \
533 })
534 #define sp_post_inc(inc) ({ \
535 unsigned long __esp = truncate_word(_regs.esp, ctxt->sp_size/8); \
536 _register_address_increment(_regs.esp, (inc), ctxt->sp_size/8); \
537 __esp; \
538 })
540 #define jmp_rel(rel) \
541 do { \
542 int _rel = (int)(rel); \
543 _regs.eip += _rel; \
544 if ( !mode_64bit() ) \
545 _regs.eip = ((op_bytes == 2) \
546 ? (uint16_t)_regs.eip : (uint32_t)_regs.eip); \
547 } while (0)
549 struct fpu_insn_ctxt {
550 uint8_t insn_bytes;
551 uint8_t exn_raised;
552 };
554 static void fpu_handle_exception(void *_fic, struct cpu_user_regs *regs)
555 {
556 struct fpu_insn_ctxt *fic = _fic;
557 fic->exn_raised = 1;
558 regs->eip += fic->insn_bytes;
559 }
561 #define get_fpu(_type, _fic) \
562 do{ (_fic)->exn_raised = 0; \
563 fail_if(ops->get_fpu == NULL); \
564 rc = ops->get_fpu(fpu_handle_exception, _fic, _type, ctxt); \
565 if ( rc ) goto done; \
566 } while (0)
567 #define put_fpu(_fic) \
568 do{ \
569 if ( ops->put_fpu != NULL ) \
570 ops->put_fpu(ctxt); \
571 generate_exception_if((_fic)->exn_raised, EXC_MF, -1); \
572 } while (0)
574 #define emulate_fpu_insn(_op) \
575 do{ struct fpu_insn_ctxt fic; \
576 get_fpu(X86EMUL_FPU_fpu, &fic); \
577 asm volatile ( \
578 "movb $2f-1f,%0 \n" \
579 "1: " _op " \n" \
580 "2: \n" \
581 : "=m" (fic.insn_bytes) : : "memory" ); \
582 put_fpu(&fic); \
583 } while (0)
585 #define emulate_fpu_insn_memdst(_op, _arg) \
586 do{ struct fpu_insn_ctxt fic; \
587 get_fpu(X86EMUL_FPU_fpu, &fic); \
588 asm volatile ( \
589 "movb $2f-1f,%0 \n" \
590 "1: " _op " %1 \n" \
591 "2: \n" \
592 : "=m" (fic.insn_bytes), "=m" (_arg) \
593 : : "memory" ); \
594 put_fpu(&fic); \
595 } while (0)
597 #define emulate_fpu_insn_stub(_bytes...) \
598 do{ uint8_t stub[] = { _bytes, 0xc3 }; \
599 struct fpu_insn_ctxt fic = { .insn_bytes = sizeof(stub)-1 }; \
600 get_fpu(X86EMUL_FPU_fpu, &fic); \
601 (*(void(*)(void))stub)(); \
602 put_fpu(&fic); \
603 } while (0)
605 static unsigned long __get_rep_prefix(
606 struct cpu_user_regs *int_regs,
607 struct cpu_user_regs *ext_regs,
608 int ad_bytes)
609 {
610 unsigned long ecx = ((ad_bytes == 2) ? (uint16_t)int_regs->ecx :
611 (ad_bytes == 4) ? (uint32_t)int_regs->ecx :
612 int_regs->ecx);
614 /* Skip the instruction if no repetitions are required. */
615 if ( ecx == 0 )
616 ext_regs->eip = int_regs->eip;
618 return ecx;
619 }
621 #define get_rep_prefix() ({ \
622 unsigned long max_reps = 1; \
623 if ( rep_prefix ) \
624 max_reps = __get_rep_prefix(&_regs, ctxt->regs, ad_bytes); \
625 if ( max_reps == 0 ) \
626 goto done; \
627 max_reps; \
628 })
630 static void __put_rep_prefix(
631 struct cpu_user_regs *int_regs,
632 struct cpu_user_regs *ext_regs,
633 int ad_bytes,
634 unsigned long reps_completed)
635 {
636 unsigned long ecx = ((ad_bytes == 2) ? (uint16_t)int_regs->ecx :
637 (ad_bytes == 4) ? (uint32_t)int_regs->ecx :
638 int_regs->ecx);
640 /* Reduce counter appropriately, and repeat instruction if non-zero. */
641 ecx -= reps_completed;
642 if ( ecx != 0 )
643 int_regs->eip = ext_regs->eip;
645 if ( ad_bytes == 2 )
646 *(uint16_t *)&int_regs->ecx = ecx;
647 else if ( ad_bytes == 4 )
648 int_regs->ecx = (uint32_t)ecx;
649 else
650 int_regs->ecx = ecx;
651 }
653 #define put_rep_prefix(reps_completed) ({ \
654 if ( rep_prefix ) \
655 __put_rep_prefix(&_regs, ctxt->regs, ad_bytes, reps_completed); \
656 })
658 /*
659 * Unsigned multiplication with double-word result.
660 * IN: Multiplicand=m[0], Multiplier=m[1]
661 * OUT: Return CF/OF (overflow status); Result=m[1]:m[0]
662 */
663 static int mul_dbl(unsigned long m[2])
664 {
665 int rc;
666 asm ( "mul %4; seto %b2"
667 : "=a" (m[0]), "=d" (m[1]), "=q" (rc)
668 : "0" (m[0]), "1" (m[1]), "2" (0) );
669 return rc;
670 }
672 /*
673 * Signed multiplication with double-word result.
674 * IN: Multiplicand=m[0], Multiplier=m[1]
675 * OUT: Return CF/OF (overflow status); Result=m[1]:m[0]
676 */
677 static int imul_dbl(unsigned long m[2])
678 {
679 int rc;
680 asm ( "imul %4; seto %b2"
681 : "=a" (m[0]), "=d" (m[1]), "=q" (rc)
682 : "0" (m[0]), "1" (m[1]), "2" (0) );
683 return rc;
684 }
686 /*
687 * Unsigned division of double-word dividend.
688 * IN: Dividend=u[1]:u[0], Divisor=v
689 * OUT: Return 1: #DE
690 * Return 0: Quotient=u[0], Remainder=u[1]
691 */
692 static int div_dbl(unsigned long u[2], unsigned long v)
693 {
694 if ( (v == 0) || (u[1] >= v) )
695 return 1;
696 asm ( "div %4"
697 : "=a" (u[0]), "=d" (u[1])
698 : "0" (u[0]), "1" (u[1]), "r" (v) );
699 return 0;
700 }
702 /*
703 * Signed division of double-word dividend.
704 * IN: Dividend=u[1]:u[0], Divisor=v
705 * OUT: Return 1: #DE
706 * Return 0: Quotient=u[0], Remainder=u[1]
707 * NB. We don't use idiv directly as it's moderately hard to work out
708 * ahead of time whether it will #DE, which we cannot allow to happen.
709 */
710 static int idiv_dbl(unsigned long u[2], unsigned long v)
711 {
712 int negu = (long)u[1] < 0, negv = (long)v < 0;
714 /* u = abs(u) */
715 if ( negu )
716 {
717 u[1] = ~u[1];
718 if ( (u[0] = -u[0]) == 0 )
719 u[1]++;
720 }
722 /* abs(u) / abs(v) */
723 if ( div_dbl(u, negv ? -v : v) )
724 return 1;
726 /* Remainder has same sign as dividend. It cannot overflow. */
727 if ( negu )
728 u[1] = -u[1];
730 /* Quotient is overflowed if sign bit is set. */
731 if ( negu ^ negv )
732 {
733 if ( (long)u[0] >= 0 )
734 u[0] = -u[0];
735 else if ( (u[0] << 1) != 0 ) /* == 0x80...0 is okay */
736 return 1;
737 }
738 else if ( (long)u[0] < 0 )
739 return 1;
741 return 0;
742 }
744 static int
745 test_cc(
746 unsigned int condition, unsigned int flags)
747 {
748 int rc = 0;
750 switch ( (condition & 15) >> 1 )
751 {
752 case 0: /* o */
753 rc |= (flags & EFLG_OF);
754 break;
755 case 1: /* b/c/nae */
756 rc |= (flags & EFLG_CF);
757 break;
758 case 2: /* z/e */
759 rc |= (flags & EFLG_ZF);
760 break;
761 case 3: /* be/na */
762 rc |= (flags & (EFLG_CF|EFLG_ZF));
763 break;
764 case 4: /* s */
765 rc |= (flags & EFLG_SF);
766 break;
767 case 5: /* p/pe */
768 rc |= (flags & EFLG_PF);
769 break;
770 case 7: /* le/ng */
771 rc |= (flags & EFLG_ZF);
772 /* fall through */
773 case 6: /* l/nge */
774 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
775 break;
776 }
778 /* Odd condition identifiers (lsb == 1) have inverted sense. */
779 return (!!rc ^ (condition & 1));
780 }
782 static int
783 get_cpl(
784 struct x86_emulate_ctxt *ctxt,
785 struct x86_emulate_ops *ops)
786 {
787 struct segment_register reg;
789 if ( ctxt->regs->eflags & EFLG_VM )
790 return 3;
792 if ( (ops->read_segment == NULL) ||
793 ops->read_segment(x86_seg_ss, &reg, ctxt) )
794 return -1;
796 return reg.attr.fields.dpl;
797 }
799 static int
800 _mode_iopl(
801 struct x86_emulate_ctxt *ctxt,
802 struct x86_emulate_ops *ops)
803 {
804 int cpl = get_cpl(ctxt, ops);
805 if ( cpl == -1 )
806 return -1;
807 return (cpl <= ((ctxt->regs->eflags >> 12) & 3));
808 }
810 #define mode_ring0() ({ \
811 int _cpl = get_cpl(ctxt, ops); \
812 fail_if(_cpl < 0); \
813 (_cpl == 0); \
814 })
815 #define mode_iopl() ({ \
816 int _iopl = _mode_iopl(ctxt, ops); \
817 fail_if(_iopl < 0); \
818 _iopl; \
819 })
821 static int ioport_access_check(
822 unsigned int first_port,
823 unsigned int bytes,
824 struct x86_emulate_ctxt *ctxt,
825 struct x86_emulate_ops *ops)
826 {
827 unsigned long iobmp;
828 struct segment_register tr;
829 int rc = X86EMUL_OKAY;
831 if ( !(ctxt->regs->eflags & EFLG_VM) && mode_iopl() )
832 return X86EMUL_OKAY;
834 fail_if(ops->read_segment == NULL);
835 if ( (rc = ops->read_segment(x86_seg_tr, &tr, ctxt)) != 0 )
836 return rc;
838 /* Ensure that the TSS is valid and has an io-bitmap-offset field. */
839 if ( !tr.attr.fields.p ||
840 ((tr.attr.fields.type & 0xd) != 0x9) ||
841 (tr.limit < 0x67) )
842 goto raise_exception;
844 if ( (rc = ops->read(x86_seg_none, tr.base + 0x66, &iobmp, 2, ctxt)) )
845 return rc;
847 /* Ensure TSS includes two bytes including byte containing first port. */
848 iobmp += first_port / 8;
849 if ( tr.limit <= iobmp )
850 goto raise_exception;
852 if ( (rc = ops->read(x86_seg_none, tr.base + iobmp, &iobmp, 2, ctxt)) )
853 return rc;
854 if ( (iobmp & (((1<<bytes)-1) << (first_port&7))) != 0 )
855 goto raise_exception;
857 done:
858 return rc;
860 raise_exception:
861 fail_if(ops->inject_hw_exception == NULL);
862 return ops->inject_hw_exception(EXC_GP, 0, ctxt) ? : X86EMUL_EXCEPTION;
863 }
865 static int
866 in_realmode(
867 struct x86_emulate_ctxt *ctxt,
868 struct x86_emulate_ops *ops)
869 {
870 unsigned long cr0;
871 int rc;
873 if ( ops->read_cr == NULL )
874 return 0;
876 rc = ops->read_cr(0, &cr0, ctxt);
877 return (!rc && !(cr0 & CR0_PE));
878 }
880 static int
881 realmode_load_seg(
882 enum x86_segment seg,
883 uint16_t sel,
884 struct x86_emulate_ctxt *ctxt,
885 struct x86_emulate_ops *ops)
886 {
887 struct segment_register reg;
888 int rc;
890 if ( (rc = ops->read_segment(seg, &reg, ctxt)) != 0 )
891 return rc;
893 reg.sel = sel;
894 reg.base = (uint32_t)sel << 4;
896 return ops->write_segment(seg, &reg, ctxt);
897 }
899 static int
900 protmode_load_seg(
901 enum x86_segment seg,
902 uint16_t sel,
903 struct x86_emulate_ctxt *ctxt,
904 struct x86_emulate_ops *ops)
905 {
906 struct segment_register desctab, cs, segr;
907 struct { uint32_t a, b; } desc;
908 unsigned long val;
909 uint8_t dpl, rpl, cpl;
910 int rc, fault_type = EXC_TS;
912 /* NULL selector? */
913 if ( (sel & 0xfffc) == 0 )
914 {
915 if ( (seg == x86_seg_cs) || (seg == x86_seg_ss) )
916 goto raise_exn;
917 memset(&segr, 0, sizeof(segr));
918 return ops->write_segment(seg, &segr, ctxt);
919 }
921 /* LDT descriptor must be in the GDT. */
922 if ( (seg == x86_seg_ldtr) && (sel & 4) )
923 goto raise_exn;
925 if ( (rc = ops->read_segment(x86_seg_cs, &cs, ctxt)) ||
926 (rc = ops->read_segment((sel & 4) ? x86_seg_ldtr : x86_seg_gdtr,
927 &desctab, ctxt)) )
928 return rc;
930 /* Check against descriptor table limit. */
931 if ( ((sel & 0xfff8) + 7) > desctab.limit )
932 goto raise_exn;
934 do {
935 if ( (rc = ops->read(x86_seg_none, desctab.base + (sel & 0xfff8),
936 &val, 4, ctxt)) )
937 return rc;
938 desc.a = val;
939 if ( (rc = ops->read(x86_seg_none, desctab.base + (sel & 0xfff8) + 4,
940 &val, 4, ctxt)) )
941 return rc;
942 desc.b = val;
944 /* Segment present in memory? */
945 if ( !(desc.b & (1u<<15)) )
946 {
947 fault_type = EXC_NP;
948 goto raise_exn;
949 }
951 /* LDT descriptor is a system segment. All others are code/data. */
952 if ( (desc.b & (1u<<12)) == ((seg == x86_seg_ldtr) << 12) )
953 goto raise_exn;
955 dpl = (desc.b >> 13) & 3;
956 rpl = sel & 3;
957 cpl = cs.sel & 3;
959 switch ( seg )
960 {
961 case x86_seg_cs:
962 /* Code segment? */
963 if ( !(desc.b & (1u<<11)) )
964 goto raise_exn;
965 /* Non-conforming segment: check DPL against RPL. */
966 if ( ((desc.b & (6u<<9)) != 6) && (dpl != rpl) )
967 goto raise_exn;
968 break;
969 case x86_seg_ss:
970 /* Writable data segment? */
971 if ( (desc.b & (5u<<9)) != (1u<<9) )
972 goto raise_exn;
973 if ( (dpl != cpl) || (dpl != rpl) )
974 goto raise_exn;
975 break;
976 case x86_seg_ldtr:
977 /* LDT system segment? */
978 if ( (desc.b & (15u<<8)) != (2u<<8) )
979 goto raise_exn;
980 goto skip_accessed_flag;
981 default:
982 /* Readable code or data segment? */
983 if ( (desc.b & (5u<<9)) == (4u<<9) )
984 goto raise_exn;
985 /* Non-conforming segment: check DPL against RPL and CPL. */
986 if ( ((desc.b & (6u<<9)) != 6) && ((dpl < cpl) || (dpl < rpl)) )
987 goto raise_exn;
988 break;
989 }
991 /* Ensure Accessed flag is set. */
992 rc = ((desc.b & 0x100) ? X86EMUL_OKAY :
993 ops->cmpxchg(
994 x86_seg_none, desctab.base + (sel & 0xfff8) + 4, desc.b,
995 desc.b | 0x100, 4, ctxt));
996 } while ( rc == X86EMUL_CMPXCHG_FAILED );
998 if ( rc )
999 return rc;
1001 /* Force the Accessed flag in our local copy. */
1002 desc.b |= 0x100;
1004 skip_accessed_flag:
1005 segr.base = (((desc.b << 0) & 0xff000000u) |
1006 ((desc.b << 16) & 0x00ff0000u) |
1007 ((desc.a >> 16) & 0x0000ffffu));
1008 segr.attr.bytes = (((desc.b >> 8) & 0x00ffu) |
1009 ((desc.b >> 12) & 0x0f00u));
1010 segr.limit = (desc.b & 0x000f0000u) | (desc.a & 0x0000ffffu);
1011 if ( segr.attr.fields.g )
1012 segr.limit = (segr.limit << 12) | 0xfffu;
1013 segr.sel = sel;
1014 return ops->write_segment(seg, &segr, ctxt);
1016 raise_exn:
1017 if ( ops->inject_hw_exception == NULL )
1018 return X86EMUL_UNHANDLEABLE;
1019 if ( (rc = ops->inject_hw_exception(fault_type, sel & 0xfffc, ctxt)) )
1020 return rc;
1021 return X86EMUL_EXCEPTION;
1024 static int
1025 load_seg(
1026 enum x86_segment seg,
1027 uint16_t sel,
1028 struct x86_emulate_ctxt *ctxt,
1029 struct x86_emulate_ops *ops)
1031 if ( (ops->read_segment == NULL) ||
1032 (ops->write_segment == NULL) )
1033 return X86EMUL_UNHANDLEABLE;
1035 if ( in_realmode(ctxt, ops) )
1036 return realmode_load_seg(seg, sel, ctxt, ops);
1038 return protmode_load_seg(seg, sel, ctxt, ops);
1041 void *
1042 decode_register(
1043 uint8_t modrm_reg, struct cpu_user_regs *regs, int highbyte_regs)
1045 void *p;
1047 switch ( modrm_reg )
1049 case 0: p = &regs->eax; break;
1050 case 1: p = &regs->ecx; break;
1051 case 2: p = &regs->edx; break;
1052 case 3: p = &regs->ebx; break;
1053 case 4: p = (highbyte_regs ?
1054 ((unsigned char *)&regs->eax + 1) :
1055 (unsigned char *)&regs->esp); break;
1056 case 5: p = (highbyte_regs ?
1057 ((unsigned char *)&regs->ecx + 1) :
1058 (unsigned char *)&regs->ebp); break;
1059 case 6: p = (highbyte_regs ?
1060 ((unsigned char *)&regs->edx + 1) :
1061 (unsigned char *)&regs->esi); break;
1062 case 7: p = (highbyte_regs ?
1063 ((unsigned char *)&regs->ebx + 1) :
1064 (unsigned char *)&regs->edi); break;
1065 #if defined(__x86_64__)
1066 case 8: p = &regs->r8; break;
1067 case 9: p = &regs->r9; break;
1068 case 10: p = &regs->r10; break;
1069 case 11: p = &regs->r11; break;
1070 case 12: p = &regs->r12; break;
1071 case 13: p = &regs->r13; break;
1072 case 14: p = &regs->r14; break;
1073 case 15: p = &regs->r15; break;
1074 #endif
1075 default: p = NULL; break;
1078 return p;
1081 #define decode_segment_failed x86_seg_tr
1082 enum x86_segment
1083 decode_segment(
1084 uint8_t modrm_reg)
1086 switch ( modrm_reg )
1088 case 0: return x86_seg_es;
1089 case 1: return x86_seg_cs;
1090 case 2: return x86_seg_ss;
1091 case 3: return x86_seg_ds;
1092 case 4: return x86_seg_fs;
1093 case 5: return x86_seg_gs;
1094 default: break;
1096 return decode_segment_failed;
1099 int
1100 x86_emulate(
1101 struct x86_emulate_ctxt *ctxt,
1102 struct x86_emulate_ops *ops)
1104 /* Shadow copy of register state. Committed on successful emulation. */
1105 struct cpu_user_regs _regs = *ctxt->regs;
1107 uint8_t b, d, sib, sib_index, sib_base, twobyte = 0, rex_prefix = 0;
1108 uint8_t modrm = 0, modrm_mod = 0, modrm_reg = 0, modrm_rm = 0;
1109 unsigned int op_bytes, def_op_bytes, ad_bytes, def_ad_bytes;
1110 #define REPE_PREFIX 1
1111 #define REPNE_PREFIX 2
1112 unsigned int lock_prefix = 0, rep_prefix = 0;
1113 int override_seg = -1, rc = X86EMUL_OKAY;
1114 struct operand src, dst;
1116 /* Data operand effective address (usually computed from ModRM). */
1117 struct operand ea;
1119 /* Default is a memory operand relative to segment DS. */
1120 ea.type = OP_MEM;
1121 ea.mem.seg = x86_seg_ds;
1122 ea.mem.off = 0;
1124 ctxt->retire.byte = 0;
1126 op_bytes = def_op_bytes = ad_bytes = def_ad_bytes = ctxt->addr_size/8;
1127 if ( op_bytes == 8 )
1129 op_bytes = def_op_bytes = 4;
1130 #ifndef __x86_64__
1131 return X86EMUL_UNHANDLEABLE;
1132 #endif
1135 /* Prefix bytes. */
1136 for ( ; ; )
1138 switch ( b = insn_fetch_type(uint8_t) )
1140 case 0x66: /* operand-size override */
1141 op_bytes = def_op_bytes ^ 6;
1142 break;
1143 case 0x67: /* address-size override */
1144 ad_bytes = def_ad_bytes ^ (mode_64bit() ? 12 : 6);
1145 break;
1146 case 0x2e: /* CS override */
1147 override_seg = x86_seg_cs;
1148 break;
1149 case 0x3e: /* DS override */
1150 override_seg = x86_seg_ds;
1151 break;
1152 case 0x26: /* ES override */
1153 override_seg = x86_seg_es;
1154 break;
1155 case 0x64: /* FS override */
1156 override_seg = x86_seg_fs;
1157 break;
1158 case 0x65: /* GS override */
1159 override_seg = x86_seg_gs;
1160 break;
1161 case 0x36: /* SS override */
1162 override_seg = x86_seg_ss;
1163 break;
1164 case 0xf0: /* LOCK */
1165 lock_prefix = 1;
1166 break;
1167 case 0xf2: /* REPNE/REPNZ */
1168 rep_prefix = REPNE_PREFIX;
1169 break;
1170 case 0xf3: /* REP/REPE/REPZ */
1171 rep_prefix = REPE_PREFIX;
1172 break;
1173 case 0x40 ... 0x4f: /* REX */
1174 if ( !mode_64bit() )
1175 goto done_prefixes;
1176 rex_prefix = b;
1177 continue;
1178 default:
1179 goto done_prefixes;
1182 /* Any legacy prefix after a REX prefix nullifies its effect. */
1183 rex_prefix = 0;
1185 done_prefixes:
1187 if ( rex_prefix & 8 ) /* REX.W */
1188 op_bytes = 8;
1190 /* Opcode byte(s). */
1191 d = opcode_table[b];
1192 if ( d == 0 )
1194 /* Two-byte opcode? */
1195 if ( b == 0x0f )
1197 twobyte = 1;
1198 b = insn_fetch_type(uint8_t);
1199 d = twobyte_table[b];
1202 /* Unrecognised? */
1203 if ( d == 0 )
1204 goto cannot_emulate;
1207 /* Lock prefix is allowed only on RMW instructions. */
1208 generate_exception_if((d & Mov) && lock_prefix, EXC_GP, 0);
1210 /* ModRM and SIB bytes. */
1211 if ( d & ModRM )
1213 modrm = insn_fetch_type(uint8_t);
1214 modrm_mod = (modrm & 0xc0) >> 6;
1215 modrm_reg = ((rex_prefix & 4) << 1) | ((modrm & 0x38) >> 3);
1216 modrm_rm = modrm & 0x07;
1218 if ( modrm_mod == 3 )
1220 modrm_rm |= (rex_prefix & 1) << 3;
1221 ea.type = OP_REG;
1222 ea.reg = decode_register(
1223 modrm_rm, &_regs, (d & ByteOp) && (rex_prefix == 0));
1225 else if ( ad_bytes == 2 )
1227 /* 16-bit ModR/M decode. */
1228 switch ( modrm_rm )
1230 case 0:
1231 ea.mem.off = _regs.ebx + _regs.esi;
1232 break;
1233 case 1:
1234 ea.mem.off = _regs.ebx + _regs.edi;
1235 break;
1236 case 2:
1237 ea.mem.seg = x86_seg_ss;
1238 ea.mem.off = _regs.ebp + _regs.esi;
1239 break;
1240 case 3:
1241 ea.mem.seg = x86_seg_ss;
1242 ea.mem.off = _regs.ebp + _regs.edi;
1243 break;
1244 case 4:
1245 ea.mem.off = _regs.esi;
1246 break;
1247 case 5:
1248 ea.mem.off = _regs.edi;
1249 break;
1250 case 6:
1251 if ( modrm_mod == 0 )
1252 break;
1253 ea.mem.seg = x86_seg_ss;
1254 ea.mem.off = _regs.ebp;
1255 break;
1256 case 7:
1257 ea.mem.off = _regs.ebx;
1258 break;
1260 switch ( modrm_mod )
1262 case 0:
1263 if ( modrm_rm == 6 )
1264 ea.mem.off = insn_fetch_type(int16_t);
1265 break;
1266 case 1:
1267 ea.mem.off += insn_fetch_type(int8_t);
1268 break;
1269 case 2:
1270 ea.mem.off += insn_fetch_type(int16_t);
1271 break;
1273 ea.mem.off = truncate_ea(ea.mem.off);
1275 else
1277 /* 32/64-bit ModR/M decode. */
1278 if ( modrm_rm == 4 )
1280 sib = insn_fetch_type(uint8_t);
1281 sib_index = ((sib >> 3) & 7) | ((rex_prefix << 2) & 8);
1282 sib_base = (sib & 7) | ((rex_prefix << 3) & 8);
1283 if ( sib_index != 4 )
1284 ea.mem.off = *(long*)decode_register(sib_index, &_regs, 0);
1285 ea.mem.off <<= (sib >> 6) & 3;
1286 if ( (modrm_mod == 0) && ((sib_base & 7) == 5) )
1287 ea.mem.off += insn_fetch_type(int32_t);
1288 else if ( sib_base == 4 )
1290 ea.mem.seg = x86_seg_ss;
1291 ea.mem.off += _regs.esp;
1292 if ( !twobyte && (b == 0x8f) )
1293 /* POP <rm> computes its EA post increment. */
1294 ea.mem.off += ((mode_64bit() && (op_bytes == 4))
1295 ? 8 : op_bytes);
1297 else if ( sib_base == 5 )
1299 ea.mem.seg = x86_seg_ss;
1300 ea.mem.off += _regs.ebp;
1302 else
1303 ea.mem.off += *(long*)decode_register(sib_base, &_regs, 0);
1305 else
1307 modrm_rm |= (rex_prefix & 1) << 3;
1308 ea.mem.off = *(long *)decode_register(modrm_rm, &_regs, 0);
1309 if ( (modrm_rm == 5) && (modrm_mod != 0) )
1310 ea.mem.seg = x86_seg_ss;
1312 switch ( modrm_mod )
1314 case 0:
1315 if ( (modrm_rm & 7) != 5 )
1316 break;
1317 ea.mem.off = insn_fetch_type(int32_t);
1318 if ( !mode_64bit() )
1319 break;
1320 /* Relative to RIP of next instruction. Argh! */
1321 ea.mem.off += _regs.eip;
1322 if ( (d & SrcMask) == SrcImm )
1323 ea.mem.off += (d & ByteOp) ? 1 :
1324 ((op_bytes == 8) ? 4 : op_bytes);
1325 else if ( (d & SrcMask) == SrcImmByte )
1326 ea.mem.off += 1;
1327 else if ( !twobyte && ((b & 0xfe) == 0xf6) &&
1328 ((modrm_reg & 7) <= 1) )
1329 /* Special case in Grp3: test has immediate operand. */
1330 ea.mem.off += (d & ByteOp) ? 1
1331 : ((op_bytes == 8) ? 4 : op_bytes);
1332 else if ( twobyte && ((b & 0xf7) == 0xa4) )
1333 /* SHLD/SHRD with immediate byte third operand. */
1334 ea.mem.off++;
1335 break;
1336 case 1:
1337 ea.mem.off += insn_fetch_type(int8_t);
1338 break;
1339 case 2:
1340 ea.mem.off += insn_fetch_type(int32_t);
1341 break;
1343 ea.mem.off = truncate_ea(ea.mem.off);
1347 if ( override_seg != -1 )
1348 ea.mem.seg = override_seg;
1350 /* Special instructions do their own operand decoding. */
1351 if ( (d & DstMask) == ImplicitOps )
1352 goto special_insn;
1354 /* Decode and fetch the source operand: register, memory or immediate. */
1355 switch ( d & SrcMask )
1357 case SrcNone:
1358 break;
1359 case SrcReg:
1360 src.type = OP_REG;
1361 if ( d & ByteOp )
1363 src.reg = decode_register(modrm_reg, &_regs, (rex_prefix == 0));
1364 src.val = *(uint8_t *)src.reg;
1365 src.bytes = 1;
1367 else
1369 src.reg = decode_register(modrm_reg, &_regs, 0);
1370 switch ( (src.bytes = op_bytes) )
1372 case 2: src.val = *(uint16_t *)src.reg; break;
1373 case 4: src.val = *(uint32_t *)src.reg; break;
1374 case 8: src.val = *(uint64_t *)src.reg; break;
1377 break;
1378 case SrcMem16:
1379 ea.bytes = 2;
1380 goto srcmem_common;
1381 case SrcMem:
1382 ea.bytes = (d & ByteOp) ? 1 : op_bytes;
1383 srcmem_common:
1384 src = ea;
1385 if ( src.type == OP_REG )
1387 switch ( src.bytes )
1389 case 1: src.val = *(uint8_t *)src.reg; break;
1390 case 2: src.val = *(uint16_t *)src.reg; break;
1391 case 4: src.val = *(uint32_t *)src.reg; break;
1392 case 8: src.val = *(uint64_t *)src.reg; break;
1395 else if ( (rc = ops->read(src.mem.seg, src.mem.off,
1396 &src.val, src.bytes, ctxt)) )
1397 goto done;
1398 break;
1399 case SrcImm:
1400 src.type = OP_IMM;
1401 src.bytes = (d & ByteOp) ? 1 : op_bytes;
1402 if ( src.bytes == 8 ) src.bytes = 4;
1403 /* NB. Immediates are sign-extended as necessary. */
1404 switch ( src.bytes )
1406 case 1: src.val = insn_fetch_type(int8_t); break;
1407 case 2: src.val = insn_fetch_type(int16_t); break;
1408 case 4: src.val = insn_fetch_type(int32_t); break;
1410 break;
1411 case SrcImmByte:
1412 src.type = OP_IMM;
1413 src.bytes = 1;
1414 src.val = insn_fetch_type(int8_t);
1415 break;
1418 /* Decode and fetch the destination operand: register or memory. */
1419 switch ( d & DstMask )
1421 case DstReg:
1422 dst.type = OP_REG;
1423 if ( d & ByteOp )
1425 dst.reg = decode_register(modrm_reg, &_regs, (rex_prefix == 0));
1426 dst.val = *(uint8_t *)dst.reg;
1427 dst.bytes = 1;
1429 else
1431 dst.reg = decode_register(modrm_reg, &_regs, 0);
1432 switch ( (dst.bytes = op_bytes) )
1434 case 2: dst.val = *(uint16_t *)dst.reg; break;
1435 case 4: dst.val = *(uint32_t *)dst.reg; break;
1436 case 8: dst.val = *(uint64_t *)dst.reg; break;
1439 break;
1440 case DstBitBase:
1441 if ( ((d & SrcMask) == SrcImmByte) || (ea.type == OP_REG) )
1443 src.val &= (op_bytes << 3) - 1;
1445 else
1447 /*
1448 * EA += BitOffset DIV op_bytes*8
1449 * BitOffset = BitOffset MOD op_bytes*8
1450 * DIV truncates towards negative infinity.
1451 * MOD always produces a positive result.
1452 */
1453 if ( op_bytes == 2 )
1454 src.val = (int16_t)src.val;
1455 else if ( op_bytes == 4 )
1456 src.val = (int32_t)src.val;
1457 if ( (long)src.val < 0 )
1459 unsigned long byte_offset;
1460 byte_offset = op_bytes + (((-src.val-1) >> 3) & ~(op_bytes-1));
1461 ea.mem.off -= byte_offset;
1462 src.val = (byte_offset << 3) + src.val;
1464 else
1466 ea.mem.off += (src.val >> 3) & ~(op_bytes - 1);
1467 src.val &= (op_bytes << 3) - 1;
1470 /* Becomes a normal DstMem operation from here on. */
1471 d = (d & ~DstMask) | DstMem;
1472 case DstMem:
1473 ea.bytes = (d & ByteOp) ? 1 : op_bytes;
1474 dst = ea;
1475 if ( dst.type == OP_REG )
1477 switch ( dst.bytes )
1479 case 1: dst.val = *(uint8_t *)dst.reg; break;
1480 case 2: dst.val = *(uint16_t *)dst.reg; break;
1481 case 4: dst.val = *(uint32_t *)dst.reg; break;
1482 case 8: dst.val = *(uint64_t *)dst.reg; break;
1485 else if ( !(d & Mov) ) /* optimisation - avoid slow emulated read */
1487 if ( (rc = ops->read(dst.mem.seg, dst.mem.off,
1488 &dst.val, dst.bytes, ctxt)) )
1489 goto done;
1490 dst.orig_val = dst.val;
1492 break;
1495 /* LOCK prefix allowed only on instructions with memory destination. */
1496 generate_exception_if(lock_prefix && (dst.type != OP_MEM), EXC_GP, 0);
1498 if ( twobyte )
1499 goto twobyte_insn;
1501 switch ( b )
1503 case 0x04 ... 0x05: /* add imm,%%eax */
1504 dst.reg = (unsigned long *)&_regs.eax;
1505 dst.val = _regs.eax;
1506 case 0x00 ... 0x03: add: /* add */
1507 emulate_2op_SrcV("add", src, dst, _regs.eflags);
1508 break;
1510 case 0x0c ... 0x0d: /* or imm,%%eax */
1511 dst.reg = (unsigned long *)&_regs.eax;
1512 dst.val = _regs.eax;
1513 case 0x08 ... 0x0b: or: /* or */
1514 emulate_2op_SrcV("or", src, dst, _regs.eflags);
1515 break;
1517 case 0x14 ... 0x15: /* adc imm,%%eax */
1518 dst.reg = (unsigned long *)&_regs.eax;
1519 dst.val = _regs.eax;
1520 case 0x10 ... 0x13: adc: /* adc */
1521 emulate_2op_SrcV("adc", src, dst, _regs.eflags);
1522 break;
1524 case 0x1c ... 0x1d: /* sbb imm,%%eax */
1525 dst.reg = (unsigned long *)&_regs.eax;
1526 dst.val = _regs.eax;
1527 case 0x18 ... 0x1b: sbb: /* sbb */
1528 emulate_2op_SrcV("sbb", src, dst, _regs.eflags);
1529 break;
1531 case 0x24 ... 0x25: /* and imm,%%eax */
1532 dst.reg = (unsigned long *)&_regs.eax;
1533 dst.val = _regs.eax;
1534 case 0x20 ... 0x23: and: /* and */
1535 emulate_2op_SrcV("and", src, dst, _regs.eflags);
1536 break;
1538 case 0x2c ... 0x2d: /* sub imm,%%eax */
1539 dst.reg = (unsigned long *)&_regs.eax;
1540 dst.val = _regs.eax;
1541 case 0x28 ... 0x2b: sub: /* sub */
1542 emulate_2op_SrcV("sub", src, dst, _regs.eflags);
1543 break;
1545 case 0x34 ... 0x35: /* xor imm,%%eax */
1546 dst.reg = (unsigned long *)&_regs.eax;
1547 dst.val = _regs.eax;
1548 case 0x30 ... 0x33: xor: /* xor */
1549 emulate_2op_SrcV("xor", src, dst, _regs.eflags);
1550 break;
1552 case 0x3c ... 0x3d: /* cmp imm,%%eax */
1553 dst.reg = (unsigned long *)&_regs.eax;
1554 dst.val = _regs.eax;
1555 case 0x38 ... 0x3b: cmp: /* cmp */
1556 emulate_2op_SrcV("cmp", src, dst, _regs.eflags);
1557 break;
1559 case 0x62: /* bound */ {
1560 unsigned long src_val2;
1561 int lb, ub, idx;
1562 generate_exception_if(mode_64bit() || (src.type != OP_MEM),
1563 EXC_UD, -1);
1564 if ( (rc = ops->read(src.mem.seg, src.mem.off + op_bytes,
1565 &src_val2, op_bytes, ctxt)) )
1566 goto done;
1567 ub = (op_bytes == 2) ? (int16_t)src_val2 : (int32_t)src_val2;
1568 lb = (op_bytes == 2) ? (int16_t)src.val : (int32_t)src.val;
1569 idx = (op_bytes == 2) ? (int16_t)dst.val : (int32_t)dst.val;
1570 generate_exception_if((idx < lb) || (idx > ub), EXC_BR, -1);
1571 dst.type = OP_NONE;
1572 break;
1575 case 0x63: /* movsxd (x86/64) / arpl (x86/32) */
1576 if ( mode_64bit() )
1578 /* movsxd */
1579 if ( src.type == OP_REG )
1580 src.val = *(int32_t *)src.reg;
1581 else if ( (rc = ops->read(src.mem.seg, src.mem.off,
1582 &src.val, 4, ctxt)) )
1583 goto done;
1584 dst.val = (int32_t)src.val;
1586 else
1588 /* arpl */
1589 uint16_t src_val = dst.val;
1590 dst = src;
1591 _regs.eflags &= ~EFLG_ZF;
1592 _regs.eflags |= ((src_val & 3) > (dst.val & 3)) ? EFLG_ZF : 0;
1593 if ( _regs.eflags & EFLG_ZF )
1594 dst.val = (dst.val & ~3) | (src_val & 3);
1595 else
1596 dst.type = OP_NONE;
1597 generate_exception_if(in_realmode(ctxt, ops), EXC_UD, -1);
1599 break;
1601 case 0x69: /* imul imm16/32 */
1602 case 0x6b: /* imul imm8 */ {
1603 unsigned long src1; /* ModR/M source operand */
1604 if ( ea.type == OP_REG )
1605 src1 = *ea.reg;
1606 else if ( (rc = ops->read(ea.mem.seg, ea.mem.off,
1607 &src1, op_bytes, ctxt)) )
1608 goto done;
1609 _regs.eflags &= ~(EFLG_OF|EFLG_CF);
1610 switch ( dst.bytes )
1612 case 2:
1613 dst.val = ((uint32_t)(int16_t)src.val *
1614 (uint32_t)(int16_t)src1);
1615 if ( (int16_t)dst.val != (uint32_t)dst.val )
1616 _regs.eflags |= EFLG_OF|EFLG_CF;
1617 break;
1618 #ifdef __x86_64__
1619 case 4:
1620 dst.val = ((uint64_t)(int32_t)src.val *
1621 (uint64_t)(int32_t)src1);
1622 if ( (int32_t)dst.val != dst.val )
1623 _regs.eflags |= EFLG_OF|EFLG_CF;
1624 break;
1625 #endif
1626 default: {
1627 unsigned long m[2] = { src.val, src1 };
1628 if ( imul_dbl(m) )
1629 _regs.eflags |= EFLG_OF|EFLG_CF;
1630 dst.val = m[0];
1631 break;
1634 break;
1637 case 0x82: /* Grp1 (x86/32 only) */
1638 generate_exception_if(mode_64bit(), EXC_UD, -1);
1639 case 0x80: case 0x81: case 0x83: /* Grp1 */
1640 switch ( modrm_reg & 7 )
1642 case 0: goto add;
1643 case 1: goto or;
1644 case 2: goto adc;
1645 case 3: goto sbb;
1646 case 4: goto and;
1647 case 5: goto sub;
1648 case 6: goto xor;
1649 case 7: goto cmp;
1651 break;
1653 case 0xa8 ... 0xa9: /* test imm,%%eax */
1654 dst.reg = (unsigned long *)&_regs.eax;
1655 dst.val = _regs.eax;
1656 case 0x84 ... 0x85: test: /* test */
1657 emulate_2op_SrcV("test", src, dst, _regs.eflags);
1658 break;
1660 case 0x86 ... 0x87: xchg: /* xchg */
1661 /* Write back the register source. */
1662 switch ( dst.bytes )
1664 case 1: *(uint8_t *)src.reg = (uint8_t)dst.val; break;
1665 case 2: *(uint16_t *)src.reg = (uint16_t)dst.val; break;
1666 case 4: *src.reg = (uint32_t)dst.val; break; /* 64b reg: zero-extend */
1667 case 8: *src.reg = dst.val; break;
1669 /* Write back the memory destination with implicit LOCK prefix. */
1670 dst.val = src.val;
1671 lock_prefix = 1;
1672 break;
1674 case 0xc6 ... 0xc7: /* mov (sole member of Grp11) */
1675 generate_exception_if((modrm_reg & 7) != 0, EXC_UD, -1);
1676 case 0x88 ... 0x8b: /* mov */
1677 dst.val = src.val;
1678 break;
1680 case 0x8c: /* mov Sreg,r/m */ {
1681 struct segment_register reg;
1682 enum x86_segment seg = decode_segment(modrm_reg);
1683 generate_exception_if(seg == decode_segment_failed, EXC_UD, -1);
1684 fail_if(ops->read_segment == NULL);
1685 if ( (rc = ops->read_segment(seg, &reg, ctxt)) != 0 )
1686 goto done;
1687 dst.val = reg.sel;
1688 if ( dst.type == OP_MEM )
1689 dst.bytes = 2;
1690 break;
1693 case 0x8e: /* mov r/m,Sreg */ {
1694 enum x86_segment seg = decode_segment(modrm_reg);
1695 generate_exception_if(seg == decode_segment_failed, EXC_UD, -1);
1696 if ( (rc = load_seg(seg, (uint16_t)src.val, ctxt, ops)) != 0 )
1697 goto done;
1698 if ( seg == x86_seg_ss )
1699 ctxt->retire.flags.mov_ss = 1;
1700 dst.type = OP_NONE;
1701 break;
1704 case 0x8d: /* lea */
1705 dst.val = ea.mem.off;
1706 break;
1708 case 0x8f: /* pop (sole member of Grp1a) */
1709 generate_exception_if((modrm_reg & 7) != 0, EXC_UD, -1);
1710 /* 64-bit mode: POP defaults to a 64-bit operand. */
1711 if ( mode_64bit() && (dst.bytes == 4) )
1712 dst.bytes = 8;
1713 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(dst.bytes),
1714 &dst.val, dst.bytes, ctxt)) != 0 )
1715 goto done;
1716 break;
1718 case 0xb0 ... 0xb7: /* mov imm8,r8 */
1719 dst.reg = decode_register(
1720 (b & 7) | ((rex_prefix & 1) << 3), &_regs, (rex_prefix == 0));
1721 dst.val = src.val;
1722 break;
1724 case 0xb8 ... 0xbf: /* mov imm{16,32,64},r{16,32,64} */
1725 if ( dst.bytes == 8 ) /* Fetch more bytes to obtain imm64 */
1726 src.val = ((uint32_t)src.val |
1727 ((uint64_t)insn_fetch_type(uint32_t) << 32));
1728 dst.reg = decode_register(
1729 (b & 7) | ((rex_prefix & 1) << 3), &_regs, 0);
1730 dst.val = src.val;
1731 break;
1733 case 0xc0 ... 0xc1: grp2: /* Grp2 */
1734 switch ( modrm_reg & 7 )
1736 case 0: /* rol */
1737 emulate_2op_SrcB("rol", src, dst, _regs.eflags);
1738 break;
1739 case 1: /* ror */
1740 emulate_2op_SrcB("ror", src, dst, _regs.eflags);
1741 break;
1742 case 2: /* rcl */
1743 emulate_2op_SrcB("rcl", src, dst, _regs.eflags);
1744 break;
1745 case 3: /* rcr */
1746 emulate_2op_SrcB("rcr", src, dst, _regs.eflags);
1747 break;
1748 case 4: /* sal/shl */
1749 case 6: /* sal/shl */
1750 emulate_2op_SrcB("sal", src, dst, _regs.eflags);
1751 break;
1752 case 5: /* shr */
1753 emulate_2op_SrcB("shr", src, dst, _regs.eflags);
1754 break;
1755 case 7: /* sar */
1756 emulate_2op_SrcB("sar", src, dst, _regs.eflags);
1757 break;
1759 break;
1761 case 0xc4: /* les */ {
1762 unsigned long sel;
1763 dst.val = x86_seg_es;
1764 les: /* dst.val identifies the segment */
1765 generate_exception_if(src.type != OP_MEM, EXC_UD, -1);
1766 if ( (rc = ops->read(src.mem.seg, src.mem.off + src.bytes,
1767 &sel, 2, ctxt)) != 0 )
1768 goto done;
1769 if ( (rc = load_seg(dst.val, (uint16_t)sel, ctxt, ops)) != 0 )
1770 goto done;
1771 dst.val = src.val;
1772 break;
1775 case 0xc5: /* lds */
1776 dst.val = x86_seg_ds;
1777 goto les;
1779 case 0xd0 ... 0xd1: /* Grp2 */
1780 src.val = 1;
1781 goto grp2;
1783 case 0xd2 ... 0xd3: /* Grp2 */
1784 src.val = _regs.ecx;
1785 goto grp2;
1787 case 0xf6 ... 0xf7: /* Grp3 */
1788 switch ( modrm_reg & 7 )
1790 case 0 ... 1: /* test */
1791 /* Special case in Grp3: test has an immediate source operand. */
1792 src.type = OP_IMM;
1793 src.bytes = (d & ByteOp) ? 1 : op_bytes;
1794 if ( src.bytes == 8 ) src.bytes = 4;
1795 switch ( src.bytes )
1797 case 1: src.val = insn_fetch_type(int8_t); break;
1798 case 2: src.val = insn_fetch_type(int16_t); break;
1799 case 4: src.val = insn_fetch_type(int32_t); break;
1801 goto test;
1802 case 2: /* not */
1803 dst.val = ~dst.val;
1804 break;
1805 case 3: /* neg */
1806 emulate_1op("neg", dst, _regs.eflags);
1807 break;
1808 case 4: /* mul */
1809 src = dst;
1810 dst.type = OP_REG;
1811 dst.reg = (unsigned long *)&_regs.eax;
1812 dst.val = *dst.reg;
1813 _regs.eflags &= ~(EFLG_OF|EFLG_CF);
1814 switch ( src.bytes )
1816 case 1:
1817 dst.val = (uint8_t)dst.val;
1818 dst.val *= src.val;
1819 if ( (uint8_t)dst.val != (uint16_t)dst.val )
1820 _regs.eflags |= EFLG_OF|EFLG_CF;
1821 dst.bytes = 2;
1822 break;
1823 case 2:
1824 dst.val = (uint16_t)dst.val;
1825 dst.val *= src.val;
1826 if ( (uint16_t)dst.val != (uint32_t)dst.val )
1827 _regs.eflags |= EFLG_OF|EFLG_CF;
1828 *(uint16_t *)&_regs.edx = dst.val >> 16;
1829 break;
1830 #ifdef __x86_64__
1831 case 4:
1832 dst.val = (uint32_t)dst.val;
1833 dst.val *= src.val;
1834 if ( (uint32_t)dst.val != dst.val )
1835 _regs.eflags |= EFLG_OF|EFLG_CF;
1836 _regs.edx = (uint32_t)(dst.val >> 32);
1837 break;
1838 #endif
1839 default: {
1840 unsigned long m[2] = { src.val, dst.val };
1841 if ( mul_dbl(m) )
1842 _regs.eflags |= EFLG_OF|EFLG_CF;
1843 _regs.edx = m[1];
1844 dst.val = m[0];
1845 break;
1848 break;
1849 case 5: /* imul */
1850 src = dst;
1851 dst.type = OP_REG;
1852 dst.reg = (unsigned long *)&_regs.eax;
1853 dst.val = *dst.reg;
1854 _regs.eflags &= ~(EFLG_OF|EFLG_CF);
1855 switch ( src.bytes )
1857 case 1:
1858 dst.val = ((uint16_t)(int8_t)src.val *
1859 (uint16_t)(int8_t)dst.val);
1860 if ( (int8_t)dst.val != (uint16_t)dst.val )
1861 _regs.eflags |= EFLG_OF|EFLG_CF;
1862 dst.bytes = 2;
1863 break;
1864 case 2:
1865 dst.val = ((uint32_t)(int16_t)src.val *
1866 (uint32_t)(int16_t)dst.val);
1867 if ( (int16_t)dst.val != (uint32_t)dst.val )
1868 _regs.eflags |= EFLG_OF|EFLG_CF;
1869 *(uint16_t *)&_regs.edx = dst.val >> 16;
1870 break;
1871 #ifdef __x86_64__
1872 case 4:
1873 dst.val = ((uint64_t)(int32_t)src.val *
1874 (uint64_t)(int32_t)dst.val);
1875 if ( (int32_t)dst.val != dst.val )
1876 _regs.eflags |= EFLG_OF|EFLG_CF;
1877 _regs.edx = (uint32_t)(dst.val >> 32);
1878 break;
1879 #endif
1880 default: {
1881 unsigned long m[2] = { src.val, dst.val };
1882 if ( imul_dbl(m) )
1883 _regs.eflags |= EFLG_OF|EFLG_CF;
1884 _regs.edx = m[1];
1885 dst.val = m[0];
1886 break;
1889 break;
1890 case 6: /* div */ {
1891 unsigned long u[2], v;
1892 src = dst;
1893 dst.type = OP_REG;
1894 dst.reg = (unsigned long *)&_regs.eax;
1895 switch ( src.bytes )
1897 case 1:
1898 u[0] = (uint16_t)_regs.eax;
1899 u[1] = 0;
1900 v = (uint8_t)src.val;
1901 generate_exception_if(
1902 div_dbl(u, v) || ((uint8_t)u[0] != (uint16_t)u[0]),
1903 EXC_DE, -1);
1904 dst.val = (uint8_t)u[0];
1905 ((uint8_t *)&_regs.eax)[1] = u[1];
1906 break;
1907 case 2:
1908 u[0] = ((uint32_t)_regs.edx << 16) | (uint16_t)_regs.eax;
1909 u[1] = 0;
1910 v = (uint16_t)src.val;
1911 generate_exception_if(
1912 div_dbl(u, v) || ((uint16_t)u[0] != (uint32_t)u[0]),
1913 EXC_DE, -1);
1914 dst.val = (uint16_t)u[0];
1915 *(uint16_t *)&_regs.edx = u[1];
1916 break;
1917 #ifdef __x86_64__
1918 case 4:
1919 u[0] = (_regs.edx << 32) | (uint32_t)_regs.eax;
1920 u[1] = 0;
1921 v = (uint32_t)src.val;
1922 generate_exception_if(
1923 div_dbl(u, v) || ((uint32_t)u[0] != u[0]),
1924 EXC_DE, -1);
1925 dst.val = (uint32_t)u[0];
1926 _regs.edx = (uint32_t)u[1];
1927 break;
1928 #endif
1929 default:
1930 u[0] = _regs.eax;
1931 u[1] = _regs.edx;
1932 v = src.val;
1933 generate_exception_if(div_dbl(u, v), EXC_DE, -1);
1934 dst.val = u[0];
1935 _regs.edx = u[1];
1936 break;
1938 break;
1940 case 7: /* idiv */ {
1941 unsigned long u[2], v;
1942 src = dst;
1943 dst.type = OP_REG;
1944 dst.reg = (unsigned long *)&_regs.eax;
1945 switch ( src.bytes )
1947 case 1:
1948 u[0] = (int16_t)_regs.eax;
1949 u[1] = ((long)u[0] < 0) ? ~0UL : 0UL;
1950 v = (int8_t)src.val;
1951 generate_exception_if(
1952 idiv_dbl(u, v) || ((int8_t)u[0] != (int16_t)u[0]),
1953 EXC_DE, -1);
1954 dst.val = (int8_t)u[0];
1955 ((int8_t *)&_regs.eax)[1] = u[1];
1956 break;
1957 case 2:
1958 u[0] = (int32_t)((_regs.edx << 16) | (uint16_t)_regs.eax);
1959 u[1] = ((long)u[0] < 0) ? ~0UL : 0UL;
1960 v = (int16_t)src.val;
1961 generate_exception_if(
1962 idiv_dbl(u, v) || ((int16_t)u[0] != (int32_t)u[0]),
1963 EXC_DE, -1);
1964 dst.val = (int16_t)u[0];
1965 *(int16_t *)&_regs.edx = u[1];
1966 break;
1967 #ifdef __x86_64__
1968 case 4:
1969 u[0] = (_regs.edx << 32) | (uint32_t)_regs.eax;
1970 u[1] = ((long)u[0] < 0) ? ~0UL : 0UL;
1971 v = (int32_t)src.val;
1972 generate_exception_if(
1973 idiv_dbl(u, v) || ((int32_t)u[0] != u[0]),
1974 EXC_DE, -1);
1975 dst.val = (int32_t)u[0];
1976 _regs.edx = (uint32_t)u[1];
1977 break;
1978 #endif
1979 default:
1980 u[0] = _regs.eax;
1981 u[1] = _regs.edx;
1982 v = src.val;
1983 generate_exception_if(idiv_dbl(u, v), EXC_DE, -1);
1984 dst.val = u[0];
1985 _regs.edx = u[1];
1986 break;
1988 break;
1990 default:
1991 goto cannot_emulate;
1993 break;
1995 case 0xfe: /* Grp4 */
1996 generate_exception_if((modrm_reg & 7) >= 2, EXC_UD, -1);
1997 case 0xff: /* Grp5 */
1998 switch ( modrm_reg & 7 )
2000 case 0: /* inc */
2001 emulate_1op("inc", dst, _regs.eflags);
2002 break;
2003 case 1: /* dec */
2004 emulate_1op("dec", dst, _regs.eflags);
2005 break;
2006 case 2: /* call (near) */
2007 case 4: /* jmp (near) */
2008 if ( (dst.bytes != 8) && mode_64bit() )
2010 dst.bytes = op_bytes = 8;
2011 if ( dst.type == OP_REG )
2012 dst.val = *dst.reg;
2013 else if ( (rc = ops->read(dst.mem.seg, dst.mem.off,
2014 &dst.val, 8, ctxt)) != 0 )
2015 goto done;
2017 src.val = _regs.eip;
2018 _regs.eip = dst.val;
2019 if ( (modrm_reg & 7) == 2 )
2020 goto push; /* call */
2021 dst.type = OP_NONE;
2022 break;
2023 case 3: /* call (far, absolute indirect) */
2024 case 5: /* jmp (far, absolute indirect) */ {
2025 unsigned long sel;
2027 generate_exception_if(dst.type != OP_MEM, EXC_UD, -1);
2029 if ( (rc = ops->read(dst.mem.seg, dst.mem.off+dst.bytes,
2030 &sel, 2, ctxt)) )
2031 goto done;
2033 if ( (modrm_reg & 7) == 3 ) /* call */
2035 struct segment_register reg;
2036 fail_if(ops->read_segment == NULL);
2037 if ( (rc = ops->read_segment(x86_seg_cs, &reg, ctxt)) ||
2038 (rc = ops->write(x86_seg_ss, sp_pre_dec(op_bytes),
2039 reg.sel, op_bytes, ctxt)) ||
2040 (rc = ops->write(x86_seg_ss, sp_pre_dec(op_bytes),
2041 _regs.eip, op_bytes, ctxt)) )
2042 goto done;
2045 if ( (rc = load_seg(x86_seg_cs, sel, ctxt, ops)) != 0 )
2046 goto done;
2047 _regs.eip = dst.val;
2049 dst.type = OP_NONE;
2050 break;
2052 case 6: /* push */
2053 /* 64-bit mode: PUSH defaults to a 64-bit operand. */
2054 if ( mode_64bit() && (dst.bytes == 4) )
2056 dst.bytes = 8;
2057 if ( dst.type == OP_REG )
2058 dst.val = *dst.reg;
2059 else if ( (rc = ops->read(dst.mem.seg, dst.mem.off,
2060 &dst.val, 8, ctxt)) != 0 )
2061 goto done;
2063 if ( (rc = ops->write(x86_seg_ss, sp_pre_dec(dst.bytes),
2064 dst.val, dst.bytes, ctxt)) != 0 )
2065 goto done;
2066 dst.type = OP_NONE;
2067 break;
2068 case 7:
2069 generate_exception_if(1, EXC_UD, -1);
2070 default:
2071 goto cannot_emulate;
2073 break;
2076 writeback:
2077 switch ( dst.type )
2079 case OP_REG:
2080 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
2081 switch ( dst.bytes )
2083 case 1: *(uint8_t *)dst.reg = (uint8_t)dst.val; break;
2084 case 2: *(uint16_t *)dst.reg = (uint16_t)dst.val; break;
2085 case 4: *dst.reg = (uint32_t)dst.val; break; /* 64b: zero-ext */
2086 case 8: *dst.reg = dst.val; break;
2088 break;
2089 case OP_MEM:
2090 if ( !(d & Mov) && (dst.orig_val == dst.val) &&
2091 !ctxt->force_writeback )
2092 /* nothing to do */;
2093 else if ( lock_prefix )
2094 rc = ops->cmpxchg(
2095 dst.mem.seg, dst.mem.off, dst.orig_val,
2096 dst.val, dst.bytes, ctxt);
2097 else
2098 rc = ops->write(
2099 dst.mem.seg, dst.mem.off, dst.val, dst.bytes, ctxt);
2100 if ( rc != 0 )
2101 goto done;
2102 default:
2103 break;
2106 /* Commit shadow register state. */
2107 _regs.eflags &= ~EFLG_RF;
2108 *ctxt->regs = _regs;
2109 if ( (_regs.eflags & EFLG_TF) && (rc == X86EMUL_OKAY) &&
2110 (ops->inject_hw_exception != NULL) )
2111 rc = ops->inject_hw_exception(EXC_DB, -1, ctxt) ? : X86EMUL_EXCEPTION;
2113 done:
2114 return rc;
2116 special_insn:
2117 dst.type = OP_NONE;
2119 /*
2120 * The only implicit-operands instructions allowed a LOCK prefix are
2121 * CMPXCHG{8,16}B, MOV CRn, MOV DRn.
2122 */
2123 generate_exception_if(lock_prefix &&
2124 ((b < 0x20) || (b > 0x23)) && /* MOV CRn/DRn */
2125 (b != 0xc7), /* CMPXCHG{8,16}B */
2126 EXC_GP, 0);
2128 if ( twobyte )
2129 goto twobyte_special_insn;
2131 switch ( b )
2133 case 0x06: /* push %%es */ {
2134 struct segment_register reg;
2135 src.val = x86_seg_es;
2136 push_seg:
2137 fail_if(ops->read_segment == NULL);
2138 if ( (rc = ops->read_segment(src.val, &reg, ctxt)) != 0 )
2139 return rc;
2140 /* 64-bit mode: PUSH defaults to a 64-bit operand. */
2141 if ( mode_64bit() && (op_bytes == 4) )
2142 op_bytes = 8;
2143 if ( (rc = ops->write(x86_seg_ss, sp_pre_dec(op_bytes),
2144 reg.sel, op_bytes, ctxt)) != 0 )
2145 goto done;
2146 break;
2149 case 0x07: /* pop %%es */
2150 src.val = x86_seg_es;
2151 pop_seg:
2152 fail_if(ops->write_segment == NULL);
2153 /* 64-bit mode: POP defaults to a 64-bit operand. */
2154 if ( mode_64bit() && (op_bytes == 4) )
2155 op_bytes = 8;
2156 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes),
2157 &dst.val, op_bytes, ctxt)) != 0 )
2158 goto done;
2159 if ( (rc = load_seg(src.val, (uint16_t)dst.val, ctxt, ops)) != 0 )
2160 return rc;
2161 break;
2163 case 0x0e: /* push %%cs */
2164 src.val = x86_seg_cs;
2165 goto push_seg;
2167 case 0x16: /* push %%ss */
2168 src.val = x86_seg_ss;
2169 goto push_seg;
2171 case 0x17: /* pop %%ss */
2172 src.val = x86_seg_ss;
2173 ctxt->retire.flags.mov_ss = 1;
2174 goto pop_seg;
2176 case 0x1e: /* push %%ds */
2177 src.val = x86_seg_ds;
2178 goto push_seg;
2180 case 0x1f: /* pop %%ds */
2181 src.val = x86_seg_ds;
2182 goto pop_seg;
2184 case 0x27: /* daa */ {
2185 uint8_t al = _regs.eax;
2186 unsigned long eflags = _regs.eflags;
2187 generate_exception_if(mode_64bit(), EXC_UD, -1);
2188 _regs.eflags &= ~(EFLG_CF|EFLG_AF);
2189 if ( ((al & 0x0f) > 9) || (eflags & EFLG_AF) )
2191 *(uint8_t *)&_regs.eax += 6;
2192 _regs.eflags |= EFLG_AF;
2194 if ( (al > 0x99) || (eflags & EFLG_CF) )
2196 *(uint8_t *)&_regs.eax += 0x60;
2197 _regs.eflags |= EFLG_CF;
2199 _regs.eflags &= ~(EFLG_SF|EFLG_ZF|EFLG_PF);
2200 _regs.eflags |= ((uint8_t)_regs.eax == 0) ? EFLG_ZF : 0;
2201 _regs.eflags |= (( int8_t)_regs.eax < 0) ? EFLG_SF : 0;
2202 _regs.eflags |= even_parity(_regs.eax) ? EFLG_PF : 0;
2203 break;
2206 case 0x2f: /* das */ {
2207 uint8_t al = _regs.eax;
2208 unsigned long eflags = _regs.eflags;
2209 generate_exception_if(mode_64bit(), EXC_UD, -1);
2210 _regs.eflags &= ~(EFLG_CF|EFLG_AF);
2211 if ( ((al & 0x0f) > 9) || (eflags & EFLG_AF) )
2213 _regs.eflags |= EFLG_AF;
2214 if ( (al < 6) || (eflags & EFLG_CF) )
2215 _regs.eflags |= EFLG_CF;
2216 *(uint8_t *)&_regs.eax -= 6;
2218 if ( (al > 0x99) || (eflags & EFLG_CF) )
2220 *(uint8_t *)&_regs.eax -= 0x60;
2221 _regs.eflags |= EFLG_CF;
2223 _regs.eflags &= ~(EFLG_SF|EFLG_ZF|EFLG_PF);
2224 _regs.eflags |= ((uint8_t)_regs.eax == 0) ? EFLG_ZF : 0;
2225 _regs.eflags |= (( int8_t)_regs.eax < 0) ? EFLG_SF : 0;
2226 _regs.eflags |= even_parity(_regs.eax) ? EFLG_PF : 0;
2227 break;
2230 case 0x37: /* aaa */
2231 case 0x3f: /* aas */
2232 generate_exception_if(mode_64bit(), EXC_UD, -1);
2233 _regs.eflags &= ~EFLG_CF;
2234 if ( ((uint8_t)_regs.eax > 9) || (_regs.eflags & EFLG_AF) )
2236 ((uint8_t *)&_regs.eax)[0] += (b == 0x37) ? 6 : -6;
2237 ((uint8_t *)&_regs.eax)[1] += (b == 0x37) ? 1 : -1;
2238 _regs.eflags |= EFLG_CF | EFLG_AF;
2240 ((uint8_t *)&_regs.eax)[0] &= 0x0f;
2241 break;
2243 case 0x40 ... 0x4f: /* inc/dec reg */
2244 dst.type = OP_REG;
2245 dst.reg = decode_register(b & 7, &_regs, 0);
2246 dst.bytes = op_bytes;
2247 dst.val = *dst.reg;
2248 if ( b & 8 )
2249 emulate_1op("dec", dst, _regs.eflags);
2250 else
2251 emulate_1op("inc", dst, _regs.eflags);
2252 break;
2254 case 0x50 ... 0x57: /* push reg */
2255 src.val = *(unsigned long *)decode_register(
2256 (b & 7) | ((rex_prefix & 1) << 3), &_regs, 0);
2257 goto push;
2259 case 0x58 ... 0x5f: /* pop reg */
2260 dst.type = OP_REG;
2261 dst.reg = decode_register(
2262 (b & 7) | ((rex_prefix & 1) << 3), &_regs, 0);
2263 dst.bytes = op_bytes;
2264 if ( mode_64bit() && (dst.bytes == 4) )
2265 dst.bytes = 8;
2266 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(dst.bytes),
2267 &dst.val, dst.bytes, ctxt)) != 0 )
2268 goto done;
2269 break;
2271 case 0x60: /* pusha */ {
2272 int i;
2273 unsigned long regs[] = {
2274 _regs.eax, _regs.ecx, _regs.edx, _regs.ebx,
2275 _regs.esp, _regs.ebp, _regs.esi, _regs.edi };
2276 generate_exception_if(mode_64bit(), EXC_UD, -1);
2277 for ( i = 0; i < 8; i++ )
2278 if ( (rc = ops->write(x86_seg_ss, sp_pre_dec(op_bytes),
2279 regs[i], op_bytes, ctxt)) != 0 )
2280 goto done;
2281 break;
2284 case 0x61: /* popa */ {
2285 int i;
2286 unsigned long dummy_esp, *regs[] = {
2287 (unsigned long *)&_regs.edi, (unsigned long *)&_regs.esi,
2288 (unsigned long *)&_regs.ebp, (unsigned long *)&dummy_esp,
2289 (unsigned long *)&_regs.ebx, (unsigned long *)&_regs.edx,
2290 (unsigned long *)&_regs.ecx, (unsigned long *)&_regs.eax };
2291 generate_exception_if(mode_64bit(), EXC_UD, -1);
2292 for ( i = 0; i < 8; i++ )
2294 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes),
2295 &dst.val, op_bytes, ctxt)) != 0 )
2296 goto done;
2297 switch ( op_bytes )
2299 case 1: *(uint8_t *)regs[i] = (uint8_t)dst.val; break;
2300 case 2: *(uint16_t *)regs[i] = (uint16_t)dst.val; break;
2301 case 4: *regs[i] = (uint32_t)dst.val; break; /* 64b: zero-ext */
2302 case 8: *regs[i] = dst.val; break;
2305 break;
2308 case 0x68: /* push imm{16,32,64} */
2309 src.val = ((op_bytes == 2)
2310 ? (int32_t)insn_fetch_type(int16_t)
2311 : insn_fetch_type(int32_t));
2312 goto push;
2314 case 0x6a: /* push imm8 */
2315 src.val = insn_fetch_type(int8_t);
2316 push:
2317 d |= Mov; /* force writeback */
2318 dst.type = OP_MEM;
2319 dst.bytes = op_bytes;
2320 if ( mode_64bit() && (dst.bytes == 4) )
2321 dst.bytes = 8;
2322 dst.val = src.val;
2323 dst.mem.seg = x86_seg_ss;
2324 dst.mem.off = sp_pre_dec(dst.bytes);
2325 break;
2327 case 0x6c ... 0x6d: /* ins %dx,%es:%edi */ {
2328 unsigned long nr_reps = get_rep_prefix();
2329 unsigned int port = (uint16_t)_regs.edx;
2330 dst.bytes = !(b & 1) ? 1 : (op_bytes == 8) ? 4 : op_bytes;
2331 dst.mem.seg = x86_seg_es;
2332 dst.mem.off = truncate_ea(_regs.edi);
2333 if ( (rc = ioport_access_check(port, dst.bytes, ctxt, ops)) != 0 )
2334 goto done;
2335 if ( (nr_reps > 1) && (ops->rep_ins != NULL) &&
2336 ((rc = ops->rep_ins(port, dst.mem.seg, dst.mem.off, dst.bytes,
2337 &nr_reps, ctxt)) != X86EMUL_UNHANDLEABLE) )
2339 if ( rc != 0 )
2340 goto done;
2342 else
2344 fail_if(ops->read_io == NULL);
2345 if ( (rc = ops->read_io(port, dst.bytes, &dst.val, ctxt)) != 0 )
2346 goto done;
2347 dst.type = OP_MEM;
2348 nr_reps = 1;
2350 register_address_increment(
2351 _regs.edi,
2352 nr_reps * ((_regs.eflags & EFLG_DF) ? -dst.bytes : dst.bytes));
2353 put_rep_prefix(nr_reps);
2354 break;
2357 case 0x6e ... 0x6f: /* outs %esi,%dx */ {
2358 unsigned long nr_reps = get_rep_prefix();
2359 unsigned int port = (uint16_t)_regs.edx;
2360 dst.bytes = !(b & 1) ? 1 : (op_bytes == 8) ? 4 : op_bytes;
2361 if ( (rc = ioport_access_check(port, dst.bytes, ctxt, ops)) != 0 )
2362 goto done;
2363 if ( (nr_reps > 1) && (ops->rep_outs != NULL) &&
2364 ((rc = ops->rep_outs(ea.mem.seg, truncate_ea(_regs.esi),
2365 port, dst.bytes,
2366 &nr_reps, ctxt)) != X86EMUL_UNHANDLEABLE) )
2368 if ( rc != 0 )
2369 goto done;
2371 else
2373 if ( (rc = ops->read(ea.mem.seg, truncate_ea(_regs.esi),
2374 &dst.val, dst.bytes, ctxt)) != 0 )
2375 goto done;
2376 fail_if(ops->write_io == NULL);
2377 if ( (rc = ops->write_io(port, dst.bytes, dst.val, ctxt)) != 0 )
2378 goto done;
2379 nr_reps = 1;
2381 register_address_increment(
2382 _regs.esi,
2383 nr_reps * ((_regs.eflags & EFLG_DF) ? -dst.bytes : dst.bytes));
2384 put_rep_prefix(nr_reps);
2385 break;
2388 case 0x70 ... 0x7f: /* jcc (short) */ {
2389 int rel = insn_fetch_type(int8_t);
2390 if ( test_cc(b, _regs.eflags) )
2391 jmp_rel(rel);
2392 break;
2395 case 0x90: /* nop / xchg %%r8,%%rax */
2396 if ( !(rex_prefix & 1) )
2397 break; /* nop */
2399 case 0x91 ... 0x97: /* xchg reg,%%rax */
2400 src.type = dst.type = OP_REG;
2401 src.bytes = dst.bytes = op_bytes;
2402 src.reg = (unsigned long *)&_regs.eax;
2403 src.val = *src.reg;
2404 dst.reg = decode_register(
2405 (b & 7) | ((rex_prefix & 1) << 3), &_regs, 0);
2406 dst.val = *dst.reg;
2407 goto xchg;
2409 case 0x98: /* cbw/cwde/cdqe */
2410 switch ( op_bytes )
2412 case 2: *(int16_t *)&_regs.eax = (int8_t)_regs.eax; break; /* cbw */
2413 case 4: _regs.eax = (uint32_t)(int16_t)_regs.eax; break; /* cwde */
2414 case 8: _regs.eax = (int32_t)_regs.eax; break; /* cdqe */
2416 break;
2418 case 0x99: /* cwd/cdq/cqo */
2419 switch ( op_bytes )
2421 case 2:
2422 *(int16_t *)&_regs.edx = ((int16_t)_regs.eax < 0) ? -1 : 0;
2423 break;
2424 case 4:
2425 _regs.edx = (uint32_t)(((int32_t)_regs.eax < 0) ? -1 : 0);
2426 break;
2427 case 8:
2428 _regs.edx = (_regs.eax < 0) ? -1 : 0;
2429 break;
2431 break;
2433 case 0x9a: /* call (far, absolute) */ {
2434 struct segment_register reg;
2435 uint16_t sel;
2436 uint32_t eip;
2438 fail_if(ops->read_segment == NULL);
2439 generate_exception_if(mode_64bit(), EXC_UD, -1);
2441 eip = insn_fetch_bytes(op_bytes);
2442 sel = insn_fetch_type(uint16_t);
2444 if ( (rc = ops->read_segment(x86_seg_cs, &reg, ctxt)) ||
2445 (rc = ops->write(x86_seg_ss, sp_pre_dec(op_bytes),
2446 reg.sel, op_bytes, ctxt)) ||
2447 (rc = ops->write(x86_seg_ss, sp_pre_dec(op_bytes),
2448 _regs.eip, op_bytes, ctxt)) )
2449 goto done;
2451 if ( (rc = load_seg(x86_seg_cs, sel, ctxt, ops)) != 0 )
2452 goto done;
2453 _regs.eip = eip;
2454 break;
2457 case 0x9b: /* wait/fwait */
2458 emulate_fpu_insn("fwait");
2459 break;
2461 case 0x9c: /* pushf */
2462 src.val = _regs.eflags;
2463 goto push;
2465 case 0x9d: /* popf */ {
2466 uint32_t mask = EFLG_VIP | EFLG_VIF | EFLG_VM;
2467 if ( !mode_ring0() )
2468 mask |= EFLG_IOPL;
2469 if ( !mode_iopl() )
2470 mask |= EFLG_IF;
2471 /* 64-bit mode: POP defaults to a 64-bit operand. */
2472 if ( mode_64bit() && (op_bytes == 4) )
2473 op_bytes = 8;
2474 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes),
2475 &dst.val, op_bytes, ctxt)) != 0 )
2476 goto done;
2477 if ( op_bytes == 2 )
2478 dst.val = (uint16_t)dst.val | (_regs.eflags & 0xffff0000u);
2479 dst.val &= 0x257fd5;
2480 _regs.eflags &= mask;
2481 _regs.eflags |= (uint32_t)(dst.val & ~mask) | 0x02;
2482 break;
2485 case 0x9e: /* sahf */
2486 *(uint8_t *)&_regs.eflags = (((uint8_t *)&_regs.eax)[1] & 0xd7) | 0x02;
2487 break;
2489 case 0x9f: /* lahf */
2490 ((uint8_t *)&_regs.eax)[1] = (_regs.eflags & 0xd7) | 0x02;
2491 break;
2493 case 0xa0 ... 0xa1: /* mov mem.offs,{%al,%ax,%eax,%rax} */
2494 /* Source EA is not encoded via ModRM. */
2495 dst.type = OP_REG;
2496 dst.reg = (unsigned long *)&_regs.eax;
2497 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
2498 if ( (rc = ops->read(ea.mem.seg, insn_fetch_bytes(ad_bytes),
2499 &dst.val, dst.bytes, ctxt)) != 0 )
2500 goto done;
2501 break;
2503 case 0xa2 ... 0xa3: /* mov {%al,%ax,%eax,%rax},mem.offs */
2504 /* Destination EA is not encoded via ModRM. */
2505 dst.type = OP_MEM;
2506 dst.mem.seg = ea.mem.seg;
2507 dst.mem.off = insn_fetch_bytes(ad_bytes);
2508 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
2509 dst.val = (unsigned long)_regs.eax;
2510 break;
2512 case 0xa4 ... 0xa5: /* movs */ {
2513 unsigned long nr_reps = get_rep_prefix();
2514 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
2515 dst.mem.seg = x86_seg_es;
2516 dst.mem.off = truncate_ea(_regs.edi);
2517 if ( (nr_reps > 1) && (ops->rep_movs != NULL) &&
2518 ((rc = ops->rep_movs(ea.mem.seg, truncate_ea(_regs.esi),
2519 dst.mem.seg, dst.mem.off, dst.bytes,
2520 &nr_reps, ctxt)) != X86EMUL_UNHANDLEABLE) )
2522 if ( rc != 0 )
2523 goto done;
2525 else
2527 if ( (rc = ops->read(ea.mem.seg, truncate_ea(_regs.esi),
2528 &dst.val, dst.bytes, ctxt)) != 0 )
2529 goto done;
2530 dst.type = OP_MEM;
2531 nr_reps = 1;
2533 register_address_increment(
2534 _regs.esi,
2535 nr_reps * ((_regs.eflags & EFLG_DF) ? -dst.bytes : dst.bytes));
2536 register_address_increment(
2537 _regs.edi,
2538 nr_reps * ((_regs.eflags & EFLG_DF) ? -dst.bytes : dst.bytes));
2539 put_rep_prefix(nr_reps);
2540 break;
2543 case 0xa6 ... 0xa7: /* cmps */ {
2544 unsigned long next_eip = _regs.eip;
2545 get_rep_prefix();
2546 src.bytes = dst.bytes = (d & ByteOp) ? 1 : op_bytes;
2547 if ( (rc = ops->read(ea.mem.seg, truncate_ea(_regs.esi),
2548 &dst.val, dst.bytes, ctxt)) ||
2549 (rc = ops->read(x86_seg_es, truncate_ea(_regs.edi),
2550 &src.val, src.bytes, ctxt)) )
2551 goto done;
2552 register_address_increment(
2553 _regs.esi, (_regs.eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
2554 register_address_increment(
2555 _regs.edi, (_regs.eflags & EFLG_DF) ? -src.bytes : src.bytes);
2556 put_rep_prefix(1);
2557 /* cmp: dst - src ==> src=*%%edi,dst=*%%esi ==> *%%esi - *%%edi */
2558 emulate_2op_SrcV("cmp", src, dst, _regs.eflags);
2559 if ( ((rep_prefix == REPE_PREFIX) && !(_regs.eflags & EFLG_ZF)) ||
2560 ((rep_prefix == REPNE_PREFIX) && (_regs.eflags & EFLG_ZF)) )
2561 _regs.eip = next_eip;
2562 break;
2565 case 0xaa ... 0xab: /* stos */ {
2566 /* unsigned long max_reps = */get_rep_prefix();
2567 dst.type = OP_MEM;
2568 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
2569 dst.mem.seg = x86_seg_es;
2570 dst.mem.off = truncate_ea(_regs.edi);
2571 dst.val = _regs.eax;
2572 register_address_increment(
2573 _regs.edi, (_regs.eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
2574 put_rep_prefix(1);
2575 break;
2578 case 0xac ... 0xad: /* lods */ {
2579 /* unsigned long max_reps = */get_rep_prefix();
2580 dst.type = OP_REG;
2581 dst.bytes = (d & ByteOp) ? 1 : op_bytes;
2582 dst.reg = (unsigned long *)&_regs.eax;
2583 if ( (rc = ops->read(ea.mem.seg, truncate_ea(_regs.esi),
2584 &dst.val, dst.bytes, ctxt)) != 0 )
2585 goto done;
2586 register_address_increment(
2587 _regs.esi, (_regs.eflags & EFLG_DF) ? -dst.bytes : dst.bytes);
2588 put_rep_prefix(1);
2589 break;
2592 case 0xae ... 0xaf: /* scas */ {
2593 unsigned long next_eip = _regs.eip;
2594 get_rep_prefix();
2595 src.bytes = dst.bytes = (d & ByteOp) ? 1 : op_bytes;
2596 dst.val = _regs.eax;
2597 if ( (rc = ops->read(x86_seg_es, truncate_ea(_regs.edi),
2598 &src.val, src.bytes, ctxt)) != 0 )
2599 goto done;
2600 register_address_increment(
2601 _regs.edi, (_regs.eflags & EFLG_DF) ? -src.bytes : src.bytes);
2602 put_rep_prefix(1);
2603 /* cmp: dst - src ==> src=*%%edi,dst=%%eax ==> %%eax - *%%edi */
2604 emulate_2op_SrcV("cmp", src, dst, _regs.eflags);
2605 if ( ((rep_prefix == REPE_PREFIX) && !(_regs.eflags & EFLG_ZF)) ||
2606 ((rep_prefix == REPNE_PREFIX) && (_regs.eflags & EFLG_ZF)) )
2607 _regs.eip = next_eip;
2608 break;
2611 case 0xc2: /* ret imm16 (near) */
2612 case 0xc3: /* ret (near) */ {
2613 int offset = (b == 0xc2) ? insn_fetch_type(uint16_t) : 0;
2614 op_bytes = mode_64bit() ? 8 : op_bytes;
2615 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes + offset),
2616 &dst.val, op_bytes, ctxt)) != 0 )
2617 goto done;
2618 _regs.eip = dst.val;
2619 break;
2622 case 0xc8: /* enter imm16,imm8 */ {
2623 uint16_t size = insn_fetch_type(uint16_t);
2624 uint8_t depth = insn_fetch_type(uint8_t) & 31;
2625 int i;
2627 dst.type = OP_REG;
2628 dst.bytes = (mode_64bit() && (op_bytes == 4)) ? 8 : op_bytes;
2629 dst.reg = (unsigned long *)&_regs.ebp;
2630 if ( (rc = ops->write(x86_seg_ss, sp_pre_dec(dst.bytes),
2631 _regs.ebp, dst.bytes, ctxt)) )
2632 goto done;
2633 dst.val = _regs.esp;
2635 if ( depth > 0 )
2637 for ( i = 1; i < depth; i++ )
2639 unsigned long ebp, temp_data;
2640 ebp = truncate_word(_regs.ebp - i*dst.bytes, ctxt->sp_size/8);
2641 if ( (rc = ops->read(x86_seg_ss, ebp,
2642 &temp_data, dst.bytes, ctxt)) ||
2643 (rc = ops->write(x86_seg_ss, sp_pre_dec(dst.bytes),
2644 temp_data, dst.bytes, ctxt)) )
2645 goto done;
2647 if ( (rc = ops->write(x86_seg_ss, sp_pre_dec(dst.bytes),
2648 dst.val, dst.bytes, ctxt)) )
2649 goto done;
2652 sp_pre_dec(size);
2653 break;
2656 case 0xc9: /* leave */
2657 /* First writeback, to %%esp. */
2658 dst.type = OP_REG;
2659 dst.bytes = (mode_64bit() && (op_bytes == 4)) ? 8 : op_bytes;
2660 dst.reg = (unsigned long *)&_regs.esp;
2661 dst.val = _regs.ebp;
2663 /* Flush first writeback, since there is a second. */
2664 switch ( dst.bytes )
2666 case 1: *(uint8_t *)dst.reg = (uint8_t)dst.val; break;
2667 case 2: *(uint16_t *)dst.reg = (uint16_t)dst.val; break;
2668 case 4: *dst.reg = (uint32_t)dst.val; break; /* 64b: zero-ext */
2669 case 8: *dst.reg = dst.val; break;
2672 /* Second writeback, to %%ebp. */
2673 dst.reg = (unsigned long *)&_regs.ebp;
2674 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(dst.bytes),
2675 &dst.val, dst.bytes, ctxt)) )
2676 goto done;
2677 break;
2679 case 0xca: /* ret imm16 (far) */
2680 case 0xcb: /* ret (far) */ {
2681 int offset = (b == 0xca) ? insn_fetch_type(uint16_t) : 0;
2682 op_bytes = mode_64bit() ? 8 : op_bytes;
2683 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes),
2684 &dst.val, op_bytes, ctxt)) ||
2685 (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes + offset),
2686 &src.val, op_bytes, ctxt)) ||
2687 (rc = load_seg(x86_seg_cs, (uint16_t)src.val, ctxt, ops)) )
2688 goto done;
2689 _regs.eip = dst.val;
2690 break;
2693 case 0xcc: /* int3 */
2694 src.val = EXC_BP;
2695 goto swint;
2697 case 0xcd: /* int imm8 */
2698 src.val = insn_fetch_type(uint8_t);
2699 swint:
2700 fail_if(ops->inject_sw_interrupt == NULL);
2701 rc = ops->inject_sw_interrupt(src.val, _regs.eip - ctxt->regs->eip,
2702 ctxt) ? : X86EMUL_EXCEPTION;
2703 goto done;
2705 case 0xce: /* into */
2706 generate_exception_if(mode_64bit(), EXC_UD, -1);
2707 if ( !(_regs.eflags & EFLG_OF) )
2708 break;
2709 src.val = EXC_OF;
2710 goto swint;
2712 case 0xcf: /* iret */ {
2713 unsigned long cs, eip, eflags;
2714 uint32_t mask = EFLG_VIP | EFLG_VIF | EFLG_VM;
2715 if ( !mode_ring0() )
2716 mask |= EFLG_IOPL;
2717 if ( !mode_iopl() )
2718 mask |= EFLG_IF;
2719 fail_if(!in_realmode(ctxt, ops));
2720 if ( (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes),
2721 &eip, op_bytes, ctxt)) ||
2722 (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes),
2723 &cs, op_bytes, ctxt)) ||
2724 (rc = ops->read(x86_seg_ss, sp_post_inc(op_bytes),
2725 &eflags, op_bytes, ctxt)) )
2726 goto done;
2727 if ( op_bytes == 2 )
2728 eflags = (uint16_t)eflags | (_regs.eflags & 0xffff0000u);
2729 eflags &= 0x257fd5;
2730 _regs.eflags &= mask;
2731 _regs.eflags |= (uint32_t)(eflags & ~mask) | 0x02;
2732 _regs.eip = eip;
2733 if ( (rc = load_seg(x86_seg_cs, (uint16_t)cs, ctxt, ops)) != 0 )
2734 goto done;
2735 break;
2738 case 0xd4: /* aam */ {
2739 unsigned int base = insn_fetch_type(uint8_t);
2740 uint8_t al = _regs.eax;
2741 generate_exception_if(mode_64bit(), EXC_UD, -1);
2742 generate_exception_if(base == 0, EXC_DE, -1);
2743 *(uint16_t *)&_regs.eax = ((al / base) << 8) | (al % base);
2744 _regs.eflags &= ~(EFLG_SF|EFLG_ZF|EFLG_PF);
2745 _regs.eflags |= ((uint8_t)_regs.eax == 0) ? EFLG_ZF : 0;
2746 _regs.eflags |= (( int8_t)_regs.eax < 0) ? EFLG_SF : 0;
2747 _regs.eflags |= even_parity(_regs.eax) ? EFLG_PF : 0;
2748 break;
2751 case 0xd5: /* aad */ {
2752 unsigned int base = insn_fetch_type(uint8_t);
2753 uint16_t ax = _regs.eax;
2754 generate_exception_if(mode_64bit(), EXC_UD, -1);
2755 *(uint16_t *)&_regs.eax = (uint8_t)(ax + ((ax >> 8) * base));
2756 _regs.eflags &= ~(EFLG_SF|EFLG_ZF|EFLG_PF);
2757 _regs.eflags |= ((uint8_t)_regs.eax == 0) ? EFLG_ZF : 0;
2758 _regs.eflags |= (( int8_t)_regs.eax < 0) ? EFLG_SF : 0;
2759 _regs.eflags |= even_parity(_regs.eax) ? EFLG_PF : 0;
2760 break;
2763 case 0xd6: /* salc */
2764 generate_exception_if(mode_64bit(), EXC_UD, -1);
2765 *(uint8_t *)&_regs.eax = (_regs.eflags & EFLG_CF) ? 0xff : 0x00;
2766 break;
2768 case 0xd7: /* xlat */ {
2769 unsigned long al = (uint8_t)_regs.eax;
2770 if ( (rc = ops->read(ea.mem.seg, truncate_ea(_regs.ebx + al),
2771 &al, 1, ctxt)) != 0 )
2772 goto done;
2773 *(uint8_t *)&_regs.eax = al;
2774 break;
2777 case 0xd9: /* FPU 0xd9 */
2778 switch ( modrm )
2780 case 0xc0 ... 0xc7: /* fld %stN */
2781 case 0xc8 ... 0xcf: /* fxch %stN */
2782 case 0xd0: /* fnop */
2783 case 0xe0: /* fchs */
2784 case 0xe1: /* fabs */
2785 case 0xe4: /* ftst */
2786 case 0xe5: /* fxam */
2787 case 0xe8: /* fld1 */
2788 case 0xe9: /* fldl2t */
2789 case 0xea: /* fldl2e */
2790 case 0xeb: /* fldpi */
2791 case 0xec: /* fldlg2 */
2792 case 0xed: /* fldln2 */
2793 case 0xee: /* fldz */
2794 case 0xf0: /* f2xm1 */
2795 case 0xf1: /* fyl2x */
2796 case 0xf2: /* fptan */
2797 case 0xf3: /* fpatan */
2798 case 0xf4: /* fxtract */
2799 case 0xf5: /* fprem1 */
2800 case 0xf6: /* fdecstp */
2801 case 0xf7: /* fincstp */
2802 case 0xf8: /* fprem */
2803 case 0xf9: /* fyl2xp1 */
2804 case 0xfa: /* fsqrt */
2805 case 0xfb: /* fsincos */
2806 case 0xfc: /* frndint */
2807 case 0xfd: /* fscale */
2808 case 0xfe: /* fsin */
2809 case 0xff: /* fcos */
2810 emulate_fpu_insn_stub(0xd9, modrm);
2811 break;
2812 default:
2813 fail_if((modrm_reg & 7) != 7);
2814 fail_if(modrm >= 0xc0);
2815 /* fnstcw m2byte */
2816 ea.bytes = 2;
2817 dst = ea;
2818 emulate_fpu_insn_memdst("fnstcw", dst.val);
2820 break;
2822 case 0xdb: /* FPU 0xdb */
2823 fail_if(modrm != 0xe3);
2824 /* fninit */
2825 emulate_fpu_insn("fninit");
2826 break;
2828 case 0xdd: /* FPU 0xdd */
2829 fail_if((modrm_reg & 7) != 7);
2830 fail_if(modrm >= 0xc0);
2831 /* fnstsw m2byte */
2832 ea.bytes = 2;
2833 dst = ea;
2834 emulate_fpu_insn_memdst("fnstsw", dst.val);
2835 break;
2837 case 0xde: /* FPU 0xde */
2838 switch ( modrm )
2840 case 0xc0 ... 0xc7: /* faddp %stN */
2841 case 0xc8 ... 0xcf: /* fmulp %stN */
2842 case 0xd9: /* fcompp */
2843 case 0xe0 ... 0xe7: /* fsubrp %stN */
2844 case 0xe8 ... 0xef: /* fsubp %stN */
2845 case 0xf0 ... 0xf7: /* fdivrp %stN */
2846 case 0xf8 ... 0xff: /* fdivp %stN */
2847 emulate_fpu_insn_stub(0xde, modrm);
2848 break;
2849 default:
2850 goto cannot_emulate;
2852 break;
2854 case 0xdf: /* FPU 0xdf */
2855 fail_if(modrm != 0xe0);
2856 /* fnstsw %ax */
2857 dst.bytes = 2;
2858 dst.type = OP_REG;
2859 dst.reg = (unsigned long *)&_regs.eax;
2860 emulate_fpu_insn_memdst("fnstsw", dst.val);
2861 break;
2863 case 0xe0 ... 0xe2: /* loop{,z,nz} */ {
2864 int rel = insn_fetch_type(int8_t);
2865 int do_jmp = !(_regs.eflags & EFLG_ZF); /* loopnz */
2866 if ( b == 0xe1 )
2867 do_jmp = !do_jmp; /* loopz */
2868 else if ( b == 0xe2 )
2869 do_jmp = 1; /* loop */
2870 switch ( ad_bytes )
2872 case 2:
2873 do_jmp &= --(*(uint16_t *)&_regs.ecx) != 0;
2874 break;
2875 case 4:
2876 do_jmp &= --(*(uint32_t *)&_regs.ecx) != 0;
2877 _regs.ecx = (uint32_t)_regs.ecx; /* zero extend in x86/64 mode */
2878 break;
2879 default: /* case 8: */
2880 do_jmp &= --_regs.ecx != 0;
2881 break;
2883 if ( do_jmp )
2884 jmp_rel(rel);
2885 break;
2888 case 0xe3: /* jcxz/jecxz (short) */ {
2889 int rel = insn_fetch_type(int8_t);
2890 if ( (ad_bytes == 2) ? !(uint16_t)_regs.ecx :
2891 (ad_bytes == 4) ? !(uint32_t)_regs.ecx : !_regs.ecx )
2892 jmp_rel(rel);
2893 break;
2896 case 0xe4: /* in imm8,%al */
2897 case 0xe5: /* in imm8,%eax */
2898 case 0xe6: /* out %al,imm8 */
2899 case 0xe7: /* out %eax,imm8 */
2900 case 0xec: /* in %dx,%al */
2901 case 0xed: /* in %dx,%eax */
2902 case 0xee: /* out %al,%dx */
2903 case 0xef: /* out %eax,%dx */ {
2904 unsigned int port = ((b < 0xe8)
2905 ? insn_fetch_type(uint8_t)
2906 : (uint16_t)_regs.edx);
2907 op_bytes = !(b & 1) ? 1 : (op_bytes == 8) ? 4 : op_bytes;
2908 if ( (rc = ioport_access_check(port, op_bytes, ctxt, ops)) != 0 )
2909 goto done;
2910 if ( b & 2 )
2912 /* out */
2913 fail_if(ops->write_io == NULL);
2914 rc = ops->write_io(port, op_bytes, _regs.eax, ctxt);
2917 else
2919 /* in */
2920 dst.type = OP_REG;
2921 dst.bytes = op_bytes;
2922 dst.reg = (unsigned long *)&_regs.eax;
2923 fail_if(ops->read_io == NULL);
2924 rc = ops->read_io(port, dst.bytes, &dst.val, ctxt);
2926 if ( rc != 0 )
2927 goto done;
2928 break;
2931 case 0xe8: /* call (near) */ {
2932 int rel = (((op_bytes == 2) && !mode_64bit())
2933 ? (int32_t)insn_fetch_type(int16_t)
2934 : insn_fetch_type(int32_t));
2935 op_bytes = mode_64bit() ? 8 : op_bytes;
2936 src.val = _regs.eip;
2937 jmp_rel(rel);
2938 goto push;
2941 case 0xe9: /* jmp (near) */ {
2942 int rel = (((op_bytes == 2) && !mode_64bit())
2943 ? (int32_t)insn_fetch_type(int16_t)
2944 : insn_fetch_type(int32_t));
2945 jmp_rel(rel);
2946 break;
2949 case 0xea: /* jmp (far, absolute) */ {
2950 uint16_t sel;
2951 uint32_t eip;
2952 generate_exception_if(mode_64bit(), EXC_UD, -1);
2953 eip = insn_fetch_bytes(op_bytes);
2954 sel = insn_fetch_type(uint16_t);
2955 if ( (rc = load_seg(x86_seg_cs, sel, ctxt, ops)) != 0 )
2956 goto done;
2957 _regs.eip = eip;
2958 break;
2961 case 0xeb: /* jmp (short) */ {
2962 int rel = insn_fetch_type(int8_t);
2963 jmp_rel(rel);
2964 break;
2967 case 0xf1: /* int1 (icebp) */
2968 src.val = EXC_DB;
2969 goto swint;
2971 case 0xf4: /* hlt */
2972 ctxt->retire.flags.hlt = 1;
2973 break;
2975 case 0xf5: /* cmc */
2976 _regs.eflags ^= EFLG_CF;
2977 break;
2979 case 0xf8: /* clc */
2980 _regs.eflags &= ~EFLG_CF;
2981 break;
2983 case 0xf9: /* stc */
2984 _regs.eflags |= EFLG_CF;
2985 break;
2987 case 0xfa: /* cli */
2988 generate_exception_if(!mode_iopl(), EXC_GP, 0);
2989 _regs.eflags &= ~EFLG_IF;
2990 break;
2992 case 0xfb: /* sti */
2993 generate_exception_if(!mode_iopl(), EXC_GP, 0);
2994 if ( !(_regs.eflags & EFLG_IF) )
2996 _regs.eflags |= EFLG_IF;
2997 ctxt->retire.flags.sti = 1;
2999 break;
3001 case 0xfc: /* cld */
3002 _regs.eflags &= ~EFLG_DF;
3003 break;
3005 case 0xfd: /* std */
3006 _regs.eflags |= EFLG_DF;
3007 break;
3009 goto writeback;
3011 twobyte_insn:
3012 switch ( b )
3014 case 0x40 ... 0x4f: /* cmovcc */
3015 dst.val = src.val;
3016 if ( !test_cc(b, _regs.eflags) )
3017 dst.type = OP_NONE;
3018 break;
3020 case 0x90 ... 0x9f: /* setcc */
3021 dst.val = test_cc(b, _regs.eflags);
3022 break;
3024 case 0xb0 ... 0xb1: /* cmpxchg */
3025 /* Save real source value, then compare EAX against destination. */
3026 src.orig_val = src.val;
3027 src.val = _regs.eax;
3028 emulate_2op_SrcV("cmp", src, dst, _regs.eflags);
3029 if ( _regs.eflags & EFLG_ZF )
3031 /* Success: write back to memory. */
3032 dst.val = src.orig_val;
3034 else
3036 /* Failure: write the value we saw to EAX. */
3037 dst.type = OP_REG;
3038 dst.reg = (unsigned long *)&_regs.eax;
3040 break;
3042 case 0xa3: bt: /* bt */
3043 emulate_2op_SrcV_nobyte("bt", src, dst, _regs.eflags);
3044 dst.type = OP_NONE;
3045 break;
3047 case 0xa4: /* shld imm8,r,r/m */
3048 case 0xa5: /* shld %%cl,r,r/m */
3049 case 0xac: /* shrd imm8,r,r/m */
3050 case 0xad: /* shrd %%cl,r,r/m */ {
3051 uint8_t shift, width = dst.bytes << 3;
3052 shift = (b & 1) ? (uint8_t)_regs.ecx : insn_fetch_type(uint8_t);
3053 if ( (shift &= width - 1) == 0 )
3054 break;
3055 dst.orig_val = truncate_word(dst.val, dst.bytes);
3056 dst.val = ((shift == width) ? src.val :
3057 (b & 8) ?
3058 /* shrd */
3059 ((dst.orig_val >> shift) |
3060 truncate_word(src.val << (width - shift), dst.bytes)) :
3061 /* shld */
3062 ((dst.orig_val << shift) |
3063 ((src.val >> (width - shift)) & ((1ull << shift) - 1))));
3064 dst.val = truncate_word(dst.val, dst.bytes);
3065 _regs.eflags &= ~(EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_PF|EFLG_CF);
3066 if ( (dst.val >> ((b & 8) ? (shift - 1) : (width - shift))) & 1 )
3067 _regs.eflags |= EFLG_CF;
3068 if ( ((dst.val ^ dst.orig_val) >> (width - 1)) & 1 )
3069 _regs.eflags |= EFLG_OF;
3070 _regs.eflags |= ((dst.val >> (width - 1)) & 1) ? EFLG_SF : 0;
3071 _regs.eflags |= (dst.val == 0) ? EFLG_ZF : 0;
3072 _regs.eflags |= even_parity(dst.val) ? EFLG_PF : 0;
3073 break;
3076 case 0xb3: btr: /* btr */
3077 emulate_2op_SrcV_nobyte("btr", src, dst, _regs.eflags);
3078 break;
3080 case 0xab: bts: /* bts */
3081 emulate_2op_SrcV_nobyte("bts", src, dst, _regs.eflags);
3082 break;
3084 case 0xaf: /* imul */
3085 _regs.eflags &= ~(EFLG_OF|EFLG_CF);
3086 switch ( dst.bytes )
3088 case 2:
3089 dst.val = ((uint32_t)(int16_t)src.val *
3090 (uint32_t)(int16_t)dst.val);
3091 if ( (int16_t)dst.val != (uint32_t)dst.val )
3092 _regs.eflags |= EFLG_OF|EFLG_CF;
3093 break;
3094 #ifdef __x86_64__
3095 case 4:
3096 dst.val = ((uint64_t)(int32_t)src.val *
3097 (uint64_t)(int32_t)dst.val);
3098 if ( (int32_t)dst.val != dst.val )
3099 _regs.eflags |= EFLG_OF|EFLG_CF;
3100 break;
3101 #endif
3102 default: {
3103 unsigned long m[2] = { src.val, dst.val };
3104 if ( imul_dbl(m) )
3105 _regs.eflags |= EFLG_OF|EFLG_CF;
3106 dst.val = m[0];
3107 break;
3110 break;
3112 case 0xb2: /* lss */
3113 dst.val = x86_seg_ss;
3114 goto les;
3116 case 0xb4: /* lfs */
3117 dst.val = x86_seg_fs;
3118 goto les;
3120 case 0xb5: /* lgs */
3121 dst.val = x86_seg_gs;
3122 goto les;
3124 case 0xb6: /* movzx rm8,r{16,32,64} */
3125 /* Recompute DstReg as we may have decoded AH/BH/CH/DH. */
3126 dst.reg = decode_register(modrm_reg, &_regs, 0);
3127 dst.bytes = op_bytes;
3128 dst.val = (uint8_t)src.val;
3129 break;
3131 case 0xbc: /* bsf */ {
3132 int zf;
3133 asm ( "bsf %2,%0; setz %b1"
3134 : "=r" (dst.val), "=q" (zf)
3135 : "r" (src.val), "1" (0) );
3136 _regs.eflags &= ~EFLG_ZF;
3137 _regs.eflags |= zf ? EFLG_ZF : 0;
3138 break;
3141 case 0xbd: /* bsr */ {
3142 int zf;
3143 asm ( "bsr %2,%0; setz %b1"
3144 : "=r" (dst.val), "=q" (zf)
3145 : "r" (src.val), "1" (0) );
3146 _regs.eflags &= ~EFLG_ZF;
3147 _regs.eflags |= zf ? EFLG_ZF : 0;
3148 break;
3151 case 0xb7: /* movzx rm16,r{16,32,64} */
3152 dst.val = (uint16_t)src.val;
3153 break;
3155 case 0xbb: btc: /* btc */
3156 emulate_2op_SrcV_nobyte("btc", src, dst, _regs.eflags);
3157 break;
3159 case 0xba: /* Grp8 */
3160 switch ( modrm_reg & 7 )
3162 case 4: goto bt;
3163 case 5: goto bts;
3164 case 6: goto btr;
3165 case 7: goto btc;
3166 default: generate_exception_if(1, EXC_UD, -1);
3168 break;
3170 case 0xbe: /* movsx rm8,r{16,32,64} */
3171 /* Recompute DstReg as we may have decoded AH/BH/CH/DH. */
3172 dst.reg = decode_register(modrm_reg, &_regs, 0);
3173 dst.bytes = op_bytes;
3174 dst.val = (int8_t)src.val;
3175 break;
3177 case 0xbf: /* movsx rm16,r{16,32,64} */
3178 dst.val = (int16_t)src.val;
3179 break;
3181 case 0xc0 ... 0xc1: /* xadd */
3182 /* Write back the register source. */
3183 switch ( dst.bytes )
3185 case 1: *(uint8_t *)src.reg = (uint8_t)dst.val; break;
3186 case 2: *(uint16_t *)src.reg = (uint16_t)dst.val; break;
3187 case 4: *src.reg = (uint32_t)dst.val; break; /* 64b reg: zero-extend */
3188 case 8: *src.reg = dst.val; break;
3190 goto add;
3192 goto writeback;
3194 twobyte_special_insn:
3195 switch ( b )
3197 case 0x01: /* Grp7 */ {
3198 struct segment_register reg;
3199 unsigned long base, limit, cr0, cr0w;
3201 if ( modrm == 0xdf ) /* invlpga */
3203 generate_exception_if(in_realmode(ctxt, ops), EXC_UD, -1);
3204 generate_exception_if(!mode_ring0(), EXC_GP, 0);
3205 fail_if(ops->invlpg == NULL);
3206 if ( (rc = ops->invlpg(x86_seg_none, truncate_ea(_regs.eax),
3207 ctxt)) )
3208 goto done;
3209 break;
3212 switch ( modrm_reg & 7 )
3214 case 0: /* sgdt */
3215 case 1: /* sidt */
3216 generate_exception_if(ea.type != OP_MEM, EXC_UD, -1);
3217 fail_if(ops->read_segment == NULL);
3218 if ( (rc = ops->read_segment((modrm_reg & 1) ?
3219 x86_seg_idtr : x86_seg_gdtr,
3220 &reg, ctxt)) )
3221 goto done;
3222 if ( op_bytes == 2 )
3223 reg.base &= 0xffffff;
3224 if ( (rc = ops->write(ea.mem.seg, ea.mem.off+0,
3225 reg.limit, 2, ctxt)) ||
3226 (rc = ops->write(ea.mem.seg, ea.mem.off+2,
3227 reg.base, mode_64bit() ? 8 : 4, ctxt)) )
3228 goto done;
3229 break;
3230 case 2: /* lgdt */
3231 case 3: /* lidt */
3232 generate_exception_if(ea.type != OP_MEM, EXC_UD, -1);
3233 fail_if(ops->write_segment == NULL);
3234 memset(&reg, 0, sizeof(reg));
3235 if ( (rc = ops->read(ea.mem.seg, ea.mem.off+0,
3236 &limit, 2, ctxt)) ||
3237 (rc = ops->read(ea.mem.seg, ea.mem.off+2,
3238 &base, mode_64bit() ? 8 : 4, ctxt)) )
3239 goto done;
3240 reg.base = base;
3241 reg.limit = limit;
3242 if ( op_bytes == 2 )
3243 reg.base &= 0xffffff;
3244 if ( (rc = ops->write_segment((modrm_reg & 1) ?
3245 x86_seg_idtr : x86_seg_gdtr,
3246 &reg, ctxt)) )
3247 goto done;
3248 break;
3249 case 4: /* smsw */
3250 ea.bytes = 2;
3251 dst = ea;
3252 fail_if(ops->read_cr == NULL);
3253 if ( (rc = ops->read_cr(0, &dst.val, ctxt)) )
3254 goto done;
3255 d |= Mov; /* force writeback */
3256 break;
3257 case 6: /* lmsw */
3258 fail_if(ops->read_cr == NULL);
3259 fail_if(ops->write_cr == NULL);
3260 if ( (rc = ops->read_cr(0, &cr0, ctxt)) )
3261 goto done;
3262 if ( ea.type == OP_REG )
3263 cr0w = *ea.reg;
3264 else if ( (rc = ops->read(ea.mem.seg, ea.mem.off,
3265 &cr0w, 2, ctxt)) )
3266 goto done;
3267 cr0 &= 0xffff0000;
3268 cr0 |= (uint16_t)cr0w;
3269 if ( (rc = ops->write_cr(0, cr0, ctxt)) )
3270 goto done;
3271 break;
3272 case 7: /* invlpg */
3273 generate_exception_if(!mode_ring0(), EXC_GP, 0);
3274 generate_exception_if(ea.type != OP_MEM, EXC_UD, -1);
3275 fail_if(ops->invlpg == NULL);
3276 if ( (rc = ops->invlpg(ea.mem.seg, ea.mem.off, ctxt)) )
3277 goto done;
3278 break;
3279 default:
3280 goto cannot_emulate;
3282 break;
3285 case 0x06: /* clts */
3286 generate_exception_if(!mode_ring0(), EXC_GP, 0);
3287 fail_if((ops->read_cr == NULL) || (ops->write_cr == NULL));
3288 if ( (rc = ops->read_cr(0, &dst.val, ctxt)) ||
3289 (rc = ops->write_cr(0, dst.val&~8, ctxt)) )
3290 goto done;
3291 break;
3293 case 0x08: /* invd */
3294 case 0x09: /* wbinvd */
3295 generate_exception_if(!mode_ring0(), EXC_GP, 0);
3296 fail_if(ops->wbinvd == NULL);
3297 if ( (rc = ops->wbinvd(ctxt)) != 0 )
3298 goto done;
3299 break;
3301 case 0x0d: /* GrpP (prefetch) */
3302 case 0x18: /* Grp16 (prefetch/nop) */
3303 case 0x19 ... 0x1f: /* nop (amd-defined) */
3304 break;
3306 case 0x20: /* mov cr,reg */
3307 case 0x21: /* mov dr,reg */
3308 case 0x22: /* mov reg,cr */
3309 case 0x23: /* mov reg,dr */
3310 generate_exception_if(ea.type != OP_REG, EXC_UD, -1);
3311 generate_exception_if(!mode_ring0(), EXC_GP, 0);
3312 modrm_reg |= lock_prefix << 3;
3313 if ( b & 2 )
3315 /* Write to CR/DR. */
3316 src.val = *(unsigned long *)decode_register(modrm_rm, &_regs, 0);
3317 if ( !mode_64bit() )
3318 src.val = (uint32_t)src.val;
3319 rc = ((b & 1)
3320 ? (ops->write_dr
3321 ? ops->write_dr(modrm_reg, src.val, ctxt)
3322 : X86EMUL_UNHANDLEABLE)
3323 : (ops->write_cr
3324 ? ops->write_cr(modrm_reg, src.val, ctxt)
3325 : X86EMUL_UNHANDLEABLE));
3327 else
3329 /* Read from CR/DR. */
3330 dst.type = OP_REG;
3331 dst.bytes = mode_64bit() ? 8 : 4;
3332 dst.reg = decode_register(modrm_rm, &_regs, 0);
3333 rc = ((b & 1)
3334 ? (ops->read_dr
3335 ? ops->read_dr(modrm_reg, &dst.val, ctxt)
3336 : X86EMUL_UNHANDLEABLE)
3337 : (ops->read_cr
3338 ? ops->read_cr(modrm_reg, &dst.val, ctxt)
3339 : X86EMUL_UNHANDLEABLE));
3341 if ( rc != 0 )
3342 goto done;
3343 break;
3345 case 0x30: /* wrmsr */ {
3346 uint64_t val = ((uint64_t)_regs.edx << 32) | (uint32_t)_regs.eax;
3347 generate_exception_if(!mode_ring0(), EXC_GP, 0);
3348 fail_if(ops->write_msr == NULL);
3349 if ( (rc = ops->write_msr((uint32_t)_regs.ecx, val, ctxt)) != 0 )
3350 goto done;
3351 break;
3354 case 0x31: /* rdtsc */ {
3355 unsigned long cr4;
3356 uint64_t val;
3357 fail_if(ops->read_cr == NULL);
3358 if ( (rc = ops->read_cr(4, &cr4, ctxt)) )
3359 goto done;
3360 generate_exception_if((cr4 & CR4_TSD) && !mode_ring0(), EXC_GP, 0);
3361 fail_if(ops->read_msr == NULL);
3362 if ( (rc = ops->read_msr(MSR_TSC, &val, ctxt)) != 0 )
3363 goto done;
3364 _regs.edx = (uint32_t)(val >> 32);
3365 _regs.eax = (uint32_t)(val >> 0);
3366 break;
3369 case 0x32: /* rdmsr */ {
3370 uint64_t val;
3371 generate_exception_if(!mode_ring0(), EXC_GP, 0);
3372 fail_if(ops->read_msr == NULL);
3373 if ( (rc = ops->read_msr((uint32_t)_regs.ecx, &val, ctxt)) != 0 )
3374 goto done;
3375 _regs.edx = (uint32_t)(val >> 32);
3376 _regs.eax = (uint32_t)(val >> 0);
3377 break;
3380 case 0x6f: /* movq mm/m64,mm */ {
3381 uint8_t stub[] = { 0x0f, 0x6f, modrm, 0xc3 };
3382 struct fpu_insn_ctxt fic = { .insn_bytes = sizeof(stub)-1 };
3383 uint64_t val;
3384 if ( ea.type == OP_MEM )
3386 unsigned long lval, hval;
3387 if ( (rc = ops->read(ea.mem.seg, ea.mem.off+0, &lval, 4, ctxt)) ||
3388 (rc = ops->read(ea.mem.seg, ea.mem.off+4, &hval, 4, ctxt)) )
3389 goto done;
3390 val = ((uint64_t)hval << 32) | (uint32_t)lval;
3391 stub[2] = modrm & 0x38; /* movq (%eax),%mmN */
3393 get_fpu(X86EMUL_FPU_mmx, &fic);
3394 asm volatile ( "call *%0" : : "r" (stub), "a" (&val) : "memory" );
3395 put_fpu(&fic);
3396 break;
3399 case 0x7f: /* movq mm,mm/m64 */ {
3400 uint8_t stub[] = { 0x0f, 0x7f, modrm, 0xc3 };
3401 struct fpu_insn_ctxt fic = { .insn_bytes = sizeof(stub)-1 };
3402 uint64_t val;
3403 if ( ea.type == OP_MEM )
3404 stub[2] = modrm & 0x38; /* movq %mmN,(%eax) */
3405 get_fpu(X86EMUL_FPU_mmx, &fic);
3406 asm volatile ( "call *%0" : : "r" (stub), "a" (&val) : "memory" );
3407 put_fpu(&fic);
3408 if ( ea.type == OP_MEM )
3410 unsigned long lval = (uint32_t)val, hval = (uint32_t)(val >> 32);
3411 if ( (rc = ops->write(ea.mem.seg, ea.mem.off+0, lval, 4, ctxt)) ||
3412 (rc = ops->write(ea.mem.seg, ea.mem.off+4, hval, 4, ctxt)) )
3413 goto done;
3415 break;
3418 case 0x80 ... 0x8f: /* jcc (near) */ {
3419 int rel = (((op_bytes == 2) && !mode_64bit())
3420 ? (int32_t)insn_fetch_type(int16_t)
3421 : insn_fetch_type(int32_t));
3422 if ( test_cc(b, _regs.eflags) )
3423 jmp_rel(rel);
3424 break;
3427 case 0xa0: /* push %%fs */
3428 src.val = x86_seg_fs;
3429 goto push_seg;
3431 case 0xa1: /* pop %%fs */
3432 src.val = x86_seg_fs;
3433 goto pop_seg;
3435 case 0xa2: /* cpuid */ {
3436 unsigned int eax = _regs.eax, ebx = _regs.ebx;
3437 unsigned int ecx = _regs.ecx, edx = _regs.edx;
3438 fail_if(ops->cpuid == NULL);
3439 if ( (rc = ops->cpuid(&eax, &ebx, &ecx, &edx, ctxt)) != 0 )
3440 goto done;
3441 _regs.eax = eax; _regs.ebx = ebx;
3442 _regs.ecx = ecx; _regs.edx = edx;
3443 break;
3446 case 0xa8: /* push %%gs */
3447 src.val = x86_seg_gs;
3448 goto push_seg;
3450 case 0xa9: /* pop %%gs */
3451 src.val = x86_seg_gs;
3452 goto pop_seg;
3454 case 0xc7: /* Grp9 (cmpxchg8b) */
3455 #if defined(__i386__)
3457 unsigned long old_lo, old_hi;
3458 generate_exception_if((modrm_reg & 7) != 1, EXC_UD, -1);
3459 generate_exception_if(ea.type != OP_MEM, EXC_UD, -1);
3460 if ( (rc = ops->read(ea.mem.seg, ea.mem.off+0, &old_lo, 4, ctxt)) ||
3461 (rc = ops->read(ea.mem.seg, ea.mem.off+4, &old_hi, 4, ctxt)) )
3462 goto done;
3463 if ( (old_lo != _regs.eax) || (old_hi != _regs.edx) )
3465 _regs.eax = old_lo;
3466 _regs.edx = old_hi;
3467 _regs.eflags &= ~EFLG_ZF;
3469 else if ( ops->cmpxchg8b == NULL )
3471 rc = X86EMUL_UNHANDLEABLE;
3472 goto done;
3474 else
3476 if ( (rc = ops->cmpxchg8b(ea.mem.seg, ea.mem.off, old_lo, old_hi,
3477 _regs.ebx, _regs.ecx, ctxt)) != 0 )
3478 goto done;
3479 _regs.eflags |= EFLG_ZF;
3481 break;
3483 #elif defined(__x86_64__)
3485 unsigned long old, new;
3486 generate_exception_if((modrm_reg & 7) != 1, EXC_UD, -1);
3487 generate_exception_if(ea.type != OP_MEM, EXC_UD, -1);
3488 if ( (rc = ops->read(ea.mem.seg, ea.mem.off, &old, 8, ctxt)) != 0 )
3489 goto done;
3490 if ( ((uint32_t)(old>>0) != (uint32_t)_regs.eax) ||
3491 ((uint32_t)(old>>32) != (uint32_t)_regs.edx) )
3493 _regs.eax = (uint32_t)(old>>0);
3494 _regs.edx = (uint32_t)(old>>32);
3495 _regs.eflags &= ~EFLG_ZF;
3497 else
3499 new = (_regs.ecx<<32)|(uint32_t)_regs.ebx;
3500 if ( (rc = ops->cmpxchg(ea.mem.seg, ea.mem.off, old,
3501 new, 8, ctxt)) != 0 )
3502 goto done;
3503 _regs.eflags |= EFLG_ZF;
3505 break;
3507 #endif
3509 case 0xc8 ... 0xcf: /* bswap */
3510 dst.type = OP_REG;
3511 dst.reg = decode_register(
3512 (b & 7) | ((rex_prefix & 1) << 3), &_regs, 0);
3513 switch ( dst.bytes = op_bytes )
3515 default: /* case 2: */
3516 /* Undefined behaviour. Writes zero on all tested CPUs. */
3517 dst.val = 0;
3518 break;
3519 case 4:
3520 #ifdef __x86_64__
3521 asm ( "bswap %k0" : "=r" (dst.val) : "0" (*dst.reg) );
3522 break;
3523 case 8:
3524 #endif
3525 asm ( "bswap %0" : "=r" (dst.val) : "0" (*dst.reg) );
3526 break;
3528 break;
3530 goto writeback;
3532 cannot_emulate:
3533 return X86EMUL_UNHANDLEABLE;